akaros/user/perfmon/pfmlib_intel_snb.c
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   1/*
   2 * pfmlib_intel_snb.c : Intel Sandy Bridge core PMU
   3 *
   4 * Copyright (c) 2010 Google, Inc
   5 * Contributed by Stephane Eranian <eranian@gmail.com>
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a copy
   8 * of this software and associated documentation files (the "Software"), to deal
   9 * in the Software without restriction, including without limitation the rights
  10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  11 * of the Software, and to permit persons to whom the Software is furnished to do so,
  12 * subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included in all
  15 * copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
  18 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
  19 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  20 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
  21 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  22 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23 */
  24/* private headers */
  25#include "pfmlib_priv.h"
  26#include "pfmlib_intel_x86_priv.h"
  27#include "events/intel_snb_events.h"
  28#include "events/intel_snbep_events.h"
  29
  30static const int snb_models[] = {
  31        42, /* Sandy Bridge (Core i7 26xx, 25xx) */
  32        0
  33};
  34
  35static const int snb_ep_models[] = {
  36        45, /* Sandy Bridge EP */
  37        0
  38};
  39
  40static int
  41pfm_snb_init(void *this)
  42{
  43        pfm_intel_x86_cfg.arch_version = 3;
  44        return PFM_SUCCESS;
  45}
  46
  47pfmlib_pmu_t intel_snb_support={
  48        .desc                   = "Intel Sandy Bridge",
  49        .name                   = "snb",
  50        .pmu                    = PFM_PMU_INTEL_SNB,
  51        .pme_count              = LIBPFM_ARRAY_SIZE(intel_snb_pe),
  52        .type                   = PFM_PMU_TYPE_CORE,
  53        .supported_plm          = INTEL_X86_PLM,
  54        .num_cntrs              = 8, /* consider with HT off by default */
  55        .num_fixed_cntrs        = 3,
  56        .max_encoding           = 2, /* offcore_response */
  57        .pe                     = intel_snb_pe,
  58        .atdesc                 = intel_x86_mods,
  59        .flags                  = PFMLIB_PMU_FL_RAW_UMASK
  60                                | INTEL_X86_PMU_FL_ECMASK,
  61        .cpu_family             = 6,
  62        .cpu_models             = snb_models,
  63        .pmu_detect             = pfm_intel_x86_model_detect,
  64        .pmu_init               = pfm_snb_init,
  65        .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding,
  66         PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding),
  67        .get_event_first        = pfm_intel_x86_get_event_first,
  68        .get_event_next         = pfm_intel_x86_get_event_next,
  69        .event_is_valid         = pfm_intel_x86_event_is_valid,
  70        .validate_table         = pfm_intel_x86_validate_table,
  71        .get_event_info         = pfm_intel_x86_get_event_info,
  72        .get_event_attr_info    = pfm_intel_x86_get_event_attr_info,
  73         PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs),
  74        .get_event_nattrs       = pfm_intel_x86_get_event_nattrs,
  75        .can_auto_encode        = pfm_intel_x86_can_auto_encode,
  76};
  77
  78pfmlib_pmu_t intel_snb_ep_support={
  79        .desc                   = "Intel Sandy Bridge EP",
  80        .name                   = "snb_ep",
  81        .pmu                    = PFM_PMU_INTEL_SNB_EP,
  82        .pme_count              = LIBPFM_ARRAY_SIZE(intel_snbep_pe),
  83        .type                   = PFM_PMU_TYPE_CORE,
  84        .supported_plm          = INTEL_X86_PLM,
  85        .num_cntrs              = 8, /* consider with HT off by default */
  86        .num_fixed_cntrs        = 3,
  87        .max_encoding           = 2, /* offcore_response */
  88        .pe                     = intel_snbep_pe,
  89        .atdesc                 = intel_x86_mods,
  90        .flags                  = PFMLIB_PMU_FL_RAW_UMASK
  91                                | INTEL_X86_PMU_FL_ECMASK,
  92        .cpu_family             = 6,
  93        .cpu_models             = snb_ep_models,
  94        .pmu_detect             = pfm_intel_x86_model_detect,
  95        .pmu_init               = pfm_snb_init,
  96        .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding,
  97         PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding),
  98        .get_event_first        = pfm_intel_x86_get_event_first,
  99        .get_event_next         = pfm_intel_x86_get_event_next,
 100        .event_is_valid         = pfm_intel_x86_event_is_valid,
 101        .validate_table         = pfm_intel_x86_validate_table,
 102        .get_event_info         = pfm_intel_x86_get_event_info,
 103        .get_event_attr_info    = pfm_intel_x86_get_event_attr_info,
 104         PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs),
 105        .get_event_nattrs       = pfm_intel_x86_get_event_nattrs,
 106        .can_auto_encode        = pfm_intel_x86_can_auto_encode,
 107};
 108