akaros/user/perfmon/pfmlib_intel_nhm.c
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   1/*
   2 * pfmlib_intel_nhm.c : Intel Nehalem core PMU
   3 *
   4 * Copyright (c) 2008 Google, Inc
   5 * Contributed by Stephane Eranian <eranian@gmail.com>
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a copy
   8 * of this software and associated documentation files (the "Software"), to deal
   9 * in the Software without restriction, including without limitation the rights
  10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  11 * of the Software, and to permit persons to whom the Software is furnished to do so,
  12 * subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included in all
  15 * copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
  18 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
  19 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  20 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
  21 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  22 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23 *
  24 * Nehalem PMU = architectural perfmon v3 + OFFCORE + PEBS v2 + LBR
  25 */
  26/* private headers */
  27#include "pfmlib_priv.h"
  28#include "pfmlib_intel_x86_priv.h"
  29
  30#if 0
  31static int pfm_nhm_lbr_encode(void *this, pfmlib_event_desc_t *e, uint64_t *codes, int *count, pfmlib_perf_attr_t *attrs);
  32static int pfm_nhm_offcore_encode(void *this, pfmlib_event_desc_t *e, uint64_t *codes, int *count, pfmlib_perf_attr_t *attrs);
  33#endif
  34
  35#include "events/intel_nhm_events.h"
  36
  37static const int nhm_models[] = {
  38        26,
  39        30,
  40        31,
  41        0
  42};
  43
  44static const int nhm_ex_models[] = {
  45        46,
  46        0
  47};
  48
  49static int
  50pfm_nhm_init(void *this)
  51{
  52        pfm_intel_x86_cfg.arch_version = 3;
  53        return PFM_SUCCESS;
  54}
  55
  56/*
  57 * the following function implement the model
  58 * specific API directly available to user
  59 */
  60
  61static const char *data_src_encodings[]={
  62/*  0 */        "unknown L3 cache miss",
  63/*  1 */        "minimal latency core cache hit. Request was satisfied by L1 data cache",
  64/*  2 */        "pending core cache HIT. Outstanding core cache miss to same cacheline address already underway",
  65/*  3 */        "data request satisfied by the L2",
  66/*  4 */        "L3 HIT. Local or remote home request that hit L3 in the uncore with no coherency actions required (snooping)",
  67/*  5 */        "L3 HIT. Local or remote home request that hit L3 and was serviced by another core with a cross core snoop where no modified copy was found (clean)",
  68/*  6 */        "L3 HIT. Local or remote home request that hit L3 and was serviced by another core with a cross core snoop where modified copies were found (HITM)",
  69/*  7 */        "reserved",
  70/*  8 */        "L3 MISS. Local homed request that missed L3 and was serviced by forwarded data following a cross package snoop where no modified copy was found (remote home requests are not counted)",
  71/*  9 */        "reserved",
  72/* 10 */        "L3 MISS. Local homed request that missed L3 and was serviced by local DRAM (go to shared state)",
  73/* 11 */        "L3 MISS. Remote homed request that missed L3 and was serviced by remote DRAM (go to shared state)",
  74/* 12 */        "L3 MISS. Local homed request that missed L3 and was serviced by local DRAM (go to exclusive state)",
  75/* 13 */        "L3 MISS. Remote homed request that missed L3 and was serviced by remote DRAM (go to exclusive state)",
  76/* 14 */        "reserved",
  77/* 15 */        "request to uncacheable memory"
  78};
  79
  80/*
  81 * return data source encoding based on index in val
  82 * To be used with PEBS load latency filtering to decode
  83 * source of the load miss
  84 */
  85const char *
  86pfm_nhm_data_src_desc(int val)
  87{
  88        if (val > 15 || val < 0)
  89                return NULL;
  90
  91        return data_src_encodings[val];
  92}
  93
  94#if 0
  95static int
  96pfm_nhm_lbr_encode(void *this, pfmlib_event_desc_t *e, uint64_t *codes, int *count, pfmlib_perf_attr_t *attrs)
  97{
  98        return PFM_ERR_NOTSUPP;
  99}
 100
 101static int
 102pfm_nhm_offcore_encode(void *this, pfmlib_event_desc_t *e, uint64_t *codes, int *count, pfmlib_perf_attr_t *attrs)
 103{
 104        return PFM_ERR_NOTSUPP;
 105}
 106#endif
 107
 108
 109pfmlib_pmu_t intel_nhm_support={
 110        .desc                   = "Intel Nehalem",
 111        .name                   = "nhm",
 112        .pmu                    = PFM_PMU_INTEL_NHM,
 113        .pme_count              = LIBPFM_ARRAY_SIZE(intel_nhm_pe),
 114        .type                   = PFM_PMU_TYPE_CORE,
 115        .supported_plm          = INTEL_X86_PLM,
 116        .num_cntrs              = 4,
 117        .num_fixed_cntrs        = 3,
 118        .max_encoding           = 2, /* because of OFFCORE_RESPONSE */
 119        .pe                     = intel_nhm_pe,
 120        .atdesc                 = intel_x86_mods,
 121        .flags                  = PFMLIB_PMU_FL_RAW_UMASK
 122                                | INTEL_X86_PMU_FL_ECMASK,
 123        .cpu_family             = 6,
 124        .cpu_models             = nhm_models,
 125        .pmu_detect             = pfm_intel_x86_model_detect,
 126        .pmu_init               = pfm_nhm_init,
 127
 128        .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding,
 129         PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding),
 130
 131        .get_event_first        = pfm_intel_x86_get_event_first,
 132        .get_event_next         = pfm_intel_x86_get_event_next,
 133        .event_is_valid         = pfm_intel_x86_event_is_valid,
 134        .validate_table         = pfm_intel_x86_validate_table,
 135        .get_event_info         = pfm_intel_x86_get_event_info,
 136        .get_event_attr_info    = pfm_intel_x86_get_event_attr_info,
 137        PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs),
 138        .get_event_nattrs       = pfm_intel_x86_get_event_nattrs,
 139        .can_auto_encode        = pfm_intel_x86_can_auto_encode,
 140};
 141
 142pfmlib_pmu_t intel_nhm_ex_support={
 143        .desc                   = "Intel Nehalem EX",
 144        .name                   = "nhm_ex",
 145        .pmu                    = PFM_PMU_INTEL_NHM_EX,
 146        .pme_count              = LIBPFM_ARRAY_SIZE(intel_nhm_pe),
 147        .type                   = PFM_PMU_TYPE_CORE,
 148        .supported_plm          = INTEL_X86_PLM,
 149        .num_cntrs              = 4,
 150        .num_fixed_cntrs        = 3,
 151        .max_encoding           = 2, /* because of OFFCORE_RESPONSE */
 152        .pe                     = intel_nhm_pe,
 153        .atdesc                 = intel_x86_mods,
 154        .flags                  = PFMLIB_PMU_FL_RAW_UMASK
 155                                | INTEL_X86_PMU_FL_ECMASK,
 156        .cpu_family             = 6,
 157        .cpu_models             = nhm_ex_models,
 158        .pmu_detect             = pfm_intel_x86_model_detect,
 159        .pmu_init               = pfm_nhm_init,
 160
 161        .get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding,
 162         PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding),
 163
 164        .get_event_first        = pfm_intel_x86_get_event_first,
 165        .get_event_next         = pfm_intel_x86_get_event_next,
 166        .event_is_valid         = pfm_intel_x86_event_is_valid,
 167        .validate_table         = pfm_intel_x86_validate_table,
 168        .get_event_info         = pfm_intel_x86_get_event_info,
 169        .get_event_attr_info    = pfm_intel_x86_get_event_attr_info,
 170        PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs),
 171        .get_event_nattrs       = pfm_intel_x86_get_event_nattrs,
 172        .can_auto_encode        = pfm_intel_x86_can_auto_encode,
 173};
 174