akaros/user/perfmon/pfmlib_intel_netburst_priv.h
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   1/*
   2 * Copyright (c) 2006 IBM Corp.
   3 * Contributed by Kevin Corry <kevcorry@us.ibm.com>
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 * pfmlib_netburst_priv.h
  24 *
  25 * Structures and definitions for use in the Pentium4/Xeon/EM64T libpfm code.
  26 */
  27
  28#ifndef _PFMLIB_INTEL_NETBURST_PRIV_H_
  29#define _PFMLIB_INTEL_NETBURST_PRIV_H_
  30
  31/* ESCR: Event Selection Control Register
  32 *
  33 * These registers are used to select which event to count along with options
  34 * for that event. There are (up to) 45 ESCRs, but each data counter is
  35 * restricted to a specific set of ESCRs.
  36 */
  37
  38/**
  39 * netburst_escr_value_t
  40 *
  41 * Bit-wise breakdown of the ESCR registers.
  42 *
  43 *    Bits     Description
  44 *   -------   -----------
  45 *   63 - 31   Reserved
  46 *   30 - 25   Event Select
  47 *   24 - 9    Event Mask
  48 *    8 - 5    Tag Value
  49 *      4      Tag Enable
  50 *      3      T0 OS - Enable counting in kernel mode (thread 0)
  51 *      2      T0 USR - Enable counting in user mode (thread 0)
  52 *      1      T1 OS - Enable counting in kernel mode (thread 1)
  53 *      0      T1 USR - Enable counting in user mode (thread 1)
  54 **/
  55
  56#define EVENT_MASK_BITS 16
  57#define EVENT_SELECT_BITS 6
  58
  59typedef union {
  60        unsigned long long val;
  61        struct {
  62                unsigned long t1_usr:1;
  63                unsigned long t1_os:1;
  64                unsigned long t0_usr:1;
  65                unsigned long t0_os:1;
  66                unsigned long tag_enable:1;
  67                unsigned long tag_value:4;
  68                unsigned long event_mask:EVENT_MASK_BITS;
  69                unsigned long event_select:EVENT_SELECT_BITS;
  70                unsigned long reserved:1;
  71        } bits;
  72} netburst_escr_value_t;
  73
  74/* CCCR: Counter Configuration Control Register
  75 *
  76 * These registers are used to configure the data counters. There are 18
  77 * CCCRs, one for each data counter.
  78 */
  79
  80/**
  81 * netburst_cccr_value_t
  82 *
  83 * Bit-wise breakdown of the CCCR registers.
  84 *
  85 *    Bits     Description
  86 *   -------   -----------
  87 *   63 - 32   Reserved
  88 *     31      OVF - The data counter overflowed.
  89 *     30      Cascade - Enable cascading of data counter when alternate
  90 *             counter overflows.
  91 *   29 - 28   Reserved
  92 *     27      OVF_PMI_T1 - Generate interrupt for LP1 on counter overflow
  93 *     26      OVF_PMI_T0 - Generate interrupt for LP0 on counter overflow
  94 *     25      FORCE_OVF - Force interrupt on every counter increment
  95 *     24      Edge - Enable rising edge detection of the threshold comparison
  96 *             output for filtering event counts.
  97 *   23 - 20   Threshold Value - Select the threshold value for comparing to
  98 *             incoming event counts.
  99 *     19      Complement - Select how incoming event count is compared with
 100 *             the threshold value.
 101 *     18      Compare - Enable filtering of event counts.
 102 *   17 - 16   Active Thread - Only used with HT enabled.
 103 *             00 - None: Count when neither LP is active.
 104 *             01 - Single: Count when only one LP is active.
 105 *             10 - Both: Count when both LPs are active.
 106 *             11 - Any: Count when either LP is active.
 107 *   15 - 13   ESCR Select - Select which ESCR to use for selecting the
 108 *             event to count.
 109 *     12      Enable - Turns the data counter on or off.
 110 *   11 - 0    Reserved
 111 **/
 112typedef union {
 113        unsigned long long val;
 114        struct {
 115                unsigned long reserved1:12;
 116                unsigned long enable:1;
 117                unsigned long escr_select:3;
 118                unsigned long active_thread:2;
 119                unsigned long compare:1;
 120                unsigned long complement:1;
 121                unsigned long threshold:4;
 122                unsigned long edge:1;
 123                unsigned long force_ovf:1;
 124                unsigned long ovf_pmi_t0:1;
 125                unsigned long ovf_pmi_t1:1;
 126                unsigned long reserved2:2;
 127                unsigned long cascade:1;
 128                unsigned long overflow:1;
 129        } bits;
 130} netburst_cccr_value_t;
 131
 132/**
 133 * netburst_event_mask_t
 134 *
 135 * Defines one bit of the event-mask for one Pentium4 event.
 136 *
 137 * @name: Event mask name
 138 * @desc: Event mask description
 139 * @bit: The bit position within the event_mask field.
 140 **/
 141typedef struct {
 142        const char *name;
 143        const char *desc;
 144        unsigned int bit;
 145        unsigned int flags;
 146} netburst_event_mask_t;
 147/*
 148 * netburst_event_mask_t->flags
 149 */
 150#define NETBURST_FL_DFL 0x1 /* event mask is default */
 151
 152#define MAX_ESCRS_PER_EVENT 2
 153
 154/*
 155 * These are the unique event codes used by perf_events.
 156 * The need to be encoded in the ESCR.event_select field when
 157 * programming for perf_events
 158 */
 159enum netburst_events {
 160        P4_EVENT_TC_DELIVER_MODE,
 161        P4_EVENT_BPU_FETCH_REQUEST,
 162        P4_EVENT_ITLB_REFERENCE,
 163        P4_EVENT_MEMORY_CANCEL,
 164        P4_EVENT_MEMORY_COMPLETE,
 165        P4_EVENT_LOAD_PORT_REPLAY,
 166        P4_EVENT_STORE_PORT_REPLAY,
 167        P4_EVENT_MOB_LOAD_REPLAY,
 168        P4_EVENT_PAGE_WALK_TYPE,
 169        P4_EVENT_BSQ_CACHE_REFERENCE,
 170        P4_EVENT_IOQ_ALLOCATION,
 171        P4_EVENT_IOQ_ACTIVE_ENTRIES,
 172        P4_EVENT_FSB_DATA_ACTIVITY,
 173        P4_EVENT_BSQ_ALLOCATION,
 174        P4_EVENT_BSQ_ACTIVE_ENTRIES,
 175        P4_EVENT_SSE_INPUT_ASSIST,
 176        P4_EVENT_PACKED_SP_UOP,
 177        P4_EVENT_PACKED_DP_UOP,
 178        P4_EVENT_SCALAR_SP_UOP,
 179        P4_EVENT_SCALAR_DP_UOP,
 180        P4_EVENT_64BIT_MMX_UOP,
 181        P4_EVENT_128BIT_MMX_UOP,
 182        P4_EVENT_X87_FP_UOP,
 183        P4_EVENT_TC_MISC,
 184        P4_EVENT_GLOBAL_POWER_EVENTS,
 185        P4_EVENT_TC_MS_XFER,
 186        P4_EVENT_UOP_QUEUE_WRITES,
 187        P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE,
 188        P4_EVENT_RETIRED_BRANCH_TYPE,
 189        P4_EVENT_RESOURCE_STALL,
 190        P4_EVENT_WC_BUFFER,
 191        P4_EVENT_B2B_CYCLES,
 192        P4_EVENT_BNR,
 193        P4_EVENT_SNOOP,
 194        P4_EVENT_RESPONSE,
 195        P4_EVENT_FRONT_END_EVENT,
 196        P4_EVENT_EXECUTION_EVENT,
 197        P4_EVENT_REPLAY_EVENT,
 198        P4_EVENT_INSTR_RETIRED,
 199        P4_EVENT_UOPS_RETIRED,
 200        P4_EVENT_UOP_TYPE,
 201        P4_EVENT_BRANCH_RETIRED,
 202        P4_EVENT_MISPRED_BRANCH_RETIRED,
 203        P4_EVENT_X87_ASSIST,
 204        P4_EVENT_MACHINE_CLEAR,
 205        P4_EVENT_INSTR_COMPLETED,
 206};
 207
 208typedef struct {
 209        const char *name;
 210        const char *desc;
 211        unsigned int event_select;
 212        unsigned int escr_select;
 213        enum netburst_events perf_code; /* perf_event event code, enum P4_EVENTS */
 214        int allowed_escrs[MAX_ESCRS_PER_EVENT];
 215        netburst_event_mask_t event_masks[EVENT_MASK_BITS];
 216} netburst_entry_t;
 217
 218#define NETBURST_ATTR_U 0
 219#define NETBURST_ATTR_K 1
 220#define NETBURST_ATTR_C 2
 221#define NETBURST_ATTR_E 3
 222#define NETBURST_ATTR_T 4
 223
 224#define _NETBURST_ATTR_U (1 << NETBURST_ATTR_U)
 225#define _NETBURST_ATTR_K (1 << NETBURST_ATTR_K)
 226
 227#define P4_REPLAY_REAL_MASK 0x00000003
 228
 229extern int pfm_netburst_get_encoding(void *this, pfmlib_event_desc_t *e);
 230extern int pfm_netburst_get_perf_encoding(void *this, pfmlib_event_desc_t *e);
 231extern void pfm_netburst_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e);
 232
 233#endif
 234