akaros/user/perfmon/pfmlib_amd64_priv.h
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   1/*
   2 * Copyright (c) 2004-2006 Hewlett-Packard Development Company, L.P.
   3 * Contributed by Stephane Eranian <eranian@hpl.hp.com>
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
   9 * of the Software, and to permit persons to whom the Software is furnished to do so,
  10 * subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in all
  13 * copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
  16 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
  17 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  18 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
  19 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  20 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * This file is part of libpfm, a performance monitoring support library for
  23 * applications on Linux.
  24 */
  25#ifndef __PFMLIB_AMD64_PRIV_H__
  26#define __PFMLIB_AMD64_PRIV_H__
  27
  28#define AMD64_MAX_GRP           4 /* must be < 32 (int) */
  29
  30typedef struct {
  31        const char              *uname; /* unit mask name */
  32        const char              *udesc; /* event/umask description */
  33        unsigned int            ucode;  /* unit mask code */
  34        unsigned int            uflags; /* unit mask flags */
  35        unsigned int            grpid;  /* unit mask group id */
  36} amd64_umask_t;
  37
  38typedef struct {
  39        const char              *name;  /* event name */
  40        const char              *desc;  /* event description */
  41        const amd64_umask_t     *umasks;/* list of umasks */
  42        unsigned int            code;   /* event code */
  43        unsigned int            numasks;/* number of umasks */
  44        unsigned int            flags;  /* flags */
  45        unsigned int            modmsk; /* modifiers bitmask */
  46        unsigned int            ngrp;   /* number of unit masks groups */
  47} amd64_entry_t;
  48
  49/*
  50 * we keep an internal revision type to avoid
  51 * dealing with arbitrarily large pfm_pmu_t
  52 * which would not fit into the 8 bits reserved
  53 * in amd64_entry_t.flags or amd64_umask_t.flags
  54 */
  55#define AMD64_FAM10H AMD64_FAM10H_REV_B
  56typedef enum {
  57        AMD64_CPU_UN = 0,
  58        AMD64_K7,
  59        AMD64_K8_REV_B,
  60        AMD64_K8_REV_C,
  61        AMD64_K8_REV_D,
  62        AMD64_K8_REV_E,
  63        AMD64_K8_REV_F,
  64        AMD64_K8_REV_G,
  65        AMD64_FAM10H_REV_B,
  66        AMD64_FAM10H_REV_C,
  67        AMD64_FAM10H_REV_D,
  68
  69        AMD64_FAM14H_REV_B,
  70} amd64_rev_t;
  71
  72typedef struct {
  73        pfm_pmu_t               revision;
  74        int                     family; /* 0 means nothing detected yet */
  75        int                     model;
  76        int                     stepping;
  77} pfm_amd64_config_t;
  78
  79extern pfm_amd64_config_t pfm_amd64_cfg;
  80
  81/* 
  82 * flags values (bottom 8 bits only)
  83 * bits 00-07: flags
  84 * bits 08-15: from revision
  85 * bits 16-23: till revision
  86 */
  87#define AMD64_FROM_REV(rev)     ((rev)<<8)
  88#define AMD64_TILL_REV(rev)     ((rev)<<16)
  89#define AMD64_NOT_SUPP          0x1ff00
  90
  91#define AMD64_FL_NCOMBO                 0x01 /* unit mask can be combined */
  92#define AMD64_FL_IBSFE                  0x02 /* IBS fetch */
  93#define AMD64_FL_IBSOP                  0x04 /* IBS op */
  94#define AMD64_FL_DFL                    0x08 /* unit mask is default choice */
  95#define AMD64_FL_OMIT                   0x10 /* umask can be omitted */
  96
  97#define AMD64_FL_TILL_K8_REV_C          AMD64_TILL_REV(AMD64_K8_REV_C)
  98#define AMD64_FL_K8_REV_D               AMD64_FROM_REV(AMD64_K8_REV_D)
  99#define AMD64_FL_K8_REV_E               AMD64_FROM_REV(AMD64_K8_REV_E)
 100#define AMD64_FL_TILL_K8_REV_E          AMD64_TILL_REV(AMD64_K8_REV_E)
 101#define AMD64_FL_K8_REV_F               AMD64_FROM_REV(AMD64_K8_REV_F)
 102#define AMD64_FL_TILL_FAM10H_REV_B      AMD64_TILL_REV(AMD64_FAM10H_REV_B)
 103#define AMD64_FL_FAM10H_REV_C           AMD64_FROM_REV(AMD64_FAM10H_REV_C)
 104#define AMD64_FL_TILL_FAM10H_REV_C      AMD64_TILL_REV(AMD64_FAM10H_REV_C)
 105#define AMD64_FL_FAM10H_REV_D           AMD64_FROM_REV(AMD64_FAM10H_REV_D)
 106
 107#define AMD64_ATTR_K    0
 108#define AMD64_ATTR_U    1
 109#define AMD64_ATTR_E    2
 110#define AMD64_ATTR_I    3
 111#define AMD64_ATTR_C    4
 112#define AMD64_ATTR_H    5
 113#define AMD64_ATTR_G    6
 114
 115#define _AMD64_ATTR_U  (1 << AMD64_ATTR_U)
 116#define _AMD64_ATTR_K  (1 << AMD64_ATTR_K)
 117#define _AMD64_ATTR_I  (1 << AMD64_ATTR_I)
 118#define _AMD64_ATTR_E  (1 << AMD64_ATTR_E)
 119#define _AMD64_ATTR_C  (1 << AMD64_ATTR_C)
 120#define _AMD64_ATTR_H  (1 << AMD64_ATTR_H)
 121#define _AMD64_ATTR_G  (1 << AMD64_ATTR_G)
 122
 123#define AMD64_BASIC_ATTRS \
 124        (_AMD64_ATTR_I|_AMD64_ATTR_E|_AMD64_ATTR_C|_AMD64_ATTR_U|_AMD64_ATTR_K)
 125
 126#define AMD64_K8_ATTRS                  (AMD64_BASIC_ATTRS)
 127#define AMD64_FAM10H_ATTRS              (AMD64_BASIC_ATTRS|_AMD64_ATTR_H|_AMD64_ATTR_G)
 128#define AMD64_FAM12H_ATTRS              (AMD64_BASIC_ATTRS|_AMD64_ATTR_H|_AMD64_ATTR_G)
 129#define AMD64_FAM14H_ATTRS              (AMD64_BASIC_ATTRS|_AMD64_ATTR_H|_AMD64_ATTR_G)
 130#define AMD64_FAM15H_ATTRS              (AMD64_BASIC_ATTRS|_AMD64_ATTR_H|_AMD64_ATTR_G)
 131
 132#define AMD64_FAM10H_PLM        (PFM_PLM0|PFM_PLM3|PFM_PLMH)
 133#define AMD64_K7_PLM            (PFM_PLM0|PFM_PLM3)
 134
 135/*
 136 * AMD64 MSR definitions
 137 */
 138typedef union {
 139        uint64_t val;                           /* complete register value */
 140        struct {
 141                uint64_t sel_event_mask:8;      /* event mask */
 142                uint64_t sel_unit_mask:8;       /* unit mask */
 143                uint64_t sel_usr:1;             /* user level */
 144                uint64_t sel_os:1;              /* system level */
 145                uint64_t sel_edge:1;            /* edge detec */
 146                uint64_t sel_pc:1;              /* pin control */
 147                uint64_t sel_int:1;             /* enable APIC intr */
 148                uint64_t sel_res1:1;            /* reserved */
 149                uint64_t sel_en:1;              /* enable */
 150                uint64_t sel_inv:1;             /* invert counter mask */
 151                uint64_t sel_cnt_mask:8;        /* counter mask */
 152                uint64_t sel_event_mask2:4;     /* 10h only: event mask [11:8] */
 153                uint64_t sel_res2:4;            /* reserved */
 154                uint64_t sel_guest:1;           /* 10h only: guest only counter */
 155                uint64_t sel_host:1;            /* 10h only: host only counter */
 156                uint64_t sel_res3:22;           /* reserved */
 157        } perfsel;
 158
 159        struct {
 160                uint64_t maxcnt:16;
 161                uint64_t cnt:16;
 162                uint64_t lat:16;
 163                uint64_t en:1;
 164                uint64_t val:1;
 165                uint64_t comp:1;
 166                uint64_t icmiss:1;
 167                uint64_t phyaddrvalid:1;
 168                uint64_t l1tlbpgsz:2;
 169                uint64_t l1tlbmiss:1;
 170                uint64_t l2tlbmiss:1;
 171                uint64_t randen:1;
 172                uint64_t reserved:6;
 173        } ibsfetch;
 174        struct {
 175                uint64_t maxcnt:16;
 176                uint64_t reserved1:1;
 177                uint64_t en:1;
 178                uint64_t val:1;
 179                uint64_t reserved2:45;
 180        } ibsop;
 181} pfm_amd64_reg_t; /* MSR 0xc001000-0xc001003 */
 182
 183/* let's define some handy shortcuts! */
 184#define sel_event_mask  perfsel.sel_event_mask
 185#define sel_unit_mask   perfsel.sel_unit_mask
 186#define sel_usr         perfsel.sel_usr
 187#define sel_os          perfsel.sel_os
 188#define sel_edge        perfsel.sel_edge
 189#define sel_pc          perfsel.sel_pc
 190#define sel_int         perfsel.sel_int
 191#define sel_en          perfsel.sel_en
 192#define sel_inv         perfsel.sel_inv
 193#define sel_cnt_mask    perfsel.sel_cnt_mask
 194#define sel_event_mask2 perfsel.sel_event_mask2
 195#define sel_guest       perfsel.sel_guest
 196#define sel_host        perfsel.sel_host
 197
 198#define IS_FAMILY_10H(p) (((pfmlib_pmu_t *)(p))->pmu_rev >= AMD64_FAM10H)
 199#define IS_FAMILY_15H(p) (((pfmlib_pmu_t *)(p))->pmu == PFM_PMU_AMD64_FAM15H_INTERLAGOS)
 200
 201extern int pfm_amd64_get_encoding(void *this, pfmlib_event_desc_t *e);
 202extern int pfm_amd64_get_event_first(void *this);
 203extern int pfm_amd64_get_event_next(void *this, int idx);
 204extern int pfm_amd64_event_is_valid(void *this, int idx);
 205extern int pfm_amd64_get_event_attr_info(void *this, int idx, int attr_idx, pfm_event_attr_info_t *info);
 206extern int pfm_amd64_get_event_info(void *this, int idx, pfm_event_info_t *info);
 207extern int pfm_amd64_validate_table(void *this, FILE *fp);
 208extern int pfm_amd64_detect(void *this);
 209extern const pfmlib_attr_desc_t amd64_mods[];
 210extern unsigned int pfm_amd64_get_event_nattrs(void *this, int pidx);
 211extern int pfm_amd64_get_num_events(void *this);
 212
 213extern int pfm_amd64_get_perf_encoding(void *this, pfmlib_event_desc_t *e);
 214extern void pfm_amd64_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e);
 215extern void pfm_amd64_nb_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e);
 216extern int pfm_amd64_family_detect(void *this);
 217#endif /* __PFMLIB_AMD64_PRIV_H__ */
 218