akaros/user/perfmon/events/amd64_events_k7.h
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   1/*
   2 * Copyright (c) 2011 Google, Inc
   3 * Contributed by Stephane Eranian <eranian@gmail.com>
   4 *
   5 * Regenerated from previous version by:
   6 *
   7 * Copyright (c) 2006, 2007 Advanced Micro Devices, Inc.
   8 * Contributed by Ray Bryant <raybry@mpdtxmail.amd.com>
   9 * Contributed by Robert Richter <robert.richter@amd.com>
  10 * Modified for K7 by Vince Weaver <vince _at_ csl.cornell.edu>
  11 *
  12 * Permission is hereby granted, free of charge, to any person obtaining a copy
  13 * of this software and associated documentation files (the "Software"), to deal
  14 * in the Software without restriction, including without limitation the rights
  15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  16 * of the Software, and to permit persons to whom the Software is furnished to do so,
  17 * subject to the following conditions:
  18 *
  19 * The above copyright notice and this permission notice shall be included in all
  20 * copies or substantial portions of the Software.
  21 *
  22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
  23 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
  24 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  25 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
  26 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  27 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28 *
  29 * This file is part of libpfm, a performance monitoring support library for
  30 * applications on Linux.
  31 *
  32 * This file has been automatically generated.
  33 *
  34 * PMU: amd64_k7 (AMD64 K7)
  35 */
  36
  37/*
  38 * Definitions taken from "AMD Athlon Processor x86 Code Optimization Guide"
  39 * Table 11 February 2002
  40 */
  41
  42static const amd64_umask_t amd64_k7_data_cache_refills[]={
  43   { .uname  = "L2_INVALID",
  44     .udesc  = "Invalid line from L2",
  45     .ucode = 0x1,
  46   },
  47   { .uname  = "L2_SHARED",
  48     .udesc  = "Shared-state line from L2",
  49     .ucode = 0x2,
  50   },
  51   { .uname  = "L2_EXCLUSIVE",
  52     .udesc  = "Exclusive-state line from L2",
  53     .ucode = 0x4,
  54   },
  55   { .uname  = "L2_OWNED",
  56     .udesc  = "Owned-state line from L2",
  57     .ucode = 0x8,
  58   },
  59   { .uname  = "L2_MODIFIED",
  60     .udesc  = "Modified-state line from L2",
  61     .ucode = 0x10,
  62   },
  63   { .uname  = "ALL",
  64     .udesc  = "Shared, Exclusive, Owned, Modified State Refills",
  65     .ucode = 0x1f,
  66     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
  67   },
  68};
  69
  70static const amd64_umask_t amd64_k7_data_cache_refills_from_system[]={
  71   { .uname  = "INVALID",
  72     .udesc  = "Invalid",
  73     .ucode = 0x1,
  74   },
  75   { .uname  = "SHARED",
  76     .udesc  = "Shared",
  77     .ucode = 0x2,
  78   },
  79   { .uname  = "EXCLUSIVE",
  80     .udesc  = "Exclusive",
  81     .ucode = 0x4,
  82   },
  83   { .uname  = "OWNED",
  84     .udesc  = "Owned",
  85     .ucode = 0x8,
  86   },
  87   { .uname  = "MODIFIED",
  88     .udesc  = "Modified",
  89     .ucode = 0x10,
  90   },
  91   { .uname  = "ALL",
  92     .udesc  = "Invalid, Shared, Exclusive, Owned, Modified",
  93     .ucode = 0x1f,
  94     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
  95   },
  96};
  97
  98static const amd64_entry_t amd64_k7_pe[]={
  99{ .name    = "DATA_CACHE_ACCESSES",
 100  .desc    = "Data Cache Accesses",
 101  .modmsk  = AMD64_BASIC_ATTRS,
 102  .code    = 0x40,
 103},
 104{ .name    = "DATA_CACHE_MISSES",
 105  .desc    = "Data Cache Misses",
 106  .modmsk  = AMD64_BASIC_ATTRS,
 107  .code    = 0x41,
 108},
 109{ .name    = "DATA_CACHE_REFILLS",
 110  .desc    = "Data Cache Refills from L2",
 111  .modmsk  = AMD64_BASIC_ATTRS,
 112  .code    = 0x42,
 113  .numasks = LIBPFM_ARRAY_SIZE(amd64_k7_data_cache_refills),
 114  .ngrp    = 1,
 115  .umasks  = amd64_k7_data_cache_refills,
 116},
 117{ .name    = "DATA_CACHE_REFILLS_FROM_SYSTEM",
 118  .desc    = "Data Cache Refills from System",
 119  .modmsk  = AMD64_BASIC_ATTRS,
 120  .code    = 0x43,
 121  .numasks = LIBPFM_ARRAY_SIZE(amd64_k7_data_cache_refills_from_system),
 122  .ngrp    = 1,
 123  .umasks  = amd64_k7_data_cache_refills_from_system,
 124},
 125{ .name    = "DATA_CACHE_LINES_EVICTED",
 126  .desc    = "Data Cache Lines Evicted",
 127  .modmsk  = AMD64_BASIC_ATTRS,
 128  .code    = 0x44,
 129  .numasks = LIBPFM_ARRAY_SIZE(amd64_k7_data_cache_refills_from_system),
 130  .ngrp    = 1,
 131  .umasks  = amd64_k7_data_cache_refills_from_system, /* identical to actual umasks list for this event */
 132},
 133{ .name    = "L1_DTLB_MISS_AND_L2_DTLB_HIT",
 134  .desc    = "L1 DTLB Miss and L2 DTLB Hit",
 135  .modmsk  = AMD64_BASIC_ATTRS,
 136  .code    = 0x45,
 137},
 138{ .name    = "L1_DTLB_AND_L2_DTLB_MISS",
 139  .desc    = "L1 DTLB and L2 DTLB Miss",
 140  .modmsk  = AMD64_BASIC_ATTRS,
 141  .code    = 0x46,
 142},
 143{ .name    = "MISALIGNED_ACCESSES",
 144  .desc    = "Misaligned Accesses",
 145  .modmsk  = AMD64_BASIC_ATTRS,
 146  .code    = 0x47,
 147},
 148{ .name    = "CPU_CLK_UNHALTED",
 149  .desc    = "CPU Clocks not Halted",
 150  .modmsk  = AMD64_BASIC_ATTRS,
 151  .code    = 0x76,
 152},
 153{ .name    = "INSTRUCTION_CACHE_FETCHES",
 154  .desc    = "Instruction Cache Fetches",
 155  .modmsk  = AMD64_BASIC_ATTRS,
 156  .code    = 0x80,
 157},
 158{ .name    = "INSTRUCTION_CACHE_MISSES",
 159  .desc    = "Instruction Cache Misses",
 160  .modmsk  = AMD64_BASIC_ATTRS,
 161  .code    = 0x81,
 162},
 163{ .name    = "L1_ITLB_MISS_AND_L2_ITLB_HIT",
 164  .desc    = "L1 ITLB Miss and L2 ITLB Hit",
 165  .modmsk  = AMD64_BASIC_ATTRS,
 166  .code    = 0x84,
 167},
 168{ .name    = "L1_ITLB_MISS_AND_L2_ITLB_MISS",
 169  .desc    = "L1 ITLB Miss and L2 ITLB Miss",
 170  .modmsk  = AMD64_BASIC_ATTRS,
 171  .code    = 0x85,
 172},
 173{ .name    = "RETIRED_INSTRUCTIONS",
 174  .desc    = "Retired Instructions (includes exceptions, interrupts, resyncs)",
 175  .modmsk  = AMD64_BASIC_ATTRS,
 176  .code    = 0xc0,
 177},
 178{ .name    = "RETIRED_UOPS",
 179  .desc    = "Retired uops",
 180  .modmsk  = AMD64_BASIC_ATTRS,
 181  .code    = 0xc1,
 182},
 183{ .name    = "RETIRED_BRANCH_INSTRUCTIONS",
 184  .desc    = "Retired Branch Instructions",
 185  .modmsk  = AMD64_BASIC_ATTRS,
 186  .code    = 0xc2,
 187},
 188{ .name    = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS",
 189  .desc    = "Retired Mispredicted Branch Instructions",
 190  .modmsk  = AMD64_BASIC_ATTRS,
 191  .code    = 0xc3,
 192},
 193{ .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS",
 194  .desc    = "Retired Taken Branch Instructions",
 195  .modmsk  = AMD64_BASIC_ATTRS,
 196  .code    = 0xc4,
 197},
 198{ .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED",
 199  .desc    = "Retired Taken Branch Instructions Mispredicted",
 200  .modmsk  = AMD64_BASIC_ATTRS,
 201  .code    = 0xc5,
 202},
 203{ .name    = "RETIRED_FAR_CONTROL_TRANSFERS",
 204  .desc    = "Retired Far Control Transfers",
 205  .modmsk  = AMD64_BASIC_ATTRS,
 206  .code    = 0xc6,
 207},
 208{ .name    = "RETIRED_BRANCH_RESYNCS",
 209  .desc    = "Retired Branch Resyncs (only non-control transfer branches)",
 210  .modmsk  = AMD64_BASIC_ATTRS,
 211  .code    = 0xc7,
 212},
 213{ .name    = "INTERRUPTS_MASKED_CYCLES",
 214  .desc    = "Interrupts-Masked Cycles",
 215  .modmsk  = AMD64_BASIC_ATTRS,
 216  .code    = 0xcd,
 217},
 218{ .name    = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING",
 219  .desc    = "Interrupts-Masked Cycles with Interrupt Pending",
 220  .modmsk  = AMD64_BASIC_ATTRS,
 221  .code    = 0xce,
 222},
 223{ .name    = "INTERRUPTS_TAKEN",
 224  .desc    = "Interrupts Taken",
 225  .modmsk  = AMD64_BASIC_ATTRS,
 226  .code    = 0xcf,
 227},
 228};
 229