akaros/tools/compilers/gcc-glibc/gcc-4.9.2-riscv.patch
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   1diff -ruN gcc-4.9.2/config.sub gcc-4.9.2-riscv/config.sub
   2--- gcc-4.9.2/config.sub        2013-10-01 09:50:56.000000000 -0700
   3+++ gcc-4.9.2-riscv/config.sub  2014-12-02 18:04:50.107949563 -0800
   4@@ -334,6 +334,9 @@
   5        ms1)
   6                basic_machine=mt-unknown
   7                ;;
   8+       riscv)
   9+               basic_machine=riscv-ucb
  10+               ;;
  11 
  12        strongarm | thumb | xscale)
  13                basic_machine=arm-unknown
  14diff -ruN gcc-4.9.2/gcc/config/riscv/constraints.md gcc-4.9.2-riscv/gcc/config/riscv/constraints.md
  15--- gcc-4.9.2/gcc/config/riscv/constraints.md   1969-12-31 16:00:00.000000000 -0800
  16+++ gcc-4.9.2-riscv/gcc/config/riscv/constraints.md     2014-12-02 18:04:50.107949563 -0800
  17@@ -0,0 +1,121 @@
  18+;; Constraint definitions for MIPS.
  19+;; Copyright (C) 2006, 2007, 2008, 2010 Free Software Foundation, Inc.
  20+;;
  21+;; This file is part of GCC.
  22+;;
  23+;; GCC is free software; you can redistribute it and/or modify
  24+;; it under the terms of the GNU General Public License as published by
  25+;; the Free Software Foundation; either version 3, or (at your option)
  26+;; any later version.
  27+;;
  28+;; GCC is distributed in the hope that it will be useful,
  29+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  30+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  31+;; GNU General Public License for more details.
  32+;;
  33+;; You should have received a copy of the GNU General Public License
  34+;; along with GCC; see the file COPYING3.  If not see
  35+;; <http://www.gnu.org/licenses/>.
  36+
  37+;; Vector register constraints
  38+
  39+(define_register_constraint "A" "VEC_GR_REGS"
  40+  "A vector integer register.")
  41+
  42+(define_register_constraint "B" "VEC_FP_REGS"
  43+  "A vector floating-point register.")
  44+
  45+;; Register constraints
  46+
  47+(define_register_constraint "d" "GR_REGS"
  48+  "An address register.  This is equivalent to @code{r} unless
  49+   generating MIPS16 code.")
  50+
  51+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
  52+  "A floating-point register (if available).")
  53+
  54+(define_register_constraint "h" "NO_REGS"
  55+  "Formerly the @code{hi} register.  This constraint is no longer supported.")
  56+
  57+(define_register_constraint "b" "ALL_REGS"
  58+  "@internal")
  59+
  60+(define_register_constraint "j" "V1_REG"
  61+  "@internal")
  62+
  63+(define_register_constraint "z" "GR_REGS"
  64+  "A floating-point condition code register.")
  65+
  66+;; This is a normal rather than a register constraint because we can
  67+;; never use the stack pointer as a reload register.
  68+(define_constraint "ks"
  69+  "@internal"
  70+  (and (match_code "reg")
  71+       (match_test "REGNO (op) == STACK_POINTER_REGNUM")))
  72+
  73+;; Integer constraints
  74+
  75+(define_constraint "Z"
  76+  "@internal"
  77+  (and (match_code "const_int")
  78+       (match_test "1")))
  79+
  80+(define_constraint "I"
  81+  "An I-type 12-bit signed immediate."
  82+  (and (match_code "const_int")
  83+       (match_test "SMALL_OPERAND (ival)")))
  84+
  85+(define_constraint "J"
  86+  "Integer zero."
  87+  (and (match_code "const_int")
  88+       (match_test "ival == 0")))
  89+
  90+;; Floating-point constraints
  91+
  92+(define_constraint "G"
  93+  "Floating-point zero."
  94+  (and (match_code "const_double")
  95+       (match_test "op == CONST0_RTX (mode)")))
  96+
  97+;; General constraints
  98+
  99+(define_constraint "Q"
 100+  "@internal"
 101+  (match_operand 0 "const_arith_operand"))
 102+
 103+(define_memory_constraint "YR"
 104+  "An address that is held in a general-purpose register."
 105+  (and (match_code "mem")
 106+       (match_test "GET_CODE(XEXP(op,0)) == REG")))
 107+
 108+(define_memory_constraint "R"
 109+  "An address that can be used in a non-macro load or store."
 110+  (and (match_code "mem")
 111+       (match_test "mips_address_insns (XEXP (op, 0), mode, false) == 1")))
 112+
 113+(define_constraint "S"
 114+  "@internal
 115+   A constant call address."
 116+  (and (match_operand 0 "call_insn_operand")
 117+       (match_test "CONSTANT_P (op)")))
 118+
 119+(define_constraint "T"
 120+  "@internal
 121+   A constant @code{move_operand}."
 122+  (and (match_operand 0 "move_operand")
 123+       (match_test "CONSTANT_P (op)")))
 124+
 125+(define_memory_constraint "W"
 126+  "@internal
 127+   A memory address based on a member of @code{BASE_REG_CLASS}.  This is
 128+   true for all references (although it can sometimes be implicit if
 129+   @samp{!TARGET_EXPLICIT_RELOCS}).  For MIPS16, it excludes stack and
 130+   constant-pool references."
 131+  (and (match_code "mem")
 132+       (match_operand 0 "memory_operand")))
 133+
 134+(define_constraint "YG"
 135+  "@internal
 136+   A vector zero."
 137+  (and (match_code "const_vector")
 138+       (match_test "op == CONST0_RTX (mode)")))
 139diff -ruN gcc-4.9.2/gcc/config/riscv/crti.asm gcc-4.9.2-riscv/gcc/config/riscv/crti.asm
 140--- gcc-4.9.2/gcc/config/riscv/crti.asm 1969-12-31 16:00:00.000000000 -0800
 141+++ gcc-4.9.2-riscv/gcc/config/riscv/crti.asm   2014-12-02 18:04:50.107949563 -0800
 142@@ -0,0 +1,42 @@
 143+/* Copyright (C) 2001, 2002 Free Software Foundation, Inc.
 144+
 145+This file is part of GCC.
 146+
 147+GCC is free software; you can redistribute it and/or modify it under
 148+the terms of the GNU General Public License as published by the Free
 149+Software Foundation; either version 3, or (at your option) any later
 150+version.
 151+
 152+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
 153+WARRANTY; without even the implied warranty of MERCHANTABILITY or
 154+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 155+for more details.
 156+
 157+Under Section 7 of GPL version 3, you are granted additional
 158+permissions described in the GCC Runtime Library Exception, version
 159+3.1, as published by the Free Software Foundation.
 160+
 161+You should have received a copy of the GNU General Public License and
 162+a copy of the GCC Runtime Library Exception along with this program;
 163+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 164+<http://www.gnu.org/licenses/>.  */
 165+
 166+#ifdef __riscv64
 167+# define SR sd
 168+#else
 169+# define SR sw
 170+#endif
 171+
 172+       .section .init,"ax",@progbits
 173+       .globl  _init
 174+       .type   _init,@function
 175+_init:
 176+       add     sp, sp, -8
 177+       SR      ra, 0(sp)
 178+
 179+       .section .fini,"ax",@progbits
 180+       .globl  _fini
 181+       .type   _fini,@function
 182+_fini:
 183+       add     sp, sp, -8
 184+       SR      ra, 0(sp)
 185diff -ruN gcc-4.9.2/gcc/config/riscv/crtn.asm gcc-4.9.2-riscv/gcc/config/riscv/crtn.asm
 186--- gcc-4.9.2/gcc/config/riscv/crtn.asm 1969-12-31 16:00:00.000000000 -0800
 187+++ gcc-4.9.2-riscv/gcc/config/riscv/crtn.asm   2014-12-02 18:04:50.107949563 -0800
 188@@ -0,0 +1,38 @@
 189+/* Copyright (C) 2001, 2002 Free Software Foundation, Inc.
 190+
 191+This file is part of GCC.
 192+
 193+GCC is free software; you can redistribute it and/or modify it under
 194+the terms of the GNU General Public License as published by the Free
 195+Software Foundation; either version 3, or (at your option) any later
 196+version.
 197+
 198+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
 199+WARraNTY; without even the implied warranty of MERCHANTABILITY or
 200+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 201+for more details.
 202+
 203+Under Section 7 of GPL version 3, you are granted additional
 204+permissions described in the GCC Runtime Library Exception, version
 205+3.1, as published by the Free Software Foundation.
 206+
 207+You should have received a copy of the GNU General Public License and
 208+a copy of the GCC Runtime Library Exception along with this program;
 209+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 210+<http://www.gnu.org/licenses/>.  */
 211+
 212+#ifdef __riscv64
 213+# define LR ld
 214+#else
 215+# define LR lw
 216+#endif
 217+
 218+       .section .init,"ax",@progbits
 219+       LR      ra, 0(sp)
 220+       addi    sp, sp, 8
 221+       ret
 222+
 223+       .section .fini,"ax",@progbits
 224+       LR      ra, 0(sp)
 225+       addi    sp, sp, 8
 226+       ret
 227diff -ruN gcc-4.9.2/gcc/config/riscv/elf.h gcc-4.9.2-riscv/gcc/config/riscv/elf.h
 228--- gcc-4.9.2/gcc/config/riscv/elf.h    1969-12-31 16:00:00.000000000 -0800
 229+++ gcc-4.9.2-riscv/gcc/config/riscv/elf.h      2014-12-02 18:04:50.107949563 -0800
 230@@ -0,0 +1,51 @@
 231+/* Target macros for mips*-elf targets.
 232+   Copyright (C) 1994, 1997, 1999, 2000, 2002, 2003, 2004, 2007, 2010
 233+   Free Software Foundation, Inc.
 234+
 235+This file is part of GCC.
 236+
 237+GCC is free software; you can redistribute it and/or modify
 238+it under the terms of the GNU General Public License as published by
 239+the Free Software Foundation; either version 3, or (at your option)
 240+any later version.
 241+
 242+GCC is distributed in the hope that it will be useful,
 243+but WITHOUT ANY WARRANTY; without even the implied warranty of
 244+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 245+GNU General Public License for more details.
 246+
 247+You should have received a copy of the GNU General Public License
 248+along with GCC; see the file COPYING3.  If not see
 249+<http://www.gnu.org/licenses/>.  */
 250+
 251+/* MIPS assemblers don't have the usual .set foo,bar construct;
 252+   .set is used for assembler options instead.  */
 253+#undef SET_ASM_OP
 254+#define ASM_OUTPUT_DEF(FILE, LABEL1, LABEL2)                   \
 255+  do                                                           \
 256+    {                                                          \
 257+      fputc ('\t', FILE);                                      \
 258+      assemble_name (FILE, LABEL1);                            \
 259+      fputs (" = ", FILE);                                     \
 260+      assemble_name (FILE, LABEL2);                            \
 261+      fputc ('\n', FILE);                                      \
 262+    }                                                          \
 263+  while (0)
 264+
 265+#undef ASM_DECLARE_OBJECT_NAME
 266+#define ASM_DECLARE_OBJECT_NAME mips_declare_object_name
 267+
 268+#undef ASM_FINISH_DECLARE_OBJECT
 269+#define ASM_FINISH_DECLARE_OBJECT mips_finish_declare_object
 270+
 271+/* Leave the linker script to choose the appropriate libraries.  */
 272+#undef  LIB_SPEC
 273+#define LIB_SPEC ""
 274+
 275+#undef  STARTFILE_SPEC
 276+#define STARTFILE_SPEC "crti%O%s crtbegin%O%s"
 277+
 278+#undef  ENDFILE_SPEC
 279+#define ENDFILE_SPEC "crtend%O%s crtn%O%s"
 280+
 281+#define NO_IMPLICIT_EXTERN_C 1
 282diff -ruN gcc-4.9.2/gcc/config/riscv/generic.md gcc-4.9.2-riscv/gcc/config/riscv/generic.md
 283--- gcc-4.9.2/gcc/config/riscv/generic.md       1969-12-31 16:00:00.000000000 -0800
 284+++ gcc-4.9.2-riscv/gcc/config/riscv/generic.md 2014-12-02 18:04:50.107949563 -0800
 285@@ -0,0 +1,105 @@
 286+;; Generic DFA-based pipeline description for MIPS targets
 287+;;   Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc.
 288+;;
 289+;; This file is part of GCC.
 290+
 291+;; GCC is free software; you can redistribute it and/or modify it
 292+;; under the terms of the GNU General Public License as published
 293+;; by the Free Software Foundation; either version 3, or (at your
 294+;; option) any later version.
 295+
 296+;; GCC is distributed in the hope that it will be useful, but WITHOUT
 297+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 298+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 299+;; License for more details.
 300+
 301+;; You should have received a copy of the GNU General Public License
 302+;; along with GCC; see the file COPYING3.  If not see
 303+;; <http://www.gnu.org/licenses/>.
 304+
 305+
 306+;; This file is derived from the old define_function_unit description.
 307+;; Each reservation can be overridden on a processor-by-processor basis.
 308+
 309+(define_insn_reservation "generic_alu" 1
 310+  (eq_attr "type" "unknown,prefetch,prefetchx,condmove,const,arith,
 311+                  shift,slt,clz,trap,multi,nop,logical,signext,move")
 312+  "alu")
 313+
 314+(define_insn_reservation "generic_load" 3
 315+  (eq_attr "type" "load,fpload,fpidxload")
 316+  "alu")
 317+
 318+(define_insn_reservation "generic_store" 1
 319+  (eq_attr "type" "store,fpstore,fpidxstore")
 320+  "alu")
 321+
 322+(define_insn_reservation "generic_xfer" 2
 323+  (eq_attr "type" "mfc,mtc")
 324+  "alu")
 325+
 326+(define_insn_reservation "generic_branch" 1
 327+  (eq_attr "type" "branch,jump,call")
 328+  "alu")
 329+
 330+(define_insn_reservation "generic_hilo" 1
 331+  (eq_attr "type" "mfhilo,mthilo")
 332+  "imuldiv*3")
 333+
 334+(define_insn_reservation "generic_imul" 17
 335+  (eq_attr "type" "imul,imul3,imadd")
 336+  "imuldiv*17")
 337+
 338+(define_insn_reservation "generic_idiv" 38
 339+  (eq_attr "type" "idiv")
 340+  "imuldiv*38")
 341+
 342+(define_insn_reservation "generic_fcvt" 1
 343+  (eq_attr "type" "fcvt")
 344+  "alu")
 345+
 346+(define_insn_reservation "generic_fmove" 2
 347+  (eq_attr "type" "fabs,fneg,fmove")
 348+  "alu")
 349+
 350+(define_insn_reservation "generic_fcmp" 3
 351+  (eq_attr "type" "fcmp")
 352+  "alu")
 353+
 354+(define_insn_reservation "generic_fadd" 4
 355+  (eq_attr "type" "fadd")
 356+  "alu")
 357+
 358+(define_insn_reservation "generic_fmul_single" 7
 359+  (and (eq_attr "type" "fmul,fmadd")
 360+       (eq_attr "mode" "SF"))
 361+  "alu")
 362+
 363+(define_insn_reservation "generic_fmul_double" 8
 364+  (and (eq_attr "type" "fmul,fmadd")
 365+       (eq_attr "mode" "DF"))
 366+  "alu")
 367+
 368+(define_insn_reservation "generic_fdiv_single" 23
 369+  (and (eq_attr "type" "fdiv,frdiv")
 370+       (eq_attr "mode" "SF"))
 371+  "alu")
 372+
 373+(define_insn_reservation "generic_fdiv_double" 36
 374+  (and (eq_attr "type" "fdiv,frdiv")
 375+       (eq_attr "mode" "DF"))
 376+  "alu")
 377+
 378+(define_insn_reservation "generic_fsqrt_single" 54
 379+  (and (eq_attr "type" "fsqrt,frsqrt")
 380+       (eq_attr "mode" "SF"))
 381+  "alu")
 382+
 383+(define_insn_reservation "generic_fsqrt_double" 112
 384+  (and (eq_attr "type" "fsqrt,frsqrt")
 385+       (eq_attr "mode" "DF"))
 386+  "alu")
 387+
 388+(define_insn_reservation "generic_frecip_fsqrt_step" 5
 389+  (eq_attr "type" "frdiv1,frdiv2,frsqrt1,frsqrt2")
 390+  "alu")
 391diff -ruN gcc-4.9.2/gcc/config/riscv/linux64.h gcc-4.9.2-riscv/gcc/config/riscv/linux64.h
 392--- gcc-4.9.2/gcc/config/riscv/linux64.h        1969-12-31 16:00:00.000000000 -0800
 393+++ gcc-4.9.2-riscv/gcc/config/riscv/linux64.h  2014-12-02 18:04:50.107949563 -0800
 394@@ -0,0 +1,58 @@
 395+/* Definitions for MIPS running Linux-based GNU systems with ELF format
 396+   using n32/64 abi.
 397+   Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2011
 398+   Free Software Foundation, Inc.
 399+
 400+This file is part of GCC.
 401+
 402+GCC is free software; you can redistribute it and/or modify
 403+it under the terms of the GNU General Public License as published by
 404+the Free Software Foundation; either version 3, or (at your option)
 405+any later version.
 406+
 407+GCC is distributed in the hope that it will be useful,
 408+but WITHOUT ANY WARRANTY; without even the implied warranty of
 409+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 410+GNU General Public License for more details.
 411+
 412+You should have received a copy of the GNU General Public License
 413+along with GCC; see the file COPYING3.  If not see
 414+<http://www.gnu.org/licenses/>.  */
 415+
 416+/* Force the default endianness and ABI flags onto the command line
 417+   in order to make the other specs easier to write.  */
 418+#undef DRIVER_SELF_SPECS
 419+#define DRIVER_SELF_SPECS \
 420+  LINUX_DRIVER_SELF_SPECS \
 421+  " %{!EB:%{!EL:%(endian_spec)}}" \
 422+  " %{" OPT_ARCH32 ": -m32} %{" OPT_ARCH64 ": -m64}" \
 423+
 424+#undef LIB_SPEC
 425+#define LIB_SPEC "\
 426+%{pthread:-lpthread} \
 427+%{shared:-lc} \
 428+%{!shared: \
 429+  %{profile:-lc_p} %{!profile:-lc}}"
 430+
 431+#define GLIBC_DYNAMIC_LINKER32 "/lib32/ld.so.1"
 432+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld.so.1"
 433+
 434+#undef LINK_SPEC
 435+#define LINK_SPEC "\
 436+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
 437+%{shared} \
 438+ %(endian_spec) \
 439+  %{!shared: \
 440+    %{!static: \
 441+      %{rdynamic:-export-dynamic} \
 442+      %{" OPT_ARCH64 ": -dynamic-linker " LINUX_DYNAMIC_LINKER64 "} \
 443+      %{" OPT_ARCH32 ": -dynamic-linker " LINUX_DYNAMIC_LINKER32 "}} \
 444+    %{static:-static}} \
 445+%{" OPT_ARCH64 ":-melf64%{EB:b}%{EL:l}riscv} \
 446+%{" OPT_ARCH32 ":-melf32%{EB:b}%{EL:l}riscv}"
 447+
 448+/* GNU/Linux doesn't use the same floating-point format that IRIX uses
 449+   for long double.  There's no need to override this here, since
 450+   ieee_quad_format is the default, but let's put this here to make
 451+   sure nobody thinks we just forgot to set it to something else.  */
 452+#define MIPS_TFMODE_FORMAT mips_quad_format
 453diff -ruN gcc-4.9.2/gcc/config/riscv/linux.h gcc-4.9.2-riscv/gcc/config/riscv/linux.h
 454--- gcc-4.9.2/gcc/config/riscv/linux.h  1969-12-31 16:00:00.000000000 -0800
 455+++ gcc-4.9.2-riscv/gcc/config/riscv/linux.h    2014-12-02 18:04:50.107949563 -0800
 456@@ -0,0 +1,115 @@
 457+/* Definitions for MIPS running Linux-based GNU systems with ELF format.
 458+   Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
 459+   2007, 2008, 2010, 2011 Free Software Foundation, Inc.
 460+
 461+This file is part of GCC.
 462+
 463+GCC is free software; you can redistribute it and/or modify
 464+it under the terms of the GNU General Public License as published by
 465+the Free Software Foundation; either version 3, or (at your option)
 466+any later version.
 467+
 468+GCC is distributed in the hope that it will be useful,
 469+but WITHOUT ANY WARRANTY; without even the implied warranty of
 470+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 471+GNU General Public License for more details.
 472+
 473+You should have received a copy of the GNU General Public License
 474+along with GCC; see the file COPYING3.  If not see
 475+<http://www.gnu.org/licenses/>.  */
 476+
 477+#undef WCHAR_TYPE
 478+#define WCHAR_TYPE "int"
 479+
 480+#undef WCHAR_TYPE_SIZE
 481+#define WCHAR_TYPE_SIZE 32
 482+
 483+#undef ASM_DECLARE_OBJECT_NAME
 484+#define ASM_DECLARE_OBJECT_NAME mips_declare_object_name
 485+
 486+#undef TARGET_VERSION
 487+#if TARGET_ENDIAN_DEFAULT == 0
 488+#define TARGET_VERSION fprintf (stderr, " (RISC-V LE Linux/ELF)");
 489+#else
 490+#define TARGET_VERSION fprintf (stderr, " (RISC-V BE Linux/ELF)");
 491+#endif
 492+
 493+/* If we don't set MASK_ABICALLS, we can't default to PIC.  */
 494+#undef TARGET_DEFAULT
 495+#define TARGET_DEFAULT MASK_ABICALLS
 496+
 497+#define TARGET_OS_CPP_BUILTINS()                               \
 498+  do {                                                         \
 499+    LINUX_TARGET_OS_CPP_BUILTINS();                            \
 500+    /* The GNU C++ standard library requires this.  */         \
 501+    if (c_dialect_cxx ())                                      \
 502+      builtin_define ("_GNU_SOURCE");                          \
 503+  } while (0)
 504+
 505+#undef SUBTARGET_CPP_SPEC
 506+#define SUBTARGET_CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
 507+
 508+/* A standard GNU/Linux mapping.  On most targets, it is included in
 509+   CC1_SPEC itself by config/linux.h, but mips.h overrides CC1_SPEC
 510+   and provides this hook instead.  */
 511+#undef SUBTARGET_CC1_SPEC
 512+#define SUBTARGET_CC1_SPEC "%{profile:-p}"
 513+
 514+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 515+
 516+/* Borrowed from sparc/linux.h */
 517+#undef LINK_SPEC
 518+#define LINK_SPEC \
 519+ "%(endian_spec) \
 520+  %{shared:-shared} \
 521+  %{!shared: \
 522+    %{!static: \
 523+      %{rdynamic:-export-dynamic} \
 524+      -dynamic-linker " LINUX_DYNAMIC_LINKER "} \
 525+      %{static:-static}}"
 526+
 527+/* The MIPS assembler has different syntax for .set. We set it to
 528+   .dummy to trap any errors.  */
 529+#undef SET_ASM_OP
 530+#define SET_ASM_OP "\t.dummy\t"
 531+
 532+#undef ASM_OUTPUT_DEF
 533+#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)                             \
 534+ do {                                                                  \
 535+       fputc ( '\t', FILE);                                            \
 536+       assemble_name (FILE, LABEL1);                                   \
 537+       fputs ( " = ", FILE);                                           \
 538+       assemble_name (FILE, LABEL2);                                   \
 539+       fputc ( '\n', FILE);                                            \
 540+ } while (0)
 541+
 542+/* The glibc _mcount stub will save $v0 for us.  Don't mess with saving
 543+   it, since ASM_OUTPUT_REG_PUSH/ASM_OUTPUT_REG_POP do not work in the
 544+   presence of $gp-relative calls.  */
 545+#undef ASM_OUTPUT_REG_PUSH
 546+#undef ASM_OUTPUT_REG_POP
 547+
 548+#undef LIB_SPEC
 549+#define LIB_SPEC "\
 550+%{pthread:-lpthread} \
 551+%{shared:-lc} \
 552+%{!shared: \
 553+  %{profile:-lc_p} %{!profile:-lc}}"
 554+
 555+#define MD_UNWIND_SUPPORT "config/riscv/linux-unwind.h"
 556+
 557+/* -march=native handling only makes sense with compiler running on
 558+   a RISC-V machine.  */
 559+#define MARCH_MTUNE_NATIVE_SPECS ""
 560+
 561+#define LINUX_DRIVER_SELF_SPECS \
 562+  MARCH_MTUNE_NATIVE_SPECS
 563+
 564+#undef DRIVER_SELF_SPECS
 565+#define DRIVER_SELF_SPECS \
 566+  LINUX_DRIVER_SELF_SPECS
 567+
 568+/* Similar to standard Linux, but adding -ffast-math support.  */
 569+#undef  ENDFILE_SPEC
 570+#define ENDFILE_SPEC \
 571+   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
 572diff -ruN gcc-4.9.2/gcc/config/riscv/linux-unwind.h gcc-4.9.2-riscv/gcc/config/riscv/linux-unwind.h
 573--- gcc-4.9.2/gcc/config/riscv/linux-unwind.h   1969-12-31 16:00:00.000000000 -0800
 574+++ gcc-4.9.2-riscv/gcc/config/riscv/linux-unwind.h     2014-12-02 18:04:50.107949563 -0800
 575@@ -0,0 +1,120 @@
 576+/* DWARF2 EH unwinding support for MIPS Linux.
 577+   Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
 578+
 579+This file is part of GCC.
 580+
 581+GCC is free software; you can redistribute it and/or modify
 582+it under the terms of the GNU General Public License as published by
 583+the Free Software Foundation; either version 3, or (at your option)
 584+any later version.
 585+
 586+GCC is distributed in the hope that it will be useful,
 587+but WITHOUT ANY WARRANTY; without even the implied warranty of
 588+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 589+GNU General Public License for more details.
 590+
 591+Under Section 7 of GPL version 3, you are granted additional
 592+permissions described in the GCC Runtime Library Exception, version
 593+3.1, as published by the Free Software Foundation.
 594+
 595+You should have received a copy of the GNU General Public License and
 596+a copy of the GCC Runtime Library Exception along with this program;
 597+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 598+<http://www.gnu.org/licenses/>.  */
 599+
 600+#ifndef inhibit_libc
 601+/* Do code reading to identify a signal frame, and set the frame
 602+   state data appropriately.  See unwind-dw2.c for the structs.  */
 603+
 604+#include <signal.h>
 605+#include <asm/unistd.h>
 606+
 607+/* The third parameter to the signal handler points to something with
 608+ * this structure defined in asm/ucontext.h, but the name clashes with
 609+ * struct ucontext from sys/ucontext.h so this private copy is used.  */
 610+typedef struct _sig_ucontext {
 611+    unsigned long         uc_flags;
 612+    struct _sig_ucontext  *uc_link;
 613+    stack_t               uc_stack;
 614+    struct sigcontext uc_mcontext;
 615+    sigset_t      uc_sigmask;
 616+} _sig_ucontext_t;
 617+
 618+#define MD_FALLBACK_FRAME_STATE_FOR mips_fallback_frame_state
 619+
 620+static _Unwind_Reason_Code
 621+mips_fallback_frame_state (struct _Unwind_Context *context,
 622+                          _Unwind_FrameState *fs)
 623+{
 624+  u_int32_t *pc = (u_int32_t *) context->ra;
 625+  struct sigcontext *sc;
 626+  _Unwind_Ptr new_cfa, reg_offset;
 627+  int i;
 628+
 629+  /* 24021061 li v0, 0x1061 (rt_sigreturn)*/
 630+  /* 0000000c syscall    */
 631+  /*    or */
 632+  /* 24021017 li v0, 0x1017 (sigreturn) */
 633+  /* 0000000c syscall  */
 634+  if (pc[1] != 0x0000000c)
 635+    return _URC_END_OF_STACK;
 636+#if _MIPS_SIM == _ABIO32
 637+  if (pc[0] == (0x24020000 | __NR_sigreturn))
 638+    {
 639+      struct sigframe {
 640+       u_int32_t ass[4];  /* Argument save space for o32.  */
 641+       u_int32_t trampoline[2];
 642+       struct sigcontext sigctx;
 643+      } *rt_ = context->cfa;
 644+      sc = &rt_->sigctx;
 645+    }
 646+  else
 647+#endif
 648+  if (pc[0] == (0x24020000 | __NR_rt_sigreturn))
 649+    {
 650+      struct rt_sigframe {
 651+       u_int32_t ass[4];  /* Argument save space for o32.  */
 652+       u_int32_t trampoline[2];
 653+       struct siginfo info;
 654+       _sig_ucontext_t uc;
 655+      } *rt_ = context->cfa;
 656+      sc = &rt_->uc.uc_mcontext;
 657+    }
 658+  else
 659+    return _URC_END_OF_STACK;
 660+
 661+  new_cfa = (_Unwind_Ptr) sc;
 662+  fs->regs.cfa_how = CFA_REG_OFFSET;
 663+  fs->regs.cfa_reg = STACK_POINTER_REGNUM;
 664+  fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa;
 665+
 666+  /* On o32 Linux, the register save slots in the sigcontext are
 667+     eight bytes.  We need the lower half of each register slot,
 668+     so slide our view of the structure back four bytes.  */
 669+#if _MIPS_SIM == _ABIO32 && defined __MIPSEB__
 670+  reg_offset = 4;
 671+#else
 672+  reg_offset = 0;
 673+#endif
 674+
 675+  for (i = 0; i < 32; i++) {
 676+    fs->regs.reg[i].how = REG_SAVED_OFFSET;
 677+    fs->regs.reg[i].loc.offset
 678+      = (_Unwind_Ptr)&(sc->sc_regs[i]) + reg_offset - new_cfa;
 679+  }
 680+  /* "PC & -2" points to the faulting instruction, but the unwind code
 681+     searches for "(ADDR & -2) - 1".  (See MASK_RETURN_ADDR for the source
 682+     of the -2 mask.)  Adding 2 here ensures that "(ADDR & -2) - 1" is the
 683+     address of the second byte of the faulting instruction.
 684+
 685+     Note that setting fs->signal_frame would not work.  As the comment
 686+     above MASK_RETURN_ADDR explains, MIPS unwinders must earch for an
 687+     odd-valued address.  */
 688+  fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].how = REG_SAVED_VAL_OFFSET;
 689+  fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].loc.offset
 690+    = (_Unwind_Ptr)(sc->sc_pc) + 2 - new_cfa;
 691+  fs->retaddr_column = DWARF_ALT_FRAME_RETURN_COLUMN;
 692+
 693+  return _URC_NO_REASON;
 694+}
 695+#endif
 696diff -ruN gcc-4.9.2/gcc/config/riscv/opcode-riscv.h gcc-4.9.2-riscv/gcc/config/riscv/opcode-riscv.h
 697--- gcc-4.9.2/gcc/config/riscv/opcode-riscv.h   1969-12-31 16:00:00.000000000 -0800
 698+++ gcc-4.9.2-riscv/gcc/config/riscv/opcode-riscv.h     2014-12-02 18:04:50.107949563 -0800
 699@@ -0,0 +1,253 @@
 700+/* riscv.h.  RISC-V opcode list for GDB, the GNU debugger.
 701+   Copyright 2011
 702+   Free Software Foundation, Inc.
 703+   Contributed by Andrew Waterman 
 704+
 705+This file is part of GDB, GAS, and the GNU binutils.
 706+
 707+GDB, GAS, and the GNU binutils are free software; you can redistribute
 708+them and/or modify them under the terms of the GNU General Public
 709+License as published by the Free Software Foundation; either version
 710+1, or (at your option) any later version.
 711+
 712+GDB, GAS, and the GNU binutils are distributed in the hope that they
 713+will be useful, but WITHOUT ANY WARRANTY; without even the implied
 714+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
 715+the GNU General Public License for more details.
 716+
 717+You should have received a copy of the GNU General Public License
 718+along with this file; see the file COPYING.  If not, write to the Free
 719+Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 720+
 721+#ifndef _RISCV_H_
 722+#define _RISCV_H_
 723+
 724+/* RVC fields */
 725+
 726+#define OP_MASK_COP            0x1f
 727+#define OP_SH_COP              0
 728+#define OP_MASK_CRD            0x1f
 729+#define OP_SH_CRD              5
 730+#define OP_MASK_CRS2   0x1f
 731+#define OP_SH_CRS2     5
 732+#define OP_MASK_CRS1   0x1f
 733+#define OP_SH_CRS1     10
 734+#define OP_MASK_CRDS           0x7
 735+#define OP_SH_CRDS             13
 736+#define OP_MASK_CRS2S  0x7
 737+#define OP_SH_CRS2S    13
 738+#define OP_MASK_CRS2BS 0x7
 739+#define OP_SH_CRS2BS   5
 740+#define OP_MASK_CRS1S  0x7
 741+#define OP_SH_CRS1S    10
 742+#define OP_MASK_CIMM6  0x3f
 743+#define OP_SH_CIMM6    10
 744+#define OP_MASK_CIMM5  0x1f
 745+#define OP_SH_CIMM5    5
 746+#define OP_MASK_CIMM10 0x3ff
 747+#define OP_SH_CIMM10   5
 748+
 749+static const char rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
 750+#define rvc_rd_regmap rvc_rs1_regmap
 751+#define rvc_rs2b_regmap rvc_rs1_regmap
 752+static const char rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
 753+
 754+#define RVC_JUMP_BITS 10
 755+#define RVC_JUMP_ALIGN_BITS 1
 756+#define RVC_JUMP_ALIGN (1 << RVC_JUMP_ALIGN_BITS)
 757+#define RVC_JUMP_REACH ((1ULL<<RVC_JUMP_BITS)*RVC_JUMP_ALIGN)
 758+
 759+#define RVC_BRANCH_BITS 5
 760+#define RVC_BRANCH_ALIGN_BITS RVC_JUMP_ALIGN_BITS
 761+#define RVC_BRANCH_ALIGN (1 << RVC_BRANCH_ALIGN_BITS)
 762+#define RVC_BRANCH_REACH ((1ULL<<RVC_BRANCH_BITS)*RVC_BRANCH_ALIGN)
 763+
 764+#define RISCV_JTYPE(insn, target) \
 765+  ((MATCH_ ## insn) | (((target) & ((1<<RISCV_JUMP_BITS)-1)) << OP_SH_TARGET))
 766+#define RISCV_LTYPE(insn, rd, bigimm) \
 767+  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | (((bigimm) & ((1<<RISCV_BIGIMM_BITS)-1)) << OP_SH_BIGIMMEDIATE))
 768+#define RISCV_ITYPE(insn, rd, rs1, imm) \
 769+  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS) | (((imm) & (RISCV_IMM_REACH-1)) << OP_SH_IMMEDIATE))
 770+#define RISCV_RTYPE(insn, rd, rs1, rs2) \
 771+  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS) | ((rs2) << OP_SH_RT))
 772+
 773+#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
 774+
 775+#define RISCV_JUMP_TARGET(address) ((address) >> RISCV_JUMP_ALIGN_BITS)
 776+#define RISCV_CONST_HIGH_PART(VALUE) \
 777+  (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
 778+#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
 779+#define RISCV_LUI_HIGH_PART(VALUE) (RISCV_CONST_HIGH_PART(VALUE) >> RISCV_IMM_BITS)
 780+
 781+/* RV fields */
 782+
 783+#define OP_MASK_OP             0x7f
 784+#define OP_SH_OP               0
 785+#define OP_MASK_RT             0x1f
 786+#define OP_SH_RT               17
 787+#define OP_MASK_FT             0x1f
 788+#define OP_SH_FT               17
 789+#define OP_MASK_RS             0x1f
 790+#define OP_SH_RS               22
 791+#define OP_MASK_FS             0x1f
 792+#define OP_SH_FS               22
 793+#define OP_MASK_FR             0x1f
 794+#define OP_SH_FR               12
 795+#define OP_MASK_RD             0x1f
 796+#define OP_SH_RD               27
 797+#define OP_MASK_FD             0x1f
 798+#define OP_SH_FD               27
 799+#define OP_MASK_SHAMT          0x3f
 800+#define OP_SH_SHAMT            10
 801+#define OP_MASK_SHAMTW         0x1f
 802+#define OP_SH_SHAMTW   10
 803+#define OP_MASK_RM             0x7
 804+#define OP_SH_RM       9
 805+
 806+static const char * const riscv_rm[8] =
 807+  { "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" };
 808+
 809+#define OP_MASK_VRD            0x1f
 810+#define OP_SH_VRD              27
 811+#define OP_MASK_VRS            0x1f
 812+#define OP_SH_VRS              22
 813+#define OP_MASK_VRT            0x1f
 814+#define OP_SH_VRT              17
 815+#define OP_MASK_VRR            0x1f
 816+#define OP_SH_VRR              12
 817+
 818+#define OP_MASK_VFD            0x1f
 819+#define OP_SH_VFD              27
 820+#define OP_MASK_VFS            0x1f
 821+#define OP_SH_VFS              22
 822+#define OP_MASK_VFT            0x1f
 823+#define OP_SH_VFT              17
 824+#define OP_MASK_VFR            0x1f
 825+#define OP_SH_VFR              12
 826+
 827+#define OP_MASK_IMMNGPR         0x3f
 828+#define OP_SH_IMMNGPR           10
 829+#define OP_MASK_IMMNFPR         0x3f
 830+#define OP_SH_IMMNFPR           16
 831+#define OP_MASK_IMMSEGNELM      0x1f
 832+#define OP_SH_IMMSEGNELM        17
 833+#define OP_MASK_IMMSEGSTNELM    0x1f
 834+#define OP_SH_IMMSEGSTNELM      12
 835+
 836+#define LINK_REG 1
 837+
 838+#define RISCV_JUMP_BITS 25
 839+#define RISCV_JUMP_ALIGN_BITS 1
 840+#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
 841+#define RISCV_JUMP_REACH ((1ULL<<RISCV_JUMP_BITS)*RISCV_JUMP_ALIGN)
 842+
 843+#define OP_MASK_TARGET         ((1<<RISCV_JUMP_BITS)-1)
 844+#define OP_SH_TARGET           7
 845+
 846+#define RISCV_IMM_BITS 12
 847+#define RISCV_IMMLO_BITS 7
 848+#define RISCV_IMMHI_BITS (RISCV_IMM_BITS - RISCV_IMMLO_BITS)
 849+#define RISCV_BIGIMM_BITS (32-RISCV_IMM_BITS)
 850+#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
 851+#define RISCV_BIGIMM_REACH (1LL<<RISCV_BIGIMM_BITS)
 852+#define RISCV_BRANCH_BITS RISCV_IMM_BITS
 853+#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
 854+#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
 855+#define RISCV_BRANCH_REACH (RISCV_IMM_REACH*RISCV_BRANCH_ALIGN)
 856+
 857+#define OP_MASK_BIGIMMEDIATE   ((1<<RISCV_BIGIMM_BITS)-1)
 858+#define OP_SH_BIGIMMEDIATE             7
 859+#define OP_MASK_IMMEDIATE      ((1<<RISCV_IMM_BITS)-1)
 860+#define OP_SH_IMMEDIATE                10
 861+#define OP_MASK_IMMLO ((1<<RISCV_IMMLO_BITS)-1)
 862+#define OP_SH_IMMLO   10
 863+#define OP_MASK_IMMHI ((1<<(RISCV_IMM_BITS-RISCV_IMMLO_BITS))-1)
 864+#define OP_SH_IMMHI   27
 865+
 866+#include "riscv-opc.h"
 867+
 868+/* This structure holds information for a particular instruction.  */
 869+
 870+struct riscv_opcode
 871+{
 872+  /* The name of the instruction.  */
 873+  const char *name;
 874+  /* A string describing the arguments for this instruction.  */
 875+  const char *args;
 876+  /* The basic opcode for the instruction.  When assembling, this
 877+     opcode is modified by the arguments to produce the actual opcode
 878+     that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 879+  unsigned long match;
 880+  /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 881+     relevant portions of the opcode when disassembling.  If the
 882+     actual opcode anded with the match field equals the opcode field,
 883+     then we have found the correct instruction.  If pinfo is
 884+     INSN_MACRO, then this field is the macro identifier.  */
 885+  unsigned long mask;
 886+  /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 887+     of bits describing the instruction, notably any relevant hazard
 888+     information.  */
 889+  unsigned long pinfo;
 890+};
 891+
 892+#define INSN_WRITE_GPR_D            0x00000001
 893+#define INSN_WRITE_GPR_RA           0x00000004
 894+#define INSN_WRITE_FPR_D            0x00000008
 895+#define INSN_READ_GPR_S             0x00000040
 896+#define INSN_READ_GPR_T             0x00000080
 897+#define INSN_READ_FPR_S             0x00000100
 898+#define INSN_READ_FPR_T             0x00000200
 899+#define INSN_READ_FPR_R                    0x00000400
 900+/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
 901+#define        INSN_ALIAS                  0x00001000
 902+/* Instruction is actually a macro.  It should be ignored by the
 903+   disassembler, and requires special treatment by the assembler.  */
 904+#define INSN_MACRO                  0xffffffff
 905+
 906+/* These are the bits which may be set in the pinfo2 field of an
 907+   instruction. */
 908+
 909+/* MIPS ISA defines, use instead of hardcoding ISA level.  */
 910+
 911+#define       ISA_UNKNOWN     0               /* Gas internal use.  */
 912+#define       ISA_RV32        1
 913+#define       ISA_RV64        2
 914+
 915+#define CPU_UNKNOWN    0
 916+#define CPU_ROCKET32 132
 917+#define CPU_ROCKET64 164
 918+
 919+/* This is a list of macro expanded instructions.
 920+
 921+   _I appended means immediate
 922+   _A appended means address
 923+   _AB appended means address with base register
 924+   _D appended means 64 bit floating point constant
 925+   _S appended means 32 bit floating point constant.  */
 926+
 927+enum
 928+{
 929+  M_LA_AB,
 930+  M_J,
 931+  M_LI,
 932+  M_NUM_MACROS
 933+};
 934+
 935+
 936+/* The order of overloaded instructions matters.  Label arguments and
 937+   register arguments look the same. Instructions that can have either
 938+   for arguments must apear in the correct order in this table for the
 939+   assembler to pick the right one. In other words, entries with
 940+   immediate operands must apear after the same instruction with
 941+   registers.
 942+
 943+   Many instructions are short hand for other instructions (i.e., The
 944+   jal <register> instruction is short for jalr <register>).  */
 945+
 946+extern const struct riscv_opcode riscv_builtin_opcodes[];
 947+extern const int bfd_riscv_num_builtin_opcodes;
 948+extern struct riscv_opcode *riscv_opcodes;
 949+extern int bfd_riscv_num_opcodes;
 950+#define NUMOPCODES bfd_riscv_num_opcodes
 951+
 952+#endif /* _MIPS_H_ */
 953diff -ruN gcc-4.9.2/gcc/config/riscv/predicates.md gcc-4.9.2-riscv/gcc/config/riscv/predicates.md
 954--- gcc-4.9.2/gcc/config/riscv/predicates.md    1969-12-31 16:00:00.000000000 -0800
 955+++ gcc-4.9.2-riscv/gcc/config/riscv/predicates.md      2014-12-02 18:04:50.107949563 -0800
 956@@ -0,0 +1,191 @@
 957+;; Predicate definitions for MIPS.
 958+;; Copyright (C) 2004, 2007, 2008 Free Software Foundation, Inc.
 959+;;
 960+;; This file is part of GCC.
 961+;;
 962+;; GCC is free software; you can redistribute it and/or modify
 963+;; it under the terms of the GNU General Public License as published by
 964+;; the Free Software Foundation; either version 3, or (at your option)
 965+;; any later version.
 966+;;
 967+;; GCC is distributed in the hope that it will be useful,
 968+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
 969+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 970+;; GNU General Public License for more details.
 971+;;
 972+;; You should have received a copy of the GNU General Public License
 973+;; along with GCC; see the file COPYING3.  If not see
 974+;; <http://www.gnu.org/licenses/>.
 975+
 976+(define_predicate "const_arith_operand"
 977+  (and (match_code "const_int")
 978+       (match_test "SMALL_OPERAND (INTVAL (op))")))
 979+
 980+(define_predicate "arith_operand"
 981+  (ior (match_operand 0 "const_arith_operand")
 982+       (match_operand 0 "register_operand")))
 983+
 984+(define_predicate "sle_operand"
 985+  (and (match_code "const_int")
 986+       (match_test "SMALL_OPERAND (INTVAL (op) + 1)")))
 987+
 988+(define_predicate "sleu_operand"
 989+  (and (match_operand 0 "sle_operand")
 990+       (match_test "INTVAL (op) + 1 != 0")))
 991+
 992+(define_predicate "const_0_operand"
 993+  (and (match_code "const_int,const_double,const_vector")
 994+       (match_test "op == CONST0_RTX (GET_MODE (op))")))
 995+
 996+(define_predicate "reg_or_0_operand"
 997+  (ior (match_operand 0 "const_0_operand")
 998+       (match_operand 0 "register_operand")))
 999+
1000+(define_predicate "const_1_operand"
1001+  (and (match_code "const_int,const_double,const_vector")
1002+       (match_test "op == CONST1_RTX (GET_MODE (op))")))
1003+
1004+(define_predicate "reg_or_1_operand"
1005+  (ior (match_operand 0 "const_1_operand")
1006+       (match_operand 0 "register_operand")))
1007+
1008+;; This is used for indexing into vectors, and hence only accepts const_int.
1009+(define_predicate "const_0_or_1_operand"
1010+  (and (match_code "const_int")
1011+       (ior (match_test "op == CONST0_RTX (GET_MODE (op))")
1012+           (match_test "op == CONST1_RTX (GET_MODE (op))"))))
1013+
1014+(define_special_predicate "pc_or_label_operand"
1015+  (match_code "pc,label_ref"))
1016+
1017+(define_predicate "const_call_insn_operand"
1018+  (match_code "const,symbol_ref,label_ref")
1019+{
1020+  enum mips_symbol_type symbol_type;
1021+
1022+  if (!mips_symbolic_constant_p (op, &symbol_type))
1023+    return false;
1024+
1025+  if (symbol_type == SYMBOL_ABSOLUTE)
1026+    {
1027+      if (GET_CODE (op) == SYMBOL_REF)
1028+       {
1029+         if (flag_pic && !riscv_symbol_binds_local_p (op))
1030+           return false;
1031+         if (SYMBOL_REF_LONG_CALL_P (op))
1032+           return false;
1033+       }
1034+      return true;
1035+    }
1036+
1037+  return false;
1038+})
1039+
1040+(define_predicate "call_insn_operand"
1041+  (ior (match_operand 0 "const_call_insn_operand")
1042+       (match_operand 0 "register_operand")))
1043+
1044+;; A legitimate CONST_INT operand that takes more than one instruction
1045+;; to load.
1046+(define_predicate "splittable_const_int_operand"
1047+  (match_code "const_int")
1048+{
1049+  /* Don't handle multi-word moves this way; we don't want to introduce
1050+     the individual word-mode moves until after reload.  */
1051+  if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1052+    return false;
1053+
1054+  /* Otherwise check whether the constant can be loaded in a single
1055+     instruction.  */
1056+  return !LUI_INT (op) && !SMALL_INT (op);
1057+})
1058+
1059+(define_predicate "move_operand"
1060+  (match_operand 0 "general_operand")
1061+{
1062+  enum mips_symbol_type symbol_type;
1063+
1064+  /* The thinking here is as follows:
1065+
1066+     (1) The move expanders should split complex load sequences into
1067+        individual instructions.  Those individual instructions can
1068+        then be optimized by all rtl passes.
1069+
1070+     (2) The target of pre-reload load sequences should not be used
1071+        to store temporary results.  If the target register is only
1072+        assigned one value, reload can rematerialize that value
1073+        on demand, rather than spill it to the stack.
1074+
1075+     (3) If we allowed pre-reload passes like combine and cse to recreate
1076+        complex load sequences, we would want to be able to split the
1077+        sequences before reload as well, so that the pre-reload scheduler
1078+        can see the individual instructions.  This falls foul of (2);
1079+        the splitter would be forced to reuse the target register for
1080+        intermediate results.
1081+
1082+     (4) We want to define complex load splitters for combine.  These
1083+        splitters can request a temporary scratch register, which avoids
1084+        the problem in (2).  They allow things like:
1085+
1086+             (set (reg T1) (high SYM))
1087+             (set (reg T2) (low (reg T1) SYM))
1088+             (set (reg X) (plus (reg T2) (const_int OFFSET)))
1089+
1090+        to be combined into:
1091+
1092+             (set (reg T3) (high SYM+OFFSET))
1093+             (set (reg X) (lo_sum (reg T3) SYM+OFFSET))
1094+
1095+        if T2 is only used this once.  */
1096+  switch (GET_CODE (op))
1097+    {
1098+    case CONST_INT:
1099+      return !splittable_const_int_operand (op, mode);
1100+
1101+    case CONST:
1102+    case SYMBOL_REF:
1103+    case LABEL_REF:
1104+      return (mips_symbolic_constant_p (op, &symbol_type)
1105+             && !mips_split_p[symbol_type]);
1106+
1107+    case HIGH:
1108+      op = XEXP (op, 0);
1109+      return mips_symbolic_constant_p (op, &symbol_type);
1110+
1111+    default:
1112+      return true;
1113+    }
1114+})
1115+
1116+(define_predicate "consttable_operand"
1117+  (match_test "CONSTANT_P (op)"))
1118+
1119+(define_predicate "symbolic_operand"
1120+  (match_code "const,symbol_ref,label_ref")
1121+{
1122+  enum mips_symbol_type type;
1123+  return mips_symbolic_constant_p (op, &type);
1124+})
1125+
1126+(define_predicate "absolute_symbolic_operand"
1127+  (match_code "const,symbol_ref,label_ref")
1128+{
1129+  enum mips_symbol_type type;
1130+  return (mips_symbolic_constant_p (op, &type)
1131+         && type == SYMBOL_ABSOLUTE);
1132+})
1133+
1134+(define_predicate "symbol_ref_operand"
1135+  (match_code "symbol_ref"))
1136+
1137+(define_predicate "equality_operator"
1138+  (match_code "eq,ne"))
1139+
1140+(define_predicate "order_operator"
1141+  (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu"))
1142+
1143+(define_predicate "fp_order_operator"
1144+  (match_code "eq,lt,le,gt,ge"))
1145+
1146+(define_predicate "fp_unorder_operator"
1147+  (match_code "ordered,unordered"))
1148diff -ruN gcc-4.9.2/gcc/config/riscv/riscv.c gcc-4.9.2-riscv/gcc/config/riscv/riscv.c
1149--- gcc-4.9.2/gcc/config/riscv/riscv.c  1969-12-31 16:00:00.000000000 -0800
1150+++ gcc-4.9.2-riscv/gcc/config/riscv/riscv.c    2014-12-02 18:04:50.111949590 -0800
1151@@ -0,0 +1,5958 @@
1152+/* Subroutines used for MIPS code generation.
1153+   Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
1154+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
1155+   2011
1156+   Free Software Foundation, Inc.
1157+   Contributed by A. Lichnewsky, lich@inria.inria.fr.
1158+   Changes by Michael Meissner, meissner@osf.org.
1159+   64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
1160+   Brendan Eich, brendan@microunity.com.
1161+
1162+This file is part of GCC.
1163+
1164+GCC is free software; you can redistribute it and/or modify
1165+it under the terms of the GNU General Public License as published by
1166+the Free Software Foundation; either version 3, or (at your option)
1167+any later version.
1168+
1169+GCC is distributed in the hope that it will be useful,
1170+but WITHOUT ANY WARRANTY; without even the implied warranty of
1171+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1172+GNU General Public License for more details.
1173+
1174+You should have received a copy of the GNU General Public License
1175+along with GCC; see the file COPYING3.  If not see
1176+<http://www.gnu.org/licenses/>.  */
1177+
1178+#include "config.h"
1179+#include "system.h"
1180+#include "coretypes.h"
1181+#include "tm.h"
1182+#include "rtl.h"
1183+#include "regs.h"
1184+#include "hard-reg-set.h"
1185+#include "insn-config.h"
1186+#include "conditions.h"
1187+#include "insn-attr.h"
1188+#include "recog.h"
1189+#include "output.h"
1190+#include "tree.h"
1191+#include "function.h"
1192+#include "expr.h"
1193+#include "optabs.h"
1194+#include "libfuncs.h"
1195+#include "flags.h"
1196+#include "reload.h"
1197+#include "tm_p.h"
1198+#include "ggc.h"
1199+#include "gstab.h"
1200+#include "hashtab.h"
1201+#include "debug.h"
1202+#include "target.h"
1203+#include "target-def.h"
1204+#include "integrate.h"
1205+#include "langhooks.h"
1206+#include "cfglayout.h"
1207+#include "sched-int.h"
1208+#include "gimple.h"
1209+#include "bitmap.h"
1210+#include "diagnostic.h"
1211+#include "target-globals.h"
1212+#include <stdint.h>
1213+
1214+/*----------------------------------------------------------------------*/
1215+/* RISCV_SYSCFG_VLEN_MAX                                                */
1216+/*----------------------------------------------------------------------*/
1217+/* Eventually we want to include syscfg.h here so that we can use the
1218+   common definition of RISCV_SYSCFG_VLEN_MAX, but for now it is not
1219+   clear how to do this. syscfg.h in in libgloss which is not used when
1220+   building the actual cross-compiler. We kind of want to use the
1221+   "version" in sims - the one for native programs instead of RISC-V
1222+   programs. Even if we could include syscfg.h though, we would still
1223+   need to figure out a way to include it in the mips-riscv.md since the
1224+   machine description file also refers to these modes. */
1225+
1226+#define RISCV_SYSCFG_VLEN_MAX 32
1227+
1228+/*----------------------------------------------------------------------*/
1229+/* MIPS_RISCV_VECTOR_MODE_NAME                                          */
1230+/*----------------------------------------------------------------------*/
1231+/* This is a helper macro which creates a RISC-V vector mode name from
1232+   the given inner_mode. It does this by concatenating a 'V' prefix, the
1233+   maximum RISC-V vector length, and the inner mode together. For
1234+   example, MIPS_RISCV_VECTOR_MODE_NAME(SI) should expand to V32SI if
1235+   the RISC-V maximum vector length is 32. We need to use the nested
1236+   macros to make sure RISCV_SYSCFG_VLEN_MAX is expanded _before_
1237+   concatenation. */
1238+
1239+#define MIPS_RISCV_VECTOR_MODE_NAME_H2( res_ ) res_
1240+
1241+#define MIPS_RISCV_VECTOR_MODE_NAME_H1( arg0_, arg1_ ) \
1242+  MIPS_RISCV_VECTOR_MODE_NAME_H2( V ## arg0_ ## arg1_ ## mode )
1243+
1244+#define MIPS_RISCV_VECTOR_MODE_NAME_H0( arg0_, arg1_ ) \
1245+  MIPS_RISCV_VECTOR_MODE_NAME_H1( arg0_, arg1_ )
1246+
1247+#define MIPS_RISCV_VECTOR_MODE_NAME( inner_mode_ ) \
1248+  MIPS_RISCV_VECTOR_MODE_NAME_H0( RISCV_SYSCFG_VLEN_MAX, inner_mode_ )
1249+
1250+/* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF.  */
1251+#define UNSPEC_ADDRESS_P(X)                                    \
1252+  (GET_CODE (X) == UNSPEC                                      \
1253+   && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST                      \
1254+   && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
1255+
1256+/* Extract the symbol or label from UNSPEC wrapper X.  */
1257+#define UNSPEC_ADDRESS(X) \
1258+  XVECEXP (X, 0, 0)
1259+
1260+/* Extract the symbol type from UNSPEC wrapper X.  */
1261+#define UNSPEC_ADDRESS_TYPE(X) \
1262+  ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
1263+
1264+/* The maximum distance between the top of the stack frame and the
1265+   value $sp has when we save and restore registers.
1266+
1267+   The value for normal-mode code must be a SMALL_OPERAND and must
1268+   preserve the maximum stack alignment.  We therefore use a value
1269+   of 0x7ff0 in this case.
1270+
1271+   MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
1272+   up to 0x7f8 bytes and can usually save or restore all the registers
1273+   that we need to save or restore.  (Note that we can only use these
1274+   instructions for o32, for which the stack alignment is 8 bytes.)
1275+
1276+   We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
1277+   RESTORE are not available.  We can then use unextended instructions
1278+   to save and restore registers, and to allocate and deallocate the top
1279+   part of the frame.  */
1280+#define MIPS_MAX_FIRST_STACK_STEP (RISCV_IMM_REACH/2 - 16)
1281+
1282+/* True if INSN is a mips.md pattern or asm statement.  */
1283+#define USEFUL_INSN_P(INSN)                                            \
1284+  (NONDEBUG_INSN_P (INSN)                                              \
1285+   && GET_CODE (PATTERN (INSN)) != USE                                 \
1286+   && GET_CODE (PATTERN (INSN)) != CLOBBER                             \
1287+   && GET_CODE (PATTERN (INSN)) != ADDR_VEC                            \
1288+   && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
1289+
1290+/* True if bit BIT is set in VALUE.  */
1291+#define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
1292+
1293+/* Classifies an address.
1294+
1295+   ADDRESS_REG
1296+       A natural register + offset address.  The register satisfies
1297+       mips_valid_base_register_p and the offset is a const_arith_operand.
1298+
1299+   ADDRESS_LO_SUM
1300+       A LO_SUM rtx.  The first operand is a valid base register and
1301+       the second operand is a symbolic address.
1302+
1303+   ADDRESS_CONST_INT
1304+       A signed 16-bit constant address.
1305+
1306+   ADDRESS_SYMBOLIC:
1307+       A constant symbolic address.  */
1308+enum mips_address_type {
1309+  ADDRESS_REG,
1310+  ADDRESS_LO_SUM,
1311+  ADDRESS_CONST_INT,
1312+  ADDRESS_SYMBOLIC
1313+};
1314+
1315+/* Macros to create an enumeration identifier for a function prototype.  */
1316+#define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
1317+#define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
1318+#define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
1319+#define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
1320+
1321+/* Classifies the prototype of a built-in function.  */
1322+enum mips_function_type {
1323+#define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
1324+#include "config/riscv/riscv-ftypes.def"
1325+#undef DEF_MIPS_FTYPE
1326+  MIPS_MAX_FTYPE_MAX
1327+};
1328+
1329+/* Specifies how a built-in function should be converted into rtl.  */
1330+enum mips_builtin_type {
1331+  /* The function corresponds directly to an .md pattern.  The return
1332+     value is mapped to operand 0 and the arguments are mapped to
1333+     operands 1 and above.  */
1334+  MIPS_BUILTIN_DIRECT,
1335+
1336+  /* The function corresponds directly to an .md pattern.  There is no return
1337+     value and the arguments are mapped to operands 0 and above.  */
1338+  MIPS_BUILTIN_DIRECT_NO_TARGET
1339+};
1340+
1341+/* Information about a function's frame layout.  */
1342+struct GTY(())  mips_frame_info {
1343+  /* The size of the frame in bytes.  */
1344+  HOST_WIDE_INT total_size;
1345+
1346+  /* Bit X is set if the function saves or restores GPR X.  */
1347+  unsigned int mask;
1348+
1349+  /* Likewise FPR X.  */
1350+  unsigned int fmask;
1351+
1352+  /* Offsets of fixed-point and floating-point save areas from frame bottom */
1353+  HOST_WIDE_INT gp_sp_offset;
1354+  HOST_WIDE_INT fp_sp_offset;
1355+
1356+  /* Offset of virtual frame pointer from stack pointer/frame bottom */
1357+  HOST_WIDE_INT frame_pointer_offset;
1358+
1359+  /* Offset of hard frame pointer from stack pointer/frame bottom */
1360+  HOST_WIDE_INT hard_frame_pointer_offset;
1361+
1362+  /* The offset of arg_pointer_rtx from the bottom of the frame.  */
1363+  HOST_WIDE_INT arg_pointer_offset;
1364+};
1365+
1366+struct GTY(())  machine_function {
1367+  /* The number of extra stack bytes taken up by register varargs.
1368+     This area is allocated by the callee at the very top of the frame.  */
1369+  int varargs_size;
1370+
1371+  /* The current frame information, calculated by mips_compute_frame_info.  */
1372+  struct mips_frame_info frame;
1373+};
1374+
1375+/* Information about a single argument.  */
1376+struct mips_arg_info {
1377+  /* True if the argument is passed in a floating-point register, or
1378+     would have been if we hadn't run out of registers.  */
1379+  bool fpr_p;
1380+
1381+  /* The number of words passed in registers, rounded up.  */
1382+  unsigned int reg_words;
1383+
1384+  /* For EABI, the offset of the first register from GP_ARG_FIRST or
1385+     FP_ARG_FIRST.  For other ABIs, the offset of the first register from
1386+     the start of the ABI's argument structure (see the CUMULATIVE_ARGS
1387+     comment for details).
1388+
1389+     The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
1390+     on the stack.  */
1391+  unsigned int reg_offset;
1392+
1393+  /* The number of words that must be passed on the stack, rounded up.  */
1394+  unsigned int stack_words;
1395+
1396+  /* The offset from the start of the stack overflow area of the argument's
1397+     first stack word.  Only meaningful when STACK_WORDS is nonzero.  */
1398+  unsigned int stack_offset;
1399+};
1400+
1401+/* Information about an address described by mips_address_type.
1402+
1403+   ADDRESS_CONST_INT
1404+       No fields are used.
1405+
1406+   ADDRESS_REG
1407+       REG is the base register and OFFSET is the constant offset.
1408+
1409+   ADDRESS_LO_SUM
1410+       REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
1411+       is the type of symbol it references.
1412+
1413+   ADDRESS_SYMBOLIC
1414+       SYMBOL_TYPE is the type of symbol that the address references.  */
1415+struct mips_address_info {
1416+  enum mips_address_type type;
1417+  rtx reg;
1418+  rtx offset;
1419+  enum mips_symbol_type symbol_type;
1420+};
1421+
1422+/* One stage in a constant building sequence.  These sequences have
1423+   the form:
1424+
1425+       A = VALUE[0]
1426+       A = A CODE[1] VALUE[1]
1427+       A = A CODE[2] VALUE[2]
1428+       ...
1429+
1430+   where A is an accumulator, each CODE[i] is a binary rtl operation
1431+   and each VALUE[i] is a constant integer.  CODE[0] is undefined.  */
1432+struct mips_integer_op {
1433+  enum rtx_code code;
1434+  unsigned HOST_WIDE_INT value;
1435+};
1436+
1437+/* The largest number of operations needed to load an integer constant.
1438+   The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
1439+   When the lowest bit is clear, we can try, but reject a sequence with
1440+   an extra SLL at the end.  */
1441+#define MIPS_MAX_INTEGER_OPS 32
1442+
1443+/* Costs of various operations on the different architectures.  */
1444+
1445+struct mips_rtx_cost_data
1446+{
1447+  unsigned short fp_add;
1448+  unsigned short fp_mult_sf;
1449+  unsigned short fp_mult_df;
1450+  unsigned short fp_div_sf;
1451+  unsigned short fp_div_df;
1452+  unsigned short int_mult_si;
1453+  unsigned short int_mult_di;
1454+  unsigned short int_div_si;
1455+  unsigned short int_div_di;
1456+  unsigned short branch_cost;
1457+  unsigned short memory_latency;
1458+};
1459+
1460+/* Global variables for machine-dependent things.  */
1461+
1462+/* The number of file directives written by mips_output_filename.  */
1463+int num_source_filenames;
1464+
1465+/* The name that appeared in the last .file directive written by
1466+   mips_output_filename, or "" if mips_output_filename hasn't
1467+   written anything yet.  */
1468+const char *current_function_file = "";
1469+
1470+/* Arrays that map GCC register numbers to debugger register numbers.  */
1471+int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
1472+int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
1473+
1474+/* The processor that we should tune the code for.  */
1475+enum processor mips_tune;
1476+
1477+/* Which cost information to use.  */
1478+static const struct mips_rtx_cost_data *mips_cost;
1479+
1480+/* Index [M][R] is true if register R is allowed to hold a value of mode M.  */
1481+bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
1482+
1483+static GTY (()) int mips_output_filename_first_time = 1;
1484+
1485+/* mips_split_p[X] is true if symbols of type X can be split by
1486+   mips_split_symbol.  */
1487+bool mips_split_p[NUM_SYMBOL_TYPES];
1488+
1489+/* mips_lo_relocs[X] is the relocation to use when a symbol of type X
1490+   appears in a LO_SUM.  It can be null if such LO_SUMs aren't valid or
1491+   if they are matched by a special .md file pattern.  */
1492+static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
1493+
1494+/* Likewise for HIGHs.  */
1495+static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
1496+
1497+/* Target state for MIPS16.  */
1498+struct target_globals *mips16_globals;
1499+
1500+/* Index R is the smallest register class that contains register R.  */
1501+const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
1502+  GR_REGS,     GR_REGS,        GR_REGS,        GR_REGS,
1503+  GR_REGS,     GR_REGS,        GR_REGS,        GR_REGS,
1504+  GR_REGS,     GR_REGS,        GR_REGS,        GR_REGS,
1505+  GR_REGS,     GR_REGS,        GR_REGS,        GR_REGS,
1506+  GR_REGS,     V1_REG,         GR_REGS,        GR_REGS,
1507+  GR_REGS,     GR_REGS,        GR_REGS,        GR_REGS,
1508+  GR_REGS,     GR_REGS,        GR_REGS,        GR_REGS,
1509+  GR_REGS,     GR_REGS,        GR_REGS,        GR_REGS,
1510+  FP_REGS,     FP_REGS,        FP_REGS,        FP_REGS,
1511+  FP_REGS,     FP_REGS,        FP_REGS,        FP_REGS,
1512+  FP_REGS,     FP_REGS,        FP_REGS,        FP_REGS,
1513+  FP_REGS,     FP_REGS,        FP_REGS,        FP_REGS,
1514+  FP_REGS,     FP_REGS,        FP_REGS,        FP_REGS,
1515+  FP_REGS,     FP_REGS,        FP_REGS,        FP_REGS,
1516+  FP_REGS,     FP_REGS,        FP_REGS,        FP_REGS,
1517+  FP_REGS,     FP_REGS,        FP_REGS,        FP_REGS,
1518+  VEC_GR_REGS, VEC_GR_REGS,    VEC_GR_REGS,    VEC_GR_REGS,
1519+  VEC_GR_REGS, VEC_GR_REGS,    VEC_GR_REGS,    VEC_GR_REGS,
1520+  VEC_GR_REGS, VEC_GR_REGS,    VEC_GR_REGS,    VEC_GR_REGS,
1521+  VEC_GR_REGS, VEC_GR_REGS,    VEC_GR_REGS,    VEC_GR_REGS,
1522+  VEC_GR_REGS, VEC_GR_REGS,    VEC_GR_REGS,    VEC_GR_REGS,
1523+  VEC_GR_REGS, VEC_GR_REGS,    VEC_GR_REGS,    VEC_GR_REGS,
1524+  VEC_GR_REGS, VEC_GR_REGS,    VEC_GR_REGS,    VEC_GR_REGS,
1525+  VEC_GR_REGS, VEC_GR_REGS,    VEC_GR_REGS,    VEC_GR_REGS,
1526+  VEC_FP_REGS, VEC_FP_REGS,    VEC_FP_REGS,    VEC_FP_REGS,
1527+  VEC_FP_REGS, VEC_FP_REGS,    VEC_FP_REGS,    VEC_FP_REGS,
1528+  VEC_FP_REGS, VEC_FP_REGS,    VEC_FP_REGS,    VEC_FP_REGS,
1529+  VEC_FP_REGS, VEC_FP_REGS,    VEC_FP_REGS,    VEC_FP_REGS,
1530+  VEC_FP_REGS, VEC_FP_REGS,    VEC_FP_REGS,    VEC_FP_REGS,
1531+  VEC_FP_REGS, VEC_FP_REGS,    VEC_FP_REGS,    VEC_FP_REGS,
1532+  VEC_FP_REGS, VEC_FP_REGS,    VEC_FP_REGS,    VEC_FP_REGS,
1533+  VEC_FP_REGS, VEC_FP_REGS,    VEC_FP_REGS,    VEC_FP_REGS,
1534+  FRAME_REGS,  FRAME_REGS,     NO_REGS,        NO_REGS,
1535+};
1536+
1537+/* The value of TARGET_ATTRIBUTE_TABLE.  */
1538+static const struct attribute_spec mips_attribute_table[] = {
1539+  /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1540+  { "long_call",   0, 0, false, true,  true,  NULL },
1541+  { "far",                0, 0, false, true,  true,  NULL },
1542+  { "near",        0, 0, false, true,  true,  NULL },
1543+  { "utfunc",      0, 0, true,  false, false, NULL },
1544+  { NULL,         0, 0, false, false, false, NULL }
1545+};
1546+
1547+/* A table describing all the processors GCC knows about.  Names are
1548+   matched in the order listed.  The first mention of an ISA level is
1549+   taken as the canonical name for that ISA.
1550+
1551+   To ease comparison, please keep this table in the same order
1552+   as GAS's mips_cpu_info_table.  Please also make sure that
1553+   MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
1554+   options correctly.  */
1555+static const struct mips_cpu_info mips_cpu_info_table[] = {
1556+  /* Entries for generic ISAs.  */
1557+  { "rocket", PROCESSOR_ROCKET, 0 },
1558+};
1559+
1560+/* Default costs.  If these are used for a processor we should look
1561+   up the actual costs.  */
1562+#define DEFAULT_COSTS COSTS_N_INSNS (8),  /* fp_add */       \
1563+                      COSTS_N_INSNS (8),  /* fp_mult_sf */   \
1564+                      COSTS_N_INSNS (8),  /* fp_mult_df */   \
1565+                      COSTS_N_INSNS (20), /* fp_div_sf */    \
1566+                      COSTS_N_INSNS (20), /* fp_div_df */    \
1567+                      COSTS_N_INSNS (10), /* int_mult_si */  \
1568+                      COSTS_N_INSNS (10), /* int_mult_di */  \
1569+                      COSTS_N_INSNS (69), /* int_div_si */   \
1570+                      COSTS_N_INSNS (69), /* int_div_di */   \
1571+                                       2, /* branch_cost */  \
1572+                                       7  /* memory_latency */
1573+
1574+/* Floating-point costs for processors without an FPU.  Just assume that
1575+   all floating-point libcalls are very expensive.  */
1576+#define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */       \
1577+                      COSTS_N_INSNS (256), /* fp_mult_sf */   \
1578+                      COSTS_N_INSNS (256), /* fp_mult_df */   \
1579+                      COSTS_N_INSNS (256), /* fp_div_sf */    \
1580+                      COSTS_N_INSNS (256)  /* fp_div_df */
1581+
1582+/* Costs to use when optimizing for size.  */
1583+static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
1584+  COSTS_N_INSNS (1),            /* fp_add */
1585+  COSTS_N_INSNS (1),            /* fp_mult_sf */
1586+  COSTS_N_INSNS (1),            /* fp_mult_df */
1587+  COSTS_N_INSNS (1),            /* fp_div_sf */
1588+  COSTS_N_INSNS (1),            /* fp_div_df */
1589+  COSTS_N_INSNS (1),            /* int_mult_si */
1590+  COSTS_N_INSNS (1),            /* int_mult_di */
1591+  COSTS_N_INSNS (1),            /* int_div_si */
1592+  COSTS_N_INSNS (1),            /* int_div_di */
1593+                  2,           /* branch_cost */
1594+                  4            /* memory_latency */
1595+};
1596+
1597+/* Costs to use when optimizing for speed, indexed by processor.  */
1598+static const struct mips_rtx_cost_data
1599+  mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
1600+  { /* Rocket */ DEFAULT_COSTS},
1601+};
1602+
1603+static int mips_register_move_cost (enum machine_mode, reg_class_t,
1604+                                   reg_class_t);
1605+static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1606+
1607+/* Predicates to test for presence of "near" and "far"/"long_call"
1608+   attributes on the given TYPE.  */
1609+
1610+static bool
1611+mips_near_type_p (const_tree type)
1612+{
1613+  return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1614+}
1615+
1616+static bool
1617+mips_far_type_p (const_tree type)
1618+{
1619+  return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1620+         || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1621+}
1622+
1623+/* Implement TARGET_COMP_TYPE_ATTRIBUTES.  */
1624+
1625+static int
1626+mips_comp_type_attributes (const_tree type1, const_tree type2)
1627+{
1628+  /* Disallow mixed near/far attributes.  */
1629+  if (mips_far_type_p (type1) && mips_near_type_p (type2))
1630+    return 0;
1631+  if (mips_near_type_p (type1) && mips_far_type_p (type2))
1632+    return 0;
1633+  return 1;
1634+}
1635+
1636+/* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1637+   and *OFFSET_PTR.  Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise.  */
1638+
1639+static void
1640+mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1641+{
1642+  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1643+    {
1644+      *base_ptr = XEXP (x, 0);
1645+      *offset_ptr = INTVAL (XEXP (x, 1));
1646+    }
1647+  else
1648+    {
1649+      *base_ptr = x;
1650+      *offset_ptr = 0;
1651+    }
1652+}
1653+
1654+/* Fill CODES with a sequence of rtl operations to load VALUE.
1655+   Return the number of operations needed.  */
1656+
1657+static int
1658+riscv_build_integer_simple (struct mips_integer_op *codes, HOST_WIDE_INT value)
1659+{
1660+  HOST_WIDE_INT low_part = RISCV_CONST_LOW_PART (value);
1661+  int cost = INT_MAX, alt_cost;
1662+  struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1663+
1664+  if (SMALL_OPERAND (value) || LUI_OPERAND (value))
1665+    {
1666+      /* Simply ADDI or LUI */
1667+      codes[0].code = UNKNOWN;
1668+      codes[0].value = value;
1669+      return 1;
1670+    }
1671+
1672+  /* End with ADDI */
1673+  if (low_part != 0)
1674+    {
1675+      cost = 1 + riscv_build_integer_simple (codes, value - low_part);
1676+      codes[cost-1].code = PLUS;
1677+      codes[cost-1].value = low_part;
1678+    }
1679+
1680+  /* End with XORI */
1681+  if (low_part < 0)
1682+    {
1683+      alt_cost = 1 + riscv_build_integer_simple (alt_codes, value ^ low_part);
1684+      alt_codes[alt_cost-1].code = XOR;
1685+      alt_codes[alt_cost-1].value = low_part;
1686+      if (alt_cost < cost)
1687+       cost = alt_cost, memcpy (codes, alt_codes, sizeof(alt_codes));
1688+    }
1689+
1690+  /* Eliminate trailing zeros and end with SLLI */
1691+  if ((value & 1) == 0)
1692+    {
1693+      int shift = __builtin_ctzl(value);
1694+      alt_cost = 1 + riscv_build_integer_simple (alt_codes, value >> shift);
1695+      alt_codes[alt_cost-1].code = ASHIFT;
1696+      alt_codes[alt_cost-1].value = shift;
1697+      if (alt_cost < cost)
1698+       cost = alt_cost, memcpy (codes, alt_codes, sizeof(alt_codes));
1699+    }
1700+
1701+  gcc_assert (cost <= MIPS_MAX_INTEGER_OPS);
1702+  return cost;
1703+}
1704+
1705+static int
1706+riscv_build_integer (struct mips_integer_op *codes, HOST_WIDE_INT value)
1707+{
1708+  int cost = riscv_build_integer_simple (codes, value);
1709+
1710+  /* Eliminate leading zeros and end with SRLI */
1711+  if (value > 0 && cost > 2)
1712+    {
1713+      struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1714+      int alt_cost, shift;
1715+
1716+      shift = __builtin_clzl(value);
1717+      alt_cost = 1 + riscv_build_integer_simple (alt_codes, value << shift);
1718+      alt_codes[alt_cost-1].code = LSHIFTRT;
1719+      alt_codes[alt_cost-1].value = shift;
1720+      if (alt_cost < cost)
1721+       cost = alt_cost, memcpy (codes, alt_codes, sizeof(alt_codes));
1722+
1723+      /* Also try filling discarded bits with 1s */
1724+      shift = __builtin_clzl(value);
1725+      alt_cost = 1 + riscv_build_integer_simple (alt_codes,
1726+                       value << shift | ((1L<<shift)-1));
1727+      alt_codes[alt_cost-1].code = LSHIFTRT;
1728+      alt_codes[alt_cost-1].value = shift;
1729+      if (alt_cost < cost)
1730+       cost = alt_cost, memcpy (codes, alt_codes, sizeof(alt_codes));
1731+    }
1732+
1733+  return cost;
1734+}
1735+
1736+/* Return true if X is a thread-local symbol.  */
1737+
1738+static bool
1739+mips_tls_symbol_p (const_rtx x)
1740+{
1741+  return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1742+}
1743+
1744+bool
1745+riscv_symbol_binds_local_p (const_rtx x)
1746+{
1747+  if (SYMBOL_REF_DECL (x))
1748+    {
1749+      if (DECL_BUILT_IN_CLASS (SYMBOL_REF_DECL (x)))
1750+       return true; /* Force local binding of memset etc. */
1751+      return targetm.binds_local_p (SYMBOL_REF_DECL (x));
1752+    }
1753+  return SYMBOL_REF_LOCAL_P (x);
1754+}
1755+
1756+/* Return the method that should be used to access SYMBOL_REF or
1757+   LABEL_REF X in context CONTEXT.  */
1758+
1759+static enum mips_symbol_type
1760+mips_classify_symbol (const_rtx x)
1761+{
1762+  if (mips_tls_symbol_p (x))
1763+    return SYMBOL_TLS;
1764+  return SYMBOL_ABSOLUTE;
1765+}
1766+
1767+/* Classify the base of symbolic expression X, given that X appears in
1768+   context CONTEXT.  */
1769+
1770+static enum mips_symbol_type
1771+mips_classify_symbolic_expression (rtx x)
1772+{
1773+  rtx offset;
1774+
1775+  split_const (x, &x, &offset);
1776+  if (UNSPEC_ADDRESS_P (x))
1777+    return UNSPEC_ADDRESS_TYPE (x);
1778+
1779+  return mips_classify_symbol (x);
1780+}
1781+
1782+/* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1783+   is the alignment in bytes of SYMBOL_REF X.  */
1784+
1785+static bool
1786+mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1787+{
1788+  HOST_WIDE_INT align;
1789+
1790+  align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1791+  return IN_RANGE (offset, 0, align - 1);
1792+}
1793+
1794+/* Return true if X is a symbolic constant that can be used in context
1795+   CONTEXT.  If it is, store the type of the symbol in *SYMBOL_TYPE.  */
1796+
1797+bool
1798+mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1799+{
1800+  rtx offset;
1801+
1802+  split_const (x, &x, &offset);
1803+  if (UNSPEC_ADDRESS_P (x))
1804+    {
1805+      *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1806+      x = UNSPEC_ADDRESS (x);
1807+    }
1808+  else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1809+    *symbol_type = mips_classify_symbol (x);
1810+  else
1811+    return false;
1812+
1813+  if (offset == const0_rtx)
1814+    return true;
1815+
1816+  if (flag_pic)
1817+  /* Load the base address from the GOT, then add the offset. The offset
1818+     calculation can usually be folded into the load or store instruction. */
1819+    return false;
1820+
1821+  /* Check whether a nonzero offset is valid for the underlying
1822+     relocations.  */
1823+  switch (*symbol_type)
1824+    {
1825+    case SYMBOL_ABSOLUTE:
1826+      /* If the target has 64-bit pointers and the object file only
1827+        supports 32-bit symbols, the values of those symbols will be
1828+        sign-extended.  In this case we can't allow an arbitrary offset
1829+        in case the 32-bit value X + OFFSET has a different sign from X.  */
1830+      return Pmode == SImode || offset_within_block_p (x, INTVAL (offset));
1831+
1832+    case SYMBOL_TPREL:
1833+      /* There is no carry between the HI and LO REL relocations, so the
1834+        offset is only valid if we know it won't lead to such a carry.  */
1835+      return mips_offset_within_alignment_p (x, INTVAL (offset));
1836+
1837+    case SYMBOL_TLS:
1838+      return false;
1839+    }
1840+  gcc_unreachable ();
1841+}
1842+
1843+/* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1844+   single instruction.  We rely on the fact that, in the worst case,
1845+   all instructions involved in a MIPS16 address calculation are usually
1846+   extended ones.  */
1847+
1848+static int
1849+mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1850+{
1851+  switch (type)
1852+    {
1853+    case SYMBOL_ABSOLUTE:
1854+    case SYMBOL_TPREL:
1855+      /* One of LUI or AUIPC, followed by one of ADDI, LD, or LW. */
1856+      return 2;
1857+
1858+    case SYMBOL_TLS:
1859+      /* We don't treat a bare TLS symbol as a constant.  */
1860+      return 0;
1861+    }
1862+  gcc_unreachable ();
1863+}
1864+
1865+/* A for_each_rtx callback.  Stop the search if *X references a
1866+   thread-local symbol.  */
1867+
1868+static int
1869+mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1870+{
1871+  return mips_tls_symbol_p (*x);
1872+}
1873+
1874+/* Implement TARGET_CANNOT_FORCE_CONST_MEM.  */
1875+
1876+static bool
1877+mips_cannot_force_const_mem (rtx x)
1878+{
1879+  enum mips_symbol_type type;
1880+  rtx base, offset;
1881+
1882+  /* There is no assembler syntax for expressing an address-sized
1883+     high part.  */
1884+  if (GET_CODE (x) == HIGH)
1885+    return true;
1886+
1887+  /* As an optimization, reject constants that mips_legitimize_move
1888+     can expand inline.
1889+
1890+     Suppose we have a multi-instruction sequence that loads constant C
1891+     into register R.  If R does not get allocated a hard register, and
1892+     R is used in an operand that allows both registers and memory
1893+     references, reload will consider forcing C into memory and using
1894+     one of the instruction's memory alternatives.  Returning false
1895+     here will force it to use an input reload instead.  */
1896+  if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
1897+    return true;
1898+
1899+  split_const (x, &base, &offset);
1900+  if (mips_symbolic_constant_p (base, &type))
1901+    {
1902+      /* The same optimization as for CONST_INT.  */
1903+      if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1904+       return true;
1905+    }
1906+
1907+  /* TLS symbols must be computed by mips_legitimize_move.  */
1908+  if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1909+    return true;
1910+
1911+  return false;
1912+}
1913+
1914+/* Return true if register REGNO is a valid base register for mode MODE.
1915+   STRICT_P is true if REG_OK_STRICT is in effect.  */
1916+
1917+int
1918+mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode ATTRIBUTE_UNUSED,
1919+                              bool strict_p)
1920+{
1921+  if (!HARD_REGISTER_NUM_P (regno))
1922+    {
1923+      if (!strict_p)
1924+       return true;
1925+      regno = reg_renumber[regno];
1926+    }
1927+
1928+  /* These fake registers will be eliminated to either the stack or
1929+     hard frame pointer, both of which are usually valid base registers.
1930+     Reload deals with the cases where the eliminated form isn't valid.  */
1931+  if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1932+    return true;
1933+
1934+  return GP_REG_P (regno);
1935+}
1936+
1937+/* Return true if X is a valid base register for mode MODE.
1938+   STRICT_P is true if REG_OK_STRICT is in effect.  */
1939+
1940+static bool
1941+mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
1942+{
1943+  if (!strict_p && GET_CODE (x) == SUBREG)
1944+    x = SUBREG_REG (x);
1945+
1946+  return (REG_P (x)
1947+         && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
1948+}
1949+
1950+/* Return true if, for every base register BASE_REG, (plus BASE_REG X)
1951+   can address a value of mode MODE.  */
1952+
1953+static bool
1954+mips_valid_offset_p (rtx x, enum machine_mode mode)
1955+{
1956+  /* Check that X is a signed 12-bit number.  */
1957+  if (!const_arith_operand (x, Pmode))
1958+    return false;
1959+
1960+  /* We may need to split multiword moves, so make sure that every word
1961+     is accessible.  */
1962+  if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
1963+      && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
1964+    return false;
1965+
1966+  return true;
1967+}
1968+
1969+/* Return true if a LO_SUM can address a value of mode MODE when the
1970+   LO_SUM symbol has type SYMBOL_TYPE.  */
1971+
1972+static bool
1973+mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
1974+{
1975+  /* Check that symbols of type SYMBOL_TYPE can be used to access values
1976+     of mode MODE.  */
1977+  if (mips_symbol_insns (symbol_type, mode) == 0)
1978+    return false;
1979+
1980+  /* Check that there is a known low-part relocation.  */
1981+  if (mips_lo_relocs[symbol_type] == NULL)
1982+    return false;
1983+
1984+  /* We may need to split multiword moves, so make sure that each word
1985+     can be accessed without inducing a carry.  This is mainly needed
1986+     for o64, which has historically only guaranteed 64-bit alignment
1987+     for 128-bit types.  */
1988+  if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
1989+      && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
1990+    return false;
1991+
1992+  return true;
1993+}
1994+
1995+/* Return true if X is a valid address for machine mode MODE.  If it is,
1996+   fill in INFO appropriately.  STRICT_P is true if REG_OK_STRICT is in
1997+   effect.  */
1998+
1999+static bool
2000+mips_classify_address (struct mips_address_info *info, rtx x,
2001+                      enum machine_mode mode, bool strict_p)
2002+{
2003+  switch (GET_CODE (x))
2004+    {
2005+    case REG:
2006+    case SUBREG:
2007+      info->type = ADDRESS_REG;
2008+      info->reg = x;
2009+      info->offset = const0_rtx;
2010+      return mips_valid_base_register_p (info->reg, mode, strict_p);
2011+
2012+    case PLUS:
2013+      info->type = ADDRESS_REG;
2014+      info->reg = XEXP (x, 0);
2015+      info->offset = XEXP (x, 1);
2016+      return (mips_valid_base_register_p (info->reg, mode, strict_p)
2017+             && mips_valid_offset_p (info->offset, mode));
2018+
2019+    case LO_SUM:
2020+      info->type = ADDRESS_LO_SUM;
2021+      info->reg = XEXP (x, 0);
2022+      info->offset = XEXP (x, 1);
2023+      /* We have to trust the creator of the LO_SUM to do something vaguely
2024+        sane.  Target-independent code that creates a LO_SUM should also
2025+        create and verify the matching HIGH.  Target-independent code that
2026+        adds an offset to a LO_SUM must prove that the offset will not
2027+        induce a carry.  Failure to do either of these things would be
2028+        a bug, and we are not required to check for it here.  The MIPS
2029+        backend itself should only create LO_SUMs for valid symbolic
2030+        constants, with the high part being either a HIGH or a copy
2031+        of _gp. */
2032+      info->symbol_type
2033+       = mips_classify_symbolic_expression (info->offset);
2034+      return (mips_valid_base_register_p (info->reg, mode, strict_p)
2035+             && mips_valid_lo_sum_p (info->symbol_type, mode));
2036+
2037+    case CONST_INT:
2038+      /* Small-integer addresses don't occur very often, but they
2039+        are legitimate if $0 is a valid base register.  */
2040+      info->type = ADDRESS_CONST_INT;
2041+      return SMALL_INT (x);
2042+
2043+    case CONST:
2044+    case LABEL_REF:
2045+    case SYMBOL_REF:
2046+      info->type = ADDRESS_SYMBOLIC;
2047+      return false;
2048+
2049+    default:
2050+      return false;
2051+    }
2052+}
2053+
2054+/* Implement TARGET_LEGITIMATE_ADDRESS_P.  */
2055+
2056+static bool
2057+mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2058+{
2059+  struct mips_address_info addr;
2060+
2061+  return mips_classify_address (&addr, x, mode, strict_p);
2062+}
2063+
2064+/* Return the number of instructions needed to load or store a value
2065+   of mode MODE at address X.  Return 0 if X isn't valid for MODE.
2066+   Assume that multiword moves may need to be split into word moves
2067+   if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2068+   enough.
2069+
2070+   For MIPS16 code, count extended instructions as two instructions.  */
2071+
2072+int
2073+mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2074+{
2075+  struct mips_address_info addr;
2076+
2077+  if (mips_classify_address (&addr, x, mode, false))
2078+    {
2079+      int factor = 1;
2080+
2081+      /* BLKmode is used for single unaligned loads and stores and should
2082+         not count as a multiword mode. */
2083+      if (mode != BLKmode && might_split_p)
2084+        factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2085+
2086+      if (addr.type == ADDRESS_SYMBOLIC)
2087+       factor *= mips_symbol_insns (addr.symbol_type, mode);
2088+
2089+      return factor;
2090+    }
2091+
2092+  return 0;
2093+}
2094+
2095+/* Return the number of instructions needed to load constant X.
2096+   Return 0 if X isn't a valid constant.  */
2097+
2098+int
2099+mips_const_insns (rtx x)
2100+{
2101+  struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2102+  enum mips_symbol_type symbol_type;
2103+  rtx offset;
2104+
2105+  switch (GET_CODE (x))
2106+    {
2107+    case HIGH:
2108+      if (!mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
2109+         || !mips_split_p[symbol_type])
2110+       return 0;
2111+
2112+      /* This is simply an LUI. */
2113+      return 1;
2114+
2115+    case CONST_INT:
2116+      return riscv_build_integer (codes, INTVAL (x));
2117+
2118+    case CONST_DOUBLE:
2119+    case CONST_VECTOR:
2120+      /* Allow zeros for normal mode, where we can use $0.  */
2121+      return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2122+
2123+    case CONST:
2124+      /* See if we can refer to X directly.  */
2125+      if (mips_symbolic_constant_p (x, &symbol_type))
2126+       return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2127+
2128+      /* Otherwise try splitting the constant into a base and offset.
2129+        If the offset is a 16-bit value, we can load the base address
2130+        into a register and then use (D)ADDIU to add in the offset.
2131+        If the offset is larger, we can load the base and offset
2132+        into separate registers and add them together with (D)ADDU.
2133+        However, the latter is only possible before reload; during
2134+        and after reload, we must have the option of forcing the
2135+        constant into the pool instead.  */
2136+      split_const (x, &x, &offset);
2137+      if (offset != 0)
2138+       {
2139+         int n = mips_const_insns (x);
2140+         if (n != 0)
2141+           {
2142+             if (SMALL_INT (offset))
2143+               return n + 1;
2144+             else if (!targetm.cannot_force_const_mem (x))
2145+               return n + 1 + riscv_build_integer (codes, INTVAL (offset));
2146+           }
2147+       }
2148+      return 0;
2149+
2150+    case SYMBOL_REF:
2151+    case LABEL_REF:
2152+      return mips_symbol_insns (mips_classify_symbol (x), MAX_MACHINE_MODE);
2153+
2154+    default:
2155+      return 0;
2156+    }
2157+}
2158+
2159+/* X is a doubleword constant that can be handled by splitting it into
2160+   two words and loading each word separately.  Return the number of
2161+   instructions required to do this.  */
2162+
2163+int
2164+mips_split_const_insns (rtx x)
2165+{
2166+  unsigned int low, high;
2167+
2168+  low = mips_const_insns (mips_subword (x, false));
2169+  high = mips_const_insns (mips_subword (x, true));
2170+  gcc_assert (low > 0 && high > 0);
2171+  return low + high;
2172+}
2173+
2174+/* Return the number of instructions needed to implement INSN,
2175+   given that it loads from or stores to MEM.  Count extended
2176+   MIPS16 instructions as two instructions.  */
2177+
2178+int
2179+mips_load_store_insns (rtx mem, rtx insn)
2180+{
2181+  enum machine_mode mode;
2182+  bool might_split_p;
2183+  rtx set;
2184+
2185+  gcc_assert (MEM_P (mem));
2186+  mode = GET_MODE (mem);
2187+
2188+  /* Try to prove that INSN does not need to be split.  */
2189+  might_split_p = true;
2190+  if (GET_MODE_BITSIZE (mode) == 64)
2191+    {
2192+      set = single_set (insn);
2193+      if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2194+       might_split_p = false;
2195+    }
2196+
2197+  return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2198+}
2199+
2200+/* Emit a move from SRC to DEST.  Assume that the move expanders can
2201+   handle all moves if !can_create_pseudo_p ().  The distinction is
2202+   important because, unlike emit_move_insn, the move expanders know
2203+   how to force Pmode objects into the constant pool even when the
2204+   constant pool address is not itself legitimate.  */
2205+
2206+rtx
2207+mips_emit_move (rtx dest, rtx src)
2208+{
2209+  return (can_create_pseudo_p ()
2210+         ? emit_move_insn (dest, src)
2211+         : emit_move_insn_1 (dest, src));
2212+}
2213+
2214+/* Emit an instruction of the form (set TARGET (CODE OP0 OP1)).  */
2215+
2216+static void
2217+mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2218+{
2219+  emit_insn (gen_rtx_SET (VOIDmode, target,
2220+                         gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2221+}
2222+
2223+/* Compute (CODE OP0 OP1) and store the result in a new register
2224+   of mode MODE.  Return that new register.  */
2225+
2226+static rtx
2227+mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2228+{
2229+  rtx reg;
2230+
2231+  reg = gen_reg_rtx (mode);
2232+  mips_emit_binary (code, reg, op0, op1);
2233+  return reg;
2234+}
2235+
2236+/* Copy VALUE to a register and return that register.  If new pseudos
2237+   are allowed, copy it into a new register, otherwise use DEST.  */
2238+
2239+static rtx
2240+mips_force_temporary (rtx dest, rtx value)
2241+{
2242+  if (can_create_pseudo_p ())
2243+    return force_reg (Pmode, value);
2244+  else
2245+    {
2246+      mips_emit_move (dest, value);
2247+      return dest;
2248+    }
2249+}
2250+
2251+/* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2252+   then add CONST_INT OFFSET to the result.  */
2253+
2254+static rtx
2255+mips_unspec_address_offset (rtx base, rtx offset,
2256+                           enum mips_symbol_type symbol_type)
2257+{
2258+  base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2259+                        UNSPEC_ADDRESS_FIRST + symbol_type);
2260+  if (offset != const0_rtx)
2261+    base = gen_rtx_PLUS (Pmode, base, offset);
2262+  return gen_rtx_CONST (Pmode, base);
2263+}
2264+
2265+/* Return an UNSPEC address with underlying address ADDRESS and symbol
2266+   type SYMBOL_TYPE.  */
2267+
2268+rtx
2269+mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2270+{
2271+  rtx base, offset;
2272+
2273+  split_const (address, &base, &offset);
2274+  return mips_unspec_address_offset (base, offset, symbol_type);
2275+}
2276+
2277+/* If OP is an UNSPEC address, return the address to which it refers,
2278+   otherwise return OP itself.  */
2279+
2280+static rtx
2281+mips_strip_unspec_address (rtx op)
2282+{
2283+  rtx base, offset;
2284+
2285+  split_const (op, &base, &offset);
2286+  if (UNSPEC_ADDRESS_P (base))
2287+    op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2288+  return op;
2289+}
2290+
2291+/* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2292+   high part to BASE and return the result.  Just return BASE otherwise.
2293+   TEMP is as for mips_force_temporary.
2294+
2295+   The returned expression can be used as the first operand to a LO_SUM.  */
2296+
2297+static rtx
2298+mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2299+                        enum mips_symbol_type symbol_type)
2300+{
2301+  if (mips_split_p[symbol_type])
2302+    {
2303+      addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2304+      addr = mips_force_temporary (temp, addr);
2305+      base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2306+    }
2307+  return base;
2308+}
2309+
2310+/* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2311+   it appears in a MEM of that mode.  Return true if ADDR is a legitimate
2312+   constant in that context and can be split into high and low parts.
2313+   If so, and if LOW_OUT is nonnull, emit the high part and store the
2314+   low part in *LOW_OUT.  Leave *LOW_OUT unchanged otherwise.
2315+
2316+   TEMP is as for mips_force_temporary and is used to load the high
2317+   part into a register.
2318+
2319+   When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2320+   a legitimize SET_SRC for an .md pattern, otherwise the low part
2321+   is guaranteed to be a legitimate address for mode MODE.  */
2322+
2323+bool
2324+mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2325+{
2326+  enum mips_symbol_type symbol_type;
2327+  rtx high;
2328+
2329+  if (!(GET_CODE (addr) == HIGH && mode == MAX_MACHINE_MODE))
2330+    {
2331+      if (mips_symbolic_constant_p (addr, &symbol_type)
2332+         && mips_symbol_insns (symbol_type, mode) > 0
2333+         && mips_split_p[symbol_type])
2334+       {
2335+         if (low_out)
2336+           {
2337+             high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2338+             high = mips_force_temporary (temp, high);
2339+             *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2340+           }
2341+         return true;
2342+       }
2343+    }
2344+  return false;
2345+}
2346+
2347+/* Return a legitimate address for REG + OFFSET.  TEMP is as for
2348+   mips_force_temporary; it is only needed when OFFSET is not a
2349+   SMALL_OPERAND.  */
2350+
2351+static rtx
2352+mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2353+{
2354+  if (!SMALL_OPERAND (offset))
2355+    {
2356+      rtx high;
2357+
2358+      /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2359+         The addition inside the macro CONST_HIGH_PART may cause an
2360+         overflow, so we need to force a sign-extension check.  */
2361+      high = gen_int_mode (RISCV_CONST_HIGH_PART (offset), Pmode);
2362+      offset = RISCV_CONST_LOW_PART (offset);
2363+      high = mips_force_temporary (temp, high);
2364+      reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2365+    }
2366+  return plus_constant (reg, offset);
2367+}
2368+
2369+/* Load an entry from the GOT. */
2370+static rtx riscv_got_load(rtx dest, rtx sym)
2371+{
2372+  return (Pmode == DImode ? gen_got_loaddi(dest, sym) : gen_got_loadsi(dest, sym));
2373+}
2374+static rtx riscv_got_load_tls_gd(rtx dest, rtx sym)
2375+{
2376+  return (Pmode == DImode ? gen_got_load_tls_gddi(dest, sym) : gen_got_load_tls_gdsi(dest, sym));
2377+}
2378+static rtx riscv_got_load_tls_ie(rtx dest, rtx sym)
2379+{
2380+  return (Pmode == DImode ? gen_got_load_tls_iedi(dest, sym) : gen_got_load_tls_iesi(dest, sym));
2381+}
2382+
2383+/* The __tls_get_attr symbol.  */
2384+static GTY(()) rtx mips_tls_symbol;
2385+
2386+/* Return an instruction sequence that calls __tls_get_addr.  SYM is
2387+   the TLS symbol we are referencing and TYPE is the symbol type to use
2388+   (either global dynamic or local dynamic).  V0 is an RTX for the
2389+   return value location.  */
2390+
2391+static rtx
2392+mips_call_tls_get_addr (rtx sym, rtx v0)
2393+{
2394+  rtx insn, a0;
2395+
2396+  a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2397+
2398+  if (!mips_tls_symbol)
2399+    mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2400+
2401+  start_sequence ();
2402+  
2403+  emit_insn (riscv_got_load_tls_gd(a0, sym));
2404+  insn = mips_expand_call (false, v0, mips_tls_symbol, const0_rtx);
2405+  RTL_CONST_CALL_P (insn) = 1;
2406+  use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2407+  insn = get_insns ();
2408+
2409+  end_sequence ();
2410+
2411+  return insn;
2412+}
2413+
2414+/* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2415+   its address.  The return value will be both a valid address and a valid
2416+   SET_SRC (either a REG or a LO_SUM).  */
2417+
2418+static rtx
2419+mips_legitimize_tls_address (rtx loc)
2420+{
2421+  rtx dest, insn, v0, tp, tmp1;
2422+  enum tls_model model;
2423+
2424+  model = SYMBOL_REF_TLS_MODEL (loc);
2425+  /* Only TARGET_ABICALLS code can have more than one module; other
2426+     code must be be static and should not use a GOT.  All TLS models
2427+     reduce to local exec in this situation.  */
2428+  if (!TARGET_ABICALLS)
2429+    model = TLS_MODEL_LOCAL_EXEC;
2430+
2431+  switch (model)
2432+    {
2433+    case TLS_MODEL_LOCAL_DYNAMIC:
2434+      /* We don't support LDM TLS, so fall through.*/
2435+    case TLS_MODEL_GLOBAL_DYNAMIC:
2436+      v0 = gen_rtx_REG (Pmode, GP_RETURN);
2437+      insn = mips_call_tls_get_addr (loc, v0);
2438+      dest = gen_reg_rtx (Pmode);
2439+      emit_libcall_block (insn, dest, v0, loc);
2440+      break;
2441+
2442+    case TLS_MODEL_INITIAL_EXEC:
2443+      tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
2444+      tmp1 = gen_reg_rtx (Pmode);
2445+      emit_insn (riscv_got_load_tls_ie(tmp1, loc));
2446+      dest = gen_reg_rtx (Pmode);
2447+      emit_insn (gen_add3_insn (dest, tmp1, tp));
2448+      break;
2449+
2450+    case TLS_MODEL_LOCAL_EXEC:
2451+      tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
2452+      tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2453+      dest = gen_rtx_LO_SUM (Pmode, tmp1,
2454+                            mips_unspec_address (loc, SYMBOL_TPREL));
2455+      break;
2456+
2457+    default:
2458+      gcc_unreachable ();
2459+    }
2460+  return dest;
2461+}
2462+
2463+/* If X is not a valid address for mode MODE, force it into a register.  */
2464+
2465+static rtx
2466+mips_force_address (rtx x, enum machine_mode mode)
2467+{
2468+  if (!mips_legitimate_address_p (mode, x, false))
2469+    x = force_reg (Pmode, x);
2470+  return x;
2471+}
2472+
2473+/* This function is used to implement LEGITIMIZE_ADDRESS.  If X can
2474+   be legitimized in a way that the generic machinery might not expect,
2475+   return a new address, otherwise return NULL.  MODE is the mode of
2476+   the memory being accessed.  */
2477+
2478+static rtx
2479+mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2480+                        enum machine_mode mode)
2481+{
2482+  rtx addr;
2483+
2484+  if (mips_tls_symbol_p (x))
2485+    return mips_legitimize_tls_address (x);
2486+
2487+  /* See if the address can split into a high part and a LO_SUM.  */
2488+  if (mips_split_symbol (NULL, x, mode, &addr))
2489+    return mips_force_address (addr, mode);
2490+
2491+  /* Handle BASE + OFFSET using mips_add_offset.  */
2492+  if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))
2493+      && INTVAL (XEXP (x, 1)) != 0)
2494+    {
2495+      rtx base = XEXP (x, 0);
2496+      HOST_WIDE_INT offset = INTVAL (XEXP (x, 1));
2497+
2498+      if (!mips_valid_base_register_p (base, mode, false))
2499+       base = copy_to_mode_reg (Pmode, base);
2500+      addr = mips_add_offset (NULL, base, offset);
2501+      return mips_force_address (addr, mode);
2502+    }
2503+
2504+  return x;
2505+}
2506+
2507+static int
2508+riscv_split_integer_cost (HOST_WIDE_INT val)
2509+{
2510+  int cost = 0;
2511+  struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2512+  int32_t loval = val, hival = (val - (int32_t)val) >> 32;
2513+
2514+  cost += riscv_build_integer(codes, loval);
2515+  if (loval != hival)
2516+    cost += riscv_build_integer(codes, hival);
2517+  return cost + 2;
2518+}
2519+
2520+/* Try to split a 64b integer into 32b parts, then reassemble. */
2521+
2522+static rtx
2523+riscv_split_integer (HOST_WIDE_INT val, enum machine_mode mode)
2524+{
2525+  int32_t loval = val, hival = (val - (int32_t)val) >> 32;
2526+  rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode);
2527+
2528+  mips_move_integer (hi, hi, hival);
2529+  mips_move_integer (lo, lo, loval);
2530+
2531+  hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32));
2532+  hi = force_reg (mode, hi);
2533+
2534+  return gen_rtx_fmt_ee (PLUS, mode, hi, lo);
2535+}
2536+
2537+/* Load VALUE into DEST.  TEMP is as for mips_force_temporary.  */
2538+
2539+void
2540+mips_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value)
2541+{
2542+  struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2543+  enum machine_mode mode;
2544+  unsigned int i, num_ops;
2545+  rtx x;
2546+
2547+  mode = GET_MODE (dest);
2548+  num_ops = riscv_build_integer (codes, value);
2549+
2550+  if (can_create_pseudo_p () && num_ops >= riscv_split_integer_cost (value))
2551+    x = riscv_split_integer (value, mode);
2552+  else
2553+    {
2554+      /* Apply each binary operation to X. */
2555+      x = GEN_INT (codes[0].value);
2556+
2557+      for (i = 1; i < num_ops; i++)
2558+        {
2559+          if (!can_create_pseudo_p ())
2560+            {
2561+              emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2562+              x = temp;
2563+            }
2564+          else
2565+            x = force_reg (mode == HImode ? SImode : mode, x);
2566+
2567+          x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2568+        }
2569+    }
2570+
2571+  emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2572+}
2573+
2574+/* Subroutine of mips_legitimize_move.  Move constant SRC into register
2575+   DEST given that SRC satisfies immediate_operand but doesn't satisfy
2576+   move_operand.  */
2577+
2578+static void
2579+mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2580+{
2581+  rtx base, offset;
2582+
2583+  /* Split moves of big integers into smaller pieces.  */
2584+  if (splittable_const_int_operand (src, mode))
2585+    {
2586+      mips_move_integer (dest, dest, INTVAL (src));
2587+      return;
2588+    }
2589+
2590+  /* Split moves of symbolic constants into high/low pairs.  */
2591+  if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2592+    {
2593+      emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2594+      return;
2595+    }
2596+
2597+  /* Generate the appropriate access sequences for TLS symbols.  */
2598+  if (mips_tls_symbol_p (src))
2599+    {
2600+      mips_emit_move (dest, mips_legitimize_tls_address (src));
2601+      return;
2602+    }
2603+
2604+  /* If we have (const (plus symbol offset)), and that expression cannot
2605+     be forced into memory, load the symbol first and add in the offset.
2606+     In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2607+     forced into memory, as it usually produces better code.  */
2608+  split_const (src, &base, &offset);
2609+  if (offset != const0_rtx
2610+      && (targetm.cannot_force_const_mem (src)
2611+         || can_create_pseudo_p ()))
2612+    {
2613+      base = mips_force_temporary (dest, base);
2614+      mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
2615+      return;
2616+    }
2617+
2618+  src = force_const_mem (mode, src);
2619+
2620+  /* When using explicit relocs, constant pool references are sometimes
2621+     not legitimate addresses.  */
2622+  mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2623+  mips_emit_move (dest, src);
2624+}
2625+
2626+/* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2627+   sequence that is valid.  */
2628+
2629+bool
2630+mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2631+{
2632+  if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2633+    {
2634+      mips_emit_move (dest, force_reg (mode, src));
2635+      return true;
2636+    }
2637+
2638+  /* We need to deal with constants that would be legitimate
2639+     immediate_operands but aren't legitimate move_operands.  */
2640+  if (CONSTANT_P (src) && !move_operand (src, mode))
2641+    {
2642+      mips_legitimize_const_move (mode, dest, src);
2643+      set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2644+      return true;
2645+    }
2646+  return false;
2647+}
2648+
2649+bool
2650+mips_legitimize_vector_move (enum machine_mode mode, rtx dest, rtx src)
2651+{
2652+  bool dest_mem, dest_mem_reg;
2653+  bool src_mem, src_mem_reg;
2654+
2655+  dest_mem = (GET_CODE(dest) == MEM);
2656+  dest_mem_reg = dest_mem && GET_CODE(XEXP(dest, 0)) == REG;
2657+
2658+  src_mem = (GET_CODE(src) == MEM);
2659+  src_mem_reg = src_mem && GET_CODE(XEXP(src, 0)) == REG;
2660+
2661+  if (dest_mem && !dest_mem_reg)
2662+  {
2663+    rtx add, scratch, base, move;
2664+    HOST_WIDE_INT offset;
2665+
2666+    mips_split_plus(XEXP(dest,0), &base, &offset);
2667+
2668+    scratch = gen_reg_rtx(Pmode);
2669+    add = gen_add3_insn(scratch, base, GEN_INT(offset));
2670+    emit_insn(add);
2671+
2672+    switch (mode)
2673+    {
2674+      case MIPS_RISCV_VECTOR_MODE_NAME(DI):
2675+        move = gen_movv32di(gen_rtx_MEM(mode, scratch), src);
2676+        break;
2677+      case MIPS_RISCV_VECTOR_MODE_NAME(SI):
2678+        move = gen_movv32si(gen_rtx_MEM(mode, scratch), src);
2679+        break;
2680+      case MIPS_RISCV_VECTOR_MODE_NAME(HI):
2681+        move = gen_movv32hi(gen_rtx_MEM(mode, scratch), src);
2682+        break;
2683+      case MIPS_RISCV_VECTOR_MODE_NAME(QI):
2684+        move = gen_movv32qi(gen_rtx_MEM(mode, scratch), src);
2685+        break;
2686+      case MIPS_RISCV_VECTOR_MODE_NAME(DF):
2687+        move = gen_movv32df(gen_rtx_MEM(mode, scratch), src);
2688+        break;
2689+      case MIPS_RISCV_VECTOR_MODE_NAME(SF):
2690+        move = gen_movv32sf(gen_rtx_MEM(mode, scratch), src);
2691+        break;
2692+      default:
2693+        gcc_unreachable();
2694+    }
2695+
2696+    emit_insn(move);
2697+
2698+    return true;
2699+  }
2700+
2701+  if (src_mem && !src_mem_reg)
2702+  {
2703+    rtx add, scratch, base, move;
2704+    HOST_WIDE_INT offset;
2705+
2706+    mips_split_plus(XEXP(src,0), &base, &offset);
2707+
2708+    scratch = gen_reg_rtx(Pmode);
2709+    add = gen_add3_insn(scratch, base, GEN_INT(offset));
2710+    emit_insn(add);
2711+
2712+    switch (mode)
2713+    {
2714+      case MIPS_RISCV_VECTOR_MODE_NAME(DI):
2715+        move = gen_movv32di(dest, gen_rtx_MEM(mode, scratch));
2716+        break;
2717+      case MIPS_RISCV_VECTOR_MODE_NAME(SI):
2718+        move = gen_movv32si(dest, gen_rtx_MEM(mode, scratch));
2719+        break;
2720+      case MIPS_RISCV_VECTOR_MODE_NAME(HI):
2721+        move = gen_movv32hi(dest, gen_rtx_MEM(mode, scratch));
2722+        break;
2723+      case MIPS_RISCV_VECTOR_MODE_NAME(QI):
2724+        move = gen_movv32qi(dest, gen_rtx_MEM(mode, scratch));
2725+        break;
2726+      case MIPS_RISCV_VECTOR_MODE_NAME(DF):
2727+        move = gen_movv32df(dest, gen_rtx_MEM(mode, scratch));
2728+        break;
2729+      case MIPS_RISCV_VECTOR_MODE_NAME(SF):
2730+        move = gen_movv32sf(dest, gen_rtx_MEM(mode, scratch));
2731+        break;
2732+      default:
2733+        gcc_unreachable();
2734+    }
2735+
2736+    emit_insn(move);
2737+
2738+    return true;
2739+  }
2740+
2741+  return false;
2742+}
2743+
2744+/* The cost of loading values from the constant pool.  It should be
2745+   larger than the cost of any constant we want to synthesize inline.  */
2746+#define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2747+
2748+/* Return true if there is a non-MIPS16 instruction that implements CODE
2749+   and if that instruction accepts X as an immediate operand.  */
2750+
2751+static int
2752+mips_immediate_operand_p (int code, HOST_WIDE_INT x)
2753+{
2754+  switch (code)
2755+    {
2756+    case ASHIFT:
2757+    case ASHIFTRT:
2758+    case LSHIFTRT:
2759+      /* All shift counts are truncated to a valid constant.  */
2760+      return true;
2761+
2762+    case AND:
2763+    case IOR:
2764+    case XOR:
2765+    case PLUS:
2766+    case LT:
2767+    case LTU:
2768+      /* These instructions take 12-bit signed immediates.  */
2769+      return SMALL_OPERAND (x);
2770+
2771+    case LE:
2772+      /* We add 1 to the immediate and use SLT.  */
2773+      return SMALL_OPERAND (x + 1);
2774+
2775+    case LEU:
2776+      /* Likewise SLTU, but reject the always-true case.  */
2777+      return SMALL_OPERAND (x + 1) && x + 1 != 0;
2778+
2779+    case GE:
2780+    case GEU:
2781+      /* We can emulate an immediate of 1 by using GT/GTU against x0. */
2782+      return x == 1;
2783+
2784+    default:
2785+      /* By default assume that x0 can be used for 0.  */
2786+      return x == 0;
2787+    }
2788+}
2789+
2790+/* Return the cost of binary operation X, given that the instruction
2791+   sequence for a word-sized or smaller operation has cost SINGLE_COST
2792+   and that the sequence of a double-word operation has cost DOUBLE_COST.
2793+   If SPEED is true, optimize for speed otherwise optimize for size.  */
2794+
2795+static int
2796+mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
2797+{
2798+  if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
2799+    single_cost = double_cost;
2800+
2801+  return (single_cost
2802+         + rtx_cost (XEXP (x, 0), SET, speed)
2803+         + rtx_cost (XEXP (x, 1), GET_CODE (x), speed));
2804+}
2805+
2806+/* Return the cost of floating-point multiplications of mode MODE.  */
2807+
2808+static int
2809+mips_fp_mult_cost (enum machine_mode mode)
2810+{
2811+  return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
2812+}
2813+
2814+/* Return the cost of floating-point divisions of mode MODE.  */
2815+
2816+static int
2817+mips_fp_div_cost (enum machine_mode mode)
2818+{
2819+  return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
2820+}
2821+
2822+/* Return the cost of sign-extending OP to mode MODE, not including the
2823+   cost of OP itself.  */
2824+
2825+static int
2826+mips_sign_extend_cost (enum machine_mode mode, rtx op)
2827+{
2828+  if (MEM_P (op))
2829+    /* Extended loads are as cheap as unextended ones.  */
2830+    return 0;
2831+
2832+  if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
2833+    /* A sign extension from SImode to DImode in 64-bit mode is free.  */
2834+    return 0;
2835+
2836+  /* We need to use a shift left and a shift right.  */
2837+  return COSTS_N_INSNS (2);
2838+}
2839+
2840+/* Return the cost of zero-extending OP to mode MODE, not including the
2841+   cost of OP itself.  */
2842+
2843+static int
2844+mips_zero_extend_cost (enum machine_mode mode, rtx op)
2845+{
2846+  if (MEM_P (op))
2847+    /* Extended loads are as cheap as unextended ones.  */
2848+    return 0;
2849+
2850+  if ((TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) ||
2851+      ((mode == DImode || mode == SImode) && GET_MODE (op) == HImode))
2852+    /* We need a shift left by 32 bits and a shift right by 32 bits.  */
2853+    return COSTS_N_INSNS (2);
2854+
2855+  /* We can use ANDI.  */
2856+  return COSTS_N_INSNS (1);
2857+}
2858+
2859+/* Implement TARGET_RTX_COSTS.  */
2860+
2861+static bool
2862+mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
2863+{
2864+  enum machine_mode mode = GET_MODE (x);
2865+  bool float_mode_p = FLOAT_MODE_P (mode);
2866+  int cost;
2867+  rtx addr;
2868+
2869+  /* The cost of a COMPARE is hard to define for MIPS.  COMPAREs don't
2870+     appear in the instruction stream, and the cost of a comparison is
2871+     really the cost of the branch or scc condition.  At the time of
2872+     writing, GCC only uses an explicit outer COMPARE code when optabs
2873+     is testing whether a constant is expensive enough to force into a
2874+     register.  We want optabs to pass such constants through the MIPS
2875+     expanders instead, so make all constants very cheap here.  */
2876+  if (outer_code == COMPARE)
2877+    {
2878+      gcc_assert (CONSTANT_P (x));
2879+      *total = 0;
2880+      return true;
2881+    }
2882+
2883+  switch (code)
2884+    {
2885+    case CONST_INT:
2886+      /* Treat *clear_upper32-style ANDs as having zero cost in the
2887+        second operand.  The cost is entirely in the first operand.
2888+
2889+        ??? This is needed because we would otherwise try to CSE
2890+        the constant operand.  Although that's the right thing for
2891+        instructions that continue to be a register operation throughout
2892+        compilation, it is disastrous for instructions that could
2893+        later be converted into a memory operation.  */
2894+      if (TARGET_64BIT
2895+         && outer_code == AND
2896+         && UINTVAL (x) == 0xffffffff)
2897+       {
2898+         *total = 0;
2899+         return true;
2900+       }
2901+
2902+      /* When not optimizing for size, we care more about the cost
2903+         of hot code, and hot code is often in a loop.  If a constant
2904+         operand needs to be forced into a register, we will often be
2905+         able to hoist the constant load out of the loop, so the load
2906+         should not contribute to the cost.  */
2907+      if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
2908+        {
2909+          *total = 0;
2910+          return true;
2911+        }
2912+      /* Fall through.  */
2913+
2914+    case CONST:
2915+    case SYMBOL_REF:
2916+    case LABEL_REF:
2917+    case CONST_DOUBLE:
2918+      cost = mips_const_insns (x);
2919+      if (cost > 0)
2920+       {
2921+         /* If the constant is likely to be stored in a GPR, SETs of
2922+            single-insn constants are as cheap as register sets; we
2923+            never want to CSE them.
2924+
2925+            Don't reduce the cost of storing a floating-point zero in
2926+            FPRs.  If we have a zero in an FPR for other reasons, we
2927+            can get better cfg-cleanup and delayed-branch results by
2928+            using it consistently, rather than using $0 sometimes and
2929+            an FPR at other times.  Also, moves between floating-point
2930+            registers are sometimes cheaper than (D)MTC1 $0.  */
2931+         if (cost == 1
2932+             && outer_code == SET
2933+             && !(float_mode_p && TARGET_HARD_FLOAT))
2934+           cost = 0;
2935+         /* When non-MIPS16 code loads a constant N>1 times, we rarely
2936+            want to CSE the constant itself.  It is usually better to
2937+            have N copies of the last operation in the sequence and one
2938+            shared copy of the other operations.  (Note that this is
2939+            not true for MIPS16 code, where the final operation in the
2940+            sequence is often an extended instruction.)
2941+
2942+            Also, if we have a CONST_INT, we don't know whether it is
2943+            for a word or doubleword operation, so we cannot rely on
2944+            the result of riscv_build_integer.  */
2945+         else if (outer_code == SET || mode == VOIDmode)
2946+           cost = 1;
2947+         *total = COSTS_N_INSNS (cost);
2948+         return true;
2949+       }
2950+      /* The value will need to be fetched from the constant pool.  */
2951+      *total = CONSTANT_POOL_COST;
2952+      return true;
2953+
2954+    case MEM:
2955+      /* If the address is legitimate, return the number of
2956+        instructions it needs.  */
2957+      addr = XEXP (x, 0);
2958+      cost = mips_address_insns (addr, mode, true);
2959+      if (cost > 0)
2960+       {
2961+         *total = COSTS_N_INSNS (cost + (speed ? mips_cost->memory_latency : 1));
2962+         return true;
2963+       }
2964+      /* Otherwise use the default handling.  */
2965+      return false;
2966+
2967+    case FFS:
2968+      *total = COSTS_N_INSNS (6);
2969+      return false;
2970+
2971+    case NOT:
2972+      *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
2973+      return false;
2974+
2975+    case AND:
2976+      /* Check for a *clear_upper32 pattern and treat it like a zero
2977+        extension.  See the pattern's comment for details.  */
2978+      if (TARGET_64BIT
2979+         && mode == DImode
2980+         && CONST_INT_P (XEXP (x, 1))
2981+         && UINTVAL (XEXP (x, 1)) == 0xffffffff)
2982+       {
2983+         *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
2984+                   + rtx_cost (XEXP (x, 0), SET, speed));
2985+         return true;
2986+       }
2987+      /* Fall through.  */
2988+
2989+    case IOR:
2990+    case XOR:
2991+      /* Double-word operations use two single-word operations.  */
2992+      *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
2993+                                speed);
2994+      return true;
2995+
2996+    case ASHIFT:
2997+    case ASHIFTRT:
2998+    case LSHIFTRT:
2999+    case ROTATE:
3000+    case ROTATERT:
3001+      if (CONSTANT_P (XEXP (x, 1)))
3002+       *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3003+                                  speed);
3004+      else
3005+       *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3006+                                  speed);
3007+      return true;
3008+
3009+    case ABS:
3010+      if (float_mode_p)
3011+        *total = mips_cost->fp_add;
3012+      else
3013+        *total = COSTS_N_INSNS (4);
3014+      return false;
3015+
3016+    case LO_SUM:
3017+      /* Low-part immediates need an extended MIPS16 instruction.  */
3018+      *total = (COSTS_N_INSNS (1)
3019+               + rtx_cost (XEXP (x, 0), SET, speed));
3020+      return true;
3021+
3022+    case LT:
3023+    case LTU:
3024+    case LE:
3025+    case LEU:
3026+    case GT:
3027+    case GTU:
3028+    case GE:
3029+    case GEU:
3030+    case EQ:
3031+    case NE:
3032+    case UNORDERED:
3033+    case LTGT:
3034+      /* Branch comparisons have VOIDmode, so use the first operand's
3035+        mode instead.  */
3036+      mode = GET_MODE (XEXP (x, 0));
3037+      if (FLOAT_MODE_P (mode))
3038+       {
3039+         *total = mips_cost->fp_add;
3040+         return false;
3041+       }
3042+      *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3043+                                speed);
3044+      return true;
3045+
3046+    case MINUS:
3047+      if (float_mode_p
3048+         && !HONOR_NANS (mode)
3049+         && !HONOR_SIGNED_ZEROS (mode))
3050+       {
3051+         /* See if we can use NMADD or NMSUB.  See mips.md for the
3052+            associated patterns.  */
3053+         rtx op0 = XEXP (x, 0);
3054+         rtx op1 = XEXP (x, 1);
3055+         if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3056+           {
3057+             *total = (mips_fp_mult_cost (mode)
3058+                       + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3059+                       + rtx_cost (XEXP (op0, 1), SET, speed)
3060+                       + rtx_cost (op1, SET, speed));
3061+             return true;
3062+           }
3063+         if (GET_CODE (op1) == MULT)
3064+           {
3065+             *total = (mips_fp_mult_cost (mode)
3066+                       + rtx_cost (op0, SET, speed)
3067+                       + rtx_cost (XEXP (op1, 0), SET, speed)
3068+                       + rtx_cost (XEXP (op1, 1), SET, speed));
3069+             return true;
3070+           }
3071+       }
3072+      /* Fall through.  */
3073+
3074+    case PLUS:
3075+      if (float_mode_p)
3076+       {
3077+         /* If this is part of a MADD or MSUB, treat the PLUS as
3078+            being free.  */
3079+         if (GET_CODE (XEXP (x, 0)) == MULT)
3080+           *total = 0;
3081+         else
3082+           *total = mips_cost->fp_add;
3083+         return false;
3084+       }
3085+
3086+      /* Double-word operations require three single-word operations and
3087+        an SLTU.  The MIPS16 version then needs to move the result of
3088+        the SLTU from $24 to a MIPS16 register.  */
3089+      *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3090+                                COSTS_N_INSNS (4),
3091+                                speed);
3092+      return true;
3093+
3094+    case NEG:
3095+      if (float_mode_p
3096+         && !HONOR_NANS (mode)
3097+         && HONOR_SIGNED_ZEROS (mode))
3098+       {
3099+         /* See if we can use NMADD or NMSUB.  See mips.md for the
3100+            associated patterns.  */
3101+         rtx op = XEXP (x, 0);
3102+         if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3103+             && GET_CODE (XEXP (op, 0)) == MULT)
3104+           {
3105+             *total = (mips_fp_mult_cost (mode)
3106+                       + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3107+                       + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3108+                       + rtx_cost (XEXP (op, 1), SET, speed));
3109+             return true;
3110+           }
3111+       }
3112+
3113+      if (float_mode_p)
3114+       *total = mips_cost->fp_add;
3115+      else
3116+       *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3117+      return false;
3118+
3119+    case MULT:
3120+      if (float_mode_p)
3121+       *total = mips_fp_mult_cost (mode);
3122+      else if (mode == DImode && !TARGET_64BIT)
3123+       /* We use a MUL and a MULH[[S]U]. */
3124+       *total = mips_cost->int_mult_si * 2;
3125+      else if (!speed)
3126+       *total = 1;
3127+      else if (mode == DImode)
3128+       *total = mips_cost->int_mult_di;
3129+      else
3130+       *total = mips_cost->int_mult_si;
3131+      return false;
3132+
3133+    case DIV:
3134+      /* Check for a reciprocal.  */
3135+      if (float_mode_p
3136+         && flag_unsafe_math_optimizations
3137+         && XEXP (x, 0) == CONST1_RTX (mode))
3138+       {
3139+         if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3140+           /* An rsqrt<mode>a or rsqrt<mode>b pattern.  Count the
3141+              division as being free.  */
3142+           *total = rtx_cost (XEXP (x, 1), SET, speed);
3143+         else
3144+           *total = (mips_fp_div_cost (mode)
3145+                     + rtx_cost (XEXP (x, 1), SET, speed));
3146+         return true;
3147+       }
3148+      /* Fall through.  */
3149+
3150+    case SQRT:
3151+    case MOD:
3152+      if (float_mode_p)
3153+       {
3154+         *total = mips_fp_div_cost (mode);
3155+         return false;
3156+       }
3157+      /* Fall through.  */
3158+
3159+    case UDIV:
3160+    case UMOD:
3161+      if (!speed)
3162+       *total = 1;
3163+      else if (mode == DImode)
3164+        *total = mips_cost->int_div_di;
3165+      else
3166+       *total = mips_cost->int_div_si;
3167+      return false;
3168+
3169+    case SIGN_EXTEND:
3170+      *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3171+      return false;
3172+
3173+    case ZERO_EXTEND:
3174+      *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3175+      return false;
3176+
3177+    case FLOAT:
3178+    case UNSIGNED_FLOAT:
3179+    case FIX:
3180+    case FLOAT_EXTEND:
3181+    case FLOAT_TRUNCATE:
3182+      *total = mips_cost->fp_add;
3183+      return false;
3184+
3185+    default:
3186+      return false;
3187+    }
3188+}
3189+
3190+/* Implement TARGET_ADDRESS_COST.  */
3191+
3192+static int
3193+mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3194+{
3195+  return mips_address_insns (addr, SImode, false);
3196+}
3197+
3198+/* Return one word of double-word value OP, taking into account the fixed
3199+   endianness of certain registers.  HIGH_P is true to select the high part,
3200+   false to select the low part.  */
3201+
3202+rtx
3203+mips_subword (rtx op, bool high_p)
3204+{
3205+  unsigned int byte, offset;
3206+  enum machine_mode mode;
3207+
3208+  mode = GET_MODE (op);
3209+  if (mode == VOIDmode)
3210+    mode = TARGET_64BIT ? TImode : DImode;
3211+
3212+  if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3213+    byte = UNITS_PER_WORD;
3214+  else
3215+    byte = 0;
3216+
3217+  if (FP_REG_RTX_P (op))
3218+    {
3219+      /* Paired FPRs are always ordered little-endian.  */
3220+      offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3221+      return gen_rtx_REG (word_mode, REGNO (op) + offset);
3222+    }
3223+
3224+  if (MEM_P (op))
3225+    return adjust_address (op, word_mode, byte);
3226+
3227+  return simplify_gen_subreg (word_mode, op, mode, byte);
3228+}
3229+
3230+/* Return true if a 64-bit move from SRC to DEST should be split into two.  */
3231+
3232+bool
3233+mips_split_64bit_move_p (rtx dest, rtx src)
3234+{
3235+  /* All 64b moves are legal in 64b mode.  All 64b FPR <-> FPR and
3236+     FPR <-> MEM moves are legal in 32b mode, too.  Although
3237+     FPR <-> GPR moves are not available in general in 32b mode,
3238+     we can at least load 0 into an FPR with fcvt.d.w fpr, x0. */
3239+  return !(TARGET_64BIT
3240+          || (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3241+          || (FP_REG_RTX_P (dest) && MEM_P (src))
3242+          || (FP_REG_RTX_P (src) && MEM_P (dest))
3243+          || (FP_REG_RTX_P(dest) && src == CONST0_RTX(GET_MODE(src))));
3244+}
3245+
3246+/* Split a doubleword move from SRC to DEST.  On 32-bit targets,
3247+   this function handles 64-bit moves for which mips_split_64bit_move_p
3248+   holds.  For 64-bit targets, this function handles 128-bit moves.  */
3249+
3250+void
3251+mips_split_doubleword_move (rtx dest, rtx src)
3252+{
3253+  rtx low_dest;
3254+
3255+   /* The operation can be split into two normal moves.  Decide in
3256+      which order to do them.  */
3257+   low_dest = mips_subword (dest, false);
3258+   if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src))
3259+     {
3260+       mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3261+       mips_emit_move (low_dest, mips_subword (src, false));
3262+     }
3263+   else
3264+     {
3265+       mips_emit_move (low_dest, mips_subword (src, false));
3266+       mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3267+     }
3268+}
3269+
3270+/* Return the appropriate instructions to move SRC into DEST.  Assume
3271+   that SRC is operand 1 and DEST is operand 0.  */
3272+
3273+const char *
3274+mips_output_move (rtx dest, rtx src)
3275+{
3276+  enum rtx_code dest_code, src_code;
3277+  enum machine_mode mode;
3278+  enum mips_symbol_type symbol_type;
3279+  bool dbl_p;
3280+
3281+  dest_code = GET_CODE (dest);
3282+  src_code = GET_CODE (src);
3283+  mode = GET_MODE (dest);
3284+  dbl_p = (GET_MODE_SIZE (mode) == 8);
3285+
3286+  if (dbl_p && mips_split_64bit_move_p (dest, src))
3287+    return "#";
3288+
3289+  if ((src_code == REG && GP_REG_P (REGNO (src)))
3290+      || (src == CONST0_RTX (mode)))
3291+    {
3292+      if (dest_code == REG)
3293+       {
3294+         if (GP_REG_P (REGNO (dest)))
3295+           return "move\t%0,%z1";
3296+
3297+         if (FP_REG_P (REGNO (dest)))
3298+           {
3299+             if (!dbl_p)
3300+               return "mxtf.s\t%0,%z1";
3301+             if (TARGET_64BIT)
3302+               return "mxtf.d\t%0,%z1";
3303+             /* in RV32, we can emulate mxtf.d %0, x0 using fcvt.d.w */
3304+             gcc_assert (src == CONST0_RTX (mode));
3305+             return "fcvt.d.w\t%0,x0";
3306+           }
3307+       }
3308+      if (dest_code == MEM)
3309+       switch (GET_MODE_SIZE (mode))
3310+         {
3311+         case 1: return "sb\t%z1,%0";
3312+         case 2: return "sh\t%z1,%0";
3313+         case 4: return "sw\t%z1,%0";
3314+         case 8: return "sd\t%z1,%0";
3315+         }
3316+    }
3317+  if (dest_code == REG && GP_REG_P (REGNO (dest)))
3318+    {
3319+      if (src_code == REG)
3320+       {
3321+         if (FP_REG_P (REGNO (src)))
3322+           return dbl_p ? "mftx.d\t%0,%1" : "mftx.s\t%0,%1";
3323+       }
3324+
3325+      if (src_code == MEM)
3326+       switch (GET_MODE_SIZE (mode))
3327+         {
3328+         case 1: return "lbu\t%0,%1";
3329+         case 2: return "lhu\t%0,%1";
3330+         case 4: return "lw\t%0,%1";
3331+         case 8: return "ld\t%0,%1";
3332+         }
3333+
3334+      if (src_code == CONST_INT)
3335+       return "li\t%0,%1\t\t\t# %X1";
3336+
3337+      if (src_code == HIGH)
3338+       return "lui\t%0,%h1";
3339+
3340+      if (mips_symbolic_constant_p (src, &symbol_type)
3341+         && mips_lo_relocs[symbol_type] != 0)
3342+       {
3343+         /* A signed 16-bit constant formed by applying a relocation
3344+            operator to a symbolic address.  */
3345+         gcc_assert (!mips_split_p[symbol_type]);
3346+         return "li\t%0,%R1";
3347+       }
3348+
3349+      if (symbolic_operand (src, VOIDmode))
3350+       {
3351+         gcc_assert (flag_pic);
3352+         return "la\t%0,%1";
3353+       }
3354+    }
3355+  if (src_code == REG && FP_REG_P (REGNO (src)))
3356+    {
3357+      if (dest_code == REG && FP_REG_P (REGNO (dest)))
3358+       return dbl_p ? "fsgnj.d\t%0,%1,%1" : "fsgnj.s\t%0,%1,%1";
3359+
3360+      if (dest_code == MEM)
3361+       return dbl_p ? "fsd\t%1,%0" : "fsw\t%1,%0";
3362+    }
3363+  if (dest_code == REG && FP_REG_P (REGNO (dest)))
3364+    {
3365+      if (src_code == MEM)
3366+       return dbl_p ? "fld\t%0,%1" : "flw\t%0,%1";
3367+    }
3368+  gcc_unreachable ();
3369+}
3370+
3371+/* Return true if CMP1 is a suitable second operand for integer ordering
3372+   test CODE.  See also the *sCC patterns in mips.md.  */
3373+
3374+static bool
3375+mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
3376+{
3377+  switch (code)
3378+    {
3379+    case GT:
3380+    case GTU:
3381+      return reg_or_0_operand (cmp1, VOIDmode);
3382+
3383+    case GE:
3384+    case GEU:
3385+      return cmp1 == const1_rtx;
3386+
3387+    case LT:
3388+    case LTU:
3389+      return arith_operand (cmp1, VOIDmode);
3390+
3391+    case LE:
3392+      return sle_operand (cmp1, VOIDmode);
3393+
3394+    case LEU:
3395+      return sleu_operand (cmp1, VOIDmode);
3396+
3397+    default:
3398+      gcc_unreachable ();
3399+    }
3400+}
3401+
3402+/* Return true if *CMP1 (of mode MODE) is a valid second operand for
3403+   integer ordering test *CODE, or if an equivalent combination can
3404+   be formed by adjusting *CODE and *CMP1.  When returning true, update
3405+   *CODE and *CMP1 with the chosen code and operand, otherwise leave
3406+   them alone.  */
3407+
3408+static bool
3409+mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
3410+                                 enum machine_mode mode)
3411+{
3412+  HOST_WIDE_INT plus_one;
3413+
3414+  if (mips_int_order_operand_ok_p (*code, *cmp1))
3415+    return true;
3416+
3417+  if (CONST_INT_P (*cmp1))
3418+    switch (*code)
3419+      {
3420+      case LE:
3421+       plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3422+       if (INTVAL (*cmp1) < plus_one)
3423+         {
3424+           *code = LT;
3425+           *cmp1 = force_reg (mode, GEN_INT (plus_one));
3426+           return true;
3427+         }
3428+       break;
3429+
3430+      case LEU:
3431+       plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3432+       if (plus_one != 0)
3433+         {
3434+           *code = LTU;
3435+           *cmp1 = force_reg (mode, GEN_INT (plus_one));
3436+           return true;
3437+         }
3438+       break;
3439+
3440+      default:
3441+       break;
3442+      }
3443+  return false;
3444+}
3445+
3446+/* Compare CMP0 and CMP1 using ordering test CODE and store the result
3447+   in TARGET.  CMP0 and TARGET are register_operands.  If INVERT_PTR
3448+   is nonnull, it's OK to set TARGET to the inverse of the result and
3449+   flip *INVERT_PTR instead.  */
3450+
3451+static void
3452+mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
3453+                         rtx target, rtx cmp0, rtx cmp1)
3454+{
3455+  enum machine_mode mode;
3456+
3457+  /* First see if there is a MIPS instruction that can do this operation.
3458+     If not, try doing the same for the inverse operation.  If that also
3459+     fails, force CMP1 into a register and try again.  */
3460+  mode = GET_MODE (cmp0);
3461+  if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
3462+    mips_emit_binary (code, target, cmp0, cmp1);
3463+  else
3464+    {
3465+      enum rtx_code inv_code = reverse_condition (code);
3466+      if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
3467+       {
3468+         cmp1 = force_reg (mode, cmp1);
3469+         mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
3470+       }
3471+      else if (invert_ptr == 0)
3472+       {
3473+         rtx inv_target;
3474+
3475+         inv_target = mips_force_binary (GET_MODE (target),
3476+                                         inv_code, cmp0, cmp1);
3477+         mips_emit_binary (XOR, target, inv_target, const1_rtx);
3478+       }
3479+      else
3480+       {
3481+         *invert_ptr = !*invert_ptr;
3482+         mips_emit_binary (inv_code, target, cmp0, cmp1);
3483+       }
3484+    }
3485+}
3486+
3487+/* Return a register that is zero iff CMP0 and CMP1 are equal.
3488+   The register will have the same mode as CMP0.  */
3489+
3490+static rtx
3491+mips_zero_if_equal (rtx cmp0, rtx cmp1)
3492+{
3493+  if (cmp1 == const0_rtx)
3494+    return cmp0;
3495+
3496+  return expand_binop (GET_MODE (cmp0), sub_optab,
3497+                      cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3498+}
3499+
3500+/* Convert *CODE into a code that can be used in a floating-point
3501+   scc instruction (C.cond.fmt).  Return true if the values of
3502+   the condition code registers will be inverted, with 0 indicating
3503+   that the condition holds.  */
3504+
3505+static bool
3506+mips_reversed_fp_cond (enum rtx_code *code)
3507+{
3508+  switch (*code)
3509+    {
3510+    case NE:
3511+    case LTGT:
3512+    case ORDERED:
3513+      *code = reverse_condition_maybe_unordered (*code);
3514+      return true;
3515+
3516+    default:
3517+      return false;
3518+    }
3519+}
3520+
3521+/* Convert a comparison into something that can be used in a branch or
3522+   conditional move.  On entry, *OP0 and *OP1 are the values being
3523+   compared and *CODE is the code used to compare them.
3524+
3525+   Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3526+   If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
3527+   otherwise any standard branch condition can be used.  The standard branch
3528+   conditions are:
3529+
3530+      - EQ or NE between two registers.
3531+      - any comparison between a register and zero.  */
3532+
3533+static void
3534+mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3535+{
3536+  rtx cmp_op0 = *op0;
3537+  rtx cmp_op1 = *op1;
3538+
3539+  if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
3540+    {
3541+      if (!need_eq_ne_p && *op1 == const0_rtx)
3542+       ;
3543+      else if (*code == EQ || *code == NE)
3544+       {
3545+         if (need_eq_ne_p)
3546+           {
3547+             *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
3548+             *op1 = const0_rtx;
3549+           }
3550+         else
3551+           *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
3552+       }
3553+      else
3554+       {
3555+         /* The comparison needs a separate scc instruction.  Store the
3556+            result of the scc in *OP0 and compare it against zero.  */
3557+         bool invert = false;
3558+         *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
3559+         mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
3560+         *code = (invert ? EQ : NE);
3561+         *op1 = const0_rtx;
3562+       }
3563+    }
3564+  else
3565+    {
3566+      enum rtx_code cmp_code;
3567+
3568+      /* Floating-point tests use a separate C.cond.fmt comparison to
3569+        set a condition code register.  The branch or conditional move
3570+        will then compare that register against zero.
3571+
3572+        Set CMP_CODE to the code of the comparison instruction and
3573+        *CODE to the code that the branch or move should use.  */
3574+      cmp_code = *code;
3575+      *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
3576+      *op0 = gen_reg_rtx (SImode);
3577+      *op1 = const0_rtx;
3578+      mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
3579+    }
3580+}
3581+
3582+/* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
3583+   and OPERAND[3].  Store the result in OPERANDS[0].
3584+
3585+   On 64-bit targets, the mode of the comparison and target will always be
3586+   SImode, thus possibly narrower than that of the comparison's operands.  */
3587+
3588+void
3589+mips_expand_scc (rtx operands[])
3590+{
3591+  rtx target = operands[0];
3592+  enum rtx_code code = GET_CODE (operands[1]);
3593+  rtx op0 = operands[2];
3594+  rtx op1 = operands[3];
3595+
3596+  gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
3597+
3598+  if (code == EQ || code == NE)
3599+    {
3600+      rtx zie = mips_zero_if_equal (op0, op1);
3601+      mips_emit_binary (code, target, zie, const0_rtx);
3602+    }
3603+  else
3604+    mips_emit_int_order_test (code, 0, target, op0, op1);
3605+}
3606+
3607+/* Compare OPERANDS[1] with OPERANDS[2] using comparison code
3608+   CODE and jump to OPERANDS[3] if the condition holds.  */
3609+
3610+void
3611+mips_expand_conditional_branch (rtx *operands)
3612+{
3613+  enum rtx_code code = GET_CODE (operands[0]);
3614+  rtx op0 = operands[1];
3615+  rtx op1 = operands[2];
3616+  rtx condition;
3617+
3618+  mips_emit_compare (&code, &op0, &op1, false);
3619+  condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3620+  emit_jump_insn (gen_condjump (condition, operands[3]));
3621+}
3622+
3623+/* Perform the comparison in OPERANDS[1].  Move OPERANDS[2] into OPERANDS[0]
3624+   if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0].  */
3625+
3626+void
3627+mips_expand_conditional_move (rtx *operands)
3628+{
3629+  rtx cond;
3630+  enum rtx_code code = GET_CODE (operands[1]);
3631+  rtx op0 = XEXP (operands[1], 0);
3632+  rtx op1 = XEXP (operands[1], 1);
3633+
3634+  mips_emit_compare (&code, &op0, &op1, true);
3635+  cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
3636+  emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3637+                         gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
3638+                                               operands[2], operands[3])));
3639+}
3640+
3641+/* Initialize *CUM for a call to a function of type FNTYPE.  */
3642+
3643+void
3644+mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype ATTRIBUTE_UNUSED)
3645+{
3646+  memset (cum, 0, sizeof (*cum));
3647+}
3648+
3649+/* Fill INFO with information about a single argument.  CUM is the
3650+   cumulative state for earlier arguments.  MODE is the mode of this
3651+   argument and TYPE is its type (if known).  NAMED is true if this
3652+   is a named (fixed) argument rather than a variable one.  */
3653+
3654+static void
3655+mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
3656+                  enum machine_mode mode, const_tree type, bool named)
3657+{
3658+  bool doubleword_aligned_p;
3659+  unsigned int num_bytes, num_words, max_regs;
3660+
3661+  /* Work out the size of the argument.  */
3662+  num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3663+  num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3664+
3665+  /* Scalar, complex and vector floating-point types are passed in
3666+     floating-point registers, as long as this is a named rather
3667+     than a variable argument.  */
3668+  info->fpr_p = (named
3669+                && (type == 0 || FLOAT_TYPE_P (type))
3670+                && (GET_MODE_CLASS (mode) == MODE_FLOAT
3671+                    || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3672+                    || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3673+                && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3674+
3675+  /* ??? According to the ABI documentation, the real and imaginary
3676+     parts of complex floats should be passed in individual registers.
3677+     The real and imaginary parts of stack arguments are supposed
3678+     to be contiguous and there should be an extra word of padding
3679+     at the end.
3680+
3681+     This has two problems.  First, it makes it impossible to use a
3682+     single "void *" va_list type, since register and stack arguments
3683+     are passed differently.  (At the time of writing, MIPSpro cannot
3684+     handle complex float varargs correctly.)  Second, it's unclear
3685+     what should happen when there is only one register free.
3686+
3687+     For now, we assume that named complex floats should go into FPRs
3688+     if there are two FPRs free, otherwise they should be passed in the
3689+     same way as a struct containing two floats.  */
3690+  if (info->fpr_p
3691+      && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3692+      && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3693+    {
3694+      if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3695+        info->fpr_p = false;
3696+      else
3697+        num_words = 2;
3698+    }
3699+
3700+  /* See whether the argument has doubleword alignment.  */
3701+  doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
3702+                         > BITS_PER_WORD);
3703+
3704+  /* Set REG_OFFSET to the register count we're interested in.
3705+     The EABI allocates the floating-point registers separately,
3706+     but the other ABIs allocate them like integer registers.  */
3707+  info->reg_offset = cum->num_gprs;
3708+
3709+  /* Advance to an even register if the argument is doubleword-aligned.  */
3710+  if (doubleword_aligned_p)
3711+    info->reg_offset += info->reg_offset & 1;
3712+
3713+  /* Work out the offset of a stack argument.  */
3714+  info->stack_offset = cum->stack_words;
3715+  if (doubleword_aligned_p)
3716+    info->stack_offset += info->stack_offset & 1;
3717+
3718+  max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3719+
3720+  /* Partition the argument between registers and stack.  */
3721+  info->reg_words = MIN (num_words, max_regs);
3722+  info->stack_words = num_words - info->reg_words;
3723+}
3724+
3725+/* INFO describes a register argument that has the normal format for the
3726+   argument's mode.  Return the register it uses, assuming that FPRs are
3727+   available if HARD_FLOAT_P.  */
3728+
3729+static unsigned int
3730+mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
3731+{
3732+  if (!info->fpr_p || !hard_float_p)
3733+    return GP_ARG_FIRST + info->reg_offset;
3734+  else
3735+    return FP_ARG_FIRST + info->reg_offset;
3736+}
3737+
3738+/* Implement TARGET_FUNCTION_ARG.  */
3739+
3740+static rtx
3741+mips_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3742+                  const_tree type, bool named)
3743+{
3744+  struct mips_arg_info info;
3745+
3746+  if (mode == VOIDmode)
3747+    return NULL;
3748+
3749+  mips_get_arg_info (&info, cum, mode, type, named);
3750+
3751+  /* Return straight away if the whole argument is passed on the stack.  */
3752+  if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3753+    return NULL;
3754+
3755+  /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
3756+     contains a double in its entirety, then that 64-bit chunk is passed
3757+     in a floating-point register.  */
3758+  if (TARGET_HARD_FLOAT
3759+      && named
3760+      && type != 0
3761+      && TREE_CODE (type) == RECORD_TYPE
3762+      && TYPE_SIZE_UNIT (type)
3763+      && host_integerp (TYPE_SIZE_UNIT (type), 1))
3764+    {
3765+      tree field;
3766+
3767+      /* First check to see if there is any such field.  */
3768+      for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
3769+       if (TREE_CODE (field) == FIELD_DECL
3770+           && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
3771+           && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3772+           && host_integerp (bit_position (field), 0)
3773+           && int_bit_position (field) % BITS_PER_WORD == 0)
3774+         break;
3775+
3776+      if (field != 0)
3777+       {
3778+         /* Now handle the special case by returning a PARALLEL
3779+            indicating where each 64-bit chunk goes.  INFO.REG_WORDS
3780+            chunks are passed in registers.  */
3781+         unsigned int i;
3782+         HOST_WIDE_INT bitpos;
3783+         rtx ret;
3784+
3785+         /* assign_parms checks the mode of ENTRY_PARM, so we must
3786+            use the actual mode here.  */
3787+         ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3788+
3789+         bitpos = 0;
3790+         field = TYPE_FIELDS (type);
3791+         for (i = 0; i < info.reg_words; i++)
3792+           {
3793+             rtx reg;
3794+
3795+             for (; field; field = DECL_CHAIN (field))
3796+               if (TREE_CODE (field) == FIELD_DECL
3797+                   && int_bit_position (field) >= bitpos)
3798+                 break;
3799+
3800+             if (field
3801+                 && int_bit_position (field) == bitpos
3802+                 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
3803+                 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3804+               reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3805+             else
3806+               reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3807+
3808+             XVECEXP (ret, 0, i)
3809+               = gen_rtx_EXPR_LIST (VOIDmode, reg,
3810+                                    GEN_INT (bitpos / BITS_PER_UNIT));
3811+
3812+             bitpos += BITS_PER_WORD;
3813+           }
3814+         return ret;
3815+       }
3816+    }
3817+
3818+  /* Handle the n32/n64 conventions for passing complex floating-point
3819+     arguments in FPR pairs.  The real part goes in the lower register
3820+     and the imaginary part goes in the upper register.  */
3821+  if (info.fpr_p
3822+      && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3823+    {
3824+      rtx real, imag;
3825+      enum machine_mode inner;
3826+      unsigned int regno;
3827+
3828+      inner = GET_MODE_INNER (mode);
3829+      regno = FP_ARG_FIRST + info.reg_offset;
3830+      if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
3831+       {
3832+         /* Real part in registers, imaginary part on stack.  */
3833+         gcc_assert (info.stack_words == info.reg_words);
3834+         return gen_rtx_REG (inner, regno);
3835+       }
3836+      else
3837+       {
3838+         gcc_assert (info.stack_words == 0);
3839+         real = gen_rtx_EXPR_LIST (VOIDmode,
3840+                                   gen_rtx_REG (inner, regno),
3841+                                   const0_rtx);
3842+         imag = gen_rtx_EXPR_LIST (VOIDmode,
3843+                                   gen_rtx_REG (inner,
3844+                                                regno + info.reg_words / 2),
3845+                                   GEN_INT (GET_MODE_SIZE (inner)));
3846+         return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3847+       }
3848+    }
3849+
3850+  return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
3851+}
3852+
3853+/* Implement TARGET_FUNCTION_ARG_ADVANCE.  */
3854+
3855+static void
3856+mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3857+                          const_tree type, bool named)
3858+{
3859+  struct mips_arg_info info;
3860+
3861+  mips_get_arg_info (&info, cum, mode, type, named);
3862+
3863+  /* Advance the register count.  This has the effect of setting
3864+     num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
3865+     argument required us to skip the final GPR and pass the whole
3866+     argument on the stack.  */
3867+  cum->num_gprs = info.reg_offset + info.reg_words;
3868+
3869+  /* Advance the stack word count.  */
3870+  if (info.stack_words > 0)
3871+    cum->stack_words = info.stack_offset + info.stack_words;
3872+}
3873+
3874+/* Implement TARGET_ARG_PARTIAL_BYTES.  */
3875+
3876+static int
3877+mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3878+                       enum machine_mode mode, tree type, bool named)
3879+{
3880+  struct mips_arg_info info;
3881+
3882+  mips_get_arg_info (&info, cum, mode, type, named);
3883+  return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3884+}
3885+
3886+/* Implement TARGET_FUNCTION_ARG_BOUNDARY.  Every parameter gets at
3887+   least PARM_BOUNDARY bits of alignment, but will be given anything up
3888+   to STACK_BOUNDARY bits if the type requires it.  */
3889+
3890+static unsigned int
3891+mips_function_arg_boundary (enum machine_mode mode, const_tree type)
3892+{
3893+  unsigned int alignment;
3894+
3895+  alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3896+  if (alignment < PARM_BOUNDARY)
3897+    alignment = PARM_BOUNDARY;
3898+  if (alignment > STACK_BOUNDARY)
3899+    alignment = STACK_BOUNDARY;
3900+  return alignment;
3901+}
3902+
3903+/* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3904+   upward rather than downward.  In other words, return true if the
3905+   first byte of the stack slot has useful data, false if the last
3906+   byte does.  */
3907+
3908+bool
3909+mips_pad_arg_upward (enum machine_mode mode, const_tree type)
3910+{
3911+  /* On little-endian targets, the first byte of every stack argument
3912+     is passed in the first byte of the stack slot.  */
3913+  if (!BYTES_BIG_ENDIAN)
3914+    return true;
3915+
3916+  /* Otherwise, integral types are padded downward: the last byte of a
3917+     stack argument is passed in the last byte of the stack slot.  */
3918+  if (type != 0
3919+      ? (INTEGRAL_TYPE_P (type)
3920+        || POINTER_TYPE_P (type)
3921+        || FIXED_POINT_TYPE_P (type))
3922+      : (SCALAR_INT_MODE_P (mode)
3923+        || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
3924+    return false;
3925+
3926+  return true;
3927+}
3928+
3929+/* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...).  Return !BYTES_BIG_ENDIAN
3930+   if the least significant byte of the register has useful data.  Return
3931+   the opposite if the most significant byte does.  */
3932+
3933+bool
3934+mips_pad_reg_upward (enum machine_mode mode, tree type)
3935+{
3936+  /* No shifting is required for floating-point arguments.  */
3937+  if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3938+    return !BYTES_BIG_ENDIAN;
3939+
3940+  /* Otherwise, apply the same padding to register arguments as we do
3941+     to stack arguments.  */
3942+  return mips_pad_arg_upward (mode, type);
3943+}
3944+
3945+/* See whether VALTYPE is a record whose fields should be returned in
3946+   floating-point registers.  If so, return the number of fields and
3947+   list them in FIELDS (which should have two elements).  Return 0
3948+   otherwise.
3949+
3950+   For n32 & n64, a structure with one or two fields is returned in
3951+   floating-point registers as long as every field has a floating-point
3952+   type.  */
3953+
3954+static int
3955+mips_fpr_return_fields (const_tree valtype, tree *fields)
3956+{
3957+  tree field;
3958+  int i;
3959+
3960+  if (TREE_CODE (valtype) != RECORD_TYPE)
3961+    return 0;
3962+
3963+  i = 0;
3964+  for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
3965+    {
3966+      if (TREE_CODE (field) != FIELD_DECL)
3967+       continue;
3968+
3969+      if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
3970+       return 0;
3971+
3972+      if (i == 2)
3973+       return 0;
3974+
3975+      fields[i++] = field;
3976+    }
3977+  return i;
3978+}
3979+
3980+/* Implement TARGET_RETURN_IN_MSB.  For n32 & n64, we should return
3981+   a value in the most significant part of $2/$3 if:
3982+
3983+      - the target is big-endian;
3984+
3985+      - the value has a structure or union type (we generalize this to
3986+       cover aggregates from other languages too); and
3987+
3988+      - the structure is not returned in floating-point registers.  */
3989+
3990+static bool
3991+mips_return_in_msb (const_tree valtype)
3992+{
3993+  tree fields[2];
3994+
3995+  return (TARGET_BIG_ENDIAN
3996+         && AGGREGATE_TYPE_P (valtype)
3997+         && mips_fpr_return_fields (valtype, fields) == 0);
3998+}
3999+
4000+/* Return true if the function return value MODE will get returned in a
4001+   floating-point register.  */
4002+
4003+static bool
4004+mips_return_mode_in_fpr_p (enum machine_mode mode)
4005+{
4006+  return ((GET_MODE_CLASS (mode) == MODE_FLOAT
4007+          || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
4008+          || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4009+         && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
4010+}
4011+
4012+/* Return the representation of an FPR return register when the
4013+   value being returned in FP_RETURN has mode VALUE_MODE and the
4014+   return type itself has mode TYPE_MODE.  On NewABI targets,
4015+   the two modes may be different for structures like:
4016+
4017+       struct __attribute__((packed)) foo { float f; }
4018+
4019+   where we return the SFmode value of "f" in FP_RETURN, but where
4020+   the structure itself has mode BLKmode.  */
4021+
4022+static rtx
4023+mips_return_fpr_single (enum machine_mode type_mode,
4024+                       enum machine_mode value_mode)
4025+{
4026+  rtx x;
4027+
4028+  x = gen_rtx_REG (value_mode, FP_RETURN);
4029+  if (type_mode != value_mode)
4030+    {
4031+      x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
4032+      x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
4033+    }
4034+  return x;
4035+}
4036+
4037+/* Return a composite value in a pair of floating-point registers.
4038+   MODE1 and OFFSET1 are the mode and byte offset for the first value,
4039+   likewise MODE2 and OFFSET2 for the second.  MODE is the mode of the
4040+   complete value.
4041+
4042+   For n32 & n64, $f0 always holds the first value and $f2 the second.
4043+   Otherwise the values are packed together as closely as possible.  */
4044+
4045+static rtx
4046+mips_return_fpr_pair (enum machine_mode mode,
4047+                     enum machine_mode mode1, HOST_WIDE_INT offset1,
4048+                     enum machine_mode mode2, HOST_WIDE_INT offset2)
4049+{
4050+  return gen_rtx_PARALLEL
4051+    (mode,
4052+     gen_rtvec (2,
4053+               gen_rtx_EXPR_LIST (VOIDmode,
4054+                                  gen_rtx_REG (mode1, FP_RETURN),
4055+                                  GEN_INT (offset1)),
4056+               gen_rtx_EXPR_LIST (VOIDmode,
4057+                                  gen_rtx_REG (mode2, FP_RETURN + 1),
4058+                                  GEN_INT (offset2))));
4059+
4060+}
4061+
4062+/* Implement FUNCTION_VALUE and LIBCALL_VALUE.  For normal calls,
4063+   VALTYPE is the return type and MODE is VOIDmode.  For libcalls,
4064+   VALTYPE is null and MODE is the mode of the return value.  */
4065+
4066+rtx
4067+mips_function_value (const_tree valtype, const_tree func, enum machine_mode mode)
4068+{
4069+  if (valtype)
4070+    {
4071+      tree fields[2];
4072+      int unsigned_p;
4073+
4074+      mode = TYPE_MODE (valtype);
4075+      unsigned_p = TYPE_UNSIGNED (valtype);
4076+
4077+      /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
4078+        return values, promote the mode here too.  */
4079+      mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
4080+
4081+      /* Handle structures whose fields are returned in $f0/$f2.  */
4082+      switch (mips_fpr_return_fields (valtype, fields))
4083+       {
4084+       case 1:
4085+         return mips_return_fpr_single (mode,
4086+                                        TYPE_MODE (TREE_TYPE (fields[0])));
4087+
4088+       case 2:
4089+         return mips_return_fpr_pair (mode,
4090+                                      TYPE_MODE (TREE_TYPE (fields[0])),
4091+                                      int_byte_position (fields[0]),
4092+                                      TYPE_MODE (TREE_TYPE (fields[1])),
4093+                                      int_byte_position (fields[1]));
4094+       }
4095+
4096+      /* If a value is passed in the most significant part of a register, see
4097+        whether we have to round the mode up to a whole number of words.  */
4098+      if (mips_return_in_msb (valtype))
4099+       {
4100+         HOST_WIDE_INT size = int_size_in_bytes (valtype);
4101+         if (size % UNITS_PER_WORD != 0)
4102+           {
4103+             size += UNITS_PER_WORD - size % UNITS_PER_WORD;
4104+             mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4105+           }
4106+       }
4107+
4108+      /* Only use FPRs for scalar, complex or vector types.  */
4109+      if (!FLOAT_TYPE_P (valtype))
4110+       return gen_rtx_REG (mode, GP_RETURN);
4111+    }
4112+
4113+  /* Handle long doubles for n32 & n64.  */
4114+  if (mode == TFmode)
4115+    return mips_return_fpr_pair (mode,
4116+                            DImode, 0,
4117+                            DImode, GET_MODE_SIZE (mode) / 2);
4118+
4119+  if (mips_return_mode_in_fpr_p (mode))
4120+    {
4121+      if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4122+        return mips_return_fpr_pair (mode,
4123+                                GET_MODE_INNER (mode), 0,
4124+                                GET_MODE_INNER (mode),
4125+                                GET_MODE_SIZE (mode) / 2);
4126+      else
4127+        return gen_rtx_REG (mode, FP_RETURN);
4128+    }
4129+
4130+  return gen_rtx_REG (mode, GP_RETURN);
4131+}
4132+
4133+/* Implement TARGET_RETURN_IN_MEMORY.  Scalars and small structures
4134+   that fit in two registers are returned in v0/v1. */
4135+
4136+static bool
4137+mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
4138+{
4139+  return !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD);
4140+}
4141+
4142+/* Implement TARGET_SETUP_INCOMING_VARARGS.  */
4143+
4144+static void
4145+mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4146+                            tree type, int *pretend_size ATTRIBUTE_UNUSED,
4147+                            int no_rtl)
4148+{
4149+  CUMULATIVE_ARGS local_cum;
4150+  int gp_saved;
4151+
4152+  /* The caller has advanced CUM up to, but not beyond, the last named
4153+     argument.  Advance a local copy of CUM past the last "real" named
4154+     argument, to find out how many registers are left over.  */
4155+  local_cum = *cum;
4156+  mips_function_arg_advance (&local_cum, mode, type, true);
4157+
4158+  /* Found out how many registers we need to save.  */
4159+  gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4160+
4161+  if (!no_rtl && gp_saved > 0)
4162+    {
4163+      rtx ptr, mem;
4164+
4165+      ptr = plus_constant (virtual_incoming_args_rtx,
4166+                          REG_PARM_STACK_SPACE (cfun->decl)
4167+                          - gp_saved * UNITS_PER_WORD);
4168+      mem = gen_frame_mem (BLKmode, ptr);
4169+      set_mem_alias_set (mem, get_varargs_alias_set ());
4170+
4171+      move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4172+                          mem, gp_saved);
4173+    }
4174+  if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4175+    cfun->machine->varargs_size = gp_saved * UNITS_PER_WORD;
4176+}
4177+
4178+/* Implement TARGET_EXPAND_BUILTIN_VA_START.  */
4179+
4180+static void
4181+mips_va_start (tree valist, rtx nextarg)
4182+{
4183+  nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4184+  std_expand_builtin_va_start (valist, nextarg);
4185+}
4186+
4187+/* Expand a call of type TYPE.  RESULT is where the result will go (null
4188+   for "call"s and "sibcall"s), ADDR is the address of the function,
4189+   ARGS_SIZE is the size of the arguments and AUX is the value passed
4190+   to us by mips_function_arg.  LAZY_P is true if this call already
4191+   involves a lazily-bound function address (such as when calling
4192+   functions through a MIPS16 hard-float stub).
4193+
4194+   Return the call itself.  */
4195+
4196+rtx
4197+mips_expand_call (bool sibcall_p, rtx result, rtx addr, rtx args_size)
4198+{
4199+  rtx pattern, insn;
4200+
4201+  if (!call_insn_operand (addr, VOIDmode))
4202+    {
4203+      rtx reg = MIPS_EPILOGUE_TEMP (Pmode, true);
4204+      mips_emit_move (reg, addr);
4205+      addr = reg;
4206+    }
4207+
4208+  if (result == 0)
4209+    {
4210+      rtx (*fn) (rtx, rtx);
4211+
4212+      if (sibcall_p)
4213+       fn = gen_sibcall_internal;
4214+      else
4215+       fn = gen_call_internal;
4216+
4217+      pattern = fn (addr, args_size);
4218+    }
4219+  else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
4220+    {
4221+      /* Handle return values created by mips_return_fpr_pair.  */
4222+      rtx (*fn) (rtx, rtx, rtx, rtx);
4223+      rtx reg1, reg2;
4224+
4225+      if (sibcall_p)
4226+       fn = gen_sibcall_value_multiple_internal;
4227+      else
4228+       fn = gen_call_value_multiple_internal;
4229+
4230+      reg1 = XEXP (XVECEXP (result, 0, 0), 0);
4231+      reg2 = XEXP (XVECEXP (result, 0, 1), 0);
4232+      pattern = fn (reg1, addr, args_size, reg2);
4233+    }
4234+  else
4235+    {
4236+      rtx (*fn) (rtx, rtx, rtx);
4237+
4238+      if (sibcall_p)
4239+       fn = gen_sibcall_value_internal;
4240+      else
4241+       fn = gen_call_value_internal;
4242+
4243+      /* Handle return values created by mips_return_fpr_single.  */
4244+      if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
4245+       result = XEXP (XVECEXP (result, 0, 0), 0);
4246+      pattern = fn (result, addr, args_size);
4247+    }
4248+
4249+  insn = emit_call_insn (pattern);
4250+
4251+  if (TARGET_USE_GOT)
4252+    {
4253+      /* See the comment above load_call<mode> for details.  */
4254+      use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
4255+              gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
4256+      emit_insn (gen_update_got_version ());
4257+    }
4258+  return insn;
4259+}
4260+
4261+/* Emit straight-line code to move LENGTH bytes from SRC to DEST.
4262+   Assume that the areas do not overlap.  */
4263+
4264+static void
4265+mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
4266+{
4267+  HOST_WIDE_INT offset, delta;
4268+  unsigned HOST_WIDE_INT bits;
4269+  int i;
4270+  enum machine_mode mode;
4271+  rtx *regs;
4272+
4273+  bits = MAX( BITS_PER_UNIT,
4274+             MIN( BITS_PER_WORD, MIN( MEM_ALIGN(src),MEM_ALIGN(dest) ) ) );
4275+
4276+  mode = mode_for_size (bits, MODE_INT, 0);
4277+  delta = bits / BITS_PER_UNIT;
4278+
4279+  /* Allocate a buffer for the temporary registers.  */
4280+  regs = XALLOCAVEC (rtx, length / delta);
4281+
4282+  /* Load as many BITS-sized chunks as possible.  Use a normal load if
4283+     the source has enough alignment, otherwise use left/right pairs.  */
4284+  for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
4285+    {
4286+      regs[i] = gen_reg_rtx (mode);
4287+       mips_emit_move (regs[i], adjust_address (src, mode, offset));
4288+    }
4289+
4290+  /* Copy the chunks to the destination.  */
4291+  for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
4292+      mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
4293+
4294+  /* Mop up any left-over bytes.  */
4295+  if (offset < length)
4296+    {
4297+      src = adjust_address (src, BLKmode, offset);
4298+      dest = adjust_address (dest, BLKmode, offset);
4299+      move_by_pieces (dest, src, length - offset,
4300+                     MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
4301+    }
4302+}
4303+
4304+/* Helper function for doing a loop-based block operation on memory
4305+   reference MEM.  Each iteration of the loop will operate on LENGTH
4306+   bytes of MEM.
4307+
4308+   Create a new base register for use within the loop and point it to
4309+   the start of MEM.  Create a new memory reference that uses this
4310+   register.  Store them in *LOOP_REG and *LOOP_MEM respectively.  */
4311+
4312+static void
4313+mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
4314+                      rtx *loop_reg, rtx *loop_mem)
4315+{
4316+  *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
4317+
4318+  /* Although the new mem does not refer to a known location,
4319+     it does keep up to LENGTH bytes of alignment.  */
4320+  *loop_mem = change_address (mem, BLKmode, *loop_reg);
4321+  set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
4322+}
4323+
4324+/* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
4325+   bytes at a time.  LENGTH must be at least BYTES_PER_ITER.  Assume that
4326+   the memory regions do not overlap.  */
4327+
4328+static void
4329+mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
4330+                     HOST_WIDE_INT bytes_per_iter)
4331+{
4332+  rtx label, src_reg, dest_reg, final_src, test;
4333+  HOST_WIDE_INT leftover;
4334+
4335+  leftover = length % bytes_per_iter;
4336+  length -= leftover;
4337+
4338+  /* Create registers and memory references for use within the loop.  */
4339+  mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
4340+  mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
4341+
4342+  /* Calculate the value that SRC_REG should have after the last iteration
4343+     of the loop.  */
4344+  final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
4345+                                  0, 0, OPTAB_WIDEN);
4346+
4347+  /* Emit the start of the loop.  */
4348+  label = gen_label_rtx ();
4349+  emit_label (label);
4350+
4351+  /* Emit the loop body.  */
4352+  mips_block_move_straight (dest, src, bytes_per_iter);
4353+
4354+  /* Move on to the next block.  */
4355+  mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
4356+  mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
4357+
4358+  /* Emit the loop condition.  */
4359+  test = gen_rtx_NE (VOIDmode, src_reg, final_src);
4360+  if (Pmode == DImode)
4361+    emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
4362+  else
4363+    emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
4364+
4365+  /* Mop up any left-over bytes.  */
4366+  if (leftover)
4367+    mips_block_move_straight (dest, src, leftover);
4368+}
4369+
4370+/* Expand a movmemsi instruction, which copies LENGTH bytes from
4371+   memory reference SRC to memory reference DEST.  */
4372+
4373+bool
4374+mips_expand_block_move (rtx dest, rtx src, rtx length)
4375+{
4376+  if (CONST_INT_P (length))
4377+    {
4378+      HOST_WIDE_INT factor, align;
4379+      
4380+      align = MIN (MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), BITS_PER_WORD);
4381+      factor = BITS_PER_WORD / align;
4382+
4383+      if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT / factor)
4384+       {
4385+         mips_block_move_straight (dest, src, INTVAL (length));
4386+         return true;
4387+       }
4388+      else if (optimize && align >= BITS_PER_WORD)
4389+       {
4390+         mips_block_move_loop (dest, src, INTVAL (length),
4391+                               MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER / factor);
4392+         return true;
4393+       }
4394+    }
4395+  return false;
4396+}
4397+
4398+/* Return true if X is a MEM with the same size as MODE.  */
4399+
4400+bool
4401+mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
4402+{
4403+  rtx size;
4404+
4405+  if (!MEM_P (x))
4406+    return false;
4407+
4408+  size = MEM_SIZE (x);
4409+  return size && INTVAL (size) == GET_MODE_SIZE (mode);
4410+}
4411+
4412+/* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs.  */
4413+
4414+static void
4415+mips_init_relocs (void)
4416+{
4417+  memset (mips_split_p, '\0', sizeof (mips_split_p));
4418+  memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
4419+  memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
4420+
4421+  if (!flag_pic)
4422+    {
4423+      mips_split_p[SYMBOL_ABSOLUTE] = true;
4424+      mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
4425+      mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
4426+    }
4427+
4428+  mips_split_p[SYMBOL_TPREL] = true;
4429+  mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
4430+  mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
4431+}
4432+
4433+/* Print symbolic operand OP, which is part of a HIGH or LO_SUM
4434+   in context CONTEXT.  RELOCS is the array of relocations to use.  */
4435+
4436+static void
4437+mips_print_operand_reloc (FILE *file, rtx op, const char **relocs)
4438+{
4439+  enum mips_symbol_type symbol_type;
4440+  const char *p;
4441+
4442+  symbol_type = mips_classify_symbolic_expression (op);
4443+  gcc_assert (relocs[symbol_type]);
4444+
4445+  fputs (relocs[symbol_type], file);
4446+  output_addr_const (file, mips_strip_unspec_address (op));
4447+  for (p = relocs[symbol_type]; *p != 0; p++)
4448+    if (*p == '(')
4449+      fputc (')', file);
4450+}
4451+
4452+/* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
4453+   associated with condition CODE.  Print the condition part of the
4454+   opcode to FILE.  */
4455+
4456+static void
4457+mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
4458+{
4459+  switch (code)
4460+    {
4461+    case EQ:
4462+    case NE:
4463+    case GT:
4464+    case GE:
4465+    case LT:
4466+    case LE:
4467+    case GTU:
4468+    case GEU:
4469+    case LTU:
4470+    case LEU:
4471+      /* Conveniently, the MIPS names for these conditions are the same
4472+        as their RTL equivalents.  */
4473+      fputs (GET_RTX_NAME (code), file);
4474+      break;
4475+
4476+    default:
4477+      output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
4478+      break;
4479+    }
4480+}
4481+
4482+/* Implement TARGET_PRINT_OPERAND.  The MIPS-specific operand codes are:
4483+
4484+   'X' Print CONST_INT OP in hexadecimal format.
4485+   'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
4486+   'd' Print CONST_INT OP in decimal.
4487+   'm' Print one less than CONST_INT OP in decimal.
4488+   'h' Print the high-part relocation associated with OP, after stripping
4489+         any outermost HIGH.
4490+   'R' Print the low-part relocation associated with OP.
4491+   'C' Print the integer branch condition for comparison OP.
4492+   'N' Print the inverse of the integer branch condition for comparison OP.
4493+   'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
4494+             'z' for (eq:?I ...), 'n' for (ne:?I ...).
4495+   't' Like 'T', but with the EQ/NE cases reversed
4496+   'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
4497+   'D' Print the second part of a double-word register or memory operand.
4498+   'L' Print the low-order register in a double-word register operand.
4499+   'M' Print high-order register in a double-word register operand.
4500+   'z' Print $0 if OP is zero, otherwise print OP normally.  */
4501+
4502+static void
4503+mips_print_operand (FILE *file, rtx op, int letter)
4504+{
4505+  enum rtx_code code;
4506+
4507+  gcc_assert (op);
4508+  code = GET_CODE (op);
4509+
4510+  switch (letter)
4511+    {
4512+    case 'X':
4513+      if (CONST_INT_P (op))
4514+       fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
4515+      else
4516+       output_operand_lossage ("invalid use of '%%%c'", letter);
4517+      break;
4518+
4519+    case 'x':
4520+      if (CONST_INT_P (op))
4521+       fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
4522+      else
4523+       output_operand_lossage ("invalid use of '%%%c'", letter);
4524+      break;
4525+
4526+    case 'd':
4527+      if (CONST_INT_P (op))
4528+       fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
4529+      else
4530+       output_operand_lossage ("invalid use of '%%%c'", letter);
4531+      break;
4532+
4533+    case 'm':
4534+      if (CONST_INT_P (op))
4535+       fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
4536+      else
4537+       output_operand_lossage ("invalid use of '%%%c'", letter);
4538+      break;
4539+
4540+    case 'h':
4541+      if (code == HIGH)
4542+       op = XEXP (op, 0);
4543+      mips_print_operand_reloc (file, op, mips_hi_relocs);
4544+      break;
4545+
4546+    case 'R':
4547+      mips_print_operand_reloc (file, op, mips_lo_relocs);
4548+      break;
4549+
4550+    case 'C':
4551+      mips_print_int_branch_condition (file, code, letter);
4552+      break;
4553+
4554+    case 'N':
4555+      mips_print_int_branch_condition (file, reverse_condition (code), letter);
4556+      break;
4557+
4558+    case 'S':
4559+      mips_print_int_branch_condition (file, swap_condition (code), letter);
4560+      break;
4561+
4562+    case 'T':
4563+    case 't':
4564+      {
4565+       int truth = (code == NE) == (letter == 'T');
4566+       fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
4567+      }
4568+      break;
4569+
4570+    case 'Z':
4571+      mips_print_operand (file, op, 0);
4572+      fputc (',', file);
4573+      break;
4574+
4575+    default:
4576+      switch (code)
4577+       {
4578+       case REG:
4579+         {
4580+           unsigned int regno = REGNO (op);
4581+           if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
4582+               || (letter == 'L' && TARGET_BIG_ENDIAN)
4583+               || letter == 'D')
4584+             regno++;
4585+           else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
4586+             output_operand_lossage ("invalid use of '%%%c'", letter);
4587+           fprintf (file, "%s", reg_names[regno]);
4588+         }
4589+         break;
4590+
4591+       case MEM:
4592+         if (letter == 'y')
4593+           fprintf (file, "%s", reg_names[REGNO(XEXP(op, 0))]);
4594+         else if (letter && letter == 'D')
4595+           output_address (plus_constant (XEXP (op, 0), 4));
4596+         else if (letter && letter != 'z')
4597+           output_operand_lossage ("invalid use of '%%%c'", letter);
4598+         else
4599+           output_address (XEXP (op, 0));
4600+         break;
4601+
4602+       default:
4603+         if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
4604+           fputs (reg_names[GP_REG_FIRST], file);
4605+         else if (letter && letter != 'z')
4606+           output_operand_lossage ("invalid use of '%%%c'", letter);
4607+         else
4608+           output_addr_const (file, mips_strip_unspec_address (op));
4609+         break;
4610+       }
4611+    }
4612+}
4613+
4614+/* Implement TARGET_PRINT_OPERAND_ADDRESS.  */
4615+
4616+static void
4617+mips_print_operand_address (FILE *file, rtx x)
4618+{
4619+  struct mips_address_info addr;
4620+
4621+  if (mips_classify_address (&addr, x, word_mode, true))
4622+    switch (addr.type)
4623+      {
4624+      case ADDRESS_REG:
4625+       mips_print_operand (file, addr.offset, 0);
4626+       fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
4627+       return;
4628+
4629+      case ADDRESS_LO_SUM:
4630+       mips_print_operand_reloc (file, addr.offset, mips_lo_relocs);
4631+       fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
4632+       return;
4633+
4634+      case ADDRESS_CONST_INT:
4635+       output_addr_const (file, x);
4636+       fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
4637+       return;
4638+
4639+      case ADDRESS_SYMBOLIC:
4640+       output_addr_const (file, mips_strip_unspec_address (x));
4641+       return;
4642+      }
4643+  gcc_unreachable ();
4644+}
4645+
4646+/* Implement TARGET_ENCODE_SECTION_INFO.  */
4647+
4648+static void
4649+mips_encode_section_info (tree decl, rtx rtl, int first)
4650+{
4651+  default_encode_section_info (decl, rtl, first);
4652+
4653+  if (TREE_CODE (decl) == FUNCTION_DECL)
4654+    {
4655+      rtx symbol = XEXP (rtl, 0);
4656+      tree type = TREE_TYPE (decl);
4657+
4658+      /* Encode whether the symbol is short or long.  */
4659+      if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
4660+         || mips_far_type_p (type))
4661+       SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
4662+    }
4663+}
4664+
4665+/* The MIPS debug format wants all automatic variables and arguments
4666+   to be in terms of the virtual frame pointer (stack pointer before
4667+   any adjustment in the function), while the MIPS 3.0 linker wants
4668+   the frame pointer to be the stack pointer after the initial
4669+   adjustment.  So, we do the adjustment here.  The arg pointer (which
4670+   is eliminated) points to the virtual frame pointer, while the frame
4671+   pointer (which may be eliminated) points to the stack pointer after
4672+   the initial adjustments.  */
4673+
4674+HOST_WIDE_INT
4675+mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
4676+{
4677+  rtx offset2 = const0_rtx;
4678+  rtx reg = eliminate_constant_term (addr, &offset2);
4679+
4680+  if (offset == 0)
4681+    offset = INTVAL (offset2);
4682+  
4683+  if (reg == stack_pointer_rtx)
4684+    offset -= cfun->machine->frame.total_size;
4685+  else
4686+    gcc_assert (reg == frame_pointer_rtx || reg == hard_frame_pointer_rtx);
4687+
4688+  return offset;
4689+}
4690+
4691+/* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME.  */
4692+
4693+static void
4694+mips_output_filename (FILE *stream, const char *name)
4695+{
4696+  /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
4697+     directives.  */
4698+  if (write_symbols == DWARF2_DEBUG)
4699+    return;
4700+  else if (mips_output_filename_first_time)
4701+    {
4702+      mips_output_filename_first_time = 0;
4703+      num_source_filenames += 1;
4704+      current_function_file = name;
4705+      fprintf (stream, "\t.file\t%d ", num_source_filenames);
4706+      output_quoted_string (stream, name);
4707+      putc ('\n', stream);
4708+    }
4709+  /* If we are emitting stabs, let dbxout.c handle this (except for
4710+     the mips_output_filename_first_time case).  */
4711+  else if (write_symbols == DBX_DEBUG)
4712+    return;
4713+  else if (name != current_function_file
4714+          && strcmp (name, current_function_file) != 0)
4715+    {
4716+      num_source_filenames += 1;
4717+      current_function_file = name;
4718+      fprintf (stream, "\t.file\t%d ", num_source_filenames);
4719+      output_quoted_string (stream, name);
4720+      putc ('\n', stream);
4721+    }
4722+}
4723+
4724+/* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL.  */
4725+
4726+static void ATTRIBUTE_UNUSED
4727+mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
4728+{
4729+  switch (size)
4730+    {
4731+    case 4:
4732+      fputs ("\t.dtprelword\t", file);
4733+      break;
4734+
4735+    case 8:
4736+      fputs ("\t.dtpreldword\t", file);
4737+      break;
4738+
4739+    default:
4740+      gcc_unreachable ();
4741+    }
4742+  output_addr_const (file, x);
4743+  fputs ("+0x8000", file);
4744+}
4745+
4746+/* Implement ASM_OUTPUT_ASCII.  */
4747+
4748+void
4749+mips_output_ascii (FILE *stream, const char *string, size_t len)
4750+{
4751+  size_t i;
4752+  int cur_pos;
4753+
4754+  cur_pos = 17;
4755+  fprintf (stream, "\t.ascii\t\"");
4756+  for (i = 0; i < len; i++)
4757+    {
4758+      int c;
4759+
4760+      c = (unsigned char) string[i];
4761+      if (ISPRINT (c))
4762+       {
4763+         if (c == '\\' || c == '\"')
4764+           {
4765+             putc ('\\', stream);
4766+             cur_pos++;
4767+           }
4768+         putc (c, stream);
4769+         cur_pos++;
4770+       }
4771+      else
4772+       {
4773+         fprintf (stream, "\\%03o", c);
4774+         cur_pos += 4;
4775+       }
4776+
4777+      if (cur_pos > 72 && i+1 < len)
4778+       {
4779+         cur_pos = 17;
4780+         fprintf (stream, "\"\n\t.ascii\t\"");
4781+       }
4782+    }
4783+  fprintf (stream, "\"\n");
4784+}
4785+
4786+/* Emit either a label, .comm, or .lcomm directive.  When using assembler
4787+   macros, mark the symbol as written so that mips_asm_output_external
4788+   won't emit an .extern for it.  STREAM is the output file, NAME is the
4789+   name of the symbol, INIT_STRING is the string that should be written
4790+   before the symbol and FINAL_STRING is the string that should be
4791+   written after it.  FINAL_STRING is a printf format that consumes the
4792+   remaining arguments.  */
4793+
4794+void
4795+mips_declare_object (FILE *stream, const char *name, const char *init_string,
4796+                    const char *final_string, ...)
4797+{
4798+  va_list ap;
4799+
4800+  fputs (init_string, stream);
4801+  assemble_name (stream, name);
4802+  va_start (ap, final_string);
4803+  vfprintf (stream, final_string, ap);
4804+  va_end (ap);
4805+}
4806+
4807+/* Declare a common object of SIZE bytes using asm directive INIT_STRING.
4808+   NAME is the name of the object and ALIGN is the required alignment
4809+   in bytes.  TAKES_ALIGNMENT_P is true if the directive takes a third
4810+   alignment argument.  */
4811+
4812+void
4813+mips_declare_common_object (FILE *stream, const char *name,
4814+                           const char *init_string,
4815+                           unsigned HOST_WIDE_INT size,
4816+                           unsigned int align, bool takes_alignment_p)
4817+{
4818+  if (!takes_alignment_p)
4819+    {
4820+      size += (align / BITS_PER_UNIT) - 1;
4821+      size -= size % (align / BITS_PER_UNIT);
4822+      mips_declare_object (stream, name, init_string,
4823+                          "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
4824+    }
4825+  else
4826+    mips_declare_object (stream, name, init_string,
4827+                        "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
4828+                        size, align / BITS_PER_UNIT);
4829+}
4830+
4831+/* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON.  This is usually the same as the
4832+   elfos.h version, but we also need to handle -muninit-const-in-rodata.  */
4833+
4834+void
4835+mips_output_aligned_decl_common (FILE *stream, tree decl ATTRIBUTE_UNUSED,
4836+                                const char *name,
4837+                                unsigned HOST_WIDE_INT size,
4838+                                unsigned int align)
4839+{
4840+  mips_declare_common_object (stream, name, "\n\t.comm\t", size, align, true);
4841+}
4842+
4843+#ifdef ASM_OUTPUT_SIZE_DIRECTIVE
4844+extern int size_directive_output;
4845+
4846+/* Implement ASM_DECLARE_OBJECT_NAME.  This is like most of the standard ELF
4847+   definitions except that it uses mips_declare_object to emit the label.  */
4848+
4849+void
4850+mips_declare_object_name (FILE *stream, const char *name,
4851+                         tree decl ATTRIBUTE_UNUSED)
4852+{
4853+#ifdef ASM_OUTPUT_TYPE_DIRECTIVE
4854+  ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
4855+#endif
4856+
4857+  size_directive_output = 0;
4858+  if (!flag_inhibit_size_directive && DECL_SIZE (decl))
4859+    {
4860+      HOST_WIDE_INT size;
4861+
4862+      size_directive_output = 1;
4863+      size = int_size_in_bytes (TREE_TYPE (decl));
4864+      ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
4865+    }
4866+
4867+  mips_declare_object (stream, name, "", ":\n");
4868+}
4869+
4870+/* Implement ASM_FINISH_DECLARE_OBJECT.  This is generic ELF stuff.  */
4871+
4872+void
4873+mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
4874+{
4875+  const char *name;
4876+
4877+  name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
4878+  if (!flag_inhibit_size_directive
4879+      && DECL_SIZE (decl) != 0
4880+      && !at_end
4881+      && top_level
4882+      && DECL_INITIAL (decl) == error_mark_node
4883+      && !size_directive_output)
4884+    {
4885+      HOST_WIDE_INT size;
4886+
4887+      size_directive_output = 1;
4888+      size = int_size_in_bytes (TREE_TYPE (decl));
4889+      ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
4890+    }
4891+}
4892+#endif
4893+
4894+/* Make the last instruction frame-related and note that it performs
4895+   the operation described by FRAME_PATTERN.  */
4896+
4897+static void
4898+mips_set_frame_expr (rtx frame_pattern)
4899+{
4900+  rtx insn;
4901+
4902+  insn = get_last_insn ();
4903+  RTX_FRAME_RELATED_P (insn) = 1;
4904+  REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4905+                                     frame_pattern,
4906+                                     REG_NOTES (insn));
4907+}
4908+
4909+/* Return a frame-related rtx that stores REG at MEM.
4910+   REG must be a single register.  */
4911+
4912+static rtx
4913+mips_frame_set (rtx mem, rtx reg)
4914+{
4915+  rtx set;
4916+
4917+  set = gen_rtx_SET (VOIDmode, mem, reg);
4918+  RTX_FRAME_RELATED_P (set) = 1;
4919+
4920+  return set;
4921+}
4922+
4923+/* Return true if the current function must save register REGNO.  */
4924+
4925+static bool
4926+mips_save_reg_p (unsigned int regno)
4927+{
4928+  bool call_saved = !global_regs[regno] && !call_really_used_regs[regno];
4929+  bool might_clobber = crtl->saves_all_registers
4930+                      || df_regs_ever_live_p (regno)
4931+                      || (regno == HARD_FRAME_POINTER_REGNUM
4932+                          && frame_pointer_needed);
4933+
4934+  return (call_saved && might_clobber)
4935+        || (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return);
4936+}
4937+
4938+/* Populate the current function's mips_frame_info structure.
4939+
4940+   MIPS stack frames look like:
4941+
4942+       +-------------------------------+
4943+       |                               |
4944+       |  incoming stack arguments     |
4945+       |                               |
4946+       +-------------------------------+
4947+       |                               |
4948+       |  caller-allocated save area   |
4949+      A |  for register arguments       |
4950+       |                               |
4951+       +-------------------------------+ <-- incoming stack pointer
4952+       |                               |
4953+       |  callee-allocated save area   |
4954+      B |  for arguments that are       |
4955+       |  split between registers and  |
4956+       |  the stack                    |
4957+       |                               |
4958+       +-------------------------------+ <-- arg_pointer_rtx
4959+       |                               |
4960+      C |  callee-allocated save area   |
4961+       |  for register varargs         |
4962+       |                               |
4963+       +-------------------------------+ <-- hard_frame_pointer_rtx;
4964+       |                               |     stack_pointer_rtx + gp_sp_offset
4965+       |  GPR save area                |       + UNITS_PER_WORD
4966+       |                               |
4967+       +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
4968+       |                               |       + UNITS_PER_HWVALUE
4969+       |  FPR save area                |
4970+       |                               |
4971+       +-------------------------------+ <-- frame_pointer_rtx (virtual)
4972+       |                               |
4973+       |  local variables              |
4974+       |                               |
4975+      P +-------------------------------+
4976+       |                               |
4977+       |  outgoing stack arguments     |
4978+       |                               |
4979+       +-------------------------------+
4980+       |                               |
4981+       |  caller-allocated save area   |
4982+       |  for register arguments       |
4983+       |                               |
4984+       +-------------------------------+ <-- stack_pointer_rtx
4985+
4986+   At least two of A, B and C will be empty.
4987+
4988+   Dynamic stack allocations such as alloca insert data at point P.
4989+   They decrease stack_pointer_rtx but leave frame_pointer_rtx and
4990+   hard_frame_pointer_rtx unchanged.  */
4991+
4992+static void
4993+mips_compute_frame_info (void)
4994+{
4995+  struct mips_frame_info *frame;
4996+  HOST_WIDE_INT offset;
4997+  unsigned int regno, i;
4998+
4999+  frame = &cfun->machine->frame;
5000+  memset (frame, 0, sizeof (*frame));
5001+
5002+  /* Find out which GPRs we need to save.  */
5003+  for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
5004+    if (mips_save_reg_p (regno))
5005+      frame->mask |= 1 << (regno - GP_REG_FIRST);
5006+
5007+  /* If this function calls eh_return, we must also save and restore the
5008+     EH data registers.  */
5009+  if (crtl->calls_eh_return)
5010+    for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
5011+      frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
5012+
5013+  /* Find out which FPRs we need to save.  This loop must iterate over
5014+     the same space as its companion in mips_for_each_saved_gpr_and_fpr.  */
5015+  if (TARGET_HARD_FLOAT)
5016+    for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5017+      if (mips_save_reg_p (regno))
5018+        frame->fmask |= 1 << (regno - FP_REG_FIRST);
5019+
5020+  /* At the bottom of the frame are any outgoing stack arguments. */
5021+  offset = crtl->outgoing_args_size;
5022+  /* Next are local stack variables. */
5023+  offset += MIPS_STACK_ALIGN (get_frame_size ());
5024+  /* The virtual frame pointer points above the local variables. */
5025+  frame->frame_pointer_offset = offset;
5026+  /* Next are the callee-saved FPRs. */
5027+  if (frame->fmask)
5028+    {
5029+      unsigned num_saved = __builtin_popcount(frame->fmask);
5030+      offset += MIPS_STACK_ALIGN (num_saved * UNITS_PER_FPREG);
5031+      frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
5032+    }
5033+  /* Next are the callee-saved GPRs. */
5034+  if (frame->mask)
5035+    {
5036+      unsigned num_saved = __builtin_popcount(frame->mask);
5037+      offset += MIPS_STACK_ALIGN (num_saved * UNITS_PER_WORD);
5038+      frame->gp_sp_offset = offset - UNITS_PER_WORD;
5039+    }
5040+  /* The hard frame pointer points above the callee-saved GPRs. */
5041+  frame->hard_frame_pointer_offset = offset;
5042+  /* Above the hard frame pointer is the callee-allocated varags save area. */
5043+  offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
5044+  frame->arg_pointer_offset = offset;
5045+  /* Next is the callee-allocated area for pretend stack arguments.  */
5046+  offset += crtl->args.pretend_args_size;
5047+  frame->total_size = offset;
5048+  /* Next points the incoming stack pointer and any incoming arguments. */
5049+}
5050+
5051+/* Make sure that we're not trying to eliminate to the wrong hard frame
5052+   pointer.  */
5053+
5054+static bool
5055+mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
5056+{
5057+  return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
5058+}
5059+
5060+/* Implement INITIAL_ELIMINATION_OFFSET.  FROM is either the frame pointer
5061+   or argument pointer.  TO is either the stack pointer or hard frame
5062+   pointer.  */
5063+
5064+HOST_WIDE_INT
5065+mips_initial_elimination_offset (int from, int to)
5066+{
5067+  HOST_WIDE_INT src, dest;
5068+
5069+  mips_compute_frame_info ();
5070+
5071+  if (to == HARD_FRAME_POINTER_REGNUM)
5072+    dest = cfun->machine->frame.hard_frame_pointer_offset;
5073+  else if (to == STACK_POINTER_REGNUM)
5074+    dest = 0; /* this is the base of all offsets */
5075+  else
5076+    gcc_unreachable ();
5077+
5078+  if (from == FRAME_POINTER_REGNUM)
5079+    src = cfun->machine->frame.frame_pointer_offset;
5080+  else if (from == ARG_POINTER_REGNUM)
5081+    src = cfun->machine->frame.arg_pointer_offset;
5082+  else
5083+    gcc_unreachable ();
5084+
5085+  return src - dest;
5086+}
5087+
5088+/* Implement TARGET_EXTRA_LIVE_ON_ENTRY.  */
5089+
5090+static void
5091+mips_extra_live_on_entry (bitmap regs)
5092+{
5093+  if (TARGET_USE_GOT)
5094+    {
5095+      /* See the comment above load_call<mode> for details.  */
5096+      bitmap_set_bit (regs, GOT_VERSION_REGNUM);
5097+    }
5098+}
5099+
5100+/* Implement RETURN_ADDR_RTX.  We do not support moving back to a
5101+   previous frame.  */
5102+
5103+rtx
5104+mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
5105+{
5106+  if (count != 0)
5107+    return const0_rtx;
5108+
5109+  return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
5110+}
5111+
5112+/* Emit code to change the current function's return address to
5113+   ADDRESS.  SCRATCH is available as a scratch register, if needed.
5114+   ADDRESS and SCRATCH are both word-mode GPRs.  */
5115+
5116+void
5117+mips_set_return_address (rtx address, rtx scratch)
5118+{
5119+  rtx slot_address;
5120+
5121+  gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
5122+  slot_address = mips_add_offset (scratch, stack_pointer_rtx,
5123+                                 cfun->machine->frame.gp_sp_offset);
5124+  mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
5125+}
5126+
5127+/* A function to save or store a register.  The first argument is the
5128+   register and the second is the stack slot.  */
5129+typedef void (*mips_save_restore_fn) (rtx, rtx);
5130+
5131+/* Use FN to save or restore register REGNO.  MODE is the register's
5132+   mode and OFFSET is the offset of its save slot from the current
5133+   stack pointer.  */
5134+
5135+static void
5136+mips_save_restore_reg (enum machine_mode mode, int regno,
5137+                      HOST_WIDE_INT offset, mips_save_restore_fn fn)
5138+{
5139+  rtx mem;
5140+
5141+  mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
5142+  fn (gen_rtx_REG (mode, regno), mem);
5143+}
5144+
5145+/* Call FN for each register that is saved by the current function.
5146+   SP_OFFSET is the offset of the current stack pointer from the start
5147+   of the frame.  */
5148+
5149+static void
5150+mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
5151+                                mips_save_restore_fn fn)
5152+{
5153+  HOST_WIDE_INT offset;
5154+  int regno;
5155+
5156+  /* Save the link register and s-registers. */
5157+  offset = cfun->machine->frame.gp_sp_offset - sp_offset;
5158+  for (regno = GP_REG_FIRST; regno <= GP_REG_LAST-1; regno++)
5159+    if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
5160+      {
5161+        mips_save_restore_reg (word_mode, regno, offset, fn);
5162+        offset -= UNITS_PER_WORD;
5163+      }
5164+
5165+  /* This loop must iterate over the same space as its companion in
5166+     mips_compute_frame_info.  */
5167+  offset = cfun->machine->frame.fp_sp_offset - sp_offset;
5168+  for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5169+    if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
5170+      {
5171+       mips_save_restore_reg (DFmode, regno, offset, fn);
5172+       offset -= GET_MODE_SIZE (DFmode);
5173+      }
5174+}
5175+
5176+/* Return true if a move between register REGNO and its save slot (MEM)
5177+   can be done in a single move.  LOAD_P is true if we are loading
5178+   from the slot, false if we are storing to it.  */
5179+
5180+static bool
5181+mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
5182+{
5183+  return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
5184+                                     GET_MODE (mem), mem, load_p) == NO_REGS;
5185+}
5186+
5187+/* Emit a move from SRC to DEST, given that one of them is a register
5188+   save slot and that the other is a register.  TEMP is a temporary
5189+   GPR of the same mode that is available if need be.  */
5190+
5191+void
5192+mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
5193+{
5194+  unsigned int regno;
5195+  rtx mem;
5196+
5197+  if (REG_P (src))
5198+    {
5199+      regno = REGNO (src);
5200+      mem = dest;
5201+    }
5202+  else
5203+    {
5204+      regno = REGNO (dest);
5205+      mem = src;
5206+    }
5207+
5208+  if (mips_direct_save_slot_move_p (regno, mem, mem == src))
5209+    mips_emit_move (dest, src);
5210+  else
5211+    {
5212+      gcc_assert (!reg_overlap_mentioned_p (dest, temp));
5213+      mips_emit_move (temp, src);
5214+      mips_emit_move (dest, temp);
5215+    }
5216+  if (MEM_P (dest))
5217+    mips_set_frame_expr (mips_frame_set (dest, src));
5218+}
5219+
5220+/* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE.  */
5221+
5222+static void
5223+mips_output_function_prologue (FILE *file ATTRIBUTE_UNUSED,
5224+                               HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5225+{
5226+  const char *fnname;
5227+
5228+  /* Get the function name the same way that toplev.c does before calling
5229+     assemble_start_function.  This is needed so that the name used here
5230+     exactly matches the name used in ASM_DECLARE_FUNCTION_NAME.  */
5231+  fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
5232+
5233+  ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, fnname, "function");
5234+  assemble_name (asm_out_file, fnname);
5235+  fputs (":\n", asm_out_file);
5236+}
5237+
5238+/* Save register REG to MEM.  Make the instruction frame-related.  */
5239+
5240+static void
5241+mips_save_reg (rtx reg, rtx mem)
5242+{
5243+  mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
5244+}
5245+
5246+
5247+/* Expand the "prologue" pattern.  */
5248+
5249+void
5250+mips_expand_prologue (void)
5251+{
5252+  const struct mips_frame_info *frame;
5253+  HOST_WIDE_INT size;
5254+  rtx insn;
5255+
5256+  frame = &cfun->machine->frame;
5257+  size = frame->total_size;
5258+
5259+  if (flag_stack_usage)
5260+    current_function_static_stack_size = size;
5261+
5262+  /* Save the registers.  Allocate up to MIPS_MAX_FIRST_STACK_STEP
5263+     bytes beforehand; this is enough to cover the register save area
5264+     without going out of range.  */
5265+  if ((frame->mask | frame->fmask) != 0)
5266+    {
5267+      HOST_WIDE_INT step1;
5268+
5269+      step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
5270+      insn = gen_add3_insn (stack_pointer_rtx,
5271+                           stack_pointer_rtx,
5272+                           GEN_INT (-step1));
5273+      RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
5274+      size -= step1;
5275+      mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
5276+    }
5277+
5278+  /* Set up the frame pointer, if we're using one.  */
5279+  if (frame_pointer_needed)
5280+    {
5281+      insn = gen_add3_insn (hard_frame_pointer_rtx, stack_pointer_rtx,
5282+                            GEN_INT (frame->hard_frame_pointer_offset - size));
5283+      RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
5284+    }
5285+
5286+  /* Allocate the rest of the frame.  */
5287+  if (size > 0)
5288+    {
5289+      if (SMALL_OPERAND (-size))
5290+       RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
5291+                                                      stack_pointer_rtx,
5292+                                                      GEN_INT (-size)))) = 1;
5293+      else
5294+       {
5295+         mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
5296+         emit_insn (gen_sub3_insn (stack_pointer_rtx,
5297+                                   stack_pointer_rtx,
5298+                                   MIPS_PROLOGUE_TEMP (Pmode)));
5299+
5300+         /* Describe the combined effect of the previous instructions.  */
5301+         mips_set_frame_expr
5302+           (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
5303+                         plus_constant (stack_pointer_rtx, -size)));
5304+       }
5305+    }
5306+}
5307+
5308+/* Emit instructions to restore register REG from slot MEM.  */
5309+
5310+static void
5311+mips_restore_reg (rtx reg, rtx mem)
5312+{
5313+  mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg), false));
5314+}
5315+
5316+static void
5317+mips_restore_reg_sibcall (rtx reg, rtx mem)
5318+{
5319+  mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg), true));
5320+}
5321+
5322+/* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
5323+   says which.  */
5324+
5325+static bool riscv_in_utfunc = false;
5326+
5327+void
5328+mips_expand_epilogue (bool sibcall_p)
5329+{
5330+  const struct mips_frame_info *frame;
5331+  HOST_WIDE_INT step1, step2;
5332+
5333+  if (!sibcall_p && mips_can_use_return_insn ())
5334+    {
5335+      if (riscv_in_utfunc)
5336+        emit_insn(gen_riscv_stop());
5337+
5338+      emit_jump_insn (gen_return ());
5339+      return;
5340+    }
5341+
5342+  /* Split the frame into two.  STEP1 is the amount of stack we should
5343+     deallocate before restoring the registers.  STEP2 is the amount we
5344+     should deallocate afterwards.
5345+
5346+     Start off by assuming that no registers need to be restored.  */
5347+  frame = &cfun->machine->frame;
5348+  step1 = frame->total_size;
5349+  step2 = 0;
5350+
5351+  /* Move past any dynamic stack allocations. */
5352+  if (cfun->calls_alloca)
5353+    {
5354+      rtx adjust = GEN_INT (-frame->hard_frame_pointer_offset);
5355+      if (!SMALL_INT (adjust))
5356+       {
5357+         mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode, sibcall_p), adjust);
5358+         adjust = MIPS_EPILOGUE_TEMP (Pmode, sibcall_p);
5359+       }
5360+
5361+      emit_insn (gen_add3_insn (stack_pointer_rtx, hard_frame_pointer_rtx, adjust));
5362+    }
5363+
5364+  /* If we need to restore registers, deallocate as much stack as
5365+     possible in the second step without going out of range.  */
5366+  if ((frame->mask | frame->fmask) != 0)
5367+    {
5368+      step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
5369+      step1 -= step2;
5370+    }
5371+
5372+  /* Set TARGET to BASE + STEP1.  */
5373+  if (step1 > 0)
5374+    {
5375+      /* Get an rtx for STEP1 that we can add to BASE.  */
5376+      rtx adjust = GEN_INT (step1);
5377+      if (!SMALL_OPERAND (step1))
5378+       {
5379+         mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode, sibcall_p), adjust);
5380+         adjust = MIPS_EPILOGUE_TEMP (Pmode, sibcall_p);
5381+       }
5382+
5383+      emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
5384+    }
5385+
5386+  /* Restore the registers.  */
5387+  mips_for_each_saved_gpr_and_fpr (frame->total_size - step2, 
5388+    sibcall_p ? mips_restore_reg_sibcall : mips_restore_reg);
5389+
5390+  /* Deallocate the final bit of the frame.  */
5391+  if (step2 > 0)
5392+    emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
5393+                             GEN_INT (step2)));
5394+
5395+  /* Add in the __builtin_eh_return stack adjustment.  We need to
5396+     use a temporary in MIPS16 code.  */
5397+  if (crtl->calls_eh_return)
5398+    emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
5399+                             EH_RETURN_STACKADJ_RTX));
5400+
5401+  if (!sibcall_p)
5402+    emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
5403+}
5404+
5405+/* Return nonzero if this function is known to have a null epilogue.
5406+   This allows the optimizer to omit jumps to jumps if no stack
5407+   was created.  */
5408+
5409+bool
5410+mips_can_use_return_insn (void)
5411+{
5412+  return reload_completed && cfun->machine->frame.total_size == 0;
5413+}
5414+
5415+/* Return true if register REGNO can store a value of mode MODE.
5416+   The result of this function is cached in mips_hard_regno_mode_ok.  */
5417+
5418+static bool
5419+mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
5420+{
5421+  unsigned int size;
5422+  enum mode_class mclass;
5423+
5424+  if (VECTOR_MODE_P(mode))
5425+  {
5426+    switch (mode)
5427+    {
5428+      case MIPS_RISCV_VECTOR_MODE_NAME(DI):
5429+      case MIPS_RISCV_VECTOR_MODE_NAME(SI):
5430+      case MIPS_RISCV_VECTOR_MODE_NAME(HI):
5431+      case MIPS_RISCV_VECTOR_MODE_NAME(QI):
5432+        return VEC_GP_REG_P(regno);
5433+
5434+      case MIPS_RISCV_VECTOR_MODE_NAME(DF):
5435+      case MIPS_RISCV_VECTOR_MODE_NAME(SF):
5436+        return VEC_FP_REG_P(regno);
5437+
5438+      default:
5439+        return false;
5440+    }
5441+  }
5442+
5443+  if (mode == CCmode)
5444+    return GP_REG_P (regno);
5445+
5446+  size = GET_MODE_SIZE (mode);
5447+  mclass = GET_MODE_CLASS (mode);
5448+
5449+  if (GP_REG_P (regno))
5450+    return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
5451+
5452+  if (FP_REG_P (regno))
5453+    {
5454+      /* Allow TFmode for CCmode reloads.  */
5455+      if (mode == TFmode)
5456+       return true;
5457+
5458+      if (mclass == MODE_FLOAT
5459+         || mclass == MODE_COMPLEX_FLOAT
5460+         || mclass == MODE_VECTOR_FLOAT)
5461+       return size <= UNITS_PER_FPVALUE;
5462+
5463+      /* Allow integer modes that fit into a single register.  We need
5464+        to put integers into FPRs when using instructions like CVT
5465+        and TRUNC.  There's no point allowing sizes smaller than a word,
5466+        because the FPU has no appropriate load/store instructions.  */
5467+      if (mclass == MODE_INT)
5468+       return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
5469+    }
5470+
5471+  if (regno == GOT_VERSION_REGNUM)
5472+    return mode == SImode;
5473+
5474+  return false;
5475+}
5476+
5477+/* Implement HARD_REGNO_NREGS.  */
5478+
5479+unsigned int
5480+mips_hard_regno_nregs (int regno, enum machine_mode mode)
5481+{
5482+  if (VECTOR_MODE_P(mode))
5483+    return 1;
5484+
5485+  if (VEC_GP_REG_P(regno) || VEC_FP_REG_P(regno))
5486+    return 1;
5487+
5488+  if (FP_REG_P (regno))
5489+    return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
5490+
5491+  /* All other registers are word-sized.  */
5492+  return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5493+}
5494+
5495+/* Implement CLASS_MAX_NREGS, taking the maximum of the cases
5496+   in mips_hard_regno_nregs.  */
5497+
5498+int
5499+mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
5500+{
5501+  int size;
5502+  HARD_REG_SET left;
5503+
5504+  if (VECTOR_MODE_P(mode))
5505+    return 1;
5506+
5507+  if ((rclass == VEC_GR_REGS) || (rclass == VEC_FP_REGS))
5508+    return 1;
5509+
5510+  size = 0x8000;
5511+  COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
5512+  if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
5513+    {
5514+      size = MIN (size, UNITS_PER_FPREG);
5515+      AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
5516+    }
5517+  if (!hard_reg_set_empty_p (left))
5518+    size = MIN (size, UNITS_PER_WORD);
5519+  return (GET_MODE_SIZE (mode) + size - 1) / size;
5520+}
5521+
5522+/* Implement CANNOT_CHANGE_MODE_CLASS.  */
5523+
5524+bool
5525+mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
5526+                              enum machine_mode to ATTRIBUTE_UNUSED,
5527+                              enum reg_class rclass)
5528+{
5529+  /* There are several problems with changing the modes of values
5530+     in floating-point registers:
5531+
5532+     - When a multi-word value is stored in paired floating-point
5533+       registers, the first register always holds the low word.
5534+       We therefore can't allow FPRs to change between single-word
5535+       and multi-word modes on big-endian targets.
5536+
5537+     - GCC assumes that each word of a multiword register can be accessed
5538+       individually using SUBREGs.  This is not true for floating-point
5539+       registers if they are bigger than a word.
5540+
5541+     - Loading a 32-bit value into a 64-bit floating-point register
5542+       will not sign-extend the value, despite what LOAD_EXTEND_OP says.
5543+       We can't allow FPRs to change from SImode to to a wider mode on
5544+       64-bit targets.
5545+
5546+     - If the FPU has already interpreted a value in one format, we must
5547+       not ask it to treat the value as having a different format.
5548+
5549+     We therefore disallow all mode changes involving FPRs.  */
5550+  return reg_classes_intersect_p (FP_REGS, rclass);
5551+}
5552+
5553+/* Return true if moves in mode MODE can use the FPU's mov.fmt instruction.  */
5554+
5555+static bool
5556+mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
5557+{
5558+  switch (mode)
5559+    {
5560+    case SFmode:
5561+    case DFmode:
5562+      return TARGET_HARD_FLOAT;
5563+
5564+    default:
5565+      return false;
5566+    }
5567+}
5568+
5569+/* Implement MODES_TIEABLE_P.  */
5570+
5571+bool
5572+mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
5573+{
5574+  /* FPRs allow no mode punning, so it's not worth tying modes if we'd
5575+     prefer to put one of them in FPRs.  */
5576+  return (mode1 == mode2
5577+         || (!mips_mode_ok_for_mov_fmt_p (mode1)
5578+             && !mips_mode_ok_for_mov_fmt_p (mode2)));
5579+}
5580+
5581+/* Implement TARGET_PREFERRED_RELOAD_CLASS.  */
5582+
5583+static reg_class_t
5584+mips_preferred_reload_class (rtx x, reg_class_t rclass)
5585+{
5586+  if (reg_class_subset_p (FP_REGS, rclass)
5587+      && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
5588+    return FP_REGS;
5589+
5590+  if (reg_class_subset_p (GR_REGS, rclass))
5591+    rclass = GR_REGS;
5592+
5593+  return rclass;
5594+}
5595+
5596+/* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
5597+   Return a "canonical" class to represent it in later calculations.  */
5598+
5599+static reg_class_t
5600+mips_canonicalize_move_class (reg_class_t rclass)
5601+{
5602+  if (reg_class_subset_p (rclass, GENERAL_REGS))
5603+    rclass = GENERAL_REGS;
5604+
5605+  return rclass;
5606+}
5607+
5608+/* Return the cost of moving a value of mode MODE from a register of
5609+   class FROM to a GPR.  Return 0 for classes that are unions of other
5610+   classes handled by this function.  */
5611+
5612+static int
5613+mips_move_to_gpr_cost (reg_class_t from)
5614+{
5615+  switch (from)
5616+    {
5617+    case GENERAL_REGS:
5618+      return 1;
5619+
5620+    case FP_REGS:
5621+      /* FP->int moves can cause recoupling on decoupled implementations */
5622+      return 4;
5623+
5624+    default:
5625+      return 0;
5626+    }
5627+}
5628+
5629+/* Return the cost of moving a value of mode MODE from a GPR to a
5630+   register of class TO.  Return 0 for classes that are unions of
5631+   other classes handled by this function.  */
5632+
5633+static int
5634+mips_move_from_gpr_cost (reg_class_t to)
5635+{
5636+  switch (to)
5637+    {
5638+    case GENERAL_REGS:
5639+    case FP_REGS:
5640+      return 1;
5641+
5642+    default:
5643+      return 0;
5644+    }
5645+}
5646+
5647+/* Implement TARGET_REGISTER_MOVE_COST.  Return 0 for classes that are the
5648+   maximum of the move costs for subclasses; regclass will work out
5649+   the maximum for us.  */
5650+
5651+static int
5652+mips_register_move_cost (enum machine_mode mode,
5653+                        reg_class_t from, reg_class_t to)
5654+{
5655+  int cost1, cost2;
5656+
5657+  from = mips_canonicalize_move_class (from);
5658+  to = mips_canonicalize_move_class (to);
5659+
5660+  /* Handle moves that can be done without using general-purpose registers.  */
5661+  if (from == FP_REGS)
5662+    if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
5663+      /* fsgnj.fmt.  */
5664+      return 1;
5665+
5666+  /* Handle cases in which only one class deviates from the ideal.  */
5667+  if (from == GENERAL_REGS)
5668+    return mips_move_from_gpr_cost (to);
5669+  if (to == GENERAL_REGS)
5670+    return mips_move_to_gpr_cost (from);
5671+
5672+  /* Handles cases that require a GPR temporary.  */
5673+  cost1 = mips_move_to_gpr_cost (from);
5674+  if (cost1 != 0)
5675+    {
5676+      cost2 = mips_move_from_gpr_cost (to);
5677+      if (cost2 != 0)
5678+       return cost1 + cost2;
5679+    }
5680+
5681+  return 0;
5682+}
5683+
5684+/* Implement TARGET_MEMORY_MOVE_COST.  */
5685+
5686+static int
5687+mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
5688+{
5689+  return (mips_cost->memory_latency
5690+         + memory_move_secondary_cost (mode, rclass, in));
5691+} 
5692+
5693+/* Implement TARGET_IRA_COVER_CLASSES.  */
5694+
5695+static const reg_class_t *
5696+mips_ira_cover_classes (void)
5697+{
5698+  static const reg_class_t no_acc_classes[] = {
5699+    GR_REGS, FP_REGS, VEC_GR_REGS, VEC_FP_REGS,
5700+    LIM_REG_CLASSES
5701+  };
5702+
5703+  return no_acc_classes;
5704+}
5705+
5706+/* Return the register class required for a secondary register when
5707+   copying between one of the registers in RCLASS and value X, which
5708+   has mode MODE.  X is the source of the move if IN_P, otherwise it
5709+   is the destination.  Return NO_REGS if no secondary register is
5710+   needed.  */
5711+
5712+enum reg_class
5713+mips_secondary_reload_class (enum reg_class rclass,
5714+                            enum machine_mode mode, rtx x,
5715+                            bool in_p ATTRIBUTE_UNUSED)
5716+{
5717+  int regno;
5718+
5719+  regno = true_regnum (x);
5720+
5721+  if (reg_class_subset_p (rclass, FP_REGS))
5722+    {
5723+      if (MEM_P (x)
5724+         && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
5725+       /* In this case we can use lwc1, swc1, ldc1 or sdc1.  We'll use
5726+          pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported.  */
5727+       return NO_REGS;
5728+
5729+      if (GP_REG_P (regno) || x == CONST0_RTX (mode))
5730+       /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1.  */
5731+       return NO_REGS;
5732+
5733+      if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
5734+       /* We can force the constant to memory and use lwc1
5735+          and ldc1.  As above, we will use pairs of lwc1s if
5736+          ldc1 is not supported.  */
5737+       return NO_REGS;
5738+
5739+      if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
5740+       /* In this case we can use mov.fmt.  */
5741+       return NO_REGS;
5742+
5743+      /* Otherwise, we need to reload through an integer register.  */
5744+      return GR_REGS;
5745+    }
5746+  if (FP_REG_P (regno))
5747+    return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
5748+
5749+  return NO_REGS;
5750+}
5751+
5752+/* Implement TARGET_MODE_REP_EXTENDED.  */
5753+
5754+static int
5755+mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
5756+{
5757+  /* On 64-bit targets, SImode register values are sign-extended to DImode.  */
5758+  if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
5759+    return SIGN_EXTEND;
5760+
5761+  return UNKNOWN;
5762+}
5763+
5764+/* Implement TARGET_VALID_POINTER_MODE.  */
5765+
5766+static bool
5767+mips_valid_pointer_mode (enum machine_mode mode)
5768+{
5769+  return mode == SImode || (TARGET_64BIT && mode == DImode);
5770+}
5771+
5772+/* Implement TARGET_VECTOR_MODE_SUPPORTED_P.  */
5773+
5774+static bool
5775+mips_vector_mode_supported_p (enum machine_mode mode ATTRIBUTE_UNUSED)
5776+{
5777+  switch (mode)
5778+    {
5779+    case MIPS_RISCV_VECTOR_MODE_NAME(DI):
5780+    case MIPS_RISCV_VECTOR_MODE_NAME(SI):
5781+    case MIPS_RISCV_VECTOR_MODE_NAME(HI):
5782+    case MIPS_RISCV_VECTOR_MODE_NAME(QI):
5783+    case MIPS_RISCV_VECTOR_MODE_NAME(DF):
5784+    case MIPS_RISCV_VECTOR_MODE_NAME(SF):
5785+      return true;
5786+
5787+    default:
5788+      return false;
5789+    }
5790+}
5791+
5792+/* Implement TARGET_SCALAR_MODE_SUPPORTED_P.  */
5793+
5794+static bool
5795+mips_scalar_mode_supported_p (enum machine_mode mode)
5796+{
5797+  if (ALL_FIXED_POINT_MODE_P (mode)
5798+      && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
5799+    return true;
5800+
5801+  return default_scalar_mode_supported_p (mode);
5802+}
5803+
5804+/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE.  */
5805+
5806+static enum machine_mode
5807+mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
5808+{
5809+  return word_mode;
5810+}
5811+
5812+/* Implement TARGET_INIT_LIBFUNCS.  */
5813+
5814+static void
5815+mips_init_libfuncs (void)
5816+{
5817+}
5818+
5819+/* Return the assembly code for INSN, which has the operands given by
5820+   OPERANDS, and which branches to OPERANDS[0] if some condition is true.
5821+   BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
5822+   is in range of a direct branch.  BRANCH_IF_FALSE is an inverted
5823+   version of BRANCH_IF_TRUE.  */
5824+
5825+const char *
5826+mips_output_conditional_branch (rtx insn, rtx *operands,
5827+                               const char *branch_if_true,
5828+                               const char *branch_if_false)
5829+{
5830+  unsigned int length;
5831+  rtx taken, not_taken;
5832+
5833+  gcc_assert (LABEL_P (operands[0]));
5834+
5835+  length = get_attr_length (insn);
5836+  if (length <= 4)
5837+    return branch_if_true;
5838+
5839+  /* Generate a reversed branch around a direct jump.  This fallback does
5840+     not use branch-likely instructions.  */
5841+  not_taken = gen_label_rtx ();
5842+  taken = operands[0];
5843+
5844+  /* Generate the reversed branch to NOT_TAKEN.  */
5845+  operands[0] = not_taken;
5846+  output_asm_insn (branch_if_false, operands);
5847+
5848+  /* Output the unconditional branch to TAKEN.  */
5849+  output_asm_insn ("j\t%0", &taken);
5850+
5851+  /* Output NOT_TAKEN.  */
5852+  targetm.asm_out.internal_label (asm_out_file, "L",
5853+                                 CODE_LABEL_NUMBER (not_taken));
5854+  return "";
5855+}
5856+
5857+/* Implement TARGET_SCHED_ADJUST_COST.  We assume that anti and output
5858+   dependencies have no cost. */
5859+
5860+static int
5861+mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
5862+                 rtx dep ATTRIBUTE_UNUSED, int cost)
5863+{
5864+  if (REG_NOTE_KIND (link) != 0)
5865+    return 0;
5866+  return cost;
5867+}
5868+
5869+/* Return the number of instructions that can be issued per cycle.  */
5870+
5871+static int
5872+mips_issue_rate (void)
5873+{
5874+  switch (mips_tune)
5875+    {
5876+    case PROCESSOR_ROCKET:
5877+      return 1;
5878+
5879+    default:
5880+      return 1;
5881+    }
5882+}
5883+
5884+/* This structure describes a single built-in function.  */
5885+struct mips_builtin_description {
5886+  /* The code of the main .md file instruction.  See mips_builtin_type
5887+     for more information.  */
5888+  enum insn_code icode;
5889+
5890+  /* The name of the built-in function.  */
5891+  const char *name;
5892+
5893+  /* Specifies how the function should be expanded.  */
5894+  enum mips_builtin_type builtin_type;
5895+
5896+  /* The function's prototype.  */
5897+  enum mips_function_type function_type;
5898+
5899+  /* Whether the function is available.  */
5900+  unsigned int (*avail) (void);
5901+};
5902+
5903+static unsigned int
5904+mips_builtin_avail_cache (void)
5905+{
5906+  return 0;
5907+}
5908+
5909+static unsigned int
5910+mips_builtin_avail_riscv (void)
5911+{
5912+  return 1;
5913+}
5914+
5915+/* Construct a mips_builtin_description from the given arguments.
5916+
5917+   INSN is the name of the associated instruction pattern, without the
5918+   leading CODE_FOR_mips_.
5919+
5920+   CODE is the floating-point condition code associated with the
5921+   function.  It can be 'f' if the field is not applicable.
5922+
5923+   NAME is the name of the function itself, without the leading
5924+   "__builtin_mips_".
5925+
5926+   BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
5927+
5928+   AVAIL is the name of the availability predicate, without the leading
5929+   mips_builtin_avail_.  */
5930+#define MIPS_BUILTIN(INSN, NAME, BUILTIN_TYPE, FUNCTION_TYPE, AVAIL)   \
5931+  { CODE_FOR_mips_ ## INSN, "__builtin_mips_" NAME,                    \
5932+    BUILTIN_TYPE, FUNCTION_TYPE, mips_builtin_avail_ ## AVAIL }
5933+
5934+/* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
5935+   mapped to instruction CODE_FOR_mips_<INSN>,  FUNCTION_TYPE and AVAIL
5936+   are as for MIPS_BUILTIN.  */
5937+#define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL)                     \
5938+  MIPS_BUILTIN (INSN, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
5939+
5940+/* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
5941+   function mapped to instruction CODE_FOR_mips_<INSN>,  FUNCTION_TYPE
5942+   and AVAIL are as for MIPS_BUILTIN.  */
5943+#define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL)           \
5944+  MIPS_BUILTIN (INSN, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET,            \
5945+               FUNCTION_TYPE, AVAIL)
5946+
5947+static const struct mips_builtin_description mips_builtins[] = {
5948+  DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache),
5949+
5950+  DIRECT_BUILTIN( riscv_vload_vdi, MIPS_VDI_FTYPE_CPOINTER, riscv ),
5951+  DIRECT_BUILTIN( riscv_vload_vsi, MIPS_VSI_FTYPE_CPOINTER, riscv ),
5952+  DIRECT_BUILTIN( riscv_vload_vhi, MIPS_VHI_FTYPE_CPOINTER, riscv ),
5953+  DIRECT_BUILTIN( riscv_vload_vqi, MIPS_VQI_FTYPE_CPOINTER, riscv ),
5954+  DIRECT_BUILTIN( riscv_vload_vdf, MIPS_VDF_FTYPE_CPOINTER, riscv ),
5955+  DIRECT_BUILTIN( riscv_vload_vsf, MIPS_VSF_FTYPE_CPOINTER, riscv ),
5956+
5957+  DIRECT_BUILTIN( riscv_vload_strided_vdi, MIPS_VDI_FTYPE_CPOINTER_DI, riscv ),
5958+  DIRECT_BUILTIN( riscv_vload_strided_vsi, MIPS_VSI_FTYPE_CPOINTER_DI, riscv ),
5959+  DIRECT_BUILTIN( riscv_vload_strided_vhi, MIPS_VHI_FTYPE_CPOINTER_DI, riscv ),
5960+  DIRECT_BUILTIN( riscv_vload_strided_vqi, MIPS_VQI_FTYPE_CPOINTER_DI, riscv ),
5961+  DIRECT_BUILTIN( riscv_vload_strided_vdf, MIPS_VDF_FTYPE_CPOINTER_DI, riscv ),
5962+  DIRECT_BUILTIN( riscv_vload_strided_vsf, MIPS_VSF_FTYPE_CPOINTER_DI, riscv ),
5963+
5964+  DIRECT_NO_TARGET_BUILTIN( riscv_vstore_vdi, MIPS_VOID_FTYPE_VDI_POINTER, riscv ),
5965+  DIRECT_NO_TARGET_BUILTIN( riscv_vstore_vsi, MIPS_VOID_FTYPE_VSI_POINTER, riscv ),
5966+  DIRECT_NO_TARGET_BUILTIN( riscv_vstore_vhi, MIPS_VOID_FTYPE_VHI_POINTER, riscv ),
5967+  DIRECT_NO_TARGET_BUILTIN( riscv_vstore_vqi, MIPS_VOID_FTYPE_VQI_POINTER, riscv ),
5968+  DIRECT_NO_TARGET_BUILTIN( riscv_vstore_vdf, MIPS_VOID_FTYPE_VDF_POINTER, riscv ),
5969+  DIRECT_NO_TARGET_BUILTIN( riscv_vstore_vsf, MIPS_VOID_FTYPE_VSF_POINTER, riscv ),
5970+
5971+  DIRECT_NO_TARGET_BUILTIN( riscv_vstore_strided_vdi, MIPS_VOID_FTYPE_VDI_POINTER_DI, riscv ),
5972+  DIRECT_NO_TARGET_BUILTIN( riscv_vstore_strided_vsi, MIPS_VOID_FTYPE_VSI_POINTER_DI, riscv ),
5973+  DIRECT_NO_TARGET_BUILTIN( riscv_vstore_strided_vhi, MIPS_VOID_FTYPE_VHI_POINTER_DI, riscv ),
5974+  DIRECT_NO_TARGET_BUILTIN( riscv_vstore_strided_vqi, MIPS_VOID_FTYPE_VQI_POINTER_DI, riscv ),
5975+  DIRECT_NO_TARGET_BUILTIN( riscv_vstore_strided_vdf, MIPS_VOID_FTYPE_VDF_POINTER_DI, riscv ),
5976+  DIRECT_NO_TARGET_BUILTIN( riscv_vstore_strided_vsf, MIPS_VOID_FTYPE_VSF_POINTER_DI, riscv ),
5977+};
5978+
5979+/* Index I is the function declaration for mips_builtins[I], or null if the
5980+   function isn't defined on this target.  */
5981+static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
5982+
5983+/* MODE is a vector mode whose elements have type TYPE.  Return the type
5984+   of the vector itself.  */
5985+
5986+static tree
5987+mips_builtin_vector_type (tree type, enum machine_mode mode)
5988+{
5989+  static tree types[2 * (int) MAX_MACHINE_MODE];
5990+  int mode_index;
5991+
5992+  mode_index = (int) mode;
5993+
5994+  if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
5995+    mode_index += MAX_MACHINE_MODE;
5996+
5997+  if (types[mode_index] == NULL_TREE)
5998+    types[mode_index] = build_vector_type_for_mode (type, mode);
5999+  return types[mode_index];
6000+}
6001+
6002+/* Return a type for 'const volatile void *'.  */
6003+
6004+static tree
6005+mips_build_cvpointer_type (void)
6006+{
6007+  static tree cache;
6008+
6009+  if (cache == NULL_TREE)
6010+    cache = build_pointer_type (build_qualified_type
6011+                               (void_type_node,
6012+                                TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
6013+  return cache;
6014+}
6015+
6016+/* Source-level argument types.  */
6017+#define MIPS_ATYPE_VOID void_type_node
6018+#define MIPS_ATYPE_INT integer_type_node
6019+#define MIPS_ATYPE_POINTER ptr_type_node
6020+#define MIPS_ATYPE_CPOINTER const_ptr_type_node
6021+#define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
6022+
6023+/* Standard mode-based argument types.  */
6024+#define MIPS_ATYPE_UQI unsigned_intQI_type_node
6025+#define MIPS_ATYPE_SI intSI_type_node
6026+#define MIPS_ATYPE_USI unsigned_intSI_type_node
6027+#define MIPS_ATYPE_DI intDI_type_node
6028+#define MIPS_ATYPE_UDI unsigned_intDI_type_node
6029+#define MIPS_ATYPE_SF float_type_node
6030+#define MIPS_ATYPE_DF double_type_node
6031+
6032+/* Vector argument types.  */
6033+#define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
6034+#define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
6035+#define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
6036+#define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
6037+#define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
6038+#define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
6039+#define MIPS_ATYPE_UV2SI                                       \
6040+  mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
6041+#define MIPS_ATYPE_UV4HI                                       \
6042+  mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
6043+#define MIPS_ATYPE_UV8QI                                       \
6044+  mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
6045+
6046+#define MIPS_ATYPE_VDI \
6047+  mips_builtin_vector_type( intDI_type_node, \
6048+    MIPS_RISCV_VECTOR_MODE_NAME(DI) )
6049+
6050+#define MIPS_ATYPE_VSI \
6051+  mips_builtin_vector_type( intSI_type_node, \
6052+    MIPS_RISCV_VECTOR_MODE_NAME(SI) )
6053+
6054+#define MIPS_ATYPE_VHI \
6055+  mips_builtin_vector_type( intHI_type_node, \
6056+    MIPS_RISCV_VECTOR_MODE_NAME(HI) )
6057+
6058+#define MIPS_ATYPE_VQI \
6059+  mips_builtin_vector_type( intQI_type_node, \
6060+    MIPS_RISCV_VECTOR_MODE_NAME(QI) )
6061+
6062+#define MIPS_ATYPE_VDF \
6063+  mips_builtin_vector_type( double_type_node, \
6064+    MIPS_RISCV_VECTOR_MODE_NAME(DF) )
6065+
6066+#define MIPS_ATYPE_VSF \
6067+  mips_builtin_vector_type( float_type_node, \
6068+    MIPS_RISCV_VECTOR_MODE_NAME(SF) )
6069+
6070+/* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
6071+   their associated MIPS_ATYPEs.  */
6072+#define MIPS_FTYPE_ATYPES1(A, B) \
6073+  MIPS_ATYPE_##A, MIPS_ATYPE_##B
6074+
6075+#define MIPS_FTYPE_ATYPES2(A, B, C) \
6076+  MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
6077+
6078+#define MIPS_FTYPE_ATYPES3(A, B, C, D) \
6079+  MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
6080+
6081+#define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
6082+  MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
6083+  MIPS_ATYPE_##E
6084+
6085+/* Return the function type associated with function prototype TYPE.  */
6086+
6087+static tree
6088+mips_build_function_type (enum mips_function_type type)
6089+{
6090+  static tree types[(int) MIPS_MAX_FTYPE_MAX];
6091+
6092+  if (types[(int) type] == NULL_TREE)
6093+    switch (type)
6094+      {
6095+#define DEF_MIPS_FTYPE(NUM, ARGS)                                      \
6096+  case MIPS_FTYPE_NAME##NUM ARGS:                                      \
6097+    types[(int) type]                                                  \
6098+      = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS,         \
6099+                                 NULL_TREE);                           \
6100+    break;
6101+#include "config/riscv/riscv-ftypes.def"
6102+#undef DEF_MIPS_FTYPE
6103+      default:
6104+       gcc_unreachable ();
6105+      }
6106+
6107+  return types[(int) type];
6108+}
6109+
6110+/* Implement TARGET_INIT_BUILTINS.  */
6111+
6112+static void
6113+mips_init_builtins (void)
6114+{
6115+  const struct mips_builtin_description *d;
6116+  unsigned int i;
6117+
6118+  /* Iterate through all of the bdesc arrays, initializing all of the
6119+     builtin functions.  */
6120+  for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
6121+    {
6122+      d = &mips_builtins[i];
6123+      if (d->avail ())
6124+       mips_builtin_decls[i]
6125+         = add_builtin_function (d->name,
6126+                                 mips_build_function_type (d->function_type),
6127+                                 i, BUILT_IN_MD, NULL, NULL);
6128+    }
6129+}
6130+
6131+/* Implement TARGET_BUILTIN_DECL.  */
6132+
6133+static tree
6134+mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
6135+{
6136+  if (code >= ARRAY_SIZE (mips_builtins))
6137+    return error_mark_node;
6138+  return mips_builtin_decls[code];
6139+}
6140+
6141+/* Take argument ARGNO from EXP's argument list and convert it into a
6142+   form suitable for input operand OPNO of instruction ICODE.  Return the
6143+   value.  */
6144+
6145+static rtx
6146+mips_prepare_builtin_arg (enum insn_code icode,
6147+                         unsigned int opno, tree exp, unsigned int argno)
6148+{
6149+  tree arg;
6150+  rtx value;
6151+  enum machine_mode mode;
6152+
6153+  arg = CALL_EXPR_ARG (exp, argno);
6154+  value = expand_normal (arg);
6155+  mode = insn_data[icode].operand[opno].mode;
6156+  if (!insn_data[icode].operand[opno].predicate (value, mode))
6157+    {
6158+      /* We need to get the mode from ARG for two reasons:
6159+
6160+          - to cope with address operands, where MODE is the mode of the
6161+            memory, rather than of VALUE itself.
6162+
6163+          - to cope with special predicates like pmode_register_operand,
6164+            where MODE is VOIDmode.  */
6165+      value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value);
6166+
6167+      /* Check the predicate again.  */
6168+      if (!insn_data[icode].operand[opno].predicate (value, mode))
6169+       {
6170+         error ("invalid argument to built-in function");
6171+         return const0_rtx;
6172+       }
6173+    }
6174+
6175+  return value;
6176+}
6177+
6178+/* Return an rtx suitable for output operand OP of instruction ICODE.
6179+   If TARGET is non-null, try to use it where possible.  */
6180+
6181+static rtx
6182+mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
6183+{
6184+  enum machine_mode mode;
6185+
6186+  mode = insn_data[icode].operand[op].mode;
6187+  if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
6188+    target = gen_reg_rtx (mode);
6189+
6190+  return target;
6191+}
6192+
6193+/* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
6194+   HAS_TARGET_P says which.  EXP is the CALL_EXPR that calls the function
6195+   and ICODE is the code of the associated .md pattern.  TARGET, if nonnull,
6196+   suggests a good place to put the result.  */
6197+
6198+static rtx
6199+mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
6200+                           bool has_target_p)
6201+{
6202+  rtx ops[MAX_RECOG_OPERANDS];
6203+  int opno, argno;
6204+
6205+  /* Map any target to operand 0.  */
6206+  opno = 0;
6207+  if (has_target_p)
6208+    {
6209+      target = mips_prepare_builtin_target (icode, opno, target);
6210+      ops[opno] = target;
6211+      opno++;
6212+    }
6213+
6214+  /* Map the arguments to the other operands.  The n_operands value
6215+     for an expander includes match_dups and match_scratches as well as
6216+     match_operands, so n_operands is only an upper bound on the number
6217+     of arguments to the expander function.  */
6218+  gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
6219+  for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
6220+    ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
6221+
6222+  switch (opno)
6223+    {
6224+    case 2:
6225+      emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
6226+      break;
6227+
6228+    case 3:
6229+      emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
6230+      break;
6231+
6232+    case 4:
6233+      emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
6234+      break;
6235+
6236+    default:
6237+      gcc_unreachable ();
6238+    }
6239+  return target;
6240+}
6241+
6242+/* Implement TARGET_EXPAND_BUILTIN.  */
6243+
6244+static rtx
6245+mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
6246+                    enum machine_mode mode ATTRIBUTE_UNUSED,
6247+                    int ignore ATTRIBUTE_UNUSED)
6248+{
6249+  tree fndecl;
6250+  unsigned int fcode, avail;
6251+  const struct mips_builtin_description *d;
6252+
6253+  fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
6254+  fcode = DECL_FUNCTION_CODE (fndecl);
6255+  gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
6256+  d = &mips_builtins[fcode];
6257+  avail = d->avail ();
6258+  gcc_assert (avail != 0);
6259+  switch (d->builtin_type)
6260+    {
6261+    case MIPS_BUILTIN_DIRECT:
6262+      return mips_expand_builtin_direct (d->icode, target, exp, true);
6263+
6264+    case MIPS_BUILTIN_DIRECT_NO_TARGET:
6265+      return mips_expand_builtin_direct (d->icode, target, exp, false);
6266+    }
6267+  gcc_unreachable ();
6268+}
6269+
6270+/* This structure records that the current function has a LO_SUM
6271+   involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
6272+   the largest offset applied to BASE by all such LO_SUMs.  */
6273+struct mips_lo_sum_offset {
6274+  rtx base;
6275+  HOST_WIDE_INT offset;
6276+};
6277+
6278+/* Return a hash value for SYMBOL_REF or LABEL_REF BASE.  */
6279+
6280+static hashval_t
6281+mips_hash_base (rtx base)
6282+{
6283+  int do_not_record_p;
6284+
6285+  return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
6286+}
6287+
6288+/* Hash-table callbacks for mips_lo_sum_offsets.  */
6289+
6290+static hashval_t
6291+mips_lo_sum_offset_hash (const void *entry)
6292+{
6293+  return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
6294+}
6295+
6296+static int
6297+mips_lo_sum_offset_eq (const void *entry, const void *value)
6298+{
6299+  return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
6300+                     (const_rtx) value);
6301+}
6302+
6303+/* Look up symbolic constant X in HTAB, which is a hash table of
6304+   mips_lo_sum_offsets.  If OPTION is NO_INSERT, return true if X can be
6305+   paired with a recorded LO_SUM, otherwise record X in the table.  */
6306+
6307+static bool
6308+mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
6309+{
6310+  rtx base, offset;
6311+  void **slot;
6312+  struct mips_lo_sum_offset *entry;
6313+
6314+  /* Split X into a base and offset.  */
6315+  split_const (x, &base, &offset);
6316+  if (UNSPEC_ADDRESS_P (base))
6317+    base = UNSPEC_ADDRESS (base);
6318+
6319+  /* Look up the base in the hash table.  */
6320+  slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
6321+  if (slot == NULL)
6322+    return false;
6323+
6324+  entry = (struct mips_lo_sum_offset *) *slot;
6325+  if (option == INSERT)
6326+    {
6327+      if (entry == NULL)
6328+       {
6329+         entry = XNEW (struct mips_lo_sum_offset);
6330+         entry->base = base;
6331+         entry->offset = INTVAL (offset);
6332+         *slot = entry;
6333+       }
6334+      else
6335+       {
6336+         if (INTVAL (offset) > entry->offset)
6337+           entry->offset = INTVAL (offset);
6338+       }
6339+    }
6340+  return INTVAL (offset) <= entry->offset;
6341+}
6342+
6343+/* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
6344+   Record every LO_SUM in *LOC.  */
6345+
6346+static int
6347+mips_record_lo_sum (rtx *loc, void *data)
6348+{
6349+  if (GET_CODE (*loc) == LO_SUM)
6350+    mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
6351+  return 0;
6352+}
6353+
6354+/* Return true if INSN is a SET of an orphaned high-part relocation.
6355+   HTAB is a hash table of mips_lo_sum_offsets that describes all the
6356+   LO_SUMs in the current function.  */
6357+
6358+static bool
6359+mips_orphaned_high_part_p (htab_t htab, rtx insn)
6360+{
6361+  rtx x, set;
6362+
6363+  set = single_set (insn);
6364+  if (set)
6365+    {
6366+      /* Check for %his.  */
6367+      x = SET_SRC (set);
6368+      if (GET_CODE (x) == HIGH
6369+         && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
6370+       return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
6371+    }
6372+  return false;
6373+}
6374+
6375+/* Delete any high-part relocations whose partnering low parts are dead. */
6376+
6377+static void
6378+mips_reorg_process_insns (void)
6379+{
6380+  rtx insn, next_insn;
6381+  htab_t htab;
6382+
6383+  /* Force all instructions to be split into their final form.  */
6384+  split_all_insns_noflow ();
6385+
6386+  /* Recalculate instruction lengths without taking nops into account.  */
6387+  shorten_branches (get_insns ());
6388+
6389+  htab = htab_create (37, mips_lo_sum_offset_hash,
6390+                     mips_lo_sum_offset_eq, free);
6391+
6392+  /* Make a first pass over the instructions, recording all the LO_SUMs.  */
6393+  for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
6394+    if (USEFUL_INSN_P (insn))
6395+      for_each_rtx (&PATTERN (insn), mips_record_lo_sum, htab);
6396+
6397+  /* Make a second pass over the instructions.  Delete orphaned
6398+     high-part relocations or turn them into NOPs.  Avoid hazards
6399+     by inserting NOPs.  */
6400+  for (insn = get_insns (); insn != 0; insn = next_insn)
6401+    {
6402+      next_insn = NEXT_INSN (insn);
6403+      if (USEFUL_INSN_P (insn))
6404+       {
6405+         /* INSN is a single instruction.  Delete it if it's an
6406+            orphaned high-part relocation.  */
6407+         if (mips_orphaned_high_part_p (htab, insn))
6408+           delete_insn (insn);
6409+       }
6410+    }
6411+
6412+  htab_delete (htab);
6413+}
6414+
6415+/* Implement TARGET_MACHINE_DEPENDENT_REORG.  */
6416+
6417+static void
6418+mips_reorg (void)
6419+{
6420+  mips_reorg_process_insns ();
6421+}
6422+
6423+/* Implement TARGET_ASM_OUTPUT_MI_THUNK.  Generate rtl rather than asm text
6424+   in order to avoid duplicating too much logic from elsewhere.  */
6425+
6426+static void
6427+mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
6428+                     HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
6429+                     tree function)
6430+{
6431+  rtx this_rtx, temp1, temp2, insn, fnaddr;
6432+  bool use_sibcall_p;
6433+
6434+  /* Pretend to be a post-reload pass while generating rtl.  */
6435+  reload_completed = 1;
6436+
6437+  /* Mark the end of the (empty) prologue.  */
6438+  emit_note (NOTE_INSN_PROLOGUE_END);
6439+
6440+  /* Determine if we can use a sibcall to call FUNCTION directly.  */
6441+  fnaddr = XEXP (DECL_RTL (function), 0);
6442+  use_sibcall_p = const_call_insn_operand (fnaddr, Pmode);
6443+
6444+  /* We need two temporary registers in some cases.  */
6445+  temp1 = gen_rtx_REG (Pmode, 2);
6446+  temp2 = gen_rtx_REG (Pmode, 3);
6447+
6448+  /* Find out which register contains the "this" pointer.  */
6449+  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
6450+    this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
6451+  else
6452+    this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
6453+
6454+  /* Add DELTA to THIS_RTX.  */
6455+  if (delta != 0)
6456+    {
6457+      rtx offset = GEN_INT (delta);
6458+      if (!SMALL_OPERAND (delta))
6459+       {
6460+         mips_emit_move (temp1, offset);
6461+         offset = temp1;
6462+       }
6463+      emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
6464+    }
6465+
6466+  /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX.  */
6467+  if (vcall_offset != 0)
6468+    {
6469+      rtx addr;
6470+
6471+      /* Set TEMP1 to *THIS_RTX.  */
6472+      mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
6473+
6474+      /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET.  */
6475+      addr = mips_add_offset (temp2, temp1, vcall_offset);
6476+
6477+      /* Load the offset and add it to THIS_RTX.  */
6478+      mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
6479+      emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
6480+    }
6481+
6482+  /* Jump to the target function.  Use a sibcall if direct jumps are
6483+     allowed, otherwise load the address into a register first.  */
6484+  if (use_sibcall_p)
6485+    {
6486+      insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
6487+      SIBLING_CALL_P (insn) = 1;
6488+    }
6489+  else
6490+    {
6491+      mips_emit_move(temp1, fnaddr);
6492+      emit_jump_insn (gen_indirect_jump (temp1));
6493+    }
6494+
6495+  /* Run just enough of rest_of_compilation.  This sequence was
6496+     "borrowed" from alpha.c.  */
6497+  insn = get_insns ();
6498+  insn_locators_alloc ();
6499+  split_all_insns_noflow ();
6500+  shorten_branches (insn);
6501+  final_start_function (insn, file, 1);
6502+  final (insn, file, 1);
6503+  final_end_function ();
6504+
6505+  /* Clean up the vars set above.  Note that final_end_function resets
6506+     the global pointer for us.  */
6507+  reload_completed = 0;
6508+}
6509+
6510+/* Implement TARGET_SET_CURRENT_FUNCTION.  Decide whether the current
6511+   function should use the MIPS16 ISA and switch modes accordingly.  */
6512+
6513+static void
6514+mips_set_current_function (tree fndecl)
6515+{
6516+  bool utfunc = fndecl && (lookup_attribute("utfunc", DECL_ATTRIBUTES(fndecl)) != NULL);
6517+  if (riscv_in_utfunc != utfunc)
6518+    reinit_regs();
6519+  riscv_in_utfunc = utfunc;
6520+}
6521+
6522+/* Allocate a chunk of memory for per-function machine-dependent data.  */
6523+
6524+static struct machine_function *
6525+mips_init_machine_status (void)
6526+{
6527+  return ggc_alloc_cleared_machine_function ();
6528+}
6529+
6530+/* Return the mips_cpu_info entry for the processor or ISA given
6531+   by CPU_STRING.  Return null if the string isn't recognized.
6532+
6533+   A similar function exists in GAS.  */
6534+
6535+static const struct mips_cpu_info *
6536+mips_parse_cpu (const char *cpu_string)
6537+{
6538+  unsigned int i;
6539+
6540+  for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
6541+    if (strcmp (mips_cpu_info_table[i].name, cpu_string) == 0)
6542+      return mips_cpu_info_table + i;
6543+
6544+  return NULL;
6545+}
6546+
6547+/* Implement TARGET_HANDLE_OPTION.  */
6548+
6549+static bool
6550+mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
6551+{
6552+  switch (code)
6553+    {
6554+    case OPT_mtune_:
6555+      return mips_parse_cpu (arg) != 0;
6556+
6557+    default:
6558+      return true;
6559+    }
6560+}
6561+
6562+/* Implement TARGET_OPTION_OVERRIDE.  */
6563+
6564+static void
6565+mips_option_override (void)
6566+{
6567+  int i, start, regno, mode;
6568+  const struct mips_cpu_info *info;
6569+
6570+#ifdef SUBTARGET_OVERRIDE_OPTIONS
6571+  SUBTARGET_OVERRIDE_OPTIONS;
6572+#endif
6573+
6574+  info = mips_parse_cpu (MIPS_CPU_STRING_DEFAULT);
6575+  gcc_assert (info);
6576+  mips_tune = info->cpu;
6577+
6578+  if (mips_tune_string != 0)
6579+    {
6580+      const struct mips_cpu_info *tune = mips_parse_cpu (mips_tune_string);
6581+      if (tune)
6582+       mips_tune = tune->cpu;
6583+    }
6584+
6585+  flag_pcc_struct_return = 0;
6586+
6587+  /* Decide which rtx_costs structure to use.  */
6588+  if (optimize_size)
6589+    mips_cost = &mips_rtx_cost_optimize_size;
6590+  else
6591+    mips_cost = &mips_rtx_cost_data[mips_tune];
6592+
6593+  /* If the user hasn't specified a branch cost, use the processor's
6594+     default.  */
6595+  if (mips_branch_cost == 0)
6596+    mips_branch_cost = mips_cost->branch_cost;
6597+
6598+  if (flag_pic)
6599+    target_flags |= MASK_ABICALLS;
6600+
6601+  /* Prefer a call to memcpy over inline code when optimizing for size,
6602+     though see MOVE_RATIO in mips.h.  */
6603+  if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
6604+    target_flags |= MASK_MEMCPY;
6605+
6606+#ifdef MIPS_TFMODE_FORMAT
6607+  REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
6608+#endif
6609+
6610+  /* .cfi_* directives generate a read-only section, so fall back on
6611+     manual .eh_frame creation if we need the section to be writable.  */
6612+  if (TARGET_WRITABLE_EH_FRAME)
6613+    flag_dwarf2_cfi_asm = 0;
6614+
6615+  /* Set up array to map GCC register number to debug register number.
6616+     Ignore the special purpose register numbers.  */
6617+
6618+  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6619+    {
6620+      mips_dbx_regno[i] = INVALID_REGNUM;
6621+      if (GP_REG_P (i) || FP_REG_P (i))
6622+       mips_dwarf_regno[i] = i;
6623+      else
6624+       mips_dwarf_regno[i] = INVALID_REGNUM;
6625+    }
6626+
6627+  start = GP_DBX_FIRST - GP_REG_FIRST;
6628+  for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
6629+    mips_dbx_regno[i] = i + start;
6630+
6631+  start = FP_DBX_FIRST - FP_REG_FIRST;
6632+  for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
6633+    mips_dbx_regno[i] = i + start;
6634+
6635+  /* Set up mips_hard_regno_mode_ok.  */
6636+  for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
6637+    for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6638+      mips_hard_regno_mode_ok[mode][regno]
6639+       = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
6640+
6641+  /* Function to allocate machine-dependent function status.  */
6642+  init_machine_status = &mips_init_machine_status;
6643+
6644+  targetm.min_anchor_offset = -RISCV_IMM_REACH/2;
6645+  targetm.max_anchor_offset = RISCV_IMM_REACH/2-1;
6646+
6647+  targetm.const_anchor = RISCV_IMM_REACH/2;
6648+
6649+  mips_init_relocs ();
6650+
6651+  restore_target_globals (&default_target_globals);
6652+}
6653+
6654+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
6655+static const struct default_options mips_option_optimization_table[] =
6656+  {
6657+    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
6658+    { OPT_LEVELS_NONE, 0, NULL, 0 }
6659+  };
6660+
6661+/* Implement TARGET_CONDITIONAL_REGISTER_USAGE.  */
6662+
6663+static void
6664+mips_conditional_register_usage (void)
6665+{
6666+  int regno;
6667+
6668+  if (!TARGET_HARD_FLOAT)
6669+    {
6670+      for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
6671+       fixed_regs[regno] = call_used_regs[regno] = 1;
6672+    }
6673+
6674+  if (riscv_in_utfunc)
6675+  {
6676+    for (regno = CALLEE_SAVED_GP_REG_FIRST;
6677+         regno <= CALLEE_SAVED_GP_REG_LAST; regno++)
6678+    {
6679+      call_used_regs[regno] = 1;
6680+      call_really_used_regs[regno] = 1;
6681+    }
6682+
6683+    call_used_regs[RETURN_ADDR_REGNUM] = 1;
6684+    call_really_used_regs[RETURN_ADDR_REGNUM] = 1;
6685+
6686+    for (regno = CALLEE_SAVED_FP_REG_FIRST;
6687+         regno <= CALLEE_SAVED_FP_REG_LAST; regno++)
6688+    {
6689+      call_used_regs[regno] = 1;
6690+      call_really_used_regs[regno] = 1;
6691+    }
6692+  }
6693+  else
6694+  {
6695+    for (regno = CALLEE_SAVED_GP_REG_FIRST;
6696+         regno <= CALLEE_SAVED_GP_REG_LAST; regno++)
6697+    {
6698+      call_used_regs[regno] = 0;
6699+      call_really_used_regs[regno] = 0;
6700+    }
6701+
6702+    call_used_regs[GP_REG_FIRST + 28] = 1;
6703+
6704+    call_used_regs[RETURN_ADDR_REGNUM] = 0;
6705+    call_really_used_regs[RETURN_ADDR_REGNUM] = 0;
6706+
6707+    for (regno = CALLEE_SAVED_FP_REG_FIRST;
6708+         regno <= CALLEE_SAVED_FP_REG_LAST; regno++)
6709+    {
6710+      call_used_regs[regno] = 0;
6711+      call_really_used_regs[regno] = 0;
6712+    }
6713+  }
6714+}
6715+
6716+/* Initialize vector TARGET to VALS.  */
6717+
6718+void
6719+mips_expand_vector_init (rtx target, rtx vals)
6720+{
6721+  enum machine_mode mode;
6722+  enum machine_mode inner;
6723+  unsigned int i, n_elts;
6724+  rtx mem;
6725+
6726+  mode = GET_MODE (target);
6727+  inner = GET_MODE_INNER (mode);
6728+  n_elts = GET_MODE_NUNITS (mode);
6729+
6730+  gcc_assert (VECTOR_MODE_P (mode));
6731+
6732+  mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
6733+  for (i = 0; i < n_elts; i++)
6734+    emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
6735+                    XVECEXP (vals, 0, i));
6736+
6737+  emit_move_insn (target, mem);
6738+}
6739+
6740+/* Implement EPILOGUE_USES.  */
6741+
6742+bool
6743+mips_epilogue_uses (unsigned int regno)
6744+{
6745+  /* Say that the epilogue uses the return address register.  Note that
6746+     in the case of sibcalls, the values "used by the epilogue" are
6747+     considered live at the start of the called function.  */
6748+  if (regno == RETURN_ADDR_REGNUM)
6749+    return true;
6750+
6751+  /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
6752+     See the comment above load_call<mode> for details.  */
6753+  if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
6754+    return true;
6755+
6756+  return false;
6757+}
6758+
6759+/* Implement TARGET_TRAMPOLINE_INIT.  */
6760+
6761+static void
6762+mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
6763+{
6764+  rtx addr, end_addr, mem;
6765+  rtx trampoline[8];
6766+  unsigned int i, j;
6767+  HOST_WIDE_INT static_chain_offset, target_function_offset;
6768+
6769+  /* Work out the offsets of the pointers from the start of the
6770+     trampoline code.  */
6771+  static_chain_offset = TRAMPOLINE_CODE_SIZE;
6772+  target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
6773+
6774+  /* Get pointers to the beginning and end of the code block.  */
6775+  addr = force_reg (Pmode, XEXP (m_tramp, 0));
6776+  end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (TRAMPOLINE_CODE_SIZE));
6777+
6778+#define OP(X) gen_int_mode (X, SImode)
6779+#define MATCH_LREG ((Pmode) == DImode ? MATCH_LD : MATCH_LW)
6780+
6781+  /* auipc   v0, 0x0
6782+     l[wd]   v1, target_function_offset(v0)
6783+     l[wd]   $static_chain, static_chain_offset(v0)
6784+     jr      v1
6785+  */
6786+  i = 0;
6787+
6788+  trampoline[i++] = OP (RISCV_LTYPE (AUIPC, STATIC_CHAIN_REGNUM, 0));
6789+  trampoline[i++] = OP (RISCV_ITYPE (LREG, MIPS_PROLOGUE_TEMP_REGNUM,
6790+                         STATIC_CHAIN_REGNUM, target_function_offset));
6791+  trampoline[i++] = OP (RISCV_ITYPE (LREG, STATIC_CHAIN_REGNUM,
6792+                         STATIC_CHAIN_REGNUM, static_chain_offset));
6793+  trampoline[i++] = OP (RISCV_ITYPE (JALR_J, 0, MIPS_PROLOGUE_TEMP_REGNUM, 0));
6794+
6795+  gcc_assert (i * 4 == TRAMPOLINE_CODE_SIZE);
6796+
6797+#undef MATCH_LREG
6798+#undef OP
6799+
6800+  /* Copy the trampoline code.  Leave any padding uninitialized.  */
6801+  for (j = 0; j < i; j++)
6802+    {
6803+      mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
6804+      mips_emit_move (mem, trampoline[j]);
6805+    }
6806+
6807+  /* Set up the static chain pointer field.  */
6808+  mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
6809+  mips_emit_move (mem, chain_value);
6810+
6811+  /* Set up the target function field.  */
6812+  mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
6813+  mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
6814+
6815+  /* Flush the code part of the trampoline.  */
6816+  emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
6817+  emit_insn (gen_clear_cache (addr, end_addr));
6818+}
6819+
6820+/* Implement TARGET_SHIFT_TRUNCATION_MASK. */
6821+
6822+static unsigned HOST_WIDE_INT
6823+mips_shift_truncation_mask (enum machine_mode mode)
6824+{
6825+  return GET_MODE_BITSIZE (mode) - 1;
6826+}
6827+
6828+const char*
6829+mips_riscv_output_vector_move(enum machine_mode mode, rtx dest, rtx src)
6830+{
6831+  bool dest_mem, dest_vgp_reg, dest_vfp_reg;
6832+  bool src_mem, src_vgp_reg, src_vfp_reg;
6833+
6834+  dest_mem = (GET_CODE(dest) == MEM);
6835+  dest_vgp_reg = (GET_CODE(dest) == REG) && VEC_GP_REG_P(REGNO(dest));
6836+  dest_vfp_reg = (GET_CODE(dest) == REG) && VEC_FP_REG_P(REGNO(dest));
6837+
6838+  src_mem = (GET_CODE(src) == MEM);
6839+  src_vgp_reg = (GET_CODE(src) == REG) && VEC_GP_REG_P(REGNO(src));
6840+  src_vfp_reg = (GET_CODE(src) == REG) && VEC_FP_REG_P(REGNO(src));
6841+
6842+  if (dest_vgp_reg && src_vgp_reg)
6843+    return "vmvv\t%0,%1";
6844+
6845+  if (dest_vfp_reg && src_vfp_reg)
6846+    return "vfmvv\t%0,%1";
6847+
6848+  if (dest_vgp_reg && src_mem)
6849+  {
6850+    switch (mode)
6851+    {
6852+      case MIPS_RISCV_VECTOR_MODE_NAME(DI): return "vld\t%0,%y1";
6853+      case MIPS_RISCV_VECTOR_MODE_NAME(SI): return "vlw\t%0,%y1";
6854+      case MIPS_RISCV_VECTOR_MODE_NAME(HI): return "vlh\t%0,%y1";
6855+      case MIPS_RISCV_VECTOR_MODE_NAME(QI): return "vlb\t%0,%y1";
6856+      default: gcc_unreachable();
6857+    }
6858+  }
6859+
6860+  if (dest_vfp_reg && src_mem)
6861+  {
6862+    switch (mode)
6863+    {
6864+      case MIPS_RISCV_VECTOR_MODE_NAME(DF): return "vfld\t%0,%y1";
6865+      case MIPS_RISCV_VECTOR_MODE_NAME(SF): return "vflw\t%0,%y1";
6866+      default: gcc_unreachable();
6867+    }
6868+  }
6869+
6870+  if (dest_mem && src_vgp_reg)
6871+  {
6872+    switch (mode)
6873+    {
6874+      case MIPS_RISCV_VECTOR_MODE_NAME(DI): return "vsd\t%1,%y0";
6875+      case MIPS_RISCV_VECTOR_MODE_NAME(SI): return "vsw\t%1,%y0";
6876+      case MIPS_RISCV_VECTOR_MODE_NAME(HI): return "vsh\t%1,%y0";
6877+      case MIPS_RISCV_VECTOR_MODE_NAME(QI): return "vsb\t%1,%y0";
6878+      default: gcc_unreachable();
6879+    }
6880+  }
6881+
6882+  if (dest_mem && src_vfp_reg)
6883+  {
6884+    switch (mode)
6885+    {
6886+      case MIPS_RISCV_VECTOR_MODE_NAME(DF): return "vfsd\t%1,%y0";
6887+      case MIPS_RISCV_VECTOR_MODE_NAME(SF): return "vfsw\t%1,%y0";
6888+      default: gcc_unreachable();
6889+    }
6890+  }
6891+
6892+  gcc_unreachable();
6893+}
6894+
6895+/* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
6896+
6897+   The complication here is that, with the combination TARGET_ABICALLS
6898+   && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
6899+   absolute addresses, and should therefore not be included in the
6900+   read-only part of a DSO.  Handle such cases by selecting a normal
6901+   data section instead of a read-only one.  The logic apes that in
6902+   default_function_rodata_section.  */
6903+
6904+static section *
6905+mips_function_rodata_section (tree decl)
6906+{
6907+  if (!TARGET_ABICALLS)
6908+    return default_function_rodata_section (decl);
6909+
6910+  if (decl && DECL_SECTION_NAME (decl))
6911+    {
6912+      const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6913+      if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
6914+       {
6915+         char *rname = ASTRDUP (name);
6916+         rname[14] = 'd';
6917+         return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
6918+       }
6919+      else if (flag_function_sections
6920+              && flag_data_sections
6921+              && strncmp (name, ".text.", 6) == 0)
6922+       {
6923+         char *rname = ASTRDUP (name);
6924+         memcpy (rname + 1, "data", 4);
6925+         return get_section (rname, SECTION_WRITE, decl);
6926+       }
6927+    }
6928+  return data_section;
6929+}
6930+
6931+
6932+
6933+/* Initialize the GCC target structure.  */
6934+#undef TARGET_ASM_ALIGNED_HI_OP
6935+#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
6936+#undef TARGET_ASM_ALIGNED_SI_OP
6937+#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
6938+#undef TARGET_ASM_ALIGNED_DI_OP
6939+#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
6940+
6941+#undef TARGET_OPTION_OVERRIDE
6942+#define TARGET_OPTION_OVERRIDE mips_option_override
6943+#undef TARGET_OPTION_OPTIMIZATION_TABLE
6944+#define TARGET_OPTION_OPTIMIZATION_TABLE mips_option_optimization_table
6945+
6946+#undef TARGET_LEGITIMIZE_ADDRESS
6947+#define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
6948+
6949+#undef TARGET_ASM_FUNCTION_PROLOGUE
6950+#define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
6951+#undef TARGET_ASM_FUNCTION_RODATA_SECTION
6952+#define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
6953+
6954+#undef TARGET_SCHED_ADJUST_COST
6955+#define TARGET_SCHED_ADJUST_COST mips_adjust_cost
6956+#undef TARGET_SCHED_ISSUE_RATE
6957+#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
6958+
6959+#undef TARGET_DEFAULT_TARGET_FLAGS
6960+#define TARGET_DEFAULT_TARGET_FLAGS            \
6961+  (TARGET_DEFAULT                              \
6962+   | TARGET_CPU_DEFAULT                                \
6963+   | (TARGET_64BIT_DEFAULT ? 0 : MASK_32BIT)   \
6964+   | TARGET_ENDIAN_DEFAULT)
6965+#undef TARGET_HANDLE_OPTION
6966+#define TARGET_HANDLE_OPTION mips_handle_option
6967+
6968+#undef TARGET_FUNCTION_OK_FOR_SIBCALL
6969+#define TARGET_FUNCTION_OK_FOR_SIBCALL hook_bool_tree_tree_true
6970+
6971+#undef TARGET_SET_CURRENT_FUNCTION
6972+#define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
6973+
6974+#undef TARGET_VALID_POINTER_MODE
6975+#define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
6976+#undef TARGET_REGISTER_MOVE_COST
6977+#define TARGET_REGISTER_MOVE_COST mips_register_move_cost
6978+#undef TARGET_MEMORY_MOVE_COST
6979+#define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
6980+#undef TARGET_RTX_COSTS
6981+#define TARGET_RTX_COSTS mips_rtx_costs
6982+#undef TARGET_ADDRESS_COST
6983+#define TARGET_ADDRESS_COST mips_address_cost
6984+
6985+#undef TARGET_MACHINE_DEPENDENT_REORG
6986+#define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
6987+
6988+#undef  TARGET_PREFERRED_RELOAD_CLASS
6989+#define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
6990+
6991+#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6992+#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6993+
6994+#undef TARGET_INIT_LIBFUNCS
6995+#define TARGET_INIT_LIBFUNCS mips_init_libfuncs
6996+
6997+#undef TARGET_EXPAND_BUILTIN_VA_START
6998+#define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
6999+
7000+#undef  TARGET_PROMOTE_FUNCTION_MODE
7001+#define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
7002+#undef TARGET_PROMOTE_PROTOTYPES
7003+#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
7004+
7005+#undef TARGET_RETURN_IN_MEMORY
7006+#define TARGET_RETURN_IN_MEMORY mips_return_in_memory
7007+#undef TARGET_RETURN_IN_MSB
7008+#define TARGET_RETURN_IN_MSB mips_return_in_msb
7009+
7010+#undef TARGET_ASM_OUTPUT_MI_THUNK
7011+#define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
7012+#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
7013+#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
7014+
7015+#undef TARGET_PRINT_OPERAND
7016+#define TARGET_PRINT_OPERAND mips_print_operand
7017+#undef TARGET_PRINT_OPERAND_ADDRESS
7018+#define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
7019+
7020+#undef TARGET_SETUP_INCOMING_VARARGS
7021+#define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
7022+#undef TARGET_STRICT_ARGUMENT_NAMING
7023+#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
7024+#undef TARGET_MUST_PASS_IN_STACK
7025+#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
7026+#undef TARGET_PASS_BY_REFERENCE
7027+#define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
7028+#undef TARGET_ARG_PARTIAL_BYTES
7029+#define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
7030+#undef TARGET_FUNCTION_ARG
7031+#define TARGET_FUNCTION_ARG mips_function_arg
7032+#undef TARGET_FUNCTION_ARG_ADVANCE
7033+#define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
7034+#undef TARGET_FUNCTION_ARG_BOUNDARY
7035+#define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
7036+
7037+#undef TARGET_MODE_REP_EXTENDED
7038+#define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
7039+
7040+#undef TARGET_VECTOR_MODE_SUPPORTED_P
7041+#define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
7042+
7043+#undef TARGET_SCALAR_MODE_SUPPORTED_P
7044+#define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
7045+
7046+#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
7047+#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
7048+
7049+#undef TARGET_INIT_BUILTINS
7050+#define TARGET_INIT_BUILTINS mips_init_builtins
7051+#undef TARGET_BUILTIN_DECL
7052+#define TARGET_BUILTIN_DECL mips_builtin_decl
7053+#undef TARGET_EXPAND_BUILTIN
7054+#define TARGET_EXPAND_BUILTIN mips_expand_builtin
7055+
7056+#undef TARGET_HAVE_TLS
7057+#define TARGET_HAVE_TLS HAVE_AS_TLS
7058+
7059+#undef TARGET_CANNOT_FORCE_CONST_MEM
7060+#define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
7061+
7062+#undef TARGET_ENCODE_SECTION_INFO
7063+#define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
7064+
7065+#undef TARGET_ATTRIBUTE_TABLE
7066+#define TARGET_ATTRIBUTE_TABLE mips_attribute_table
7067+/* All our function attributes are related to how out-of-line copies should
7068+   be compiled or called.  They don't in themselves prevent inlining.  */
7069+#undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
7070+#define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
7071+
7072+#undef TARGET_EXTRA_LIVE_ON_ENTRY
7073+#define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
7074+
7075+#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
7076+#define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
7077+
7078+#undef  TARGET_COMP_TYPE_ATTRIBUTES
7079+#define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
7080+
7081+#ifdef HAVE_AS_DTPRELWORD
7082+#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
7083+#define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
7084+#endif
7085+
7086+#undef TARGET_IRA_COVER_CLASSES
7087+#define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
7088+
7089+#undef TARGET_LEGITIMATE_ADDRESS_P
7090+#define TARGET_LEGITIMATE_ADDRESS_P    mips_legitimate_address_p
7091+
7092+#undef TARGET_CAN_ELIMINATE
7093+#define TARGET_CAN_ELIMINATE mips_can_eliminate
7094+
7095+#undef TARGET_CONDITIONAL_REGISTER_USAGE
7096+#define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
7097+
7098+#undef TARGET_TRAMPOLINE_INIT
7099+#define TARGET_TRAMPOLINE_INIT mips_trampoline_init
7100+
7101+#undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
7102+#define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
7103+
7104+#undef TARGET_SHIFT_TRUNCATION_MASK
7105+#define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
7106+
7107+struct gcc_target targetm = TARGET_INITIALIZER;
7108+
7109+#include "gt-riscv.h"
7110diff -ruN gcc-4.9.2/gcc/config/riscv/riscv-ftypes.def gcc-4.9.2-riscv/gcc/config/riscv/riscv-ftypes.def
7111--- gcc-4.9.2/gcc/config/riscv/riscv-ftypes.def 1969-12-31 16:00:00.000000000 -0800
7112+++ gcc-4.9.2-riscv/gcc/config/riscv/riscv-ftypes.def   2014-12-02 18:04:50.107949563 -0800
7113@@ -0,0 +1,157 @@
7114+/* Definitions of prototypes for MIPS built-in functions.  -*- C -*-
7115+   Copyright (C) 2007, 2008
7116+   Free Software Foundation, Inc.
7117+
7118+This file is part of GCC.
7119+
7120+GCC is free software; you can redistribute it and/or modify
7121+it under the terms of the GNU General Public License as published by
7122+the Free Software Foundation; either version 3, or (at your option)
7123+any later version.
7124+
7125+GCC is distributed in the hope that it will be useful,
7126+but WITHOUT ANY WARRANTY; without even the implied warranty of
7127+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
7128+GNU General Public License for more details.
7129+
7130+You should have received a copy of the GNU General Public License
7131+along with GCC; see the file COPYING3.  If not see
7132+<http://www.gnu.org/licenses/>.  */
7133+
7134+/* Invoke DEF_MIPS_FTYPE (NARGS, LIST) for each prototype used by
7135+   MIPS built-in functions, where:
7136+
7137+      NARGS is the number of arguments.
7138+      LIST contains the return-type code followed by the codes for each
7139+        argument type.
7140+
7141+   Argument- and return-type codes are either modes or one of the following:
7142+
7143+      VOID for void_type_node
7144+      INT for integer_type_node
7145+      POINTER for ptr_type_node
7146+
7147+   (we don't use PTR because that's a ANSI-compatibillity macro).
7148+
7149+   Please keep this list lexicographically sorted by the LIST argument.  */
7150+DEF_MIPS_FTYPE (1, (DF, DF))
7151+DEF_MIPS_FTYPE (2, (DF, DF, DF))
7152+
7153+DEF_MIPS_FTYPE (2, (DI, DI, DI))
7154+DEF_MIPS_FTYPE (2, (DI, DI, SI))
7155+DEF_MIPS_FTYPE (3, (DI, DI, SI, SI))
7156+DEF_MIPS_FTYPE (3, (DI, DI, USI, USI))
7157+DEF_MIPS_FTYPE (3, (DI, DI, V2HI, V2HI))
7158+DEF_MIPS_FTYPE (3, (DI, DI, V4QI, V4QI))
7159+DEF_MIPS_FTYPE (2, (DI, SI, SI))
7160+DEF_MIPS_FTYPE (2, (DI, USI, USI))
7161+
7162+DEF_MIPS_FTYPE (2, (INT, DF, DF))
7163+DEF_MIPS_FTYPE (2, (INT, SF, SF))
7164+DEF_MIPS_FTYPE (2, (INT, V2SF, V2SF))
7165+DEF_MIPS_FTYPE (4, (INT, V2SF, V2SF, V2SF, V2SF))
7166+
7167+DEF_MIPS_FTYPE (2, (SI, DI, SI))
7168+DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
7169+DEF_MIPS_FTYPE (1, (SI, SI))
7170+DEF_MIPS_FTYPE (2, (SI, SI, SI))
7171+DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
7172+DEF_MIPS_FTYPE (1, (SI, V2HI))
7173+DEF_MIPS_FTYPE (2, (SI, V2HI, V2HI))
7174+DEF_MIPS_FTYPE (1, (SI, V4QI))
7175+DEF_MIPS_FTYPE (2, (SI, V4QI, V4QI))
7176+DEF_MIPS_FTYPE (1, (SI, VOID))
7177+
7178+DEF_MIPS_FTYPE (1, (SF, SF))
7179+DEF_MIPS_FTYPE (2, (SF, SF, SF))
7180+DEF_MIPS_FTYPE (1, (SF, V2SF))
7181+
7182+DEF_MIPS_FTYPE (2, (UDI, UDI, UDI))
7183+DEF_MIPS_FTYPE (2, (UDI, UV2SI, UV2SI))
7184+
7185+DEF_MIPS_FTYPE (2, (UV2SI, UV2SI, UQI))
7186+DEF_MIPS_FTYPE (2, (UV2SI, UV2SI, UV2SI))
7187+
7188+DEF_MIPS_FTYPE (2, (UV4HI, UV4HI, UQI))
7189+DEF_MIPS_FTYPE (2, (UV4HI, UV4HI, USI))
7190+DEF_MIPS_FTYPE (3, (UV4HI, UV4HI, UV4HI, UQI))
7191+DEF_MIPS_FTYPE (3, (UV4HI, UV4HI, UV4HI, USI))
7192+DEF_MIPS_FTYPE (2, (UV4HI, UV4HI, UV4HI))
7193+DEF_MIPS_FTYPE (1, (UV4HI, UV8QI))
7194+DEF_MIPS_FTYPE (2, (UV4HI, UV8QI, UV8QI))
7195+
7196+DEF_MIPS_FTYPE (2, (UV8QI, UV4HI, UV4HI))
7197+DEF_MIPS_FTYPE (1, (UV8QI, UV8QI))
7198+DEF_MIPS_FTYPE (2, (UV8QI, UV8QI, UV8QI))
7199+
7200+DEF_MIPS_FTYPE (1, (V2HI, SI))
7201+DEF_MIPS_FTYPE (2, (V2HI, SI, SI))
7202+DEF_MIPS_FTYPE (3, (V2HI, SI, SI, SI))
7203+DEF_MIPS_FTYPE (1, (V2HI, V2HI))
7204+DEF_MIPS_FTYPE (2, (V2HI, V2HI, SI))
7205+DEF_MIPS_FTYPE (2, (V2HI, V2HI, V2HI))
7206+DEF_MIPS_FTYPE (1, (V2HI, V4QI))
7207+DEF_MIPS_FTYPE (2, (V2HI, V4QI, V2HI))
7208+
7209+DEF_MIPS_FTYPE (2, (V2SF, SF, SF))
7210+DEF_MIPS_FTYPE (1, (V2SF, V2SF))
7211+DEF_MIPS_FTYPE (2, (V2SF, V2SF, V2SF))
7212+DEF_MIPS_FTYPE (3, (V2SF, V2SF, V2SF, INT))
7213+DEF_MIPS_FTYPE (4, (V2SF, V2SF, V2SF, V2SF, V2SF))
7214+
7215+DEF_MIPS_FTYPE (2, (V2SI, V2SI, UQI))
7216+DEF_MIPS_FTYPE (2, (V2SI, V2SI, V2SI))
7217+DEF_MIPS_FTYPE (2, (V2SI, V4HI, V4HI))
7218+
7219+DEF_MIPS_FTYPE (2, (V4HI, V2SI, V2SI))
7220+DEF_MIPS_FTYPE (2, (V4HI, V4HI, UQI))
7221+DEF_MIPS_FTYPE (2, (V4HI, V4HI, USI))
7222+DEF_MIPS_FTYPE (2, (V4HI, V4HI, V4HI))
7223+DEF_MIPS_FTYPE (3, (V4HI, V4HI, V4HI, UQI))
7224+DEF_MIPS_FTYPE (3, (V4HI, V4HI, V4HI, USI))
7225+
7226+DEF_MIPS_FTYPE (1, (V4QI, SI))
7227+DEF_MIPS_FTYPE (2, (V4QI, V2HI, V2HI))
7228+DEF_MIPS_FTYPE (1, (V4QI, V4QI))
7229+DEF_MIPS_FTYPE (2, (V4QI, V4QI, SI))
7230+DEF_MIPS_FTYPE (2, (V4QI, V4QI, V4QI))
7231+
7232+DEF_MIPS_FTYPE (2, (V8QI, V4HI, V4HI))
7233+DEF_MIPS_FTYPE (1, (V8QI, V8QI))
7234+DEF_MIPS_FTYPE (2, (V8QI, V8QI, V8QI))
7235+
7236+DEF_MIPS_FTYPE (2, (VOID, SI, CVPOINTER))
7237+DEF_MIPS_FTYPE (2, (VOID, SI, SI))
7238+DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI))
7239+DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
7240+
7241+/* RISC-V builtin function types */
7242+
7243+DEF_MIPS_FTYPE (1, (VDI, CPOINTER))
7244+DEF_MIPS_FTYPE (1, (VSI, CPOINTER))
7245+DEF_MIPS_FTYPE (1, (VHI, CPOINTER))
7246+DEF_MIPS_FTYPE (1, (VQI, CPOINTER))
7247+DEF_MIPS_FTYPE (1, (VDF, CPOINTER))
7248+DEF_MIPS_FTYPE (1, (VSF, CPOINTER))
7249+
7250+DEF_MIPS_FTYPE (2, (VDI, CPOINTER, DI))
7251+DEF_MIPS_FTYPE (2, (VSI, CPOINTER, DI))
7252+DEF_MIPS_FTYPE (2, (VHI, CPOINTER, DI))
7253+DEF_MIPS_FTYPE (2, (VQI, CPOINTER, DI))
7254+DEF_MIPS_FTYPE (2, (VDF, CPOINTER, DI))
7255+DEF_MIPS_FTYPE (2, (VSF, CPOINTER, DI))
7256+
7257+DEF_MIPS_FTYPE (2, (VOID, VDI, POINTER))
7258+DEF_MIPS_FTYPE (2, (VOID, VSI, POINTER))
7259+DEF_MIPS_FTYPE (2, (VOID, VHI, POINTER))
7260+DEF_MIPS_FTYPE (2, (VOID, VQI, POINTER))
7261+DEF_MIPS_FTYPE (2, (VOID, VDF, POINTER))
7262+DEF_MIPS_FTYPE (2, (VOID, VSF, POINTER))
7263+
7264+DEF_MIPS_FTYPE (3, (VOID, VDI, POINTER, DI))
7265+DEF_MIPS_FTYPE (3, (VOID, VSI, POINTER, DI))
7266+DEF_MIPS_FTYPE (3, (VOID, VHI, POINTER, DI))
7267+DEF_MIPS_FTYPE (3, (VOID, VQI, POINTER, DI))
7268+DEF_MIPS_FTYPE (3, (VOID, VDF, POINTER, DI))
7269+DEF_MIPS_FTYPE (3, (VOID, VSF, POINTER, DI))
7270+
7271diff -ruN gcc-4.9.2/gcc/config/riscv/riscv.h gcc-4.9.2-riscv/gcc/config/riscv/riscv.h
7272--- gcc-4.9.2/gcc/config/riscv/riscv.h  1969-12-31 16:00:00.000000000 -0800
7273+++ gcc-4.9.2-riscv/gcc/config/riscv/riscv.h    2014-12-02 18:04:50.111949590 -0800
7274@@ -0,0 +1,1666 @@
7275+/* Definitions of target machine for GNU compiler.  MIPS version.
7276+   Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
7277+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
7278+   Free Software Foundation, Inc.
7279+   Contributed by A. Lichnewsky (lich@inria.inria.fr).
7280+   Changed by Michael Meissner (meissner@osf.org).
7281+   64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7282+   Brendan Eich (brendan@microunity.com).
7283+
7284+This file is part of GCC.