akaros/kern/include/coreboot_tables.h
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   1/*
   2 * This file is part of the libpayload project.
   3 *
   4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5 *
   6 * Redistribution and use in source and binary forms, with or without
   7 * modification, are permitted provided that the following conditions
   8 * are met:
   9 * 1. Redistributions of source code must retain the above copyright
  10 *    notice, this list of conditions and the following disclaimer.
  11 * 2. Redistributions in binary form must reproduce the above copyright
  12 *    notice, this list of conditions and the following disclaimer in the
  13 *    documentation and/or other materials provided with the distribution.
  14 * 3. The name of the author may not be used to endorse or promote products
  15 *    derived from this software without specific prior written permission.
  16 *
  17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27 * SUCH DAMAGE.
  28 */
  29
  30#pragma once
  31
  32#include <arch/types.h>
  33
  34/* Maximum number of memory range definitions. */
  35#define SYSINFO_MAX_MEM_RANGES 32
  36/* Allow a maximum of 8 GPIOs */
  37#define SYSINFO_MAX_GPIOS 8
  38
  39struct cb_serial;
  40
  41struct sysinfo_t {
  42        unsigned int cpu_khz;
  43        struct cb_serial *serial;
  44        unsigned short ser_ioport;
  45        unsigned long ser_base; // for mmapped serial
  46
  47        int n_memranges;
  48
  49        struct memrange {
  50                unsigned long long base;
  51                unsigned long long size;
  52                unsigned int type;
  53        } memrange[SYSINFO_MAX_MEM_RANGES];
  54
  55        struct cb_cmos_option_table *option_table;
  56        uint32_t cmos_range_start;
  57        uint32_t cmos_range_end;
  58        uint32_t cmos_checksum_location;
  59#ifdef CONFIG_CHROMEOS
  60        uint32_t vbnv_start;
  61        uint32_t vbnv_size;
  62#endif
  63
  64        char *version;
  65        char *extra_version;
  66        char *build;
  67        char *compile_time;
  68        char *compile_by;
  69        char *compile_host;
  70        char *compile_domain;
  71        char *compiler;
  72        char *linker;
  73        char *assembler;
  74
  75        char *cb_version;
  76
  77        struct cb_framebuffer *framebuffer;
  78
  79#ifdef CONFIG_CHROMEOS
  80        int num_gpios;
  81        struct cb_gpio gpios[SYSINFO_MAX_GPIOS];
  82#endif
  83
  84        unsigned long *mbtable; /** Pointer to the multiboot table */
  85
  86        struct cb_header *header;
  87        struct cb_mainboard *mainboard;
  88
  89        /* these are chromeos specific and may or may not be valid. */
  90        void    *vboot_handoff;
  91        uint32_t        vboot_handoff_size;
  92        void    *vdat_addr;
  93        uint32_t        vdat_size;
  94
  95#ifdef CONFIG_X86
  96        int x86_rom_var_mtrr_index;
  97#endif
  98
  99        void    *tstamp_table;
 100        void    *cbmem_cons;
 101        void    *mrc_cache;
 102        void    *acpi_gnvs;
 103};
 104
 105extern struct sysinfo_t lib_sysinfo;
 106
 107struct cbuint64 {
 108        uint32_t lo;
 109        uint32_t hi;
 110};
 111
 112struct cb_header {
 113        uint8_t signature[4];
 114        uint32_t header_bytes;
 115        uint32_t header_checksum;
 116        uint32_t table_bytes;
 117        uint32_t table_checksum;
 118        uint32_t table_entries;
 119};
 120
 121struct cb_record {
 122        uint32_t tag;
 123        uint32_t size;
 124};
 125
 126#define CB_TAG_UNUSED     0x0000
 127#define CB_TAG_MEMORY     0x0001
 128
 129struct cb_memory_range {
 130        struct cbuint64 start;
 131        struct cbuint64 size;
 132        uint32_t type;
 133};
 134
 135#define CB_MEM_RAM          1
 136#define CB_MEM_RESERVED     2
 137#define CB_MEM_ACPI         3
 138#define CB_MEM_NVS          4
 139#define CB_MEM_UNUSABLE     5
 140#define CB_MEM_VENDOR_RSVD  6
 141#define CB_MEM_TABLE       16
 142
 143struct cb_memory {
 144        uint32_t tag;
 145        uint32_t size;
 146        struct cb_memory_range map[0];
 147};
 148
 149#define CB_TAG_HWRPB      0x0002
 150
 151struct cb_hwrpb {
 152        uint32_t tag;
 153        uint32_t size;
 154        uint64_t hwrpb;
 155};
 156
 157#define CB_TAG_MAINBOARD  0x0003
 158
 159struct cb_mainboard {
 160        uint32_t tag;
 161        uint32_t size;
 162        uint8_t vendor_idx;
 163        uint8_t part_number_idx;
 164        uint8_t strings[0];
 165};
 166
 167#define CB_TAG_VERSION        0x0004
 168#define CB_TAG_EXTRA_VERSION  0x0005
 169#define CB_TAG_BUILD          0x0006
 170#define CB_TAG_COMPILE_TIME   0x0007
 171#define CB_TAG_COMPILE_BY     0x0008
 172#define CB_TAG_COMPILE_HOST   0x0009
 173#define CB_TAG_COMPILE_DOMAIN 0x000a
 174#define CB_TAG_COMPILER       0x000b
 175#define CB_TAG_LINKER         0x000c
 176#define CB_TAG_ASSEMBLER      0x000d
 177
 178struct cb_string {
 179        uint32_t tag;
 180        uint32_t size;
 181        uint8_t string[0];
 182};
 183
 184#define CB_TAG_SERIAL         0x000f
 185
 186struct cb_serial {
 187        uint32_t tag;
 188        uint32_t size;
 189#define CB_SERIAL_TYPE_IO_MAPPED     1
 190#define CB_SERIAL_TYPE_MEMORY_MAPPED 2
 191        uint32_t type;
 192        uint32_t baseaddr;
 193        uint32_t baud;
 194};
 195
 196#define CB_TAG_CONSOLE       0x00010
 197
 198struct cb_console {
 199        uint32_t tag;
 200        uint32_t size;
 201        uint16_t type;
 202};
 203
 204#define CB_TAG_CONSOLE_SERIAL8250 0
 205#define CB_TAG_CONSOLE_VGA        1 // OBSOLETE
 206#define CB_TAG_CONSOLE_BTEXT      2 // OBSOLETE
 207#define CB_TAG_CONSOLE_LOGBUF     3 // OBSOLETE
 208#define CB_TAG_CONSOLE_SROM       4 // OBSOLETE
 209#define CB_TAG_CONSOLE_EHCI       5
 210
 211#define CB_TAG_FORWARD       0x00011
 212
 213struct cb_forward {
 214        uint32_t tag;
 215        uint32_t size;
 216        uint64_t forward;
 217};
 218
 219#define CB_TAG_FRAMEBUFFER      0x0012
 220struct cb_framebuffer {
 221        uint32_t tag;
 222        uint32_t size;
 223
 224        uint64_t physical_address;
 225        uint32_t x_resolution;
 226        uint32_t y_resolution;
 227        uint32_t bytes_per_line;
 228        uint8_t bits_per_pixel;
 229        uint8_t red_mask_pos;
 230        uint8_t red_mask_size;
 231        uint8_t green_mask_pos;
 232        uint8_t green_mask_size;
 233        uint8_t blue_mask_pos;
 234        uint8_t blue_mask_size;
 235        uint8_t reserved_mask_pos;
 236        uint8_t reserved_mask_size;
 237};
 238
 239#define CB_TAG_GPIO 0x0013
 240#define CB_GPIO_ACTIVE_LOW 0
 241#define CB_GPIO_ACTIVE_HIGH 1
 242#define CB_GPIO_MAX_NAME_LENGTH 16
 243struct cb_gpio {
 244        uint32_t port;
 245        uint32_t polarity;
 246        uint32_t value;
 247        uint8_t name[CB_GPIO_MAX_NAME_LENGTH];
 248};
 249
 250struct cb_gpios {
 251        uint32_t tag;
 252        uint32_t size;
 253
 254        uint32_t count;
 255        struct cb_gpio gpios[0];
 256};
 257
 258#define CB_TAG_VDAT             0x0015
 259#define CB_TAG_VBNV             0x0019
 260#define CB_TAG_VBOOT_HANDOFF    0x0020
 261#define CB_TAG_DMA              0x0022
 262struct cb_range {
 263        uint32_t tag;
 264        uint32_t size;
 265        uint64_t range_start;
 266        uint32_t range_size;
 267};
 268
 269#define CB_TAG_TIMESTAMPS       0x0016
 270#define CB_TAG_CBMEM_CONSOLE    0x0017
 271#define CB_TAG_MRC_CACHE        0x0018
 272#define CB_TAG_ACPI_GNVS        0x0024
 273struct cb_cbmem_tab {
 274        uint32_t tag;
 275        uint32_t size;
 276        uint64_t cbmem_tab;
 277};
 278
 279#define CB_TAG_X86_ROM_MTRR     0x0021
 280struct cb_x86_rom_mtrr {
 281        uint32_t tag;
 282        uint32_t size;
 283        /* The variable range MTRR index covering the ROM. If one wants to
 284         * enable caching the ROM, the variable MTRR needs to be set to
 285         * write-protect. To disable the caching after enabling set the
 286         * type to uncacheable. */
 287        uint32_t index;
 288};
 289
 290
 291#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
 292struct cb_cmos_option_table {
 293        uint32_t tag;
 294        uint32_t size;
 295        uint32_t header_length;
 296};
 297
 298#define CB_TAG_OPTION         0x00c9
 299#define CB_CMOS_MAX_NAME_LENGTH    32
 300struct cb_cmos_entries {
 301        uint32_t tag;
 302        uint32_t size;
 303        uint32_t bit;
 304        uint32_t length;
 305        uint32_t config;
 306        uint32_t config_id;
 307        uint8_t name[CB_CMOS_MAX_NAME_LENGTH];
 308};
 309
 310
 311#define CB_TAG_OPTION_ENUM    0x00ca
 312#define CB_CMOS_MAX_TEXT_LENGTH 32
 313struct cb_cmos_enums {
 314        uint32_t tag;
 315        uint32_t size;
 316        uint32_t config_id;
 317        uint32_t value;
 318        uint8_t text[CB_CMOS_MAX_TEXT_LENGTH];
 319};
 320
 321#define CB_TAG_OPTION_DEFAULTS 0x00cb
 322#define CB_CMOS_IMAGE_BUFFER_SIZE 128
 323struct cb_cmos_defaults {
 324        uint32_t tag;
 325        uint32_t size;
 326        uint32_t name_length;
 327        uint8_t name[CB_CMOS_MAX_NAME_LENGTH];
 328        uint8_t default_set[CB_CMOS_IMAGE_BUFFER_SIZE];
 329};
 330
 331#define CB_TAG_OPTION_CHECKSUM 0x00cc
 332#define CB_CHECKSUM_NONE        0
 333#define CB_CHECKSUM_PCBIOS      1
 334struct  cb_cmos_checksum {
 335        uint32_t tag;
 336        uint32_t size;
 337        uint32_t range_start;
 338        uint32_t range_end;
 339        uint32_t location;
 340        uint32_t type;
 341};
 342
 343/* Helpful inlines */
 344
 345static inline uint64_t cb_unpack64(struct cbuint64 val)
 346{
 347        return (((uint64_t) val.hi) << 32) | val.lo;
 348}
 349
 350static inline uint16_t cb_checksum(const void *ptr, unsigned len)
 351{
 352        return ipchecksum((uint8_t *)ptr, len);
 353}
 354
 355static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm)
 356{
 357        return (char *)(cbm->strings + cbm->vendor_idx);
 358}
 359
 360static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm)
 361{
 362        return (char *)(cbm->strings + cbm->part_number_idx);
 363}
 364
 365/* Helpful macros */
 366
 367#define MEM_RANGE_COUNT(_rec) \
 368        (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
 369
 370#define MEM_RANGE_PTR(_rec, _idx) \
 371        (void *)(((uint8_t *) (_rec)) + sizeof(*(_rec)) \
 372                + (sizeof((_rec)->map[0]) * (_idx)))
 373
 374int get_coreboot_info(struct sysinfo_t *info);
 375