akaros/kern/drivers/net/ethermii.h
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   1/* This file is part of the UCB release of Plan 9. It is subject to the license
   2 * terms in the LICENSE file found in the top-level directory of this
   3 * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
   4 * part of the UCB release of Plan 9, including this file, may be copied,
   5 * modified, propagated, or distributed except according to the terms contained
   6 * in the LICENSE file. */
   7
   8enum {                                  /* registers */
   9        Bmcr            = 0x00,         /* Basic Mode Control */
  10        Bmsr            = 0x01,         /* Basic Mode Status */
  11        Phyidr1         = 0x02,         /* PHY Identifier #1 */
  12        Phyidr2         = 0x03,         /* PHY Identifier #2 */
  13        Anar            = 0x04,         /* Auto-Negotiation Advertisement */
  14        Anlpar          = 0x05,         /* AN Link Partner Ability */
  15        Aner            = 0x06,         /* AN Expansion */
  16        Annptr          = 0x07,         /* AN Next Page TX */
  17        Annprr          = 0x08,         /* AN Next Page RX */
  18        Mscr            = 0x09,         /* MASTER-SLAVE Control */
  19        Mssr            = 0x0a,         /* MASTER-SLAVE Status */
  20        Esr             = 0x0f,         /* Extended Status */
  21
  22        NMiiPhyr        = 32,
  23        NMiiPhy         = 32,
  24};
  25
  26enum {                                  /* Bmcr */
  27        BmcrSs1         = 0x0040,       /* Speed Select[1] */
  28        BmcrCte         = 0x0080,       /* Collision Test Enable */
  29        BmcrDm          = 0x0100,       /* Duplex Mode */
  30        BmcrRan         = 0x0200,       /* Restart Auto-Negotiation */
  31        BmcrI           = 0x0400,       /* Isolate */
  32        BmcrPd          = 0x0800,       /* Power Down */
  33        BmcrAne         = 0x1000,       /* Auto-Negotiation Enable */
  34        BmcrSs0         = 0x2000,       /* Speed Select[0] */
  35        BmcrLe          = 0x4000,       /* Loopback Enable */
  36        BmcrR           = 0x8000,       /* Reset */
  37};
  38
  39enum {                                  /* Bmsr */
  40        BmsrEc          = 0x0001,       /* Extended Capability */
  41        BmsrJd          = 0x0002,       /* Jabber Detect */
  42        BmsrLs          = 0x0004,       /* Link Status */
  43        BmsrAna         = 0x0008,       /* Auto-Negotiation Ability */
  44        BmsrRf          = 0x0010,       /* Remote Fault */
  45        BmsrAnc         = 0x0020,       /* Auto-Negotiation Complete */
  46        BmsrPs          = 0x0040,       /* Preamble Suppression Capable */
  47        BmsrEs          = 0x0100,       /* Extended Status */
  48        Bmsr100T2HD     = 0x0200,       /* 100BASE-T2 HD Capable */
  49        Bmsr100T2FD     = 0x0400,       /* 100BASE-T2 FD Capable */
  50        Bmsr10THD       = 0x0800,       /* 10BASE-T HD Capable */
  51        Bmsr10TFD       = 0x1000,       /* 10BASE-T FD Capable */
  52        Bmsr100TXHD     = 0x2000,       /* 100BASE-TX HD Capable */
  53        Bmsr100TXFD     = 0x4000,       /* 100BASE-TX FD Capable */
  54        Bmsr100T4       = 0x8000,       /* 100BASE-T4 Capable */
  55};
  56
  57enum {                                  /* Anar/Anlpar */
  58        Ana10G          = 0x0001,
  59
  60        Ana10HD         = 0x0020,       /* Advertise 10BASE-T */
  61        Ana10FD         = 0x0040,       /* Advertise 10BASE-T FD */
  62        AnaTXHD         = 0x0080,       /* Advertise 100BASE-TX */
  63        AnaTXFD         = 0x0100,       /* Advertise 100BASE-TX FD */
  64        AnaT4           = 0x0200,       /* Advertise 100BASE-T4 */
  65        AnaP            = 0x0400,       /* Pause */
  66        AnaAP           = 0x0800,       /* Asymmetrical Pause */
  67        AnaRf           = 0x2000,       /* Remote Fault */
  68        AnaAck          = 0x4000,       /* Acknowledge */
  69        AnaNp           = 0x8000,       /* Next Page Indication */
  70};
  71
  72enum {                                  /* Mscr */
  73        Mscr1000THD     = 0x0100,       /* Advertise 1000BASE-T HD */
  74        Mscr1000TFD     = 0x0200,       /* Advertise 1000BASE-T FD */
  75};
  76
  77enum {                                  /* Mssr */
  78        Mssr1000THD     = 0x0400,       /* Link Partner 1000BASE-T HD able */
  79        Mssr1000TFD     = 0x0800,       /* Link Partner 1000BASE-T FD able */
  80};
  81
  82enum {                                  /* Esr */
  83        Esr1000THD      = 0x1000,       /* 1000BASE-T HD Capable */
  84        Esr1000TFD      = 0x2000,       /* 1000BASE-T FD Capable */
  85        Esr1000XHD      = 0x4000,       /* 1000BASE-X HD Capable */
  86        Esr1000XFD      = 0x8000,       /* 1000BASE-X FD Capable */
  87};
  88
  89struct mii {
  90        spinlock_t lock;
  91        int     nphy;
  92        int     mask;
  93        struct miiphy*  phy[NMiiPhy];
  94        struct miiphy*  curphy;
  95
  96        void*   ctlr;
  97        int     (*rw)(struct mii*, int unused_int, int, int, int);
  98};
  99
 100struct miiphy {
 101        struct mii*     mii;
 102        int     phyno;
 103        int     phyid;
 104        int     oui;
 105
 106        int     anar;
 107        int     fc;
 108        int     mscr;
 109
 110        int     link;
 111        int     speed;
 112        int     fd;
 113        int     rfc;
 114        int     tfc;
 115};
 116
 117int miimir(struct mii *mii, int r);
 118int miimiw(struct mii *mii, int r, int data);
 119int miireset(struct mii *mii);
 120int miiane(struct mii *mii, int a, int p, int e);
 121int miistatus(struct mii *mii);
 122char *miidumpphy(struct mii *mii, char *p, char *e);
 123void miidetach(struct mii *mii);
 124struct mii *miiattach(void *ctlr, int mask, int (*rw)(struct mii *,
 125                                                      int unused_int,
 126                                                      int unused2, int unused3,
 127                                                      int unused4));
 128