akaros/kern/drivers/net/bnx2x/bnx2x_sp.h
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   1/* bnx2x_sp.h: Broadcom Everest network driver.
   2 *
   3 * Copyright (c) 2011-2013 Broadcom Corporation
   4 *
   5 * Unless you and Broadcom execute a separate written software license
   6 * agreement governing use of this software, this software is licensed to you
   7 * under the terms of the GNU General Public License version 2, available
   8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   9 *
  10 * Notwithstanding the above, under no circumstances may you combine this
  11 * software in any way with any other Broadcom software provided under a
  12 * license other than the GPL, without Broadcom's express prior written
  13 * consent.
  14 *
  15 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  16 * Written by: Vladislav Zolotarov
  17 *
  18 */
  19#pragma once
  20
  21struct bnx2x;
  22struct eth_context;
  23
  24/* Bits representing general command's configuration */
  25enum {
  26        RAMROD_TX,
  27        RAMROD_RX,
  28        /* Wait until all pending commands complete */
  29        RAMROD_COMP_WAIT,
  30        /* Don't send a ramrod, only update a registry */
  31        RAMROD_DRV_CLR_ONLY,
  32        /* Configure HW according to the current object state */
  33        RAMROD_RESTORE,
  34         /* Execute the next command now */
  35        RAMROD_EXEC,
  36        /* Don't add a new command and continue execution of postponed
  37         * commands. If not set a new command will be added to the
  38         * pending commands list.
  39         */
  40        RAMROD_CONT,
  41        /* If there is another pending ramrod, wait until it finishes and
  42         * re-try to submit this one. This flag can be set only in sleepable
  43         * context, and should not be set from the context that completes the
  44         * ramrods as deadlock will occur.
  45         */
  46        RAMROD_RETRY,
  47};
  48
  49typedef enum {
  50        BNX2X_OBJ_TYPE_RX,
  51        BNX2X_OBJ_TYPE_TX,
  52        BNX2X_OBJ_TYPE_RX_TX,
  53} bnx2x_obj_type;
  54
  55/* Public slow path states */
  56enum {
  57        BNX2X_FILTER_MAC_PENDING,
  58        BNX2X_FILTER_VLAN_PENDING,
  59        BNX2X_FILTER_VLAN_MAC_PENDING,
  60        BNX2X_FILTER_RX_MODE_PENDING,
  61        BNX2X_FILTER_RX_MODE_SCHED,
  62        BNX2X_FILTER_ISCSI_ETH_START_SCHED,
  63        BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
  64        BNX2X_FILTER_FCOE_ETH_START_SCHED,
  65        BNX2X_FILTER_FCOE_ETH_STOP_SCHED,
  66        BNX2X_FILTER_MCAST_PENDING,
  67        BNX2X_FILTER_MCAST_SCHED,
  68        BNX2X_FILTER_RSS_CONF_PENDING,
  69        BNX2X_AFEX_FCOE_Q_UPDATE_PENDING,
  70        BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
  71};
  72
  73struct bnx2x_raw_obj {
  74        uint8_t         func_id;
  75
  76        /* Queue params */
  77        uint8_t         cl_id;
  78        uint32_t                cid;
  79
  80        /* Ramrod data buffer params */
  81        void            *rdata;
  82        dma_addr_t      rdata_mapping;
  83
  84        /* Ramrod state params */
  85        int             state;   /* "ramrod is pending" state bit */
  86        unsigned long   *pstate; /* pointer to state buffer */
  87
  88        bnx2x_obj_type  obj_type;
  89
  90        int (*wait_comp)(struct bnx2x *bp,
  91                         struct bnx2x_raw_obj *o);
  92
  93        bool (*check_pending)(struct bnx2x_raw_obj *o);
  94        void (*clear_pending)(struct bnx2x_raw_obj *o);
  95        void (*set_pending)(struct bnx2x_raw_obj *o);
  96};
  97
  98/************************* VLAN-MAC commands related parameters ***************/
  99struct bnx2x_mac_ramrod_data {
 100        uint8_t mac[Eaddrlen];
 101        uint8_t is_inner_mac;
 102};
 103
 104struct bnx2x_vlan_ramrod_data {
 105        uint16_t vlan;
 106};
 107
 108struct bnx2x_vlan_mac_ramrod_data {
 109        uint8_t mac[Eaddrlen];
 110        uint8_t is_inner_mac;
 111        uint16_t vlan;
 112};
 113
 114union bnx2x_classification_ramrod_data {
 115        struct bnx2x_mac_ramrod_data mac;
 116        struct bnx2x_vlan_ramrod_data vlan;
 117        struct bnx2x_vlan_mac_ramrod_data vlan_mac;
 118};
 119
 120/* VLAN_MAC commands */
 121enum bnx2x_vlan_mac_cmd {
 122        BNX2X_VLAN_MAC_ADD,
 123        BNX2X_VLAN_MAC_DEL,
 124        BNX2X_VLAN_MAC_MOVE,
 125};
 126
 127struct bnx2x_vlan_mac_data {
 128        /* Requested command: BNX2X_VLAN_MAC_XX */
 129        enum bnx2x_vlan_mac_cmd cmd;
 130        /* used to contain the data related vlan_mac_flags bits from
 131         * ramrod parameters.
 132         */
 133        unsigned long vlan_mac_flags;
 134
 135        /* Needed for MOVE command */
 136        struct bnx2x_vlan_mac_obj *target_obj;
 137
 138        union bnx2x_classification_ramrod_data u;
 139};
 140
 141/*************************** Exe Queue obj ************************************/
 142union bnx2x_exe_queue_cmd_data {
 143        struct bnx2x_vlan_mac_data vlan_mac;
 144
 145        struct {
 146                /* TODO */
 147        } mcast;
 148};
 149
 150struct bnx2x_exeq_elem {
 151        struct list_head                link;
 152
 153        /* Length of this element in the exe_chunk. */
 154        int                             cmd_len;
 155
 156        union bnx2x_exe_queue_cmd_data  cmd_data;
 157};
 158
 159union bnx2x_qable_obj;
 160
 161union bnx2x_exeq_comp_elem {
 162        union event_ring_elem *elem;
 163};
 164
 165struct bnx2x_exe_queue_obj;
 166
 167typedef int (*exe_q_validate)(struct bnx2x *bp,
 168                              union bnx2x_qable_obj *o,
 169                              struct bnx2x_exeq_elem *elem);
 170
 171typedef int (*exe_q_remove)(struct bnx2x *bp,
 172                            union bnx2x_qable_obj *o,
 173                            struct bnx2x_exeq_elem *elem);
 174
 175/* Return positive if entry was optimized, 0 - if not, negative
 176 * in case of an error.
 177 */
 178typedef int (*exe_q_optimize)(struct bnx2x *bp,
 179                              union bnx2x_qable_obj *o,
 180                              struct bnx2x_exeq_elem *elem);
 181typedef int (*exe_q_execute)(struct bnx2x *bp,
 182                             union bnx2x_qable_obj *o,
 183                             struct list_head *exe_chunk,
 184                             unsigned long *ramrod_flags);
 185typedef struct bnx2x_exeq_elem *
 186                        (*exe_q_get)(struct bnx2x_exe_queue_obj *o,
 187                                     struct bnx2x_exeq_elem *elem);
 188
 189struct bnx2x_exe_queue_obj {
 190        /* Commands pending for an execution. */
 191        struct list_head        exe_queue;
 192
 193        /* Commands pending for an completion. */
 194        struct list_head        pending_comp;
 195
 196        spinlock_t              lock;
 197
 198        /* Maximum length of commands' list for one execution */
 199        int                     exe_chunk_len;
 200
 201        union bnx2x_qable_obj   *owner;
 202
 203        /****** Virtual functions ******/
 204        /**
 205         * Called before commands execution for commands that are really
 206         * going to be executed (after 'optimize').
 207         *
 208         * Must run under exe_queue->lock
 209         */
 210        exe_q_validate          validate;
 211
 212        /**
 213         * Called before removing pending commands, cleaning allocated
 214         * resources (e.g., credits from validate)
 215         */
 216         exe_q_remove           remove;
 217
 218        /**
 219         * This will try to cancel the current pending commands list
 220         * considering the new command.
 221         *
 222         * Returns the number of optimized commands or a negative error code
 223         *
 224         * Must run under exe_queue->lock
 225         */
 226        exe_q_optimize          optimize;
 227
 228        /**
 229         * Run the next commands chunk (owner specific).
 230         */
 231        exe_q_execute           execute;
 232
 233        /**
 234         * Return the exe_queue element containing the specific command
 235         * if any. Otherwise return NULL.
 236         */
 237        exe_q_get               get;
 238};
 239/***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
 240/*
 241 * Element in the VLAN_MAC registry list having all currently configured
 242 * rules.
 243 */
 244struct bnx2x_vlan_mac_registry_elem {
 245        struct list_head        link;
 246
 247        /* Used to store the cam offset used for the mac/vlan/vlan-mac.
 248         * Relevant for 57710 and 57711 only. VLANs and MACs share the
 249         * same CAM for these chips.
 250         */
 251        int                     cam_offset;
 252
 253        /* Needed for DEL and RESTORE flows */
 254        unsigned long           vlan_mac_flags;
 255
 256        union bnx2x_classification_ramrod_data u;
 257};
 258
 259/* Bits representing VLAN_MAC commands specific flags */
 260enum {
 261        BNX2X_UC_LIST_MAC,
 262        BNX2X_ETH_MAC,
 263        BNX2X_ISCSI_ETH_MAC,
 264        BNX2X_NETQ_ETH_MAC,
 265        BNX2X_DONT_CONSUME_CAM_CREDIT,
 266        BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
 267};
 268/* When looking for matching filters, some flags are not interesting */
 269#define BNX2X_VLAN_MAC_CMP_MASK (1 << BNX2X_UC_LIST_MAC | \
 270                                 1 << BNX2X_ETH_MAC | \
 271                                 1 << BNX2X_ISCSI_ETH_MAC | \
 272                                 1 << BNX2X_NETQ_ETH_MAC)
 273#define BNX2X_VLAN_MAC_CMP_FLAGS(flags) \
 274        ((flags) & BNX2X_VLAN_MAC_CMP_MASK)
 275
 276struct bnx2x_vlan_mac_ramrod_params {
 277        /* Object to run the command from */
 278        struct bnx2x_vlan_mac_obj *vlan_mac_obj;
 279
 280        /* General command flags: COMP_WAIT, etc. */
 281        unsigned long ramrod_flags;
 282
 283        /* Command specific configuration request */
 284        struct bnx2x_vlan_mac_data user_req;
 285};
 286
 287struct bnx2x_vlan_mac_obj {
 288        struct bnx2x_raw_obj raw;
 289
 290        /* Bookkeeping list: will prevent the addition of already existing
 291         * entries.
 292         */
 293        struct list_head                head;
 294        /* Implement a simple reader/writer lock on the head list.
 295         * all these fields should only be accessed under the exe_queue lock
 296         */
 297        uint8_t         head_reader; /* Num. of readers accessing head list */
 298        bool            head_exe_request; /* Pending execution request. */
 299        unsigned long   saved_ramrod_flags; /* Ramrods of pending execution */
 300
 301        /* TODO: Add it's initialization in the init functions */
 302        struct bnx2x_exe_queue_obj      exe_queue;
 303
 304        /* MACs credit pool */
 305        struct bnx2x_credit_pool_obj    *macs_pool;
 306
 307        /* VLANs credit pool */
 308        struct bnx2x_credit_pool_obj    *vlans_pool;
 309
 310        /* RAMROD command to be used */
 311        int                             ramrod_cmd;
 312
 313        /* copy first n elements onto preallocated buffer
 314         *
 315         * @param n number of elements to get
 316         * @param buf buffer preallocated by caller into which elements
 317         *            will be copied. Note elements are 4-byte aligned
 318         *            so buffer size must be able to accommodate the
 319         *            aligned elements.
 320         *
 321         * @return number of copied bytes
 322         */
 323        int (*get_n_elements)(struct bnx2x *bp,
 324                              struct bnx2x_vlan_mac_obj *o, int n,
 325                              uint8_t *base,
 326                              uint8_t stride, uint8_t size);
 327
 328        /**
 329         * Checks if ADD-ramrod with the given params may be performed.
 330         *
 331         * @return zero if the element may be added
 332         */
 333
 334        int (*check_add)(struct bnx2x *bp,
 335                         struct bnx2x_vlan_mac_obj *o,
 336                         union bnx2x_classification_ramrod_data *data);
 337
 338        /**
 339         * Checks if DEL-ramrod with the given params may be performed.
 340         *
 341         * @return true if the element may be deleted
 342         */
 343        struct bnx2x_vlan_mac_registry_elem *
 344                (*check_del)(struct bnx2x *bp,
 345                             struct bnx2x_vlan_mac_obj *o,
 346                             union bnx2x_classification_ramrod_data *data);
 347
 348        /**
 349         * Checks if DEL-ramrod with the given params may be performed.
 350         *
 351         * @return true if the element may be deleted
 352         */
 353        bool (*check_move)(struct bnx2x *bp,
 354                           struct bnx2x_vlan_mac_obj *src_o,
 355                           struct bnx2x_vlan_mac_obj *dst_o,
 356                           union bnx2x_classification_ramrod_data *data);
 357
 358        /**
 359         *  Update the relevant credit object(s) (consume/return
 360         *  correspondingly).
 361         */
 362        bool (*get_credit)(struct bnx2x_vlan_mac_obj *o);
 363        bool (*put_credit)(struct bnx2x_vlan_mac_obj *o);
 364        bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset);
 365        bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset);
 366
 367        /**
 368         * Configures one rule in the ramrod data buffer.
 369         */
 370        void (*set_one_rule)(struct bnx2x *bp,
 371                             struct bnx2x_vlan_mac_obj *o,
 372                             struct bnx2x_exeq_elem *elem, int rule_idx,
 373                             int cam_offset);
 374
 375        /**
 376        *  Delete all configured elements having the given
 377        *  vlan_mac_flags specification. Assumes no pending for
 378        *  execution commands. Will schedule all all currently
 379        *  configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags
 380        *  specification for deletion and will use the given
 381        *  ramrod_flags for the last DEL operation.
 382         *
 383         * @param bp
 384         * @param o
 385         * @param ramrod_flags RAMROD_XX flags
 386         *
 387         * @return 0 if the last operation has completed successfully
 388         *         and there are no more elements left, positive value
 389         *         if there are pending for completion commands,
 390         *         negative value in case of failure.
 391         */
 392        int (*delete_all)(struct bnx2x *bp,
 393                          struct bnx2x_vlan_mac_obj *o,
 394                          unsigned long *vlan_mac_flags,
 395                          unsigned long *ramrod_flags);
 396
 397        /**
 398         * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously
 399         * configured elements list.
 400         *
 401         * @param bp
 402         * @param p Command parameters (RAMROD_COMP_WAIT bit in
 403         *          ramrod_flags is only taken into an account)
 404         * @param ppos a pointer to the cookie that should be given back in the
 405         *        next call to make function handle the next element. If
 406         *        *ppos is set to NULL it will restart the iterator.
 407         *        If returned *ppos == NULL this means that the last
 408         *        element has been handled.
 409         *
 410         * @return int
 411         */
 412        int (*restore)(struct bnx2x *bp,
 413                       struct bnx2x_vlan_mac_ramrod_params *p,
 414                       struct bnx2x_vlan_mac_registry_elem **ppos);
 415
 416        /**
 417         * Should be called on a completion arrival.
 418         *
 419         * @param bp
 420         * @param o
 421         * @param cqe Completion element we are handling
 422         * @param ramrod_flags if RAMROD_CONT is set the next bulk of
 423         *                     pending commands will be executed.
 424         *                     RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE
 425         *                     may also be set if needed.
 426         *
 427         * @return 0 if there are neither pending nor waiting for
 428         *         completion commands. Positive value if there are
 429         *         pending for execution or for completion commands.
 430         *         Negative value in case of an error (including an
 431         *         error in the cqe).
 432         */
 433        int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
 434                        union event_ring_elem *cqe,
 435                        unsigned long *ramrod_flags);
 436
 437        /**
 438         * Wait for completion of all commands. Don't schedule new ones,
 439         * just wait. It assumes that the completion code will schedule
 440         * for new commands.
 441         */
 442        int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o);
 443};
 444
 445enum {
 446        BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0,
 447        BNX2X_LLH_CAM_ETH_LINE,
 448        BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
 449};
 450
 451/** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
 452
 453/* RX_MODE ramrod special flags: set in rx_mode_flags field in
 454 * a bnx2x_rx_mode_ramrod_params.
 455 */
 456enum {
 457        BNX2X_RX_MODE_FCOE_ETH,
 458        BNX2X_RX_MODE_ISCSI_ETH,
 459};
 460
 461enum {
 462        BNX2X_ACCEPT_UNICAST,
 463        BNX2X_ACCEPT_MULTICAST,
 464        BNX2X_ACCEPT_ALL_UNICAST,
 465        BNX2X_ACCEPT_ALL_MULTICAST,
 466        BNX2X_ACCEPT_BROADCAST,
 467        BNX2X_ACCEPT_UNMATCHED,
 468        BNX2X_ACCEPT_ANY_VLAN
 469};
 470
 471struct bnx2x_rx_mode_ramrod_params {
 472        struct bnx2x_rx_mode_obj *rx_mode_obj;
 473        unsigned long *pstate;
 474        int state;
 475        uint8_t cl_id;
 476        uint32_t cid;
 477        uint8_t func_id;
 478        unsigned long ramrod_flags;
 479        unsigned long rx_mode_flags;
 480
 481        /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to
 482         * a tstorm_eth_mac_filter_config (e1x).
 483         */
 484        void *rdata;
 485        dma_addr_t rdata_mapping;
 486
 487        /* Rx mode settings */
 488        unsigned long rx_accept_flags;
 489
 490        /* internal switching settings */
 491        unsigned long tx_accept_flags;
 492};
 493
 494struct bnx2x_rx_mode_obj {
 495        int (*config_rx_mode)(struct bnx2x *bp,
 496                              struct bnx2x_rx_mode_ramrod_params *p);
 497
 498        int (*wait_comp)(struct bnx2x *bp,
 499                         struct bnx2x_rx_mode_ramrod_params *p);
 500};
 501
 502/********************** Set multicast group ***********************************/
 503
 504struct bnx2x_mcast_list_elem {
 505        struct list_head link;
 506        uint8_t *mac;
 507};
 508
 509union bnx2x_mcast_config_data {
 510        uint8_t *mac;
 511        uint8_t bin; /* used in a RESTORE flow */
 512};
 513
 514struct bnx2x_mcast_ramrod_params {
 515        struct bnx2x_mcast_obj *mcast_obj;
 516
 517        /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */
 518        unsigned long ramrod_flags;
 519
 520        struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */
 521        /** TODO:
 522         *      - rename it to macs_num.
 523         *      - Add a new command type for handling pending commands
 524         *        (remove "zero semantics").
 525         *
 526         *  Length of mcast_list. If zero and ADD_CONT command - post
 527         *  pending commands.
 528         */
 529        int mcast_list_len;
 530};
 531
 532enum bnx2x_mcast_cmd {
 533        BNX2X_MCAST_CMD_ADD,
 534        BNX2X_MCAST_CMD_CONT,
 535        BNX2X_MCAST_CMD_DEL,
 536        BNX2X_MCAST_CMD_RESTORE,
 537};
 538
 539struct bnx2x_mcast_obj {
 540        struct bnx2x_raw_obj raw;
 541
 542        union {
 543                struct {
 544                #define BNX2X_MCAST_BINS_NUM    256
 545                #define BNX2X_MCAST_VEC_SZ      (BNX2X_MCAST_BINS_NUM / 64)
 546                        uint64_t vec[BNX2X_MCAST_VEC_SZ];
 547
 548                        /** Number of BINs to clear. Should be updated
 549                         *  immediately when a command arrives in order to
 550                         *  properly create DEL commands.
 551                         */
 552                        int num_bins_set;
 553                } aprox_match;
 554
 555                struct {
 556                        struct list_head macs;
 557                        int num_macs_set;
 558                } exact_match;
 559        } registry;
 560
 561        /* Pending commands */
 562        struct list_head pending_cmds_head;
 563
 564        /* A state that is set in raw.pstate, when there are pending commands */
 565        int sched_state;
 566
 567        /* Maximal number of mcast MACs configured in one command */
 568        int max_cmd_len;
 569
 570        /* Total number of currently pending MACs to configure: both
 571         * in the pending commands list and in the current command.
 572         */
 573        int total_pending_num;
 574
 575        uint8_t engine_id;
 576
 577        /**
 578         * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above)
 579         */
 580        int (*config_mcast)(struct bnx2x *bp,
 581                            struct bnx2x_mcast_ramrod_params *p,
 582                            enum bnx2x_mcast_cmd cmd);
 583
 584        /**
 585         * Fills the ramrod data during the RESTORE flow.
 586         *
 587         * @param bp
 588         * @param o
 589         * @param start_idx Registry index to start from
 590         * @param rdata_idx Index in the ramrod data to start from
 591         *
 592         * @return -1 if we handled the whole registry or index of the last
 593         *         handled registry element.
 594         */
 595        int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
 596                           int start_bin, int *rdata_idx);
 597
 598        int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
 599                           struct bnx2x_mcast_ramrod_params *p,
 600                           enum bnx2x_mcast_cmd cmd);
 601
 602        void (*set_one_rule)(struct bnx2x *bp,
 603                             struct bnx2x_mcast_obj *o, int idx,
 604                             union bnx2x_mcast_config_data *cfg_data,
 605                             enum bnx2x_mcast_cmd cmd);
 606
 607        /** Checks if there are more mcast MACs to be set or a previous
 608         *  command is still pending.
 609         */
 610        bool (*check_pending)(struct bnx2x_mcast_obj *o);
 611
 612        /**
 613         * Set/Clear/Check SCHEDULED state of the object
 614         */
 615        void (*set_sched)(struct bnx2x_mcast_obj *o);
 616        void (*clear_sched)(struct bnx2x_mcast_obj *o);
 617        bool (*check_sched)(struct bnx2x_mcast_obj *o);
 618
 619        /* Wait until all pending commands complete */
 620        int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o);
 621
 622        /**
 623         * Handle the internal object counters needed for proper
 624         * commands handling. Checks that the provided parameters are
 625         * feasible.
 626         */
 627        int (*validate)(struct bnx2x *bp,
 628                        struct bnx2x_mcast_ramrod_params *p,
 629                        enum bnx2x_mcast_cmd cmd);
 630
 631        /**
 632         * Restore the values of internal counters in case of a failure.
 633         */
 634        void (*revert)(struct bnx2x *bp,
 635                       struct bnx2x_mcast_ramrod_params *p,
 636                       int old_num_bins);
 637
 638        int (*get_registry_size)(struct bnx2x_mcast_obj *o);
 639        void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n);
 640};
 641
 642/*************************** Credit handling **********************************/
 643struct bnx2x_credit_pool_obj {
 644
 645        /* Current amount of credit in the pool */
 646        atomic_t        credit;
 647
 648        /* Maximum allowed credit. put() will check against it. */
 649        int             pool_sz;
 650
 651        /* Allocate a pool table statically.
 652         *
 653         * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272)
 654         *
 655         * The set bit in the table will mean that the entry is available.
 656         */
 657#define BNX2X_POOL_VEC_SIZE     (MAX_MAC_CREDIT_E2 / 64)
 658        uint64_t                pool_mirror[BNX2X_POOL_VEC_SIZE];
 659
 660        /* Base pool offset (initialized differently */
 661        int             base_pool_offset;
 662
 663        /**
 664         * Get the next free pool entry.
 665         *
 666         * @return true if there was a free entry in the pool
 667         */
 668        bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry);
 669
 670        /**
 671         * Return the entry back to the pool.
 672         *
 673         * @return true if entry is legal and has been successfully
 674         *         returned to the pool.
 675         */
 676        bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry);
 677
 678        /**
 679         * Get the requested amount of credit from the pool.
 680         *
 681         * @param cnt Amount of requested credit
 682         * @return true if the operation is successful
 683         */
 684        bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt);
 685
 686        /**
 687         * Returns the credit to the pool.
 688         *
 689         * @param cnt Amount of credit to return
 690         * @return true if the operation is successful
 691         */
 692        bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt);
 693
 694        /**
 695         * Reads the current amount of credit.
 696         */
 697        int (*check)(struct bnx2x_credit_pool_obj *o);
 698};
 699
 700/*************************** RSS configuration ********************************/
 701enum {
 702        /* RSS_MODE bits are mutually exclusive */
 703        BNX2X_RSS_MODE_DISABLED,
 704        BNX2X_RSS_MODE_REGULAR,
 705
 706        BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */
 707
 708        BNX2X_RSS_IPV4,
 709        BNX2X_RSS_IPV4_TCP,
 710        BNX2X_RSS_IPV4_UDP,
 711        BNX2X_RSS_IPV6,
 712        BNX2X_RSS_IPV6_TCP,
 713        BNX2X_RSS_IPV6_UDP,
 714        BNX2X_RSS_GRE_INNER_HDRS,
 715};
 716
 717struct bnx2x_config_rss_params {
 718        struct bnx2x_rss_config_obj *rss_obj;
 719
 720        /* may have RAMROD_COMP_WAIT set only */
 721        unsigned long   ramrod_flags;
 722
 723        /* BNX2X_RSS_X bits */
 724        unsigned long   rss_flags;
 725
 726        /* Number hash bits to take into an account */
 727        uint8_t         rss_result_mask;
 728
 729        /* Indirection table */
 730        uint8_t         ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
 731
 732        /* RSS hash values */
 733        uint32_t                rss_key[10];
 734
 735        /* valid only iff BNX2X_RSS_UPDATE_TOE is set */
 736        uint16_t                toe_rss_bitmap;
 737};
 738
 739struct bnx2x_rss_config_obj {
 740        struct bnx2x_raw_obj    raw;
 741
 742        /* RSS engine to use */
 743        uint8_t                 engine_id;
 744
 745        /* Last configured indirection table */
 746        uint8_t                 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
 747
 748        /* flags for enabling 4-tupple hash on UDP */
 749        uint8_t                 udp_rss_v4;
 750        uint8_t                 udp_rss_v6;
 751
 752        int (*config_rss)(struct bnx2x *bp,
 753                          struct bnx2x_config_rss_params *p);
 754};
 755
 756/*********************** Queue state update ***********************************/
 757
 758/* UPDATE command options */
 759enum {
 760        BNX2X_Q_UPDATE_IN_VLAN_REM,
 761        BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
 762        BNX2X_Q_UPDATE_OUT_VLAN_REM,
 763        BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
 764        BNX2X_Q_UPDATE_ANTI_SPOOF,
 765        BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG,
 766        BNX2X_Q_UPDATE_ACTIVATE,
 767        BNX2X_Q_UPDATE_ACTIVATE_CHNG,
 768        BNX2X_Q_UPDATE_DEF_VLAN_EN,
 769        BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
 770        BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
 771        BNX2X_Q_UPDATE_SILENT_VLAN_REM,
 772        BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
 773        BNX2X_Q_UPDATE_TX_SWITCHING,
 774        BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
 775        BNX2X_Q_UPDATE_PTP_PKTS,
 776};
 777
 778/* Allowed Queue states */
 779enum bnx2x_q_state {
 780        BNX2X_Q_STATE_RESET,
 781        BNX2X_Q_STATE_INITIALIZED,
 782        BNX2X_Q_STATE_ACTIVE,
 783        BNX2X_Q_STATE_MULTI_COS,
 784        BNX2X_Q_STATE_MCOS_TERMINATED,
 785        BNX2X_Q_STATE_INACTIVE,
 786        BNX2X_Q_STATE_STOPPED,
 787        BNX2X_Q_STATE_TERMINATED,
 788        BNX2X_Q_STATE_FLRED,
 789        BNX2X_Q_STATE_MAX,
 790};
 791
 792/* Allowed Queue states */
 793enum bnx2x_q_logical_state {
 794        BNX2X_Q_LOGICAL_STATE_ACTIVE,
 795        BNX2X_Q_LOGICAL_STATE_STOPPED,
 796};
 797
 798/* Allowed commands */
 799enum bnx2x_queue_cmd {
 800        BNX2X_Q_CMD_INIT,
 801        BNX2X_Q_CMD_SETUP,
 802        BNX2X_Q_CMD_SETUP_TX_ONLY,
 803        BNX2X_Q_CMD_DEACTIVATE,
 804        BNX2X_Q_CMD_ACTIVATE,
 805        BNX2X_Q_CMD_UPDATE,
 806        BNX2X_Q_CMD_UPDATE_TPA,
 807        BNX2X_Q_CMD_HALT,
 808        BNX2X_Q_CMD_CFC_DEL,
 809        BNX2X_Q_CMD_TERMINATE,
 810        BNX2X_Q_CMD_EMPTY,
 811        BNX2X_Q_CMD_MAX,
 812};
 813
 814/* queue SETUP + INIT flags */
 815enum {
 816        BNX2X_Q_FLG_TPA,
 817        BNX2X_Q_FLG_TPA_IPV6,
 818        BNX2X_Q_FLG_TPA_GRO,
 819        BNX2X_Q_FLG_STATS,
 820        BNX2X_Q_FLG_ZERO_STATS,
 821        BNX2X_Q_FLG_ACTIVE,
 822        BNX2X_Q_FLG_OV,
 823        BNX2X_Q_FLG_VLAN,
 824        BNX2X_Q_FLG_COS,
 825        BNX2X_Q_FLG_HC,
 826        BNX2X_Q_FLG_HC_EN,
 827        BNX2X_Q_FLG_DHC,
 828        BNX2X_Q_FLG_FCOE,
 829        BNX2X_Q_FLG_LEADING_RSS,
 830        BNX2X_Q_FLG_MCAST,
 831        BNX2X_Q_FLG_DEF_VLAN,
 832        BNX2X_Q_FLG_TX_SWITCH,
 833        BNX2X_Q_FLG_TX_SEC,
 834        BNX2X_Q_FLG_ANTI_SPOOF,
 835        BNX2X_Q_FLG_SILENT_VLAN_REM,
 836        BNX2X_Q_FLG_FORCE_DEFAULT_PRI,
 837        BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN,
 838        BNX2X_Q_FLG_PCSUM_ON_PKT,
 839        BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
 840};
 841
 842/* Queue type options: queue type may be a combination of below. */
 843enum bnx2x_q_type {
 844        /** TODO: Consider moving both these flags into the init()
 845         *        ramrod params.
 846         */
 847        BNX2X_Q_TYPE_HAS_RX,
 848        BNX2X_Q_TYPE_HAS_TX,
 849};
 850
 851#define BNX2X_PRIMARY_CID_INDEX                 0
 852#define BNX2X_MULTI_TX_COS_E1X                  3 /* QM only */
 853#define BNX2X_MULTI_TX_COS_E2_E3A0              2
 854#define BNX2X_MULTI_TX_COS_E3B0                 3
 855#define BNX2X_MULTI_TX_COS                      3 /* Maximum possible */
 856
 857#define MAC_PAD (ALIGN(Eaddrlen, sizeof(uint32_t)) - Eaddrlen)
 858/* DMAE channel to be used by FW for timesync workaroun. A driver that sends
 859 * timesync-related ramrods must not use this DMAE command ID.
 860 */
 861#define FW_DMAE_CMD_ID 6
 862
 863struct bnx2x_queue_init_params {
 864        struct {
 865                unsigned long   flags;
 866                uint16_t                hc_rate;
 867                uint8_t         fw_sb_id;
 868                uint8_t         sb_cq_index;
 869        } tx;
 870
 871        struct {
 872                unsigned long   flags;
 873                uint16_t                hc_rate;
 874                uint8_t         fw_sb_id;
 875                uint8_t         sb_cq_index;
 876        } rx;
 877
 878        /* CID context in the host memory */
 879        struct eth_context *cxts[BNX2X_MULTI_TX_COS];
 880
 881        /* maximum number of cos supported by hardware */
 882        uint8_t max_cos;
 883};
 884
 885struct bnx2x_queue_terminate_params {
 886        /* index within the tx_only cids of this queue object */
 887        uint8_t cid_index;
 888};
 889
 890struct bnx2x_queue_cfc_del_params {
 891        /* index within the tx_only cids of this queue object */
 892        uint8_t cid_index;
 893};
 894
 895struct bnx2x_queue_update_params {
 896        unsigned long   update_flags; /* BNX2X_Q_UPDATE_XX bits */
 897        uint16_t                def_vlan;
 898        uint16_t                silent_removal_value;
 899        uint16_t                silent_removal_mask;
 900/* index within the tx_only cids of this queue object */
 901        uint8_t         cid_index;
 902};
 903
 904struct bnx2x_queue_update_tpa_params {
 905        dma_addr_t sge_map;
 906        uint8_t update_ipv4;
 907        uint8_t update_ipv6;
 908        uint8_t max_tpa_queues;
 909        uint8_t max_sges_pkt;
 910        uint8_t complete_on_both_clients;
 911        uint8_t dont_verify_thr;
 912        uint8_t tpa_mode;
 913        uint8_t _pad;
 914
 915        uint16_t sge_buff_sz;
 916        uint16_t max_agg_sz;
 917
 918        uint16_t sge_pause_thr_low;
 919        uint16_t sge_pause_thr_high;
 920};
 921
 922struct rxq_pause_params {
 923        uint16_t                bd_th_lo;
 924        uint16_t                bd_th_hi;
 925        uint16_t                rcq_th_lo;
 926        uint16_t                rcq_th_hi;
 927        uint16_t                sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */
 928        uint16_t                sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */
 929        uint16_t                pri_map;
 930};
 931
 932/* general */
 933struct bnx2x_general_setup_params {
 934        /* valid iff BNX2X_Q_FLG_STATS */
 935        uint8_t         stat_id;
 936
 937        uint8_t         spcl_id;
 938        uint16_t                mtu;
 939        uint8_t         cos;
 940
 941        uint8_t         fp_hsi;
 942};
 943
 944struct bnx2x_rxq_setup_params {
 945        /* dma */
 946        dma_addr_t      dscr_map;
 947        dma_addr_t      sge_map;
 948        dma_addr_t      rcq_map;
 949        dma_addr_t      rcq_np_map;
 950
 951        uint16_t                drop_flags;
 952        uint16_t                buf_sz;
 953        uint8_t         fw_sb_id;
 954        uint8_t         cl_qzone_id;
 955
 956        /* valid iff BNX2X_Q_FLG_TPA */
 957        uint16_t                tpa_agg_sz;
 958        uint16_t                sge_buf_sz;
 959        uint8_t         max_sges_pkt;
 960        uint8_t         max_tpa_queues;
 961        uint8_t         rss_engine_id;
 962
 963        /* valid iff BNX2X_Q_FLG_MCAST */
 964        uint8_t         mcast_engine_id;
 965
 966        uint8_t         cache_line_log;
 967
 968        uint8_t         sb_cq_index;
 969
 970        /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */
 971        uint16_t silent_removal_value;
 972        uint16_t silent_removal_mask;
 973};
 974
 975struct bnx2x_txq_setup_params {
 976        /* dma */
 977        dma_addr_t      dscr_map;
 978
 979        uint8_t         fw_sb_id;
 980        uint8_t         sb_cq_index;
 981        uint8_t         cos;            /* valid iff BNX2X_Q_FLG_COS */
 982        uint16_t                traffic_type;
 983        /* equals to the leading rss client id, used for TX classification*/
 984        uint8_t         tss_leading_cl_id;
 985
 986        /* valid iff BNX2X_Q_FLG_DEF_VLAN */
 987        uint16_t                default_vlan;
 988};
 989
 990struct bnx2x_queue_setup_params {
 991        struct bnx2x_general_setup_params gen_params;
 992        struct bnx2x_txq_setup_params txq_params;
 993        struct bnx2x_rxq_setup_params rxq_params;
 994        struct rxq_pause_params pause_params;
 995        unsigned long flags;
 996};
 997
 998struct bnx2x_queue_setup_tx_only_params {
 999        struct bnx2x_general_setup_params       gen_params;
1000        struct bnx2x_txq_setup_params           txq_params;
1001        unsigned long                           flags;
1002        /* index within the tx_only cids of this queue object */
1003        uint8_t                                 cid_index;
1004};
1005
1006struct bnx2x_queue_state_params {
1007        struct bnx2x_queue_sp_obj *q_obj;
1008
1009        /* Current command */
1010        enum bnx2x_queue_cmd cmd;
1011
1012        /* may have RAMROD_COMP_WAIT set only */
1013        unsigned long ramrod_flags;
1014
1015        /* Params according to the current command */
1016        union {
1017                struct bnx2x_queue_update_params        update;
1018                struct bnx2x_queue_update_tpa_params    update_tpa;
1019                struct bnx2x_queue_setup_params         setup;
1020                struct bnx2x_queue_init_params          init;
1021                struct bnx2x_queue_setup_tx_only_params tx_only;
1022                struct bnx2x_queue_terminate_params     terminate;
1023                struct bnx2x_queue_cfc_del_params       cfc_del;
1024        } params;
1025};
1026
1027struct bnx2x_viflist_params {
1028        uint8_t echo_res;
1029        uint8_t func_bit_map_res;
1030};
1031
1032struct bnx2x_queue_sp_obj {
1033        uint32_t                cids[BNX2X_MULTI_TX_COS];
1034        uint8_t         cl_id;
1035        uint8_t         func_id;
1036
1037        /* number of traffic classes supported by queue.
1038         * The primary connection of the queue supports the first traffic
1039         * class. Any further traffic class is supported by a tx-only
1040         * connection.
1041         *
1042         * Therefore max_cos is also a number of valid entries in the cids
1043         * array.
1044         */
1045        uint8_t max_cos;
1046        uint8_t num_tx_only, next_tx_only;
1047
1048        enum bnx2x_q_state state, next_state;
1049
1050        /* bits from enum bnx2x_q_type */
1051        unsigned long   type;
1052
1053        /* BNX2X_Q_CMD_XX bits. This object implements "one
1054         * pending" paradigm but for debug and tracing purposes it's
1055         * more convenient to have different bits for different
1056         * commands.
1057         */
1058        unsigned long   pending;
1059
1060        /* Buffer to use as a ramrod data and its mapping */
1061        void            *rdata;
1062        dma_addr_t      rdata_mapping;
1063
1064        /**
1065         * Performs one state change according to the given parameters.
1066         *
1067         * @return 0 in case of success and negative value otherwise.
1068         */
1069        int (*send_cmd)(struct bnx2x *bp,
1070                        struct bnx2x_queue_state_params *params);
1071
1072        /**
1073         * Sets the pending bit according to the requested transition.
1074         */
1075        int (*set_pending)(struct bnx2x_queue_sp_obj *o,
1076                           struct bnx2x_queue_state_params *params);
1077
1078        /**
1079         * Checks that the requested state transition is legal.
1080         */
1081        int (*check_transition)(struct bnx2x *bp,
1082                                struct bnx2x_queue_sp_obj *o,
1083                                struct bnx2x_queue_state_params *params);
1084
1085        /**
1086         * Completes the pending command.
1087         */
1088        int (*complete_cmd)(struct bnx2x *bp,
1089                            struct bnx2x_queue_sp_obj *o,
1090                            enum bnx2x_queue_cmd);
1091
1092        int (*wait_comp)(struct bnx2x *bp,
1093                         struct bnx2x_queue_sp_obj *o,
1094                         enum bnx2x_queue_cmd cmd);
1095};
1096
1097/********************** Function state update *********************************/
1098
1099/* UPDATE command options */
1100enum {
1101        BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
1102        BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
1103        BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
1104        BNX2X_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG,
1105        BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
1106        BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
1107        BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
1108        BNX2X_F_UPDATE_TUNNEL_CLSS_EN,
1109        BNX2X_F_UPDATE_TUNNEL_INNER_GRE_RSS_EN,
1110};
1111
1112/* Allowed Function states */
1113enum bnx2x_func_state {
1114        BNX2X_F_STATE_RESET,
1115        BNX2X_F_STATE_INITIALIZED,
1116        BNX2X_F_STATE_STARTED,
1117        BNX2X_F_STATE_TX_STOPPED,
1118        BNX2X_F_STATE_MAX,
1119};
1120
1121/* Allowed Function commands */
1122enum bnx2x_func_cmd {
1123        BNX2X_F_CMD_HW_INIT,
1124        BNX2X_F_CMD_START,
1125        BNX2X_F_CMD_STOP,
1126        BNX2X_F_CMD_HW_RESET,
1127        BNX2X_F_CMD_AFEX_UPDATE,
1128        BNX2X_F_CMD_AFEX_VIFLISTS,
1129        BNX2X_F_CMD_TX_STOP,
1130        BNX2X_F_CMD_TX_START,
1131        BNX2X_F_CMD_SWITCH_UPDATE,
1132        BNX2X_F_CMD_SET_TIMESYNC,
1133        BNX2X_F_CMD_MAX,
1134};
1135
1136struct bnx2x_func_hw_init_params {
1137        /* A load phase returned by MCP.
1138         *
1139         * May be:
1140         *              FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1141         *              FW_MSG_CODE_DRV_LOAD_COMMON
1142         *              FW_MSG_CODE_DRV_LOAD_PORT
1143         *              FW_MSG_CODE_DRV_LOAD_FUNCTION
1144         */
1145        uint32_t load_phase;
1146};
1147
1148struct bnx2x_func_hw_reset_params {
1149        /* A load phase returned by MCP.
1150         *
1151         * May be:
1152         *              FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1153         *              FW_MSG_CODE_DRV_LOAD_COMMON
1154         *              FW_MSG_CODE_DRV_LOAD_PORT
1155         *              FW_MSG_CODE_DRV_LOAD_FUNCTION
1156         */
1157        uint32_t reset_phase;
1158};
1159
1160struct bnx2x_func_start_params {
1161        /* Multi Function mode:
1162         *      - Single Function
1163         *      - Switch Dependent
1164         *      - Switch Independent
1165         */
1166        uint16_t mf_mode;
1167
1168        /* Switch Dependent mode outer VLAN tag */
1169        uint16_t sd_vlan_tag;
1170
1171        /* Function cos mode */
1172        uint8_t network_cos_mode;
1173
1174        /* TUNN_MODE_NONE/TUNN_MODE_VXLAN/TUNN_MODE_GRE */
1175        uint8_t tunnel_mode;
1176
1177        /* tunneling classification enablement */
1178        uint8_t tunn_clss_en;
1179
1180        /* NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
1181        uint8_t gre_tunnel_type;
1182
1183        /* Enables Inner GRE RSS on the function, depends on the client RSS
1184         * capailities
1185         */
1186        uint8_t inner_gre_rss_en;
1187
1188        /* Allows accepting of packets failing MF classification, possibly
1189         * only matching a given ethertype
1190         */
1191        uint8_t class_fail;
1192        uint16_t class_fail_ethtype;
1193
1194        /* Override priority of output packets */
1195        uint8_t sd_vlan_force_pri;
1196        uint8_t sd_vlan_force_pri_val;
1197
1198        /* Replace vlan's ethertype */
1199        uint16_t sd_vlan_eth_type;
1200
1201        /* Prevent inner vlans from being added by FW */
1202        uint8_t no_added_tags;
1203};
1204
1205struct bnx2x_func_switch_update_params {
1206        unsigned long changes; /* BNX2X_F_UPDATE_XX bits */
1207        uint16_t vlan;
1208        uint16_t vlan_eth_type;
1209        uint8_t vlan_force_prio;
1210        uint8_t tunnel_mode;
1211        uint8_t gre_tunnel_type;
1212};
1213
1214struct bnx2x_func_afex_update_params {
1215        uint16_t vif_id;
1216        uint16_t afex_default_vlan;
1217        uint8_t allowed_priorities;
1218};
1219
1220struct bnx2x_func_afex_viflists_params {
1221        uint16_t vif_list_index;
1222        uint8_t func_bit_map;
1223        uint8_t afex_vif_list_command;
1224        uint8_t func_to_clear;
1225};
1226
1227struct bnx2x_func_tx_start_params {
1228        struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1229        uint8_t dcb_enabled;
1230        uint8_t dcb_version;
1231        uint8_t dont_add_pri_0_en;
1232};
1233
1234struct bnx2x_func_set_timesync_params {
1235        /* Reset, set or keep the current drift value */
1236        uint8_t drift_adjust_cmd;
1237
1238        /* Dec, inc or keep the current offset */
1239        uint8_t offset_cmd;
1240
1241        /* Drift value direction */
1242        uint8_t add_sub_drift_adjust_value;
1243
1244        /* Drift, period and offset values to be used according to the commands
1245         * above.
1246         */
1247        uint8_t drift_adjust_value;
1248        uint32_t drift_adjust_period;
1249        uint64_t offset_delta;
1250};
1251
1252struct bnx2x_func_state_params {
1253        struct bnx2x_func_sp_obj *f_obj;
1254
1255        /* Current command */
1256        enum bnx2x_func_cmd cmd;
1257
1258        /* may have RAMROD_COMP_WAIT set only */
1259        unsigned long   ramrod_flags;
1260
1261        /* Params according to the current command */
1262        union {
1263                struct bnx2x_func_hw_init_params hw_init;
1264                struct bnx2x_func_hw_reset_params hw_reset;
1265                struct bnx2x_func_start_params start;
1266                struct bnx2x_func_switch_update_params switch_update;
1267                struct bnx2x_func_afex_update_params afex_update;
1268                struct bnx2x_func_afex_viflists_params afex_viflists;
1269                struct bnx2x_func_tx_start_params tx_start;
1270                struct bnx2x_func_set_timesync_params set_timesync;
1271        } params;
1272};
1273
1274struct bnx2x_func_sp_drv_ops {
1275        /* Init tool + runtime initialization:
1276         *      - Common Chip
1277         *      - Common (per Path)
1278         *      - Port
1279         *      - Function phases
1280         */
1281        int (*init_hw_cmn_chip)(struct bnx2x *bp);
1282        int (*init_hw_cmn)(struct bnx2x *bp);
1283        int (*init_hw_port)(struct bnx2x *bp);
1284        int (*init_hw_func)(struct bnx2x *bp);
1285
1286        /* Reset Function HW: Common, Port, Function phases. */
1287        void (*reset_hw_cmn)(struct bnx2x *bp);
1288        void (*reset_hw_port)(struct bnx2x *bp);
1289        void (*reset_hw_func)(struct bnx2x *bp);
1290
1291        /* Init/Free GUNZIP resources */
1292        int (*gunzip_init)(struct bnx2x *bp);
1293        void (*gunzip_end)(struct bnx2x *bp);
1294
1295        /* Prepare/Release FW resources */
1296        int (*init_fw)(struct bnx2x *bp);
1297        void (*release_fw)(struct bnx2x *bp);
1298};
1299
1300struct bnx2x_func_sp_obj {
1301        enum bnx2x_func_state   state, next_state;
1302
1303        /* BNX2X_FUNC_CMD_XX bits. This object implements "one
1304         * pending" paradigm but for debug and tracing purposes it's
1305         * more convenient to have different bits for different
1306         * commands.
1307         */
1308        unsigned long           pending;
1309
1310        /* Buffer to use as a ramrod data and its mapping */
1311        void                    *rdata;
1312        dma_addr_t              rdata_mapping;
1313
1314        /* Buffer to use as a afex ramrod data and its mapping.
1315         * This can't be same rdata as above because afex ramrod requests
1316         * can arrive to the object in parallel to other ramrod requests.
1317         */
1318        void                    *afex_rdata;
1319        dma_addr_t              afex_rdata_mapping;
1320
1321        /* this mutex validates that when pending flag is taken, the next
1322         * ramrod to be sent will be the one set the pending bit
1323         */
1324        qlock_t         one_pending_mutex;
1325
1326        /* Driver interface */
1327        struct bnx2x_func_sp_drv_ops    *drv;
1328
1329        /**
1330         * Performs one state change according to the given parameters.
1331         *
1332         * @return 0 in case of success and negative value otherwise.
1333         */
1334        int (*send_cmd)(struct bnx2x *bp,
1335                        struct bnx2x_func_state_params *params);
1336
1337        /**
1338         * Checks that the requested state transition is legal.
1339         */
1340        int (*check_transition)(struct bnx2x *bp,
1341                                struct bnx2x_func_sp_obj *o,
1342                                struct bnx2x_func_state_params *params);
1343
1344        /**
1345         * Completes the pending command.
1346         */
1347        int (*complete_cmd)(struct bnx2x *bp,
1348                            struct bnx2x_func_sp_obj *o,
1349                            enum bnx2x_func_cmd cmd);
1350
1351        int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o,
1352                         enum bnx2x_func_cmd cmd);
1353};
1354
1355/********************** Interfaces ********************************************/
1356/* Queueable objects set */
1357union bnx2x_qable_obj {
1358        struct bnx2x_vlan_mac_obj vlan_mac;
1359};
1360/************** Function state update *********/
1361void bnx2x_init_func_obj(struct bnx2x *bp,
1362                         struct bnx2x_func_sp_obj *obj,
1363                         void *rdata, dma_addr_t rdata_mapping,
1364                         void *afex_rdata, dma_addr_t afex_rdata_mapping,
1365                         struct bnx2x_func_sp_drv_ops *drv_iface);
1366
1367int bnx2x_func_state_change(struct bnx2x *bp,
1368                            struct bnx2x_func_state_params *params);
1369
1370enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
1371                                           struct bnx2x_func_sp_obj *o);
1372/******************* Queue State **************/
1373void bnx2x_init_queue_obj(struct bnx2x *bp,
1374                          struct bnx2x_queue_sp_obj *obj, uint8_t cl_id,
1375                          uint32_t *cids,
1376                          uint8_t cid_cnt, uint8_t func_id, void *rdata,
1377                          dma_addr_t rdata_mapping, unsigned long type);
1378
1379int bnx2x_queue_state_change(struct bnx2x *bp,
1380                             struct bnx2x_queue_state_params *params);
1381
1382int bnx2x_get_q_logical_state(struct bnx2x *bp,
1383                               struct bnx2x_queue_sp_obj *obj);
1384
1385/********************* VLAN-MAC ****************/
1386void bnx2x_init_mac_obj(struct bnx2x *bp,
1387                        struct bnx2x_vlan_mac_obj *mac_obj,
1388                        uint8_t cl_id, uint32_t cid, uint8_t func_id,
1389                        void *rdata,
1390                        dma_addr_t rdata_mapping, int state,
1391                        unsigned long *pstate, bnx2x_obj_type type,
1392                        struct bnx2x_credit_pool_obj *macs_pool);
1393
1394void bnx2x_init_vlan_obj(struct bnx2x *bp,
1395                         struct bnx2x_vlan_mac_obj *vlan_obj,
1396                         uint8_t cl_id, uint32_t cid, uint8_t func_id,
1397                         void *rdata,
1398                         dma_addr_t rdata_mapping, int state,
1399                         unsigned long *pstate, bnx2x_obj_type type,
1400                         struct bnx2x_credit_pool_obj *vlans_pool);
1401
1402int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp,
1403                                        struct bnx2x_vlan_mac_obj *o);
1404void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp,
1405                                  struct bnx2x_vlan_mac_obj *o);
1406int bnx2x_vlan_mac_h_write_lock(struct bnx2x *bp,
1407                                struct bnx2x_vlan_mac_obj *o);
1408int bnx2x_config_vlan_mac(struct bnx2x *bp,
1409                           struct bnx2x_vlan_mac_ramrod_params *p);
1410
1411int bnx2x_vlan_mac_move(struct bnx2x *bp,
1412                        struct bnx2x_vlan_mac_ramrod_params *p,
1413                        struct bnx2x_vlan_mac_obj *dest_o);
1414
1415/********************* RX MODE ****************/
1416
1417void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
1418                            struct bnx2x_rx_mode_obj *o);
1419
1420/**
1421 * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters.
1422 *
1423 * @p: Command parameters
1424 *
1425 * Return: 0 - if operation was successful and there is no pending completions,
1426 *         positive number - if there are pending completions,
1427 *         negative - if there were errors
1428 */
1429int bnx2x_config_rx_mode(struct bnx2x *bp,
1430                         struct bnx2x_rx_mode_ramrod_params *p);
1431
1432/****************** MULTICASTS ****************/
1433
1434void bnx2x_init_mcast_obj(struct bnx2x *bp,
1435                          struct bnx2x_mcast_obj *mcast_obj,
1436                          uint8_t mcast_cl_id, uint32_t mcast_cid,
1437                          uint8_t func_id,
1438                          uint8_t engine_id, void *rdata,
1439                          dma_addr_t rdata_mapping,
1440                          int state, unsigned long *pstate,
1441                          bnx2x_obj_type type);
1442
1443/**
1444 * bnx2x_config_mcast - Configure multicast MACs list.
1445 *
1446 * @cmd: command to execute: BNX2X_MCAST_CMD_X
1447 *
1448 * May configure a new list
1449 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up
1450 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current
1451 * configuration, continue to execute the pending commands
1452 * (BNX2X_MCAST_CMD_CONT).
1453 *
1454 * If previous command is still pending or if number of MACs to
1455 * configure is more that maximum number of MACs in one command,
1456 * the current command will be enqueued to the tail of the
1457 * pending commands list.
1458 *
1459 * Return: 0 is operation was successful and there are no pending completions,
1460 *         negative if there were errors, positive if there are pending
1461 *         completions.
1462 */
1463int bnx2x_config_mcast(struct bnx2x *bp,
1464                       struct bnx2x_mcast_ramrod_params *p,
1465                       enum bnx2x_mcast_cmd cmd);
1466
1467/****************** CREDIT POOL ****************/
1468void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
1469                                struct bnx2x_credit_pool_obj *p,
1470                                uint8_t func_id,
1471                                uint8_t func_num);
1472void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
1473                                 struct bnx2x_credit_pool_obj *p,
1474                                 uint8_t func_id,
1475                                 uint8_t func_num);
1476
1477/****************** RSS CONFIGURATION ****************/
1478void bnx2x_init_rss_config_obj(struct bnx2x *bp,
1479                               struct bnx2x_rss_config_obj *rss_obj,
1480                               uint8_t cl_id, uint32_t cid, uint8_t func_id,
1481                               uint8_t engine_id,
1482                               void *rdata, dma_addr_t rdata_mapping,
1483                               int state, unsigned long *pstate,
1484                               bnx2x_obj_type type);
1485
1486/**
1487 * bnx2x_config_rss - Updates RSS configuration according to provided parameters
1488 *
1489 * Return: 0 in case of success
1490 */
1491int bnx2x_config_rss(struct bnx2x *bp,
1492                     struct bnx2x_config_rss_params *p);
1493
1494/**
1495 * bnx2x_get_rss_ind_table - Return the current ind_table configuration.
1496 *
1497 * @ind_table: buffer to fill with the current indirection
1498 *                  table content. Should be at least
1499 *                  T_ETH_INDIRECTION_TABLE_SIZE bytes long.
1500 */
1501void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
1502                             uint8_t *ind_table);
1503