akaros/kern/drivers/net/bnx2x/bnx2x_reg.h
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   1/* bnx2x_reg.h: Broadcom Everest network driver.
   2 *
   3 * Copyright (c) 2007-2013 Broadcom Corporation
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation.
   8 *
   9 * The registers description starts with the register Access type followed
  10 * by size in bits. For example [RW 32]. The access types are:
  11 * R  - Read only
  12 * RC - Clear on read
  13 * RW - Read/Write
  14 * ST - Statistics register (clear on read)
  15 * W  - Write only
  16 * WB - Wide bus register - the size is over 32 bits and it should be
  17 *      read/write in consecutive 32 bits accesses
  18 * WR - Write Clear (write 1 to clear the bit)
  19 *
  20 */
  21#pragma once
  22
  23#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR                        (0x1<<0)
  24#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS                (0x1<<2)
  25#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU               (0x1<<5)
  26#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT                (0x1<<3)
  27#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR                       (0x1<<4)
  28#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND                 (0x1<<1)
  29/* [RW 1] Initiate the ATC array - reset all the valid bits */
  30#define ATC_REG_ATC_INIT_ARRAY                                   0x1100b8
  31/* [R 1] ATC initalization done */
  32#define ATC_REG_ATC_INIT_DONE                                    0x1100bc
  33/* [RC 6] Interrupt register #0 read clear */
  34#define ATC_REG_ATC_INT_STS_CLR                                  0x1101c0
  35/* [RW 5] Parity mask register #0 read/write */
  36#define ATC_REG_ATC_PRTY_MASK                                    0x1101d8
  37/* [R 5] Parity register #0 read */
  38#define ATC_REG_ATC_PRTY_STS                                     0x1101cc
  39/* [RC 5] Parity register #0 read clear */
  40#define ATC_REG_ATC_PRTY_STS_CLR                                 0x1101d0
  41/* [RW 19] Interrupt mask register #0 read/write */
  42#define BRB1_REG_BRB1_INT_MASK                                   0x60128
  43/* [R 19] Interrupt register #0 read */
  44#define BRB1_REG_BRB1_INT_STS                                    0x6011c
  45/* [RW 4] Parity mask register #0 read/write */
  46#define BRB1_REG_BRB1_PRTY_MASK                                  0x60138
  47/* [R 4] Parity register #0 read */
  48#define BRB1_REG_BRB1_PRTY_STS                                   0x6012c
  49/* [RC 4] Parity register #0 read clear */
  50#define BRB1_REG_BRB1_PRTY_STS_CLR                               0x60130
  51/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
  52 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
  53 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
  54 * following reset the first rbc access to this reg must be write; there can
  55 * be no more rbc writes after the first one; there can be any number of rbc
  56 * read following the first write; rbc access not following these rules will
  57 * result in hang condition. */
  58#define BRB1_REG_FREE_LIST_PRS_CRDT                              0x60200
  59/* [RW 10] The number of free blocks below which the full signal to class 0
  60 * is asserted */
  61#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0                         0x601d0
  62#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1                         0x60230
  63/* [RW 11] The number of free blocks above which the full signal to class 0
  64 * is de-asserted */
  65#define BRB1_REG_FULL_0_XON_THRESHOLD_0                          0x601d4
  66#define BRB1_REG_FULL_0_XON_THRESHOLD_1                          0x60234
  67/* [RW 11] The number of free blocks below which the full signal to class 1
  68 * is asserted */
  69#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0                         0x601d8
  70#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1                         0x60238
  71/* [RW 11] The number of free blocks above which the full signal to class 1
  72 * is de-asserted */
  73#define BRB1_REG_FULL_1_XON_THRESHOLD_0                          0x601dc
  74#define BRB1_REG_FULL_1_XON_THRESHOLD_1                          0x6023c
  75/* [RW 11] The number of free blocks below which the full signal to the LB
  76 * port is asserted */
  77#define BRB1_REG_FULL_LB_XOFF_THRESHOLD                          0x601e0
  78/* [RW 10] The number of free blocks above which the full signal to the LB
  79 * port is de-asserted */
  80#define BRB1_REG_FULL_LB_XON_THRESHOLD                           0x601e4
  81/* [RW 10] The number of free blocks above which the High_llfc signal to
  82   interface #n is de-asserted. */
  83#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0                      0x6014c
  84/* [RW 10] The number of free blocks below which the High_llfc signal to
  85   interface #n is asserted. */
  86#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0                       0x6013c
  87/* [RW 11] The number of blocks guarantied for the LB port */
  88#define BRB1_REG_LB_GUARANTIED                                   0x601ec
  89/* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
  90 * before signaling XON. */
  91#define BRB1_REG_LB_GUARANTIED_HYST                              0x60264
  92/* [RW 24] LL RAM data. */
  93#define BRB1_REG_LL_RAM                                          0x61000
  94/* [RW 10] The number of free blocks above which the Low_llfc signal to
  95   interface #n is de-asserted. */
  96#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0                       0x6016c
  97/* [RW 10] The number of free blocks below which the Low_llfc signal to
  98   interface #n is asserted. */
  99#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0                        0x6015c
 100/* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
 101 * register is applicable only when per_class_guaranty_mode is set. */
 102#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED                        0x60244
 103/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
 104 * 1 before signaling XON. The register is applicable only when
 105 * per_class_guaranty_mode is set. */
 106#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST                   0x60254
 107/* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
 108 * register is applicable only when per_class_guaranty_mode is set. */
 109#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED                        0x60248
 110/* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
 111 * before signaling XON. The register is applicable only when
 112 * per_class_guaranty_mode is set. */
 113#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST                   0x60258
 114/* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
 115 * is applicable only when per_class_guaranty_mode is set. */
 116#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED                        0x6024c
 117/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
 118 * 1 before signaling XON. The register is applicable only when
 119 * per_class_guaranty_mode is set. */
 120#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST                   0x6025c
 121/* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The
 122 * register is applicable only when per_class_guaranty_mode is set. */
 123#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED                        0x60250
 124/* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC
 125 * 1 before signaling XON. The register is applicable only when
 126 * per_class_guaranty_mode is set. */
 127#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST                   0x60260
 128/* [RW 11] The number of blocks guarantied for the MAC port. The register is
 129 * applicable only when per_class_guaranty_mode is reset. */
 130#define BRB1_REG_MAC_GUARANTIED_0                                0x601e8
 131#define BRB1_REG_MAC_GUARANTIED_1                                0x60240
 132/* [R 24] The number of full blocks. */
 133#define BRB1_REG_NUM_OF_FULL_BLOCKS                              0x60090
 134/* [ST 32] The number of cycles that the write_full signal towards MAC #0
 135   was asserted. */
 136#define BRB1_REG_NUM_OF_FULL_CYCLES_0                            0x600c8
 137#define BRB1_REG_NUM_OF_FULL_CYCLES_1                            0x600cc
 138#define BRB1_REG_NUM_OF_FULL_CYCLES_4                            0x600d8
 139/* [ST 32] The number of cycles that the pause signal towards MAC #0 was
 140   asserted. */
 141#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0                           0x600b8
 142#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1                           0x600bc
 143/* [RW 10] The number of free blocks below which the pause signal to class 0
 144 * is asserted */
 145#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0                        0x601c0
 146#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1                        0x60220
 147/* [RW 11] The number of free blocks above which the pause signal to class 0
 148 * is de-asserted */
 149#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0                         0x601c4
 150#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1                         0x60224
 151/* [RW 11] The number of free blocks below which the pause signal to class 1
 152 * is asserted */
 153#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0                        0x601c8
 154#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1                        0x60228
 155/* [RW 11] The number of free blocks above which the pause signal to class 1
 156 * is de-asserted */
 157#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0                         0x601cc
 158#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1                         0x6022c
 159/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
 160#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0                          0x60078
 161#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1                          0x6007c
 162/* [RW 10] Write client 0: Assert pause threshold. */
 163#define BRB1_REG_PAUSE_LOW_THRESHOLD_0                           0x60068
 164/* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC
 165 * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC
 166 * mode). 1=per-class guaranty mode (new mode). */
 167#define BRB1_REG_PER_CLASS_GUARANTY_MODE                         0x60268
 168/* [R 24] The number of full blocks occpied by port. */
 169#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0                           0x60094
 170/* [RW 1] Reset the design by software. */
 171#define BRB1_REG_SOFT_RESET                                      0x600dc
 172/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
 173#define CCM_REG_CAM_OCCUP                                        0xd0188
 174/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
 175   acknowledge output is deasserted; all other signals are treated as usual;
 176   if 1 - normal activity. */
 177#define CCM_REG_CCM_CFC_IFEN                                     0xd003c
 178/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
 179   disregarded; valid is deasserted; all other signals are treated as usual;
 180   if 1 - normal activity. */
 181#define CCM_REG_CCM_CQM_IFEN                                     0xd000c
 182/* [RW 1] If set the Q index; received from the QM is inserted to event ID.
 183   Otherwise 0 is inserted. */
 184#define CCM_REG_CCM_CQM_USE_Q                                    0xd00c0
 185/* [RW 11] Interrupt mask register #0 read/write */
 186#define CCM_REG_CCM_INT_MASK                                     0xd01e4
 187/* [R 11] Interrupt register #0 read */
 188#define CCM_REG_CCM_INT_STS                                      0xd01d8
 189/* [RW 27] Parity mask register #0 read/write */
 190#define CCM_REG_CCM_PRTY_MASK                                    0xd01f4
 191/* [R 27] Parity register #0 read */
 192#define CCM_REG_CCM_PRTY_STS                                     0xd01e8
 193/* [RC 27] Parity register #0 read clear */
 194#define CCM_REG_CCM_PRTY_STS_CLR                                 0xd01ec
 195/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
 196   REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
 197   Is used to determine the number of the AG context REG-pairs written back;
 198   when the input message Reg1WbFlg isn't set. */
 199#define CCM_REG_CCM_REG0_SZ                                      0xd00c4
 200/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
 201   disregarded; valid is deasserted; all other signals are treated as usual;
 202   if 1 - normal activity. */
 203#define CCM_REG_CCM_STORM0_IFEN                                  0xd0004
 204/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
 205   disregarded; valid is deasserted; all other signals are treated as usual;
 206   if 1 - normal activity. */
 207#define CCM_REG_CCM_STORM1_IFEN                                  0xd0008
 208/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
 209   disregarded; valid output is deasserted; all other signals are treated as
 210   usual; if 1 - normal activity. */
 211#define CCM_REG_CDU_AG_RD_IFEN                                   0xd0030
 212/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
 213   are disregarded; all other signals are treated as usual; if 1 - normal
 214   activity. */
 215#define CCM_REG_CDU_AG_WR_IFEN                                   0xd002c
 216/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
 217   disregarded; valid output is deasserted; all other signals are treated as
 218   usual; if 1 - normal activity. */
 219#define CCM_REG_CDU_SM_RD_IFEN                                   0xd0038
 220/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
 221   input is disregarded; all other signals are treated as usual; if 1 -
 222   normal activity. */
 223#define CCM_REG_CDU_SM_WR_IFEN                                   0xd0034
 224/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
 225   the initial credit value; read returns the current value of the credit
 226   counter. Must be initialized to 1 at start-up. */
 227#define CCM_REG_CFC_INIT_CRD                                     0xd0204
 228/* [RW 2] Auxiliary counter flag Q number 1. */
 229#define CCM_REG_CNT_AUX1_Q                                       0xd00c8
 230/* [RW 2] Auxiliary counter flag Q number 2. */
 231#define CCM_REG_CNT_AUX2_Q                                       0xd00cc
 232/* [RW 28] The CM header value for QM request (primary). */
 233#define CCM_REG_CQM_CCM_HDR_P                                    0xd008c
 234/* [RW 28] The CM header value for QM request (secondary). */
 235#define CCM_REG_CQM_CCM_HDR_S                                    0xd0090
 236/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
 237   acknowledge output is deasserted; all other signals are treated as usual;
 238   if 1 - normal activity. */
 239#define CCM_REG_CQM_CCM_IFEN                                     0xd0014
 240/* [RW 6] QM output initial credit. Max credit available - 32. Write writes
 241   the initial credit value; read returns the current value of the credit
 242   counter. Must be initialized to 32 at start-up. */
 243#define CCM_REG_CQM_INIT_CRD                                     0xd020c
 244/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
 245   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
 246   prioritised); 2 stands for weight 2; tc. */
 247#define CCM_REG_CQM_P_WEIGHT                                     0xd00b8
 248/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
 249   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
 250   prioritised); 2 stands for weight 2; tc. */
 251#define CCM_REG_CQM_S_WEIGHT                                     0xd00bc
 252/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
 253   acknowledge output is deasserted; all other signals are treated as usual;
 254   if 1 - normal activity. */
 255#define CCM_REG_CSDM_IFEN                                        0xd0018
 256/* [RC 1] Set when the message length mismatch (relative to last indication)
 257   at the SDM interface is detected. */
 258#define CCM_REG_CSDM_LENGTH_MIS                                  0xd0170
 259/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
 260   weight 8 (the most prioritised); 1 stands for weight 1(least
 261   prioritised); 2 stands for weight 2; tc. */
 262#define CCM_REG_CSDM_WEIGHT                                      0xd00b4
 263/* [RW 28] The CM header for QM formatting in case of an error in the QM
 264   inputs. */
 265#define CCM_REG_ERR_CCM_HDR                                      0xd0094
 266/* [RW 8] The Event ID in case the input message ErrorFlg is set. */
 267#define CCM_REG_ERR_EVNT_ID                                      0xd0098
 268/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
 269   writes the initial credit value; read returns the current value of the
 270   credit counter. Must be initialized to 64 at start-up. */
 271#define CCM_REG_FIC0_INIT_CRD                                    0xd0210
 272/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
 273   writes the initial credit value; read returns the current value of the
 274   credit counter. Must be initialized to 64 at start-up. */
 275#define CCM_REG_FIC1_INIT_CRD                                    0xd0214
 276/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
 277   - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
 278   ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
 279   ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
 280   outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
 281#define CCM_REG_GR_ARB_TYPE                                      0xd015c
 282/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
 283   highest priority is 3. It is supposed; that the Store channel priority is
 284   the compliment to 4 of the rest priorities - Aggregation channel; Load
 285   (FIC0) channel and Load (FIC1). */
 286#define CCM_REG_GR_LD0_PR                                        0xd0164
 287/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
 288   highest priority is 3. It is supposed; that the Store channel priority is
 289   the compliment to 4 of the rest priorities - Aggregation channel; Load
 290   (FIC0) channel and Load (FIC1). */
 291#define CCM_REG_GR_LD1_PR                                        0xd0168
 292/* [RW 2] General flags index. */
 293#define CCM_REG_INV_DONE_Q                                       0xd0108
 294/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
 295   context and sent to STORM; for a specific connection type. The double
 296   REG-pairs are used in order to align to STORM context row size of 128
 297   bits. The offset of these data in the STORM context is always 0. Index
 298   _(0..15) stands for the connection type (one of 16). */
 299#define CCM_REG_N_SM_CTX_LD_0                                    0xd004c
 300#define CCM_REG_N_SM_CTX_LD_1                                    0xd0050
 301#define CCM_REG_N_SM_CTX_LD_2                                    0xd0054
 302#define CCM_REG_N_SM_CTX_LD_3                                    0xd0058
 303#define CCM_REG_N_SM_CTX_LD_4                                    0xd005c
 304/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
 305   acknowledge output is deasserted; all other signals are treated as usual;
 306   if 1 - normal activity. */
 307#define CCM_REG_PBF_IFEN                                         0xd0028
 308/* [RC 1] Set when the message length mismatch (relative to last indication)
 309   at the pbf interface is detected. */
 310#define CCM_REG_PBF_LENGTH_MIS                                   0xd0180
 311/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
 312   weight 8 (the most prioritised); 1 stands for weight 1(least
 313   prioritised); 2 stands for weight 2; tc. */
 314#define CCM_REG_PBF_WEIGHT                                       0xd00ac
 315#define CCM_REG_PHYS_QNUM1_0                                     0xd0134
 316#define CCM_REG_PHYS_QNUM1_1                                     0xd0138
 317#define CCM_REG_PHYS_QNUM2_0                                     0xd013c
 318#define CCM_REG_PHYS_QNUM2_1                                     0xd0140
 319#define CCM_REG_PHYS_QNUM3_0                                     0xd0144
 320#define CCM_REG_PHYS_QNUM3_1                                     0xd0148
 321#define CCM_REG_QOS_PHYS_QNUM0_0                                 0xd0114
 322#define CCM_REG_QOS_PHYS_QNUM0_1                                 0xd0118
 323#define CCM_REG_QOS_PHYS_QNUM1_0                                 0xd011c
 324#define CCM_REG_QOS_PHYS_QNUM1_1                                 0xd0120
 325#define CCM_REG_QOS_PHYS_QNUM2_0                                 0xd0124
 326#define CCM_REG_QOS_PHYS_QNUM2_1                                 0xd0128
 327#define CCM_REG_QOS_PHYS_QNUM3_0                                 0xd012c
 328#define CCM_REG_QOS_PHYS_QNUM3_1                                 0xd0130
 329/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
 330   disregarded; acknowledge output is deasserted; all other signals are
 331   treated as usual; if 1 - normal activity. */
 332#define CCM_REG_STORM_CCM_IFEN                                   0xd0010
 333/* [RC 1] Set when the message length mismatch (relative to last indication)
 334   at the STORM interface is detected. */
 335#define CCM_REG_STORM_LENGTH_MIS                                 0xd016c
 336/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
 337   mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
 338   weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
 339   tc. */
 340#define CCM_REG_STORM_WEIGHT                                     0xd009c
 341/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
 342   disregarded; acknowledge output is deasserted; all other signals are
 343   treated as usual; if 1 - normal activity. */
 344#define CCM_REG_TSEM_IFEN                                        0xd001c
 345/* [RC 1] Set when the message length mismatch (relative to last indication)
 346   at the tsem interface is detected. */
 347#define CCM_REG_TSEM_LENGTH_MIS                                  0xd0174
 348/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
 349   weight 8 (the most prioritised); 1 stands for weight 1(least
 350   prioritised); 2 stands for weight 2; tc. */
 351#define CCM_REG_TSEM_WEIGHT                                      0xd00a0
 352/* [RW 1] Input usem Interface enable. If 0 - the valid input is
 353   disregarded; acknowledge output is deasserted; all other signals are
 354   treated as usual; if 1 - normal activity. */
 355#define CCM_REG_USEM_IFEN                                        0xd0024
 356/* [RC 1] Set when message length mismatch (relative to last indication) at
 357   the usem interface is detected. */
 358#define CCM_REG_USEM_LENGTH_MIS                                  0xd017c
 359/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
 360   weight 8 (the most prioritised); 1 stands for weight 1(least
 361   prioritised); 2 stands for weight 2; tc. */
 362#define CCM_REG_USEM_WEIGHT                                      0xd00a8
 363/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
 364   disregarded; acknowledge output is deasserted; all other signals are
 365   treated as usual; if 1 - normal activity. */
 366#define CCM_REG_XSEM_IFEN                                        0xd0020
 367/* [RC 1] Set when the message length mismatch (relative to last indication)
 368   at the xsem interface is detected. */
 369#define CCM_REG_XSEM_LENGTH_MIS                                  0xd0178
 370/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
 371   weight 8 (the most prioritised); 1 stands for weight 1(least
 372   prioritised); 2 stands for weight 2; tc. */
 373#define CCM_REG_XSEM_WEIGHT                                      0xd00a4
 374/* [RW 19] Indirect access to the descriptor table of the XX protection
 375   mechanism. The fields are: [5:0] - message length; [12:6] - message
 376   pointer; 18:13] - next pointer. */
 377#define CCM_REG_XX_DESCR_TABLE                                   0xd0300
 378#define CCM_REG_XX_DESCR_TABLE_SIZE                              24
 379/* [R 7] Used to read the value of XX protection Free counter. */
 380#define CCM_REG_XX_FREE                                          0xd0184
 381/* [RW 6] Initial value for the credit counter; responsible for fulfilling
 382   of the Input Stage XX protection buffer by the XX protection pending
 383   messages. Max credit available - 127. Write writes the initial credit
 384   value; read returns the current value of the credit counter. Must be
 385   initialized to maximum XX protected message size - 2 at start-up. */
 386#define CCM_REG_XX_INIT_CRD                                      0xd0220
 387/* [RW 7] The maximum number of pending messages; which may be stored in XX
 388   protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
 389   At write comprises the start value of the ~ccm_registers_xx_free.xx_free
 390   counter. */
 391#define CCM_REG_XX_MSG_NUM                                       0xd0224
 392/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
 393#define CCM_REG_XX_OVFL_EVNT_ID                                  0xd0044
 394/* [RW 18] Indirect access to the XX table of the XX protection mechanism.
 395   The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
 396   header pointer. */
 397#define CCM_REG_XX_TABLE                                         0xd0280
 398#define CDU_REG_CDU_CHK_MASK0                                    0x101000
 399#define CDU_REG_CDU_CHK_MASK1                                    0x101004
 400#define CDU_REG_CDU_CONTROL0                                     0x101008
 401#define CDU_REG_CDU_DEBUG                                        0x101010
 402#define CDU_REG_CDU_GLOBAL_PARAMS                                0x101020
 403/* [RW 7] Interrupt mask register #0 read/write */
 404#define CDU_REG_CDU_INT_MASK                                     0x10103c
 405/* [R 7] Interrupt register #0 read */
 406#define CDU_REG_CDU_INT_STS                                      0x101030
 407/* [RW 5] Parity mask register #0 read/write */
 408#define CDU_REG_CDU_PRTY_MASK                                    0x10104c
 409/* [R 5] Parity register #0 read */
 410#define CDU_REG_CDU_PRTY_STS                                     0x101040
 411/* [RC 5] Parity register #0 read clear */
 412#define CDU_REG_CDU_PRTY_STS_CLR                                 0x101044
 413/* [RC 32] logging of error data in case of a CDU load error:
 414   {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
 415   ype_error; ctual_active; ctual_compressed_context}; */
 416#define CDU_REG_ERROR_DATA                                       0x101014
 417/* [WB 216] L1TT ram access. each entry has the following format :
 418   {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
 419   ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
 420#define CDU_REG_L1TT                                             0x101800
 421/* [WB 24] MATT ram access. each entry has the following
 422   format:{RegionLength[11:0]; egionOffset[11:0]} */
 423#define CDU_REG_MATT                                             0x101100
 424/* [RW 1] when this bit is set the CDU operates in e1hmf mode */
 425#define CDU_REG_MF_MODE                                          0x101050
 426/* [R 1] indication the initializing the activity counter by the hardware
 427   was done. */
 428#define CFC_REG_AC_INIT_DONE                                     0x104078
 429/* [RW 13] activity counter ram access */
 430#define CFC_REG_ACTIVITY_COUNTER                                 0x104400
 431#define CFC_REG_ACTIVITY_COUNTER_SIZE                            256
 432/* [R 1] indication the initializing the cams by the hardware was done. */
 433#define CFC_REG_CAM_INIT_DONE                                    0x10407c
 434/* [RW 2] Interrupt mask register #0 read/write */
 435#define CFC_REG_CFC_INT_MASK                                     0x104108
 436/* [R 2] Interrupt register #0 read */
 437#define CFC_REG_CFC_INT_STS                                      0x1040fc
 438/* [RC 2] Interrupt register #0 read clear */
 439#define CFC_REG_CFC_INT_STS_CLR                                  0x104100
 440/* [RW 4] Parity mask register #0 read/write */
 441#define CFC_REG_CFC_PRTY_MASK                                    0x104118
 442/* [R 4] Parity register #0 read */
 443#define CFC_REG_CFC_PRTY_STS                                     0x10410c
 444/* [RC 4] Parity register #0 read clear */
 445#define CFC_REG_CFC_PRTY_STS_CLR                                 0x104110
 446/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
 447#define CFC_REG_CID_CAM                                          0x104800
 448#define CFC_REG_CONTROL0                                         0x104028
 449#define CFC_REG_DEBUG0                                           0x104050
 450/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
 451   vector) whether the cfc should be disabled upon it */
 452#define CFC_REG_DISABLE_ON_ERROR                                 0x104044
 453/* [RC 14] CFC error vector. when the CFC detects an internal error it will
 454   set one of these bits. the bit description can be found in CFC
 455   specifications */
 456#define CFC_REG_ERROR_VECTOR                                     0x10403c
 457/* [WB 93] LCID info ram access */
 458#define CFC_REG_INFO_RAM                                         0x105000
 459#define CFC_REG_INFO_RAM_SIZE                                    1024
 460#define CFC_REG_INIT_REG                                         0x10404c
 461#define CFC_REG_INTERFACES                                       0x104058
 462/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
 463   field allows changing the priorities of the weighted-round-robin arbiter
 464   which selects which CFC load client should be served next */
 465#define CFC_REG_LCREQ_WEIGHTS                                    0x104084
 466/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
 467#define CFC_REG_LINK_LIST                                        0x104c00
 468#define CFC_REG_LINK_LIST_SIZE                                   256
 469/* [R 1] indication the initializing the link list by the hardware was done. */
 470#define CFC_REG_LL_INIT_DONE                                     0x104074
 471/* [R 9] Number of allocated LCIDs which are at empty state */
 472#define CFC_REG_NUM_LCIDS_ALLOC                                  0x104020
 473/* [R 9] Number of Arriving LCIDs in Link List Block */
 474#define CFC_REG_NUM_LCIDS_ARRIVING                               0x104004
 475#define CFC_REG_NUM_LCIDS_INSIDE_PF                              0x104120
 476/* [R 9] Number of Leaving LCIDs in Link List Block */
 477#define CFC_REG_NUM_LCIDS_LEAVING                                0x104018
 478#define CFC_REG_WEAK_ENABLE_PF                                   0x104124
 479/* [RW 8] The event id for aggregated interrupt 0 */
 480#define CSDM_REG_AGG_INT_EVENT_0                                 0xc2038
 481#define CSDM_REG_AGG_INT_EVENT_10                                0xc2060
 482#define CSDM_REG_AGG_INT_EVENT_11                                0xc2064
 483#define CSDM_REG_AGG_INT_EVENT_12                                0xc2068
 484#define CSDM_REG_AGG_INT_EVENT_13                                0xc206c
 485#define CSDM_REG_AGG_INT_EVENT_14                                0xc2070
 486#define CSDM_REG_AGG_INT_EVENT_15                                0xc2074
 487#define CSDM_REG_AGG_INT_EVENT_16                                0xc2078
 488#define CSDM_REG_AGG_INT_EVENT_2                                 0xc2040
 489#define CSDM_REG_AGG_INT_EVENT_3                                 0xc2044
 490#define CSDM_REG_AGG_INT_EVENT_4                                 0xc2048
 491#define CSDM_REG_AGG_INT_EVENT_5                                 0xc204c
 492#define CSDM_REG_AGG_INT_EVENT_6                                 0xc2050
 493#define CSDM_REG_AGG_INT_EVENT_7                                 0xc2054
 494#define CSDM_REG_AGG_INT_EVENT_8                                 0xc2058
 495#define CSDM_REG_AGG_INT_EVENT_9                                 0xc205c
 496/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
 497   or auto-mask-mode (1) */
 498#define CSDM_REG_AGG_INT_MODE_10                                 0xc21e0
 499#define CSDM_REG_AGG_INT_MODE_11                                 0xc21e4
 500#define CSDM_REG_AGG_INT_MODE_12                                 0xc21e8
 501#define CSDM_REG_AGG_INT_MODE_13                                 0xc21ec
 502#define CSDM_REG_AGG_INT_MODE_14                                 0xc21f0
 503#define CSDM_REG_AGG_INT_MODE_15                                 0xc21f4
 504#define CSDM_REG_AGG_INT_MODE_16                                 0xc21f8
 505#define CSDM_REG_AGG_INT_MODE_6                                  0xc21d0
 506#define CSDM_REG_AGG_INT_MODE_7                                  0xc21d4
 507#define CSDM_REG_AGG_INT_MODE_8                                  0xc21d8
 508#define CSDM_REG_AGG_INT_MODE_9                                  0xc21dc
 509/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
 510#define CSDM_REG_CFC_RSP_START_ADDR                              0xc2008
 511/* [RW 16] The maximum value of the completion counter #0 */
 512#define CSDM_REG_CMP_COUNTER_MAX0                                0xc201c
 513/* [RW 16] The maximum value of the completion counter #1 */
 514#define CSDM_REG_CMP_COUNTER_MAX1                                0xc2020
 515/* [RW 16] The maximum value of the completion counter #2 */
 516#define CSDM_REG_CMP_COUNTER_MAX2                                0xc2024
 517/* [RW 16] The maximum value of the completion counter #3 */
 518#define CSDM_REG_CMP_COUNTER_MAX3                                0xc2028
 519/* [RW 13] The start address in the internal RAM for the completion
 520   counters. */
 521#define CSDM_REG_CMP_COUNTER_START_ADDR                          0xc200c
 522/* [RW 32] Interrupt mask register #0 read/write */
 523#define CSDM_REG_CSDM_INT_MASK_0                                 0xc229c
 524#define CSDM_REG_CSDM_INT_MASK_1                                 0xc22ac
 525/* [R 32] Interrupt register #0 read */
 526#define CSDM_REG_CSDM_INT_STS_0                                  0xc2290
 527#define CSDM_REG_CSDM_INT_STS_1                                  0xc22a0
 528/* [RW 11] Parity mask register #0 read/write */
 529#define CSDM_REG_CSDM_PRTY_MASK                                  0xc22bc
 530/* [R 11] Parity register #0 read */
 531#define CSDM_REG_CSDM_PRTY_STS                                   0xc22b0
 532/* [RC 11] Parity register #0 read clear */
 533#define CSDM_REG_CSDM_PRTY_STS_CLR                               0xc22b4
 534#define CSDM_REG_ENABLE_IN1                                      0xc2238
 535#define CSDM_REG_ENABLE_IN2                                      0xc223c
 536#define CSDM_REG_ENABLE_OUT1                                     0xc2240
 537#define CSDM_REG_ENABLE_OUT2                                     0xc2244
 538/* [RW 4] The initial number of messages that can be sent to the pxp control
 539   interface without receiving any ACK. */
 540#define CSDM_REG_INIT_CREDIT_PXP_CTRL                            0xc24bc
 541/* [ST 32] The number of ACK after placement messages received */
 542#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE                          0xc227c
 543/* [ST 32] The number of packet end messages received from the parser */
 544#define CSDM_REG_NUM_OF_PKT_END_MSG                              0xc2274
 545/* [ST 32] The number of requests received from the pxp async if */
 546#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ                            0xc2278
 547/* [ST 32] The number of commands received in queue 0 */
 548#define CSDM_REG_NUM_OF_Q0_CMD                                   0xc2248
 549/* [ST 32] The number of commands received in queue 10 */
 550#define CSDM_REG_NUM_OF_Q10_CMD                                  0xc226c
 551/* [ST 32] The number of commands received in queue 11 */
 552#define CSDM_REG_NUM_OF_Q11_CMD                                  0xc2270
 553/* [ST 32] The number of commands received in queue 1 */
 554#define CSDM_REG_NUM_OF_Q1_CMD                                   0xc224c
 555/* [ST 32] The number of commands received in queue 3 */
 556#define CSDM_REG_NUM_OF_Q3_CMD                                   0xc2250
 557/* [ST 32] The number of commands received in queue 4 */
 558#define CSDM_REG_NUM_OF_Q4_CMD                                   0xc2254
 559/* [ST 32] The number of commands received in queue 5 */
 560#define CSDM_REG_NUM_OF_Q5_CMD                                   0xc2258
 561/* [ST 32] The number of commands received in queue 6 */
 562#define CSDM_REG_NUM_OF_Q6_CMD                                   0xc225c
 563/* [ST 32] The number of commands received in queue 7 */
 564#define CSDM_REG_NUM_OF_Q7_CMD                                   0xc2260
 565/* [ST 32] The number of commands received in queue 8 */
 566#define CSDM_REG_NUM_OF_Q8_CMD                                   0xc2264
 567/* [ST 32] The number of commands received in queue 9 */
 568#define CSDM_REG_NUM_OF_Q9_CMD                                   0xc2268
 569/* [RW 13] The start address in the internal RAM for queue counters */
 570#define CSDM_REG_Q_COUNTER_START_ADDR                            0xc2010
 571/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
 572#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY                        0xc2548
 573/* [R 1] parser fifo empty in sdm_sync block */
 574#define CSDM_REG_SYNC_PARSER_EMPTY                               0xc2550
 575/* [R 1] parser serial fifo empty in sdm_sync block */
 576#define CSDM_REG_SYNC_SYNC_EMPTY                                 0xc2558
 577/* [RW 32] Tick for timer counter. Applicable only when
 578   ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
 579#define CSDM_REG_TIMER_TICK                                      0xc2000
 580/* [RW 5] The number of time_slots in the arbitration cycle */
 581#define CSEM_REG_ARB_CYCLE_SIZE                                  0x200034
 582/* [RW 3] The source that is associated with arbitration element 0. Source
 583   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
 584   sleeping thread with priority 1; 4- sleeping thread with priority 2 */
 585#define CSEM_REG_ARB_ELEMENT0                                    0x200020
 586/* [RW 3] The source that is associated with arbitration element 1. Source
 587   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
 588   sleeping thread with priority 1; 4- sleeping thread with priority 2.
 589   Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
 590#define CSEM_REG_ARB_ELEMENT1                                    0x200024
 591/* [RW 3] The source that is associated with arbitration element 2. Source
 592   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
 593   sleeping thread with priority 1; 4- sleeping thread with priority 2.
 594   Could not be equal to register ~csem_registers_arb_element0.arb_element0
 595   and ~csem_registers_arb_element1.arb_element1 */
 596#define CSEM_REG_ARB_ELEMENT2                                    0x200028
 597/* [RW 3] The source that is associated with arbitration element 3. Source
 598   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
 599   sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
 600   not be equal to register ~csem_registers_arb_element0.arb_element0 and
 601   ~csem_registers_arb_element1.arb_element1 and
 602   ~csem_registers_arb_element2.arb_element2 */
 603#define CSEM_REG_ARB_ELEMENT3                                    0x20002c
 604/* [RW 3] The source that is associated with arbitration element 4. Source
 605   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
 606   sleeping thread with priority 1; 4- sleeping thread with priority 2.
 607   Could not be equal to register ~csem_registers_arb_element0.arb_element0
 608   and ~csem_registers_arb_element1.arb_element1 and
 609   ~csem_registers_arb_element2.arb_element2 and
 610   ~csem_registers_arb_element3.arb_element3 */
 611#define CSEM_REG_ARB_ELEMENT4                                    0x200030
 612/* [RW 32] Interrupt mask register #0 read/write */
 613#define CSEM_REG_CSEM_INT_MASK_0                                 0x200110
 614#define CSEM_REG_CSEM_INT_MASK_1                                 0x200120
 615/* [R 32] Interrupt register #0 read */
 616#define CSEM_REG_CSEM_INT_STS_0                                  0x200104
 617#define CSEM_REG_CSEM_INT_STS_1                                  0x200114
 618/* [RW 32] Parity mask register #0 read/write */
 619#define CSEM_REG_CSEM_PRTY_MASK_0                                0x200130
 620#define CSEM_REG_CSEM_PRTY_MASK_1                                0x200140
 621/* [R 32] Parity register #0 read */
 622#define CSEM_REG_CSEM_PRTY_STS_0                                 0x200124
 623#define CSEM_REG_CSEM_PRTY_STS_1                                 0x200134
 624/* [RC 32] Parity register #0 read clear */
 625#define CSEM_REG_CSEM_PRTY_STS_CLR_0                             0x200128
 626#define CSEM_REG_CSEM_PRTY_STS_CLR_1                             0x200138
 627#define CSEM_REG_ENABLE_IN                                       0x2000a4
 628#define CSEM_REG_ENABLE_OUT                                      0x2000a8
 629/* [RW 32] This address space contains all registers and memories that are
 630   placed in SEM_FAST block. The SEM_FAST registers are described in
 631   appendix B. In order to access the sem_fast registers the base address
 632   ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
 633#define CSEM_REG_FAST_MEMORY                                     0x220000
 634/* [RW 1] Disables input messages from FIC0 May be updated during run_time
 635   by the microcode */
 636#define CSEM_REG_FIC0_DISABLE                                    0x200224
 637/* [RW 1] Disables input messages from FIC1 May be updated during run_time
 638   by the microcode */
 639#define CSEM_REG_FIC1_DISABLE                                    0x200234
 640/* [RW 15] Interrupt table Read and write access to it is not possible in
 641   the middle of the work */
 642#define CSEM_REG_INT_TABLE                                       0x200400
 643/* [ST 24] Statistics register. The number of messages that entered through
 644   FIC0 */
 645#define CSEM_REG_MSG_NUM_FIC0                                    0x200000
 646/* [ST 24] Statistics register. The number of messages that entered through
 647   FIC1 */
 648#define CSEM_REG_MSG_NUM_FIC1                                    0x200004
 649/* [ST 24] Statistics register. The number of messages that were sent to
 650   FOC0 */
 651#define CSEM_REG_MSG_NUM_FOC0                                    0x200008
 652/* [ST 24] Statistics register. The number of messages that were sent to
 653   FOC1 */
 654#define CSEM_REG_MSG_NUM_FOC1                                    0x20000c
 655/* [ST 24] Statistics register. The number of messages that were sent to
 656   FOC2 */
 657#define CSEM_REG_MSG_NUM_FOC2                                    0x200010
 658/* [ST 24] Statistics register. The number of messages that were sent to
 659   FOC3 */
 660#define CSEM_REG_MSG_NUM_FOC3                                    0x200014
 661/* [RW 1] Disables input messages from the passive buffer May be updated
 662   during run_time by the microcode */
 663#define CSEM_REG_PAS_DISABLE                                     0x20024c
 664/* [WB 128] Debug only. Passive buffer memory */
 665#define CSEM_REG_PASSIVE_BUFFER                                  0x202000
 666/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
 667#define CSEM_REG_PRAM                                            0x240000
 668/* [R 16] Valid sleeping threads indication have bit per thread */
 669#define CSEM_REG_SLEEP_THREADS_VALID                             0x20026c
 670/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
 671#define CSEM_REG_SLOW_EXT_STORE_EMPTY                            0x2002a0
 672/* [RW 16] List of free threads . There is a bit per thread. */
 673#define CSEM_REG_THREADS_LIST                                    0x2002e4
 674/* [RW 3] The arbitration scheme of time_slot 0 */
 675#define CSEM_REG_TS_0_AS                                         0x200038
 676/* [RW 3] The arbitration scheme of time_slot 10 */
 677#define CSEM_REG_TS_10_AS                                        0x200060
 678/* [RW 3] The arbitration scheme of time_slot 11 */
 679#define CSEM_REG_TS_11_AS                                        0x200064
 680/* [RW 3] The arbitration scheme of time_slot 12 */
 681#define CSEM_REG_TS_12_AS                                        0x200068
 682/* [RW 3] The arbitration scheme of time_slot 13 */
 683#define CSEM_REG_TS_13_AS                                        0x20006c
 684/* [RW 3] The arbitration scheme of time_slot 14 */
 685#define CSEM_REG_TS_14_AS                                        0x200070
 686/* [RW 3] The arbitration scheme of time_slot 15 */
 687#define CSEM_REG_TS_15_AS                                        0x200074
 688/* [RW 3] The arbitration scheme of time_slot 16 */
 689#define CSEM_REG_TS_16_AS                                        0x200078
 690/* [RW 3] The arbitration scheme of time_slot 17 */
 691#define CSEM_REG_TS_17_AS                                        0x20007c
 692/* [RW 3] The arbitration scheme of time_slot 18 */
 693#define CSEM_REG_TS_18_AS                                        0x200080
 694/* [RW 3] The arbitration scheme of time_slot 1 */
 695#define CSEM_REG_TS_1_AS                                         0x20003c
 696/* [RW 3] The arbitration scheme of time_slot 2 */
 697#define CSEM_REG_TS_2_AS                                         0x200040
 698/* [RW 3] The arbitration scheme of time_slot 3 */
 699#define CSEM_REG_TS_3_AS                                         0x200044
 700/* [RW 3] The arbitration scheme of time_slot 4 */
 701#define CSEM_REG_TS_4_AS                                         0x200048
 702/* [RW 3] The arbitration scheme of time_slot 5 */
 703#define CSEM_REG_TS_5_AS                                         0x20004c
 704/* [RW 3] The arbitration scheme of time_slot 6 */
 705#define CSEM_REG_TS_6_AS                                         0x200050
 706/* [RW 3] The arbitration scheme of time_slot 7 */
 707#define CSEM_REG_TS_7_AS                                         0x200054
 708/* [RW 3] The arbitration scheme of time_slot 8 */
 709#define CSEM_REG_TS_8_AS                                         0x200058
 710/* [RW 3] The arbitration scheme of time_slot 9 */
 711#define CSEM_REG_TS_9_AS                                         0x20005c
 712/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
 713 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
 714#define CSEM_REG_VFPF_ERR_NUM                                    0x200380
 715/* [RW 1] Parity mask register #0 read/write */
 716#define DBG_REG_DBG_PRTY_MASK                                    0xc0a8
 717/* [R 1] Parity register #0 read */
 718#define DBG_REG_DBG_PRTY_STS                                     0xc09c
 719/* [RC 1] Parity register #0 read clear */
 720#define DBG_REG_DBG_PRTY_STS_CLR                                 0xc0a0
 721/* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
 722 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
 723 * 4.Completion function=0; 5.Error handling=0 */
 724#define DMAE_REG_BACKWARD_COMP_EN                                0x10207c
 725/* [RW 32] Commands memory. The address to command X; row Y is to calculated
 726   as 14*X+Y. */
 727#define DMAE_REG_CMD_MEM                                         0x102400
 728#define DMAE_REG_CMD_MEM_SIZE                                    224
 729/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
 730   initial value is all ones. */
 731#define DMAE_REG_CRC16C_INIT                                     0x10201c
 732/* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
 733   CRC-16 T10 initial value is all ones. */
 734#define DMAE_REG_CRC16T10_INIT                                   0x102020
 735/* [RW 2] Interrupt mask register #0 read/write */
 736#define DMAE_REG_DMAE_INT_MASK                                   0x102054
 737/* [RW 4] Parity mask register #0 read/write */
 738#define DMAE_REG_DMAE_PRTY_MASK                                  0x102064
 739/* [R 4] Parity register #0 read */
 740#define DMAE_REG_DMAE_PRTY_STS                                   0x102058
 741/* [RC 4] Parity register #0 read clear */
 742#define DMAE_REG_DMAE_PRTY_STS_CLR                               0x10205c
 743/* [RW 1] Command 0 go. */
 744#define DMAE_REG_GO_C0                                           0x102080
 745/* [RW 1] Command 1 go. */
 746#define DMAE_REG_GO_C1                                           0x102084
 747/* [RW 1] Command 10 go. */
 748#define DMAE_REG_GO_C10                                          0x102088
 749/* [RW 1] Command 11 go. */
 750#define DMAE_REG_GO_C11                                          0x10208c
 751/* [RW 1] Command 12 go. */
 752#define DMAE_REG_GO_C12                                          0x102090
 753/* [RW 1] Command 13 go. */
 754#define DMAE_REG_GO_C13                                          0x102094
 755/* [RW 1] Command 14 go. */
 756#define DMAE_REG_GO_C14                                          0x102098
 757/* [RW 1] Command 15 go. */
 758#define DMAE_REG_GO_C15                                          0x10209c
 759/* [RW 1] Command 2 go. */
 760#define DMAE_REG_GO_C2                                           0x1020a0
 761/* [RW 1] Command 3 go. */
 762#define DMAE_REG_GO_C3                                           0x1020a4
 763/* [RW 1] Command 4 go. */
 764#define DMAE_REG_GO_C4                                           0x1020a8
 765/* [RW 1] Command 5 go. */
 766#define DMAE_REG_GO_C5                                           0x1020ac
 767/* [RW 1] Command 6 go. */
 768#define DMAE_REG_GO_C6                                           0x1020b0
 769/* [RW 1] Command 7 go. */
 770#define DMAE_REG_GO_C7                                           0x1020b4
 771/* [RW 1] Command 8 go. */
 772#define DMAE_REG_GO_C8                                           0x1020b8
 773/* [RW 1] Command 9 go. */
 774#define DMAE_REG_GO_C9                                           0x1020bc
 775/* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
 776   input is disregarded; valid is deasserted; all other signals are treated
 777   as usual; if 1 - normal activity. */
 778#define DMAE_REG_GRC_IFEN                                        0x102008
 779/* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
 780   acknowledge input is disregarded; valid is deasserted; full is asserted;
 781   all other signals are treated as usual; if 1 - normal activity. */
 782#define DMAE_REG_PCI_IFEN                                        0x102004
 783/* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
 784   initial value to the credit counter; related to the address. Read returns
 785   the current value of the counter. */
 786#define DMAE_REG_PXP_REQ_INIT_CRD                                0x1020c0
 787/* [RW 8] Aggregation command. */
 788#define DORQ_REG_AGG_CMD0                                        0x170060
 789/* [RW 8] Aggregation command. */
 790#define DORQ_REG_AGG_CMD1                                        0x170064
 791/* [RW 8] Aggregation command. */
 792#define DORQ_REG_AGG_CMD2                                        0x170068
 793/* [RW 8] Aggregation command. */
 794#define DORQ_REG_AGG_CMD3                                        0x17006c
 795/* [RW 28] UCM Header. */
 796#define DORQ_REG_CMHEAD_RX                                       0x170050
 797/* [RW 32] Doorbell address for RBC doorbells (function 0). */
 798#define DORQ_REG_DB_ADDR0                                        0x17008c
 799/* [RW 5] Interrupt mask register #0 read/write */
 800#define DORQ_REG_DORQ_INT_MASK                                   0x170180
 801/* [R 5] Interrupt register #0 read */
 802#define DORQ_REG_DORQ_INT_STS                                    0x170174
 803/* [RC 5] Interrupt register #0 read clear */
 804#define DORQ_REG_DORQ_INT_STS_CLR                                0x170178
 805/* [RW 2] Parity mask register #0 read/write */
 806#define DORQ_REG_DORQ_PRTY_MASK                                  0x170190
 807/* [R 2] Parity register #0 read */
 808#define DORQ_REG_DORQ_PRTY_STS                                   0x170184
 809/* [RC 2] Parity register #0 read clear */
 810#define DORQ_REG_DORQ_PRTY_STS_CLR                               0x170188
 811/* [RW 8] The address to write the DPM CID to STORM. */
 812#define DORQ_REG_DPM_CID_ADDR                                    0x170044
 813/* [RW 5] The DPM mode CID extraction offset. */
 814#define DORQ_REG_DPM_CID_OFST                                    0x170030
 815/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
 816#define DORQ_REG_DQ_FIFO_AFULL_TH                                0x17007c
 817/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
 818#define DORQ_REG_DQ_FIFO_FULL_TH                                 0x170078
 819/* [R 13] Current value of the DQ FIFO fill level according to following
 820   pointer. The range is 0 - 256 FIFO rows; where each row stands for the
 821   doorbell. */
 822#define DORQ_REG_DQ_FILL_LVLF                                    0x1700a4
 823/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
 824   equal to full threshold; reset on full clear. */
 825#define DORQ_REG_DQ_FULL_ST                                      0x1700c0
 826/* [RW 28] The value sent to CM header in the case of CFC load error. */
 827#define DORQ_REG_ERR_CMHEAD                                      0x170058
 828#define DORQ_REG_IF_EN                                           0x170004
 829#define DORQ_REG_MAX_RVFID_SIZE                          0x1701ec
 830#define DORQ_REG_MODE_ACT                                        0x170008
 831/* [RW 5] The normal mode CID extraction offset. */
 832#define DORQ_REG_NORM_CID_OFST                                   0x17002c
 833/* [RW 28] TCM Header when only TCP context is loaded. */
 834#define DORQ_REG_NORM_CMHEAD_TX                                  0x17004c
 835/* [RW 3] The number of simultaneous outstanding requests to Context Fetch
 836   Interface. */
 837#define DORQ_REG_OUTST_REQ                                       0x17003c
 838#define DORQ_REG_PF_USAGE_CNT                                    0x1701d0
 839#define DORQ_REG_REGN                                            0x170038
 840/* [R 4] Current value of response A counter credit. Initial credit is
 841   configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
 842   register. */
 843#define DORQ_REG_RSPA_CRD_CNT                                    0x1700ac
 844/* [R 4] Current value of response B counter credit. Initial credit is
 845   configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
 846   register. */
 847#define DORQ_REG_RSPB_CRD_CNT                                    0x1700b0
 848/* [RW 4] The initial credit at the Doorbell Response Interface. The write
 849   writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
 850   read reads this written value. */
 851#define DORQ_REG_RSP_INIT_CRD                                    0x170048
 852#define DORQ_REG_RSPB_CRD_CNT                                    0x1700b0
 853#define DORQ_REG_VF_NORM_CID_BASE                                0x1701a0
 854#define DORQ_REG_VF_NORM_CID_OFST                                0x1701f4
 855#define DORQ_REG_VF_NORM_CID_WND_SIZE                            0x1701a4
 856#define DORQ_REG_VF_NORM_MAX_CID_COUNT                           0x1701e4
 857#define DORQ_REG_VF_NORM_VF_BASE                                 0x1701a8
 858/* [RW 10] VF type validation mask value */
 859#define DORQ_REG_VF_TYPE_MASK_0                                  0x170218
 860/* [RW 17] VF type validation Min MCID value */
 861#define DORQ_REG_VF_TYPE_MAX_MCID_0                              0x1702d8
 862/* [RW 17] VF type validation Max MCID value */
 863#define DORQ_REG_VF_TYPE_MIN_MCID_0                              0x170298
 864/* [RW 10] VF type validation comp value */
 865#define DORQ_REG_VF_TYPE_VALUE_0                                 0x170258
 866#define DORQ_REG_VF_USAGE_CT_LIMIT                               0x170340
 867
 868/* [RW 4] Initial activity counter value on the load request; when the
 869   shortcut is done. */
 870#define DORQ_REG_SHRT_ACT_CNT                                    0x170070
 871/* [RW 28] TCM Header when both ULP and TCP context is loaded. */
 872#define DORQ_REG_SHRT_CMHEAD                                     0x170054
 873#define HC_CONFIG_0_REG_ATTN_BIT_EN_0                            (0x1<<4)
 874#define HC_CONFIG_0_REG_BLOCK_DISABLE_0                          (0x1<<0)
 875#define HC_CONFIG_0_REG_INT_LINE_EN_0                            (0x1<<3)
 876#define HC_CONFIG_0_REG_MSI_ATTN_EN_0                            (0x1<<7)
 877#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0                        (0x1<<2)
 878#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0                          (0x1<<1)
 879#define HC_CONFIG_1_REG_BLOCK_DISABLE_1                          (0x1<<0)
 880#define DORQ_REG_VF_USAGE_CNT                                    0x170320
 881#define HC_REG_AGG_INT_0                                         0x108050
 882#define HC_REG_AGG_INT_1                                         0x108054
 883#define HC_REG_ATTN_BIT                                          0x108120
 884#define HC_REG_ATTN_IDX                                          0x108100
 885#define HC_REG_ATTN_MSG0_ADDR_L                                  0x108018
 886#define HC_REG_ATTN_MSG1_ADDR_L                                  0x108020
 887#define HC_REG_ATTN_NUM_P0                                       0x108038
 888#define HC_REG_ATTN_NUM_P1                                       0x10803c
 889#define HC_REG_COMMAND_REG                                       0x108180
 890#define HC_REG_CONFIG_0                                          0x108000
 891#define HC_REG_CONFIG_1                                          0x108004
 892#define HC_REG_FUNC_NUM_P0                                       0x1080ac
 893#define HC_REG_FUNC_NUM_P1                                       0x1080b0
 894/* [RW 3] Parity mask register #0 read/write */
 895#define HC_REG_HC_PRTY_MASK                                      0x1080a0
 896/* [R 3] Parity register #0 read */
 897#define HC_REG_HC_PRTY_STS                                       0x108094
 898/* [RC 3] Parity register #0 read clear */
 899#define HC_REG_HC_PRTY_STS_CLR                                   0x108098
 900#define HC_REG_INT_MASK                                          0x108108
 901#define HC_REG_LEADING_EDGE_0                                    0x108040
 902#define HC_REG_LEADING_EDGE_1                                    0x108048
 903#define HC_REG_MAIN_MEMORY                                       0x108800
 904#define HC_REG_MAIN_MEMORY_SIZE                                  152
 905#define HC_REG_P0_PROD_CONS                                      0x108200
 906#define HC_REG_P1_PROD_CONS                                      0x108400
 907#define HC_REG_PBA_COMMAND                                       0x108140
 908#define HC_REG_PCI_CONFIG_0                                      0x108010
 909#define HC_REG_PCI_CONFIG_1                                      0x108014
 910#define HC_REG_STATISTIC_COUNTERS                                0x109000
 911#define HC_REG_TRAILING_EDGE_0                                   0x108044
 912#define HC_REG_TRAILING_EDGE_1                                   0x10804c
 913#define HC_REG_UC_RAM_ADDR_0                                     0x108028
 914#define HC_REG_UC_RAM_ADDR_1                                     0x108030
 915#define HC_REG_USTORM_ADDR_FOR_COALESCE                          0x108068
 916#define HC_REG_VQID_0                                            0x108008
 917#define HC_REG_VQID_1                                            0x10800c
 918#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN             (0x1<<1)
 919#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE                 (0x1<<0)
 920#define IGU_REG_ATTENTION_ACK_BITS                               0x130108
 921/* [R 4] Debug: attn_fsm */
 922#define IGU_REG_ATTN_FSM                                         0x130054
 923#define IGU_REG_ATTN_MSG_ADDR_H                          0x13011c
 924#define IGU_REG_ATTN_MSG_ADDR_L                          0x130120
 925/* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
 926 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
 927 * write done didn't receive. */
 928#define IGU_REG_ATTN_WRITE_DONE_PENDING                  0x130030
 929#define IGU_REG_BLOCK_CONFIGURATION                              0x130000
 930#define IGU_REG_COMMAND_REG_32LSB_DATA                           0x130124
 931#define IGU_REG_COMMAND_REG_CTRL                                 0x13012c
 932/* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
 933 * is clear. The bits in this registers are set and clear via the producer
 934 * command. Data valid only in addresses 0-4. all the rest are zero. */
 935#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP                         0x130200
 936/* [R 5] Debug: ctrl_fsm */
 937#define IGU_REG_CTRL_FSM                                         0x130064
 938/* [R 1] data available for error memory. If this bit is clear do not red
 939 * from error_handling_memory. */
 940#define IGU_REG_ERROR_HANDLING_DATA_VALID                        0x130130
 941/* [RW 11] Parity mask register #0 read/write */
 942#define IGU_REG_IGU_PRTY_MASK                                    0x1300a8
 943/* [R 11] Parity register #0 read */
 944#define IGU_REG_IGU_PRTY_STS                                     0x13009c
 945/* [RC 11] Parity register #0 read clear */
 946#define IGU_REG_IGU_PRTY_STS_CLR                                 0x1300a0
 947/* [R 4] Debug: int_handle_fsm */
 948#define IGU_REG_INT_HANDLE_FSM                                   0x130050
 949#define IGU_REG_LEADING_EDGE_LATCH                               0x130134
 950/* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
 951 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
 952 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
 953#define IGU_REG_MAPPING_MEMORY                                   0x131000
 954#define IGU_REG_MAPPING_MEMORY_SIZE                              136
 955#define IGU_REG_PBA_STATUS_LSB                                   0x130138
 956#define IGU_REG_PBA_STATUS_MSB                                   0x13013c
 957#define IGU_REG_PCI_PF_MSI_EN                                    0x130140
 958#define IGU_REG_PCI_PF_MSIX_EN                                   0x130144
 959#define IGU_REG_PCI_PF_MSIX_FUNC_MASK                            0x130148
 960/* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
 961 * pending; 1 = pending. Pendings means interrupt was asserted; and write
 962 * done was not received. Data valid only in addresses 0-4. all the rest are
 963 * zero. */
 964#define IGU_REG_PENDING_BITS_STATUS                              0x130300
 965#define IGU_REG_PF_CONFIGURATION                                 0x130154
 966/* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
 967 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
 968 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
 969 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
 970 * - In backward compatible mode; for non default SB; each even line in the
 971 * memory holds the U producer and each odd line hold the C producer. The
 972 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
 973 * last 20 producers are for the DSB for each PF. each PF has five segments
 974 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
 975 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
 976#define IGU_REG_PROD_CONS_MEMORY                                 0x132000
 977/* [R 3] Debug: pxp_arb_fsm */
 978#define IGU_REG_PXP_ARB_FSM                                      0x130068
 979/* [RW 6] Write one for each bit will reset the appropriate memory. When the
 980 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
 981 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
 982 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
 983#define IGU_REG_RESET_MEMORIES                                   0x130158
 984/* [R 4] Debug: sb_ctrl_fsm */
 985#define IGU_REG_SB_CTRL_FSM                                      0x13004c
 986#define IGU_REG_SB_INT_BEFORE_MASK_LSB                           0x13015c
 987#define IGU_REG_SB_INT_BEFORE_MASK_MSB                           0x130160
 988#define IGU_REG_SB_MASK_LSB                                      0x130164
 989#define IGU_REG_SB_MASK_MSB                                      0x130168
 990/* [RW 16] Number of command that were dropped without causing an interrupt
 991 * due to: read access for WO BAR address; or write access for RO BAR
 992 * address or any access for reserved address or PCI function error is set
 993 * and address is not MSIX; PBA or cleanup */
 994#define IGU_REG_SILENT_DROP                                      0x13016c
 995/* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
 996 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
 997 * PF; 68-71 number of ATTN messages per PF */
 998#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT                       0x130800
 999/* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
1000 * timer mask command arrives. Value must be bigger than 100. */
1001#define IGU_REG_TIMER_MASKING_VALUE                              0x13003c
1002#define IGU_REG_TRAILING_EDGE_LATCH                              0x130104
1003#define IGU_REG_VF_CONFIGURATION                                 0x130170
1004/* [WB_R 32] Each bit represent write done pending bits status for that SB
1005 * (MSI/MSIX message was sent and write done was not received yet). 0 =
1006 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
1007#define IGU_REG_WRITE_DONE_PENDING                               0x130480
1008#define MCP_A_REG_MCPR_SCRATCH                                   0x3a0000
1009#define MCP_REG_MCPR_ACCESS_LOCK                                 0x8009c
1010#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER                         0x8501c
1011#define MCP_REG_MCPR_GP_INPUTS                                   0x800c0
1012#define MCP_REG_MCPR_GP_OENABLE                                  0x800c8
1013#define MCP_REG_MCPR_GP_OUTPUTS                                  0x800c4
1014#define MCP_REG_MCPR_IMC_COMMAND                                 0x85900
1015#define MCP_REG_MCPR_IMC_DATAREG0                                0x85920
1016#define MCP_REG_MCPR_IMC_SLAVE_CONTROL                           0x85904
1017#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER                         0x8501c
1018#define MCP_REG_MCPR_NVM_ACCESS_ENABLE                           0x86424
1019#define MCP_REG_MCPR_NVM_ADDR                                    0x8640c
1020#define MCP_REG_MCPR_NVM_CFG4                                    0x8642c
1021#define MCP_REG_MCPR_NVM_COMMAND                                 0x86400
1022#define MCP_REG_MCPR_NVM_READ                                    0x86410
1023#define MCP_REG_MCPR_NVM_SW_ARB                                  0x86420
1024#define MCP_REG_MCPR_NVM_WRITE                                   0x86408
1025#define MCP_REG_MCPR_SCRATCH                                     0xa0000
1026#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK             (0x1<<1)
1027#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK             (0x1<<0)
1028/* [R 32] read first 32 bit after inversion of function 0. mapped as
1029   follows: [0] NIG attention for function0; [1] NIG attention for
1030   function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
1031   [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
1032   GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
1033   glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
1034   [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
1035   MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
1036   Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
1037   interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
1038   error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
1039   interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
1040   Parity error; [31] PBF Hw interrupt; */
1041#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0                       0xa42c
1042#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1                       0xa430
1043/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
1044   NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1045   mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1046   [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1047   PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1048   function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1049   Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1050   mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1051   BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1052   Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1053   interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1054   Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1055   interrupt; */
1056#define MISC_REG_AEU_AFTER_INVERT_1_MCP                          0xa434
1057/* [R 32] read second 32 bit after inversion of function 0. mapped as
1058   follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1059   Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1060   interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1061   error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1062   interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1063   NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1064   [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1065   interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1066   Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1067   Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1068   Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1069   interrupt; */
1070#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0                       0xa438
1071#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1                       0xa43c
1072/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
1073   PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
1074   [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
1075   [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
1076   XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1077   DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1078   error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1079   PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1080   [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1081   [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1082   [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1083   [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1084#define MISC_REG_AEU_AFTER_INVERT_2_MCP                          0xa440
1085/* [R 32] read third 32 bit after inversion of function 0. mapped as
1086   follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
1087   error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
1088   PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1089   interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1090   error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1091   Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1092   pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1093   MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1094   SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1095   timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1096   func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1097   attn1; */
1098#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0                       0xa444
1099#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1                       0xa448
1100/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
1101   CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
1102   Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
1103   Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
1104   error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
1105   interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
1106   MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
1107   Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
1108   timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
1109   func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
1110   func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
1111   timers attn_4 func1; [30] General attn0; [31] General attn1; */
1112#define MISC_REG_AEU_AFTER_INVERT_3_MCP                          0xa44c
1113/* [R 32] read fourth 32 bit after inversion of function 0. mapped as
1114   follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1115   General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1116   [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1117   attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1118   [14] General attn16; [15] General attn17; [16] General attn18; [17]
1119   General attn19; [18] General attn20; [19] General attn21; [20] Main power
1120   interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1121   Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1122   Latched timeout attention; [27] GRC Latched reserved access attention;
1123   [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1124   Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1125#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0                       0xa450
1126#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1                       0xa454
1127/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
1128   General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
1129   [4] General attn6; [5] General attn7; [6] General attn8; [7] General
1130   attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
1131   General attn13; [12] General attn14; [13] General attn15; [14] General
1132   attn16; [15] General attn17; [16] General attn18; [17] General attn19;
1133   [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
1134   RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
1135   RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
1136   attention; [27] GRC Latched reserved access attention; [28] MCP Latched
1137   rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
1138   ump_tx_parity; [31] MCP Latched scpad_parity; */
1139#define MISC_REG_AEU_AFTER_INVERT_4_MCP                          0xa458
1140/* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
1141 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1142 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1143 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1144#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0                       0xa700
1145/* [W 14] write to this register results with the clear of the latched
1146   signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
1147   d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
1148   latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
1149   GRC Latched reserved access attention; one in d7 clears Latched
1150   rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
1151   Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
1152   ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
1153   pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
1154   from this register return zero */
1155#define MISC_REG_AEU_CLR_LATCH_SIGNAL                            0xa45c
1156/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1157   as follows: [0] NIG attention for function0; [1] NIG attention for
1158   function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1159   0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1160   GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1161   function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1162   Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1163   SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1164   indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1165   [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1166   SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1167   TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1168   TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1169#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0                        0xa06c
1170#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1                        0xa07c
1171#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2                        0xa08c
1172#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3                        0xa09c
1173#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5                        0xa0bc
1174#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6                        0xa0cc
1175#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7                        0xa0dc
1176/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
1177   as follows: [0] NIG attention for function0; [1] NIG attention for
1178   function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1179   1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1180   GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1181   function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1182   Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1183   SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
1184   indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1185   [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1186   SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1187   TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1188   TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1189#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0                        0xa10c
1190#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1                        0xa11c
1191#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2                        0xa12c
1192#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3                        0xa13c
1193#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5                        0xa15c
1194#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6                        0xa16c
1195#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7                        0xa17c
1196/* [RW 32] first 32b for enabling the output for close the gate nig. mapped
1197   as follows: [0] NIG attention for function0; [1] NIG attention for
1198   function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1199   0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1200   GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1201   function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1202   Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1203   SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1204   indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1205   [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1206   SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1207   TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1208   TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1209#define MISC_REG_AEU_ENABLE1_NIG_0                               0xa0ec
1210#define MISC_REG_AEU_ENABLE1_NIG_1                               0xa18c
1211/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
1212   as follows: [0] NIG attention for function0; [1] NIG attention for
1213   function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1214   0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1215   GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1216   function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1217   Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1218   SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1219   indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1220   [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1221   SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1222   TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1223   TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1224#define MISC_REG_AEU_ENABLE1_PXP_0                               0xa0fc
1225#define MISC_REG_AEU_ENABLE1_PXP_1                               0xa19c
1226/* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1227   as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1228   Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1229   interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1230   error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1231   interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1232   NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1233   [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1234   interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1235   Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1236   Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1237   Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1238   interrupt; */
1239#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0                        0xa070
1240#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1                        0xa080
1241/* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1242   as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1243   Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1244   interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1245   error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1246   interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1247   NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1248   [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1249   interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1250   Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1251   Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1252   Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1253   interrupt; */
1254#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0                        0xa110
1255#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1                        0xa120
1256/* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1257   as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1258   Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1259   interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1260   error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1261   interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1262   NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1263   [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1264   interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1265   Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1266   Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1267   Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1268   interrupt; */
1269#define MISC_REG_AEU_ENABLE2_NIG_0                               0xa0f0
1270#define MISC_REG_AEU_ENABLE2_NIG_1                               0xa190
1271/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1272   as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1273   Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1274   interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1275   error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1276   interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1277   NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1278   [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1279   interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1280   Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1281   Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1282   Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1283   interrupt; */
1284#define MISC_REG_AEU_ENABLE2_PXP_0                               0xa100
1285#define MISC_REG_AEU_ENABLE2_PXP_1                               0xa1a0
1286/* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1287   as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1288   Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1289   [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1290   interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1291   error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1292   Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1293   pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1294   MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1295   SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1296   timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1297   func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1298   attn1; */
1299#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0                        0xa074
1300#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1                        0xa084
1301/* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1302   as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1303   Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1304   [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1305   interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1306   error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1307   Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1308   pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1309   MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1310   SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1311   timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1312   func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1313   attn1; */
1314#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0                        0xa114
1315#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1                        0xa124
1316/* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1317   as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1318   Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1319   [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1320   interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1321   error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1322   Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1323   pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1324   MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1325   SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1326   timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1327   func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1328   attn1; */
1329#define MISC_REG_AEU_ENABLE3_NIG_0                               0xa0f4
1330#define MISC_REG_AEU_ENABLE3_NIG_1                               0xa194
1331/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1332   as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1333   Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1334   [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1335   interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1336   error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1337   Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1338   pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1339   MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1340   SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1341   timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1342   func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1343   attn1; */
1344#define MISC_REG_AEU_ENABLE3_PXP_0                               0xa104
1345#define MISC_REG_AEU_ENABLE3_PXP_1                               0xa1a4
1346/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1347   as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1348   General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1349   [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1350   attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1351   [14] General attn16; [15] General attn17; [16] General attn18; [17]
1352   General attn19; [18] General attn20; [19] General attn21; [20] Main power
1353   interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1354   Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1355   Latched timeout attention; [27] GRC Latched reserved access attention;
1356   [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1357   Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1358#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0                        0xa078
1359#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2                        0xa098
1360#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4                        0xa0b8
1361#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5                        0xa0c8
1362#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6                        0xa0d8
1363#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7                        0xa0e8
1364/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1365   as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1366   General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1367   [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1368   attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1369   [14] General attn16; [15] General attn17; [16] General attn18; [17]
1370   General attn19; [18] General attn20; [19] General attn21; [20] Main power
1371   interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1372   Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1373   Latched timeout attention; [27] GRC Latched reserved access attention;
1374   [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1375   Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1376#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0                        0xa118
1377#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2                        0xa138
1378#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4                        0xa158
1379#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5                        0xa168
1380#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6                        0xa178
1381#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7                        0xa188
1382/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1383   as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1384   General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1385   [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1386   attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1387   [14] General attn16; [15] General attn17; [16] General attn18; [17]
1388   General attn19; [18] General attn20; [19] General attn21; [20] Main power
1389   interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1390   Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1391   Latched timeout attention; [27] GRC Latched reserved access attention;
1392   [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1393   Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1394#define MISC_REG_AEU_ENABLE4_NIG_0                               0xa0f8
1395#define MISC_REG_AEU_ENABLE4_NIG_1                               0xa198
1396/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1397   as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1398   General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1399   [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1400   attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1401   [14] General attn16; [15] General attn17; [16] General attn18; [17]
1402   General attn19; [18] General attn20; [19] General attn21; [20] Main power
1403   interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1404   Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1405   Latched timeout attention; [27] GRC Latched reserved access attention;
1406   [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1407   Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1408#define MISC_REG_AEU_ENABLE4_PXP_0                               0xa108
1409#define MISC_REG_AEU_ENABLE4_PXP_1                               0xa1a8
1410/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
1411 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1412 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1413 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1414 * parity; [31-10] Reserved; */
1415#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0                        0xa688
1416/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped
1417 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1418 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1419 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1420 * parity; [31-10] Reserved; */
1421#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0                        0xa6b0
1422/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1423   128 bit vector */
1424#define MISC_REG_AEU_GENERAL_ATTN_0                              0xa000
1425#define MISC_REG_AEU_GENERAL_ATTN_1                              0xa004
1426#define MISC_REG_AEU_GENERAL_ATTN_10                             0xa028
1427#define MISC_REG_AEU_GENERAL_ATTN_11                             0xa02c
1428#define MISC_REG_AEU_GENERAL_ATTN_12                             0xa030
1429#define MISC_REG_AEU_GENERAL_ATTN_2                              0xa008
1430#define MISC_REG_AEU_GENERAL_ATTN_3                              0xa00c
1431#define MISC_REG_AEU_GENERAL_ATTN_4                              0xa010
1432#define MISC_REG_AEU_GENERAL_ATTN_5                              0xa014
1433#define MISC_REG_AEU_GENERAL_ATTN_6                              0xa018
1434#define MISC_REG_AEU_GENERAL_ATTN_7                              0xa01c
1435#define MISC_REG_AEU_GENERAL_ATTN_8                              0xa020
1436#define MISC_REG_AEU_GENERAL_ATTN_9                              0xa024
1437#define MISC_REG_AEU_GENERAL_MASK                                0xa61c
1438/* [RW 32] first 32b for inverting the input for function 0; for each bit:
1439   0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1440   function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1441   [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1442   [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1443   function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1444   Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1445   SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1446   for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1447   Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1448   interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1449   Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1450   Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1451#define MISC_REG_AEU_INVERTER_1_FUNC_0                           0xa22c
1452#define MISC_REG_AEU_INVERTER_1_FUNC_1                           0xa23c
1453/* [RW 32] second 32b for inverting the input for function 0; for each bit:
1454   0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1455   error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1456   interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1457   Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1458   interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1459   DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1460   error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1461   PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1462   [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1463   [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1464   [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1465   [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1466#define MISC_REG_AEU_INVERTER_2_FUNC_0                           0xa230
1467#define MISC_REG_AEU_INVERTER_2_FUNC_1                           0xa240
1468/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1469   [9:8] = raserved. Zero = mask; one = unmask */
1470#define MISC_REG_AEU_MASK_ATTN_FUNC_0                            0xa060
1471#define MISC_REG_AEU_MASK_ATTN_FUNC_1                            0xa064
1472/* [RW 1] If set a system kill occurred */
1473#define MISC_REG_AEU_SYS_KILL_OCCURRED                           0xa610
1474/* [RW 32] Represent the status of the input vector to the AEU when a system
1475   kill occurred. The register is reset in por reset. Mapped as follows: [0]
1476   NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1477   mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1478   [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1479   PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1480   function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1481   Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1482   mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1483   BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1484   Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1485   interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1486   Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1487   interrupt; */
1488#define MISC_REG_AEU_SYS_KILL_STATUS_0                           0xa600
1489#define MISC_REG_AEU_SYS_KILL_STATUS_1                           0xa604
1490#define MISC_REG_AEU_SYS_KILL_STATUS_2                           0xa608
1491#define MISC_REG_AEU_SYS_KILL_STATUS_3                           0xa60c
1492/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1493   Port. */
1494#define MISC_REG_BOND_ID                                         0xa400
1495/* [R 16] These bits indicate the part number for the chip. */
1496#define MISC_REG_CHIP_NUM                                        0xa408
1497/* [R 4] These bits indicate the base revision of the chip. This value
1498   starts at 0x0 for the A0 tape-out and increments by one for each
1499   all-layer tape-out. */
1500#define MISC_REG_CHIP_REV                                        0xa40c
1501/* [R 14] otp_misc_do[100:0] spare bits collection: 13:11-
1502 * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72];
1503 * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. */
1504#define MISC_REG_CHIP_TYPE                                       0xac60
1505#define MISC_REG_CHIP_TYPE_57811_MASK                            (1<<1)
1506#define MISC_REG_CPMU_LP_DR_ENABLE                               0xa858
1507/* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled
1508 * by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk
1509 * 25MHz. Reset on hard reset. */
1510#define MISC_REG_CPMU_LP_FW_ENABLE_P0                            0xa84c
1511/* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI
1512 * counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset. */
1513#define MISC_REG_CPMU_LP_IDLE_THR_P0                             0xa8a0
1514/* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that
1515 * the Vmain SM end state is disabled. When 0 indicates that the Vmain SM
1516 * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that
1517 * the FW command that all Queues are empty is disabled. When 0 indicates
1518 * that the FW command that all Queues are empty is enabled. [2] - FW Early
1519 * Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early
1520 * Exit command is disabled. When 0 indicates that the FW Early Exit command
1521 * is enabled. This bit applicable only in the EXIT Events Mask registers.
1522 * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication
1523 * is disabled. When 0 indicates that the PBF Request indication is enabled.
1524 * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF
1525 * Request indication is disabled. When 0 indicates that the Tx Other Than
1526 * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1
1527 * indicates that the RX EEE LPI Status indication is disabled. When 0
1528 * indicates that the RX EEE LPI Status indication is enabled. In the EXIT
1529 * Events Masks registers; this bit masks the falling edge detect of the LPI
1530 * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that
1531 * the Tx Pause indication is disabled. When 0 indicates that the Tx Pause
1532 * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the
1533 * BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY
1534 * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM
1535 * IDLE indication is disabled. When 0 indicates that the QM IDLE indication
1536 * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When
1537 * 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0
1538 * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1
1539 * Status Mask. When 1 indicates that the L1 Status indication from the PCIE
1540 * CORE is disabled. When 0 indicates that the RX EEE LPI Status indication
1541 * from the PCIE CORE is enabled. In the EXIT Events Masks registers; this
1542 * bit masks the falling edge detect of the L1 status (L1 is on - off). [11]
1543 * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE
1544 * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI
1545 * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1
1546 * indicates that the P0 EEE LPI REQ indication is disabled. When =0
1547 * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE
1548 * LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is
1549 * disabled. When =0 indicates that the P0 EEE LPI REQ indication is
1550 * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
1551 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
1552 * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1
1553 * REQ indication is disabled. When =0 indicates that the L1 indication is
1554 * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates
1555 * that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx
1556 * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status
1557 * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This
1558 * bit is applicable only in the EXIT Events Masks registers. [17] - L1
1559 * Status Edge Detect Mask. When =1 indicates that the L1 Status Falling
1560 * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off).
1561 * When =0 indicates that the L1 Status Falling Edge Detect indication from
1562 * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in
1563 * the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset. */
1564#define MISC_REG_CPMU_LP_MASK_ENT_P0                             0xa880
1565/* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates
1566 * that the Vmain SM end state is disabled. When 0 indicates that the Vmain
1567 * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates
1568 * that the FW command that all Queues are empty is disabled. When 0
1569 * indicates that the FW command that all Queues are empty is enabled. [2] -
1570 * FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW
1571 * Early Exit command is disabled. When 0 indicates that the FW Early Exit
1572 * command is enabled. This bit applicable only in the EXIT Events Mask
1573 * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request
1574 * indication is disabled. When 0 indicates that the PBF Request indication
1575 * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other
1576 * Than PBF Request indication is disabled. When 0 indicates that the Tx
1577 * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status
1578 * Mask. When 1 indicates that the RX EEE LPI Status indication is disabled.
1579 * When 0 indicates that the RX LPI Status indication is enabled. In the
1580 * EXIT Events Masks registers; this bit masks the falling edge detect of
1581 * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1
1582 * indicates that the Tx Pause indication is disabled. When 0 indicates that
1583 * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1
1584 * indicates that the BRB1 EMPTY indication is disabled. When 0 indicates
1585 * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1
1586 * indicates that the QM IDLE indication is disabled. When 0 indicates that
1587 * the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9]
1588 * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for
1589 * LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for
1590 * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1
1591 * Status indication from the PCIE CORE is disabled. When 0 indicates that
1592 * the RX EEE LPI Status indication from the PCIE CORE is enabled. In the
1593 * EXIT Events Masks registers; this bit masks the falling edge detect of
1594 * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When
1595 * =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When
1596 * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1
1597 * E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication
1598 * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is
1599 * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
1600 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
1601 * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates
1602 * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that
1603 * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1
1604 * indicates that the L1 REQ indication is disabled. When =0 indicates that
1605 * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask.
1606 * When =1 indicates that the RX EEE LPI Status Falling Edge Detect
1607 * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that
1608 * the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE
1609 * LPI is on - off). This bit is applicable only in the EXIT Events Masks
1610 * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the
1611 * L1 Status Falling Edge Detect indication from the PCIE CORE is disabled
1612 * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge
1613 * Detect indication from the PCIE CORE is enabled (L1 is on - off). This
1614 * bit is applicable only in the EXIT Events Masks registers.Clock 25MHz.
1615 * Reset on hard reset. */
1616#define MISC_REG_CPMU_LP_MASK_EXT_P0                             0xa888
1617/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
1618 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
1619 * register. Reset on hard reset. */
1620#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0                           0xa8b8
1621/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
1622 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
1623 * register. Reset on hard reset. */
1624#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1                           0xa8bc
1625/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1626   32 clients. Each client can be controlled by one driver only. One in each
1627   bit represent that this driver control the appropriate client (Ex: bit 5
1628   is set means this driver control client number 5). addr1 = set; addr0 =
1629   clear; read from both addresses will give the same result = status. write
1630   to address 1 will set a request to control all the clients that their
1631   appropriate bit (in the write command) is set. if the client is free (the
1632   appropriate bit in all the other drivers is clear) one will be written to
1633   that driver register; if the client isn't free the bit will remain zero.
1634   if the appropriate bit is set (the driver request to gain control on a
1635   client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1636   interrupt will be asserted). write to address 0 will set a request to
1637   free all the clients that their appropriate bit (in the write command) is
1638   set. if the appropriate bit is clear (the driver request to free a client
1639   it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1640   be asserted). */
1641#define MISC_REG_DRIVER_CONTROL_1                                0xa510
1642#define MISC_REG_DRIVER_CONTROL_7                                0xa3c8
1643/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1644   only. */
1645#define MISC_REG_E1HMF_MODE                                      0xa5f8
1646/* [R 1] Status of four port mode path swap input pin. */
1647#define MISC_REG_FOUR_PORT_PATH_SWAP                             0xa75c
1648/* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1649   the path_swap output is equal to 4 port mode path swap input pin; if it
1650   is 1 - the path_swap output is equal to bit[1] of this register; [1] -
1651   Overwrite value. If bit[0] of this register is 1 this is the value that
1652   receives the path_swap output. Reset on Hard reset. */
1653#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR                        0xa738
1654/* [R 1] Status of 4 port mode port swap input pin. */
1655#define MISC_REG_FOUR_PORT_PORT_SWAP                             0xa754
1656/* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1657   the port_swap output is equal to 4 port mode port swap input pin; if it
1658   is 1 - the port_swap output is equal to bit[1] of this register; [1] -
1659   Overwrite value. If bit[0] of this register is 1 this is the value that
1660   receives the port_swap output. Reset on Hard reset. */
1661#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR                        0xa734
1662/* [RW 32] Debug only: spare RW register reset by core reset */
1663#define MISC_REG_GENERIC_CR_0                                    0xa460
1664#define MISC_REG_GENERIC_CR_1                                    0xa464
1665/* [RW 32] Debug only: spare RW register reset by por reset */
1666#define MISC_REG_GENERIC_POR_1                                   0xa474
1667/* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
1668   use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
1669   can not be configured as an output. Each output has its output enable in
1670   the MCP register space; but this bit needs to be set to make use of that.
1671   Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
1672   set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
1673   When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
1674   the i/o to an output and will drive the TimeSync output. Bit[31:7]:
1675   spare. Global register. Reset by hard reset. */
1676#define MISC_REG_GEN_PURP_HWG                                    0xa9a0
1677/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1678   these bits is written as a '1'; the corresponding SPIO bit will turn off
1679   it's drivers and become an input. This is the reset state of all GPIO
1680   pins. The read value of these bits will be a '1' if that last command
1681   (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1682   [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1683   as a '1'; the corresponding GPIO bit will drive low. The read value of
1684   these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1685   this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1686   SET When any of these bits is written as a '1'; the corresponding GPIO
1687   bit will drive high (if it has that capability). The read value of these
1688   bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1689   bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1690   RO; These bits indicate the read value of each of the eight GPIO pins.
1691   This is the result value of the pin; not the drive value. Writing these
1692   bits will have not effect. */
1693#define MISC_REG_GPIO                                            0xa490
1694/* [RW 8] These bits enable the GPIO_INTs to signals event to the
1695   IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1696   p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1697   [7] p1_gpio_3; */
1698#define MISC_REG_GPIO_EVENT_EN                                   0xa2bc
1699/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1700   '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1701   This will acknowledge an interrupt on the falling edge of corresponding
1702   GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1703   Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1704   register. This will acknowledge an interrupt on the rising edge of
1705   corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1706   OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1707   value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1708   of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1709   interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1710   is '1'; then the interrupt is due to a high to low edge (reset value 0).
1711   [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1712   current GPIO interrupt state for each GPIO pin. This bit is cleared when
1713   the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1714   set when the GPIO input does not match the current value in #OLD_VALUE
1715   (reset value 0). */
1716#define MISC_REG_GPIO_INT                                        0xa494
1717/* [R 28] this field hold the last information that caused reserved
1718   attention. bits [19:0] - address; [22:20] function; [23] reserved;
1719   [27:24] the master that caused the attention - according to the following
1720   encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1721   dbu; 8 = dmae */
1722#define MISC_REG_GRC_RSV_ATTN                                    0xa3c0
1723/* [R 28] this field hold the last information that caused timeout
1724   attention. bits [19:0] - address; [22:20] function; [23] reserved;
1725   [27:24] the master that caused the attention - according to the following
1726   encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1727   dbu; 8 = dmae */
1728#define MISC_REG_GRC_TIMEOUT_ATTN                                0xa3c4
1729/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1730   access that does not finish within
1731   ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1732   cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1733   assert it attention output. */
1734#define MISC_REG_GRC_TIMEOUT_EN                                  0xa280
1735/* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1736   the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1737   111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1738   (reset value 001) Charge pump current control; 111 for 720u; 011 for
1739   600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1740   Global bias control; When bit 7 is high bias current will be 10 0gh; When
1741   bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1742   Pll_observe (reset value 010) Bits to control observability. bit 10 is
1743   for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1744   (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1745   and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1746   sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1747   internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1748   connected to RESET input directly. [15] capRetry_en (reset value 0)
1749   enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1750   value 0) bit to continuously monitor vco freq (inverted). [17]
1751   freqDetRestart_en (reset value 0) bit to enable restart when not freq
1752   locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1753   retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1754   0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1755   pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1756   (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1757   0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1758   bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1759   enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1760   capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1761   restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1762   register bits. */
1763#define MISC_REG_LCPLL_CTRL_1                                    0xa2a4
1764#define MISC_REG_LCPLL_CTRL_REG_2                                0xa2a8
1765/* [RW 1] LCPLL power down. Global register. Active High. Reset on POR
1766 * reset. */
1767#define MISC_REG_LCPLL_E40_PWRDWN                                0xaa74
1768/* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */
1769#define MISC_REG_LCPLL_E40_RESETB_ANA                            0xaa78
1770/* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR
1771 * reset. */
1772#define MISC_REG_LCPLL_E40_RESETB_DIG                            0xaa7c
1773/* [RW 4] Interrupt mask register #0 read/write */
1774#define MISC_REG_MISC_INT_MASK                                   0xa388
1775/* [RW 1] Parity mask register #0 read/write */
1776#define MISC_REG_MISC_PRTY_MASK                                  0xa398
1777/* [R 1] Parity register #0 read */
1778#define MISC_REG_MISC_PRTY_STS                                   0xa38c
1779/* [RC 1] Parity register #0 read clear */
1780#define MISC_REG_MISC_PRTY_STS_CLR                               0xa390
1781#define MISC_REG_NIG_WOL_P0                                      0xa270
1782#define MISC_REG_NIG_WOL_P1                                      0xa274
1783/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1784   assertion */
1785#define MISC_REG_PCIE_HOT_RESET                                  0xa618
1786/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1787   inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1788   divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1789   divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1790   divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1791   divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1792   freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1793   (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1794   1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1795   Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1796   value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1797   1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1798   [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1799   Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1800   testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1801   testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1802   testa_en (reset value 0); */
1803#define MISC_REG_PLL_STORM_CTRL_1                                0xa294
1804#define MISC_REG_PLL_STORM_CTRL_2                                0xa298
1805#define MISC_REG_PLL_STORM_CTRL_3                                0xa29c
1806#define MISC_REG_PLL_STORM_CTRL_4                                0xa2a0
1807/* [R 1] Status of 4 port mode enable input pin. */
1808#define MISC_REG_PORT4MODE_EN                                    0xa750
1809/* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1810 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1811 * the port4mode_en output is equal to bit[1] of this register; [1] -
1812 * Overwrite value. If bit[0] of this register is 1 this is the value that
1813 * receives the port4mode_en output . */
1814#define MISC_REG_PORT4MODE_EN_OVWR                               0xa720
1815/* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1816   write/read zero = the specific block is in reset; addr 0-wr- the write
1817   value will be written to the register; addr 1-set - one will be written
1818   to all the bits that have the value of one in the data written (bits that
1819   have the value of zero will not be change) ; addr 2-clear - zero will be
1820   written to all the bits that have the value of one in the data written
1821   (bits that have the value of zero will not be change); addr 3-ignore;
1822   read ignore from all addr except addr 00; inside order of the bits is:
1823   [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1824   [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1825   rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1826   [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1827   Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1828   rst_pxp_rq_rd_wr; 31:17] reserved */
1829#define MISC_REG_RESET_REG_1                                     0xa580
1830#define MISC_REG_RESET_REG_2                                     0xa590
1831/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1832   shared with the driver resides */
1833#define MISC_REG_SHARED_MEM_ADDR                                 0xa2b4
1834/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1835   the corresponding SPIO bit will turn off it's drivers and become an
1836   input. This is the reset state of all SPIO pins. The read value of these
1837   bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1838   bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1839   is written as a '1'; the corresponding SPIO bit will drive low. The read
1840   value of these bits will be a '1' if that last command (#SET; #CLR; or
1841#FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1842   these bits is written as a '1'; the corresponding SPIO bit will drive
1843   high (if it has that capability). The read value of these bits will be a
1844   '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1845   (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1846   each of the eight SPIO pins. This is the result value of the pin; not the
1847   drive value. Writing these bits will have not effect. Each 8 bits field
1848   is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1849   from VAUX. (This is an output pin only; the FLOAT field is not applicable
1850   for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1851   VAUX. (This is an output pin only; FLOAT field is not applicable for this
1852   pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1853   select VAUX supply. (This is an output pin only; it is not controlled by
1854   the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1855   field is not applicable for this pin; only the VALUE fields is relevant -
1856   it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1857   Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1858   device ID select; read by UMP firmware. */
1859#define MISC_REG_SPIO                                            0xa4fc
1860/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1861   according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1862   [7:0] reserved */
1863#define MISC_REG_SPIO_EVENT_EN                                   0xa2b8
1864/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1865   corresponding bit in the #OLD_VALUE register. This will acknowledge an
1866   interrupt on the falling edge of corresponding SPIO input (reset value
1867   0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1868   in the #OLD_VALUE register. This will acknowledge an interrupt on the
1869   rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1870   RO; These bits indicate the old value of the SPIO input value. When the
1871   ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1872   that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1873   to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1874   interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1875   RO; These bits indicate the current SPIO interrupt state for each SPIO
1876   pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1877   command bit is written. This bit is set when the SPIO input does not
1878   match the current value in #OLD_VALUE (reset value 0). */
1879#define MISC_REG_SPIO_INT                                        0xa500
1880/* [RW 32] reload value for counter 4 if reload; the value will be reload if
1881   the counter reached zero and the reload bit
1882   (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1883#define MISC_REG_SW_TIMER_RELOAD_VAL_4                           0xa2fc
1884/* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1885   in this register. address 0 - timer 1; address 1 - timer 2, ...  address 7 -
1886   timer 8 */
1887#define MISC_REG_SW_TIMER_VAL                                    0xa5c0
1888/* [R 1] Status of two port mode path swap input pin. */
1889#define MISC_REG_TWO_PORT_PATH_SWAP                              0xa758
1890/* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1891   path_swap output is equal to 2 port mode path swap input pin; if it is 1
1892   - the path_swap output is equal to bit[1] of this register; [1] -
1893   Overwrite value. If bit[0] of this register is 1 this is the value that
1894   receives the path_swap output. Reset on Hard reset. */
1895#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR                         0xa72c
1896/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1897   loaded; 0-prepare; -unprepare */
1898#define MISC_REG_UNPREPARED                                      0xa424
1899#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST      (0x1<<0)
1900#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST      (0x1<<1)
1901#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN    (0x1<<4)
1902#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST      (0x1<<2)
1903#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN       (0x1<<3)
1904/* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
1905 * not it is the recipient of the message on the MDIO interface. The value
1906 * is compared to the value on ctrl_md_devad. Drives output
1907 * misc_xgxs0_phy_addr. Global register. */
1908#define MISC_REG_WC0_CTRL_PHY_ADDR                               0xa9cc
1909#define MISC_REG_WC0_RESET                                       0xac30
1910/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
1911   side. This should be less than or equal to phy_port_mode; if some of the
1912   ports are not used. This enables reduction of frequency on the core side.
1913   This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
1914   Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
1915   input for the XMAC_MP core; and should be changed only while reset is
1916   held low. Reset on Hard reset. */
1917#define MISC_REG_XMAC_CORE_PORT_MODE                             0xa964
1918/* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
1919   Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
1920   01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
1921   XMAC_MP core; and should be changed only while reset is held low. Reset
1922   on Hard reset. */
1923#define MISC_REG_XMAC_PHY_PORT_MODE                              0xa960
1924/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1925 * Reads from this register will clear bits 31:0. */
1926#define MSTAT_REG_RX_STAT_GR64_LO                                0x200
1927/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
1928 * 31:0. Reads from this register will clear bits 31:0. */
1929#define MSTAT_REG_TX_STAT_GTXPOK_LO                              0
1930#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST      (0x1<<0)
1931#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST      (0x1<<1)
1932#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN    (0x1<<4)
1933#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST      (0x1<<2)
1934#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN       (0x1<<3)
1935#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN                  (0x1<<0)
1936#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN                  (0x1<<0)
1937#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT      (0x1<<0)
1938#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS    (0x1<<9)
1939#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G          (0x1<<15)
1940#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS      (0xf<<18)
1941/* [RW 1] Input enable for RX_BMAC0 IF */
1942#define NIG_REG_BMAC0_IN_EN                                      0x100ac
1943/* [RW 1] output enable for TX_BMAC0 IF */
1944#define NIG_REG_BMAC0_OUT_EN                                     0x100e0
1945/* [RW 1] output enable for TX BMAC pause port 0 IF */
1946#define NIG_REG_BMAC0_PAUSE_OUT_EN                               0x10110
1947/* [RW 1] output enable for RX_BMAC0_REGS IF */
1948#define NIG_REG_BMAC0_REGS_OUT_EN                                0x100e8
1949/* [RW 1] output enable for RX BRB1 port0 IF */
1950#define NIG_REG_BRB0_OUT_EN                                      0x100f8
1951/* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1952#define NIG_REG_BRB0_PAUSE_IN_EN                                 0x100c4
1953/* [RW 1] output enable for RX BRB1 port1 IF */
1954#define NIG_REG_BRB1_OUT_EN                                      0x100fc
1955/* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1956#define NIG_REG_BRB1_PAUSE_IN_EN                                 0x100c8
1957/* [RW 1] output enable for RX BRB1 LP IF */
1958#define NIG_REG_BRB_LB_OUT_EN                                    0x10100
1959/* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1960   error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1961   72:73]-vnic_num; 81:74]-sideband_info */
1962#define NIG_REG_DEBUG_PACKET_LB                                  0x10800
1963/* [RW 1] Input enable for TX Debug packet */
1964#define NIG_REG_EGRESS_DEBUG_IN_EN                               0x100dc
1965/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1966   packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1967   First packet may be deleted from the middle. And last packet will be
1968   always deleted till the end. */
1969#define NIG_REG_EGRESS_DRAIN0_MODE                               0x10060
1970/* [RW 1] Output enable to EMAC0 */
1971#define NIG_REG_EGRESS_EMAC0_OUT_EN                              0x10120
1972/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1973   to emac for port0; other way to bmac for port0 */
1974#define NIG_REG_EGRESS_EMAC0_PORT                                0x10058
1975/* [RW 1] Input enable for TX PBF user packet port0 IF */
1976#define NIG_REG_EGRESS_PBF0_IN_EN                                0x100cc
1977/* [RW 1] Input enable for TX PBF user packet port1 IF */
1978#define NIG_REG_EGRESS_PBF1_IN_EN                                0x100d0
1979/* [RW 1] Input enable for TX UMP management packet port0 IF */
1980#define NIG_REG_EGRESS_UMP0_IN_EN                                0x100d4
1981/* [RW 1] Input enable for RX_EMAC0 IF */
1982#define NIG_REG_EMAC0_IN_EN                                      0x100a4
1983/* [RW 1] output enable for TX EMAC pause port 0 IF */
1984#define NIG_REG_EMAC0_PAUSE_OUT_EN                               0x10118
1985/* [R 1] status from emac0. This bit is set when MDINT from either the
1986   EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1987   be cleared in the attached PHY device that is driving the MINT pin. */
1988#define NIG_REG_EMAC0_STATUS_MISC_MI_INT                         0x10494
1989/* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1990   are described in appendix A. In order to access the BMAC0 registers; the
1991   base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1992   added to each BMAC register offset */
1993#define NIG_REG_INGRESS_BMAC0_MEM                                0x10c00
1994/* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1995   are described in appendix A. In order to access the BMAC0 registers; the
1996   base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1997   added to each BMAC register offset */
1998#define NIG_REG_INGRESS_BMAC1_MEM                                0x11000
1999/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
2000#define NIG_REG_INGRESS_EOP_LB_EMPTY                             0x104e0
2001/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
2002   packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
2003#define NIG_REG_INGRESS_EOP_LB_FIFO                              0x104e4
2004/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
2005   logic for interrupts must be used. Enable per bit of interrupt of
2006   ~latch_status.latch_status */
2007#define NIG_REG_LATCH_BC_0                                       0x16210
2008/* [RW 27] Latch for each interrupt from Unicore.b[0]
2009   status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
2010   b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
2011   b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
2012   b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
2013   b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
2014   b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
2015   b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
2016   b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
2017   b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
2018   b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
2019   b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
2020   b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
2021#define NIG_REG_LATCH_STATUS_0                                   0x18000
2022/* [RW 1] led 10g for port 0 */
2023#define NIG_REG_LED_10G_P0                                       0x10320
2024/* [RW 1] led 10g for port 1 */
2025#define NIG_REG_LED_10G_P1                                       0x10324
2026/* [RW 1] Port0: This bit is set to enable the use of the
2027   ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
2028   defined below. If this bit is cleared; then the blink rate will be about
2029   8Hz. */
2030#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0                    0x10318
2031/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
2032   Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
2033   is reset to 0x080; giving a default blink period of approximately 8Hz. */
2034#define NIG_REG_LED_CONTROL_BLINK_RATE_P0                        0x10310
2035/* [RW 1] Port0: If set along with the
2036 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
2037   bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
2038   bit; the Traffic LED will blink with the blink rate specified in
2039   ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
2040   ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
2041   fields. */
2042#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0                     0x10308
2043/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
2044   Traffic LED will then be controlled via bit ~nig_registers_
2045   led_control_traffic_p0.led_control_traffic_p0 and bit
2046   ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
2047#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0                  0x102f8
2048/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
2049   turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
2050   set; the LED will blink with blink rate specified in
2051   ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
2052   ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
2053   fields. */
2054#define NIG_REG_LED_CONTROL_TRAFFIC_P0                           0x10300
2055/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
2056   9-11PHY7; 12 MAC4; 13-15 PHY10; */
2057#define NIG_REG_LED_MODE_P0                                      0x102f0
2058/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
2059   tsdm enable; b2- usdm enable */
2060#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0                         0x16070
2061#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1                         0x16074
2062/* [RW 1] SAFC enable for port0. This register may get 1 only when
2063   ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
2064   port */
2065#define NIG_REG_LLFC_ENABLE_0                                    0x16208
2066#define NIG_REG_LLFC_ENABLE_1                                    0x1620c
2067/* [RW 16] classes are high-priority for port0 */
2068#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0                     0x16058
2069#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1                     0x1605c
2070/* [RW 16] classes are low-priority for port0 */
2071#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0                      0x16060
2072#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1                      0x16064
2073/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
2074#define NIG_REG_LLFC_OUT_EN_0                                    0x160c8
2075#define NIG_REG_LLFC_OUT_EN_1                                    0x160cc
2076#define NIG_REG_LLH0_ACPI_PAT_0_CRC                              0x1015c
2077#define NIG_REG_LLH0_ACPI_PAT_6_LEN                              0x10154
2078#define NIG_REG_LLH0_BRB1_DRV_MASK                               0x10244
2079#define NIG_REG_LLH0_BRB1_DRV_MASK_MF                            0x16048
2080/* [RW 1] send to BRB1 if no match on any of RMP rules. */
2081#define NIG_REG_LLH0_BRB1_NOT_MCP                                0x1025c
2082/* [RW 2] Determine the classification participants. 0: no classification.1:
2083   classification upon VLAN id. 2: classification upon MAC address. 3:
2084   classification upon both VLAN id & MAC addr. */
2085#define NIG_REG_LLH0_CLS_TYPE                                    0x16080
2086/* [RW 32] cm header for llh0 */
2087#define NIG_REG_LLH0_CM_HEADER                                   0x1007c
2088#define NIG_REG_LLH0_DEST_IP_0_1                                 0x101dc
2089#define NIG_REG_LLH0_DEST_MAC_0_0                                0x101c0
2090/* [RW 16] destination TCP address 1. The LLH will look for this address in
2091   all incoming packets. */
2092#define NIG_REG_LLH0_DEST_TCP_0                                  0x10220
2093/* [RW 16] destination UDP address 1 The LLH will look for this address in
2094   all incoming packets. */
2095#define NIG_REG_LLH0_DEST_UDP_0                                  0x10214
2096#define NIG_REG_LLH0_ERROR_MASK                                  0x1008c
2097/* [RW 8] event id for llh0 */
2098#define NIG_REG_LLH0_EVENT_ID                                    0x10084
2099#define NIG_REG_LLH0_FUNC_EN                                     0x160fc
2100#define NIG_REG_LLH0_FUNC_MEM                                    0x16180
2101#define NIG_REG_LLH0_FUNC_MEM_ENABLE                             0x16140
2102#define NIG_REG_LLH0_FUNC_VLAN_ID                                0x16100
2103/* [RW 1] Determine the IP version to look for in
2104   ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
2105#define NIG_REG_LLH0_IPV4_IPV6_0                                 0x10208
2106/* [RW 1] t bit for llh0 */
2107#define NIG_REG_LLH0_T_BIT                                       0x10074
2108/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
2109#define NIG_REG_LLH0_VLAN_ID_0                                   0x1022c
2110/* [RW 8] init credit counter for port0 in LLH */
2111#define NIG_REG_LLH0_XCM_INIT_CREDIT                             0x10554
2112#define NIG_REG_LLH0_XCM_MASK                                    0x10130
2113#define NIG_REG_LLH1_BRB1_DRV_MASK                               0x10248
2114/* [RW 1] send to BRB1 if no match on any of RMP rules. */
2115#define NIG_REG_LLH1_BRB1_NOT_MCP                                0x102dc
2116/* [RW 2] Determine the classification participants. 0: no classification.1:
2117   classification upon VLAN id. 2: classification upon MAC address. 3:
2118   classification upon both VLAN id & MAC addr. */
2119#define NIG_REG_LLH1_CLS_TYPE                                    0x16084
2120/* [RW 32] cm header for llh1 */
2121#define NIG_REG_LLH1_CM_HEADER                                   0x10080
2122#define NIG_REG_LLH1_ERROR_MASK                                  0x10090
2123/* [RW 8] event id for llh1 */
2124#define NIG_REG_LLH1_EVENT_ID                                    0x10088
2125#define NIG_REG_LLH1_FUNC_EN                                     0x16104
2126#define NIG_REG_LLH1_FUNC_MEM                                    0x161c0
2127#define NIG_REG_LLH1_FUNC_MEM_ENABLE                             0x16160
2128#define NIG_REG_LLH1_FUNC_MEM_SIZE                               16
2129/* [RW 1] When this bit is set; the LLH will classify the packet before
2130 * sending it to the BRB or calculating WoL on it. This bit controls port 1
2131 * only. The legacy llh_multi_function_mode bit controls port 0. */
2132#define NIG_REG_LLH1_MF_MODE                                     0x18614
2133/* [RW 8] init credit counter for port1 in LLH */
2134#define NIG_REG_LLH1_XCM_INIT_CREDIT                             0x10564
2135#define NIG_REG_LLH1_XCM_MASK                                    0x10134
2136/* [RW 1] When this bit is set; the LLH will expect all packets to be with
2137   e1hov */
2138#define NIG_REG_LLH_E1HOV_MODE                                   0x160d8
2139/* [RW 1] When this bit is set; the LLH will classify the packet before
2140   sending it to the BRB or calculating WoL on it. */
2141#define NIG_REG_LLH_MF_MODE                                      0x16024
2142#define NIG_REG_MASK_INTERRUPT_PORT0                             0x10330
2143#define NIG_REG_MASK_INTERRUPT_PORT1                             0x10334
2144/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
2145#define NIG_REG_NIG_EMAC0_EN                                     0x1003c
2146/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
2147#define NIG_REG_NIG_EMAC1_EN                                     0x10040
2148/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
2149   EMAC0 to strip the CRC from the ingress packets. */
2150#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC                         0x10044
2151/* [R 32] Interrupt register #0 read */
2152#define NIG_REG_NIG_INT_STS_0                                    0x103b0
2153#define NIG_REG_NIG_INT_STS_1                                    0x103c0
2154/* [RC 32] Interrupt register #0 read clear */
2155#define NIG_REG_NIG_INT_STS_CLR_0                                0x103b4
2156/* [R 32] Legacy E1 and E1H location for parity error mask register. */
2157#define NIG_REG_NIG_PRTY_MASK                                    0x103dc
2158/* [RW 32] Parity mask register #0 read/write */
2159#define NIG_REG_NIG_PRTY_MASK_0                                  0x183c8
2160#define NIG_REG_NIG_PRTY_MASK_1                                  0x183d8
2161/* [R 32] Legacy E1 and E1H location for parity error status register. */
2162#define NIG_REG_NIG_PRTY_STS                                     0x103d0
2163/* [R 32] Parity register #0 read */
2164#define NIG_REG_NIG_PRTY_STS_0                                   0x183bc
2165#define NIG_REG_NIG_PRTY_STS_1                                   0x183cc
2166/* [R 32] Legacy E1 and E1H location for parity error status clear register. */
2167#define NIG_REG_NIG_PRTY_STS_CLR                                 0x103d4
2168/* [RC 32] Parity register #0 read clear */
2169#define NIG_REG_NIG_PRTY_STS_CLR_0                               0x183c0
2170#define NIG_REG_NIG_PRTY_STS_CLR_1                               0x183d0
2171#define MCPR_IMC_COMMAND_ENABLE                                  (1L<<31)
2172#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT                     16
2173#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT                      28
2174#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT               8
2175/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2176 * Ethernet header. */
2177#define NIG_REG_P0_HDRS_AFTER_BASIC                              0x18038
2178/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
2179 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
2180 * disabled when this bit is set. */
2181#define NIG_REG_P0_HWPFC_ENABLE                          0x18078
2182#define NIG_REG_P0_LLH_FUNC_MEM2                                 0x18480
2183#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE                  0x18440
2184/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
2185 * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
2186 * indicates the validity of the data in the buffer. Writing a 1 to bit 16
2187 * will clear the buffer.
2188 */
2189#define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID                        0x1875c
2190/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2191 * the host. This location returns the lower 32 bits of timestamp value.
2192 */
2193#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB                       0x18754
2194/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2195 * the host. This location returns the upper 32 bits of timestamp value.
2196 */
2197#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB                       0x18758
2198/* [RW 11] Mask register for the various parameters used in determining PTP
2199 * packet presence. Set each bit to 1 to mask out the particular parameter.
2200 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2201 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2202 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2203 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2204 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2205 * MAC DA 2. The reset default is set to mask out all parameters.
2206 */
2207#define NIG_REG_P0_LLH_PTP_PARAM_MASK                            0x187a0
2208/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
2209 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2210 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2211 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2212 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2213 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2214 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2215 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
2216 * packets only and require that the packet is IPv4 for the rules to match.
2217 * Note that rules 4-7 are for IPv6 packets only and require that the packet
2218 * is IPv6 for the rules to match.
2219 */
2220#define NIG_REG_P0_LLH_PTP_RULE_MASK                             0x187a4
2221/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
2222#define NIG_REG_P0_LLH_PTP_TO_HOST                               0x187ac
2223/* [RW 1] Input enable for RX MAC interface. */
2224#define NIG_REG_P0_MAC_IN_EN                                     0x185ac
2225/* [RW 1] Output enable for TX MAC interface */
2226#define NIG_REG_P0_MAC_OUT_EN                                    0x185b0
2227/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2228#define NIG_REG_P0_MAC_PAUSE_OUT_EN                              0x185b4
2229/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2230 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2231 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2232 * priority field is extracted from the outer-most VLAN in receive packet.
2233 * Only COS 0 and COS 1 are supported in E2. */
2234#define NIG_REG_P0_PKT_PRIORITY_TO_COS                           0x18054
2235/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
2236 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
2237 * V1 frame format in timesync event detection on RX side. Bit 2 enables V2
2238 * frame format in timesync event detection on RX side. Bit 3 enables
2239 * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
2240 * detection on TX side. Bit 5 enables V2 frame format in timesync event
2241 * detection on TX side. Note that for HW to detect PTP packet and extract
2242 * data from the packet, at least one of the version bits of that traffic
2243 * direction has to be enabled.
2244 */
2245#define NIG_REG_P0_PTP_EN                                        0x18788
2246/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2247 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2248 * than one bit may be set; allowing multiple priorities to be mapped to one
2249 * COS. */
2250#define NIG_REG_P0_RX_COS0_PRIORITY_MASK                         0x18058
2251/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2252 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2253 * than one bit may be set; allowing multiple priorities to be mapped to one
2254 * COS. */
2255#define NIG_REG_P0_RX_COS1_PRIORITY_MASK                         0x1805c
2256/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2257 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2258 * than one bit may be set; allowing multiple priorities to be mapped to one
2259 * COS. */
2260#define NIG_REG_P0_RX_COS2_PRIORITY_MASK                         0x186b0
2261/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
2262 * priority is mapped to COS 3 when the corresponding mask bit is 1. More
2263 * than one bit may be set; allowing multiple priorities to be mapped to one
2264 * COS. */
2265#define NIG_REG_P0_RX_COS3_PRIORITY_MASK                         0x186b4
2266/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
2267 * priority is mapped to COS 4 when the corresponding mask bit is 1. More
2268 * than one bit may be set; allowing multiple priorities to be mapped to one
2269 * COS. */
2270#define NIG_REG_P0_RX_COS4_PRIORITY_MASK                         0x186b8
2271/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
2272 * priority is mapped to COS 5 when the corresponding mask bit is 1. More
2273 * than one bit may be set; allowing multiple priorities to be mapped to one
2274 * COS. */
2275#define NIG_REG_P0_RX_COS5_PRIORITY_MASK                         0x186bc
2276/* [R 1] RX FIFO for receiving data from MAC is empty. */
2277/* [RW 15] Specify which of the credit registers the client is to be mapped
2278 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
2279 * clients that are not subject to WFQ credit blocking - their
2280 * specifications here are not used. */
2281#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP                      0x180f0
2282/* [RW 32] Specify which of the credit registers the client is to be mapped
2283 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2284 * for client 0; bits [35:32] are for client 8. For clients that are not
2285 * subject to WFQ credit blocking - their specifications here are not used.
2286 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2287 * input clients to ETS arbiter. The reset default is set for management and
2288 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2289 * use credit registers 0-5 respectively (0x543210876). Note that credit
2290 * registers can not be shared between clients. */
2291#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB                 0x18688
2292/* [RW 4] Specify which of the credit registers the client is to be mapped
2293 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2294 * for client 0; bits [35:32] are for client 8. For clients that are not
2295 * subject to WFQ credit blocking - their specifications here are not used.
2296 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2297 * input clients to ETS arbiter. The reset default is set for management and
2298 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2299 * use credit registers 0-5 respectively (0x543210876). Note that credit
2300 * registers can not be shared between clients. */
2301#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB                 0x1868c
2302/* [RW 5] Specify whether the client competes directly in the strict
2303 * priority arbiter. The bits are mapped according to client ID (client IDs
2304 * are defined in tx_arb_priority_client). Default value is set to enable
2305 * strict priorities for clients 0-2 -- management and debug traffic. */
2306#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT                       0x180e8
2307/* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
2308 * bits are mapped according to client ID (client IDs are defined in
2309 * tx_arb_priority_client). Default value is 0 for not using WFQ credit
2310 * blocking. */
2311#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ          0x180ec
2312/* [RW 32] Specify the upper bound that credit register 0 is allowed to
2313 * reach. */
2314#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0                   0x1810c
2315#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1                   0x18110
2316#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2                   0x18114
2317#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3                   0x18118
2318#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4                   0x1811c
2319#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5                   0x186a0
2320#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6                   0x186a4
2321#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7                   0x186a8
2322#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8                   0x186ac
2323/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2324 * when it is time to increment. */
2325#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0                        0x180f8
2326#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1                        0x180fc
2327#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2                        0x18100
2328#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3                        0x18104
2329#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4                        0x18108
2330#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5                        0x18690
2331#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6                        0x18694
2332#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7                        0x18698
2333#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8                        0x1869c
2334/* [RW 12] Specify the number of strict priority arbitration slots between
2335 * two round-robin arbitration slots to avoid starvation. A value of 0 means
2336 * no strict priority cycles - the strict priority with anti-starvation
2337 * arbiter becomes a round-robin arbiter. */
2338#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS                   0x180f4
2339/* [RW 15] Specify the client number to be assigned to each priority of the
2340 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
2341 * are for priority 0 client; bits [14:12] are for priority 4 client. The
2342 * clients are assigned the following IDs: 0-management; 1-debug traffic
2343 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2344 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
2345 * for management at priority 0; debug traffic at priorities 1 and 2; COS0
2346 * traffic at priority 3; and COS1 traffic at priority 4. */
2347#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT                        0x180e4
2348/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2349 * Ethernet header. */
2350#define NIG_REG_P1_HDRS_AFTER_BASIC                              0x1818c
2351#define NIG_REG_P1_LLH_FUNC_MEM2                                 0x184c0
2352#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE                  0x18460a
2353/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
2354 * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
2355 * indicates the validity of the data in the buffer. Writing a 1 to bit 16
2356 * will clear the buffer.
2357 */
2358#define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID                        0x18774
2359/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2360 * the host. This location returns the lower 32 bits of timestamp value.
2361 */
2362#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB                       0x1876c
2363/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2364 * the host. This location returns the upper 32 bits of timestamp value.
2365 */
2366#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB                       0x18770
2367/* [RW 11] Mask register for the various parameters used in determining PTP
2368 * packet presence. Set each bit to 1 to mask out the particular parameter.
2369 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2370 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2371 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2372 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2373 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2374 * MAC DA 2. The reset default is set to mask out all parameters.
2375 */
2376#define NIG_REG_P1_LLH_PTP_PARAM_MASK                            0x187c8
2377/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
2378 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2379 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2380 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2381 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2382 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2383 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2384 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
2385 * packets only and require that the packet is IPv4 for the rules to match.
2386 * Note that rules 4-7 are for IPv6 packets only and require that the packet
2387 * is IPv6 for the rules to match.
2388 */
2389#define NIG_REG_P1_LLH_PTP_RULE_MASK                             0x187cc
2390/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
2391#define NIG_REG_P1_LLH_PTP_TO_HOST                               0x187d4
2392/* [RW 32] Specify the client number to be assigned to each priority of the
2393 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2394 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2395 * client; bits [35-32] are for priority 8 client. The clients are assigned
2396 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2397 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2398 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2399 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2400 * accommodate the 9 input clients to ETS arbiter. */
2401#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB                   0x18680
2402/* [RW 4] Specify the client number to be assigned to each priority of the
2403 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2404 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2405 * client; bits [35-32] are for priority 8 client. The clients are assigned
2406 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2407 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2408 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2409 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2410 * accommodate the 9 input clients to ETS arbiter. */
2411#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB                   0x18684
2412/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
2413 * packets to BRB LB interface to forward the packet to the host. All
2414 * packets from MCP are forwarded to the network when this bit is cleared -
2415 * regardless of the configured destination in tx_mng_destination register.
2416 * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter
2417 * for BRB LB interface is bypassed and PBF LB traffic is always selected to
2418 * send to BRB LB.
2419 */
2420#define NIG_REG_P0_TX_MNG_HOST_ENABLE                            0x182f4
2421#define NIG_REG_P1_HWPFC_ENABLE                                  0x181d0
2422#define NIG_REG_P1_MAC_IN_EN                                     0x185c0
2423/* [RW 1] Output enable for TX MAC interface */
2424#define NIG_REG_P1_MAC_OUT_EN                                    0x185c4
2425/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2426#define NIG_REG_P1_MAC_PAUSE_OUT_EN                              0x185c8
2427/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2428 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2429 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2430 * priority field is extracted from the outer-most VLAN in receive packet.
2431 * Only COS 0 and COS 1 are supported in E2. */
2432#define NIG_REG_P1_PKT_PRIORITY_TO_COS                           0x181a8
2433/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
2434 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
2435 * V1 frame format in timesync event detection on RX side. Bit 2 enables V2
2436 * frame format in timesync event detection on RX side. Bit 3 enables
2437 * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
2438 * detection on TX side. Bit 5 enables V2 frame format in timesync event
2439 * detection on TX side. Note that for HW to detect PTP packet and extract
2440 * data from the packet, at least one of the version bits of that traffic
2441 * direction has to be enabled.
2442 */
2443#define NIG_REG_P1_PTP_EN                                        0x187b0
2444/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2445 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2446 * than one bit may be set; allowing multiple priorities to be mapped to one
2447 * COS. */
2448#define NIG_REG_P1_RX_COS0_PRIORITY_MASK                         0x181ac
2449/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2450 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2451 * than one bit may be set; allowing multiple priorities to be mapped to one
2452 * COS. */
2453#define NIG_REG_P1_RX_COS1_PRIORITY_MASK                         0x181b0
2454/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2455 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2456 * than one bit may be set; allowing multiple priorities to be mapped to one
2457 * COS. */
2458#define NIG_REG_P1_RX_COS2_PRIORITY_MASK                         0x186f8
2459/* [R 1] RX FIFO for receiving data from MAC is empty. */
2460#define NIG_REG_P1_RX_MACFIFO_EMPTY                              0x1858c
2461/* [R 1] TLLH FIFO is empty. */
2462#define NIG_REG_P1_TLLH_FIFO_EMPTY                               0x18338
2463/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
2464 * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
2465 * indicates the validity of the data in the buffer. Bit 17 indicates that
2466 * the sequence ID is valid and it is waiting for the TX timestamp value.
2467 * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
2468 * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
2469 */
2470#define NIG_REG_P0_TLLH_PTP_BUF_SEQID                            0x187e0
2471/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2472 * MCP. This location returns the lower 32 bits of timestamp value.
2473 */
2474#define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB                           0x187d8
2475/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2476 * MCP. This location returns the upper 32 bits of timestamp value.
2477 */
2478#define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB                           0x187dc
2479/* [RW 11] Mask register for the various parameters used in determining PTP
2480 * packet presence. Set each bit to 1 to mask out the particular parameter.
2481 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2482 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2483 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2484 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2485 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2486 * MAC DA 2. The reset default is set to mask out all parameters.
2487 */
2488#define NIG_REG_P0_TLLH_PTP_PARAM_MASK                           0x187f0
2489/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
2490 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2491 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2492 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2493 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2494 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2495 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2496 * default is to mask out all of the rules.
2497 */
2498#define NIG_REG_P0_TLLH_PTP_RULE_MASK                            0x187f4
2499/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
2500 * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
2501 * indicates the validity of the data in the buffer. Bit 17 indicates that
2502 * the sequence ID is valid and it is waiting for the TX timestamp value.
2503 * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
2504 * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
2505 */
2506#define NIG_REG_P1_TLLH_PTP_BUF_SEQID                            0x187ec
2507/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2508 * MCP. This location returns the lower 32 bits of timestamp value.
2509 */
2510#define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB                           0x187e4
2511/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2512 * MCP. This location returns the upper 32 bits of timestamp value.
2513 */
2514#define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB                           0x187e8
2515/* [RW 11] Mask register for the various parameters used in determining PTP
2516 * packet presence. Set each bit to 1 to mask out the particular parameter.
2517 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2518 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2519 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2520 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2521 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2522 * MAC DA 2. The reset default is set to mask out all parameters.
2523 */
2524#define NIG_REG_P1_TLLH_PTP_PARAM_MASK                           0x187f8
2525/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
2526 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2527 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2528 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2529 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2530 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2531 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2532 * default is to mask out all of the rules.
2533 */
2534#define NIG_REG_P1_TLLH_PTP_RULE_MASK                            0x187fc
2535/* [RW 32] Specify which of the credit registers the client is to be mapped
2536 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2537 * for client 0; bits [35:32] are for client 8. For clients that are not
2538 * subject to WFQ credit blocking - their specifications here are not used.
2539 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2540 * input clients to ETS arbiter. The reset default is set for management and
2541 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2542 * use credit registers 0-5 respectively (0x543210876). Note that credit
2543 * registers can not be shared between clients. Note also that there are
2544 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2545 * credit registers 0-5 are valid. This register should be configured
2546 * appropriately before enabling WFQ. */
2547#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB                 0x186e8
2548/* [RW 4] Specify which of the credit registers the client is to be mapped
2549 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2550 * for client 0; bits [35:32] are for client 8. For clients that are not
2551 * subject to WFQ credit blocking - their specifications here are not used.
2552 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2553 * input clients to ETS arbiter. The reset default is set for management and
2554 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2555 * use credit registers 0-5 respectively (0x543210876). Note that credit
2556 * registers can not be shared between clients. Note also that there are
2557 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2558 * credit registers 0-5 are valid. This register should be configured
2559 * appropriately before enabling WFQ. */
2560#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB                 0x186ec
2561/* [RW 9] Specify whether the client competes directly in the strict
2562 * priority arbiter. The bits are mapped according to client ID (client IDs
2563 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2564 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2565 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
2566 * Default value is set to enable strict priorities for all clients. */
2567#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT                       0x18234
2568/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
2569 * bits are mapped according to client ID (client IDs are defined in
2570 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2571 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
2572 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
2573 * 0 for not using WFQ credit blocking. */
2574#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ                  0x18238
2575#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0                   0x18258
2576#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1                   0x1825c
2577#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2                   0x18260
2578#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3                   0x18264
2579#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4                   0x18268
2580#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5                   0x186f4
2581/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2582 * when it is time to increment. */
2583#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0                        0x18244
2584#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1                        0x18248
2585#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2                        0x1824c
2586#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3                        0x18250
2587#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4                        0x18254
2588#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5                        0x186f0
2589/* [RW 12] Specify the number of strict priority arbitration slots between
2590   two round-robin arbitration slots to avoid starvation. A value of 0 means
2591   no strict priority cycles - the strict priority with anti-starvation
2592   arbiter becomes a round-robin arbiter. */
2593#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS                   0x18240
2594/* [RW 32] Specify the client number to be assigned to each priority of the
2595   strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2596   value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2597   client; bits [35-32] are for priority 8 client. The clients are assigned
2598   the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2599   traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2600   6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2601   set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2602   accommodate the 9 input clients to ETS arbiter. Note that this register
2603   is the same as the one for port 0, except that port 1 only has COS 0-2
2604   traffic. There is no traffic for COS 3-5 of port 1. */
2605#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB                   0x186e0
2606/* [RW 4] Specify the client number to be assigned to each priority of the
2607   strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2608   value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2609   client; bits [35-32] are for priority 8 client. The clients are assigned
2610   the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2611   traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2612   6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2613   set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2614   accommodate the 9 input clients to ETS arbiter. Note that this register
2615   is the same as the one for port 0, except that port 1 only has COS 0-2
2616   traffic. There is no traffic for COS 3-5 of port 1. */
2617#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB                   0x186e4
2618/* [R 1] TX FIFO for transmitting data to MAC is empty. */
2619#define NIG_REG_P1_TX_MACFIFO_EMPTY                              0x18594
2620/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
2621 * packets to BRB LB interface to forward the packet to the host. All
2622 * packets from MCP are forwarded to the network when this bit is cleared -
2623 * regardless of the configured destination in tx_mng_destination register.
2624 */
2625#define NIG_REG_P1_TX_MNG_HOST_ENABLE                            0x182f8
2626/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
2627   forwarded to the host. */
2628#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY                        0x182b8
2629/* [RW 32] Specify the upper bound that credit register 0 is allowed to
2630 * reach. */
2631/* [RW 1] Pause enable for port0. This register may get 1 only when
2632   ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
2633   port */
2634#define NIG_REG_PAUSE_ENABLE_0                                   0x160c0
2635#define NIG_REG_PAUSE_ENABLE_1                                   0x160c4
2636/* [RW 1] Input enable for RX PBF LP IF */
2637#define NIG_REG_PBF_LB_IN_EN                                     0x100b4
2638/* [RW 1] Value of this register will be transmitted to port swap when
2639   ~nig_registers_strap_override.strap_override =1 */
2640#define NIG_REG_PORT_SWAP                                        0x10394
2641/* [RW 1] PPP enable for port0. This register may get 1 only when
2642 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
2643 * same port */
2644#define NIG_REG_PPP_ENABLE_0                                     0x160b0
2645#define NIG_REG_PPP_ENABLE_1                                     0x160b4
2646/* [RW 1] output enable for RX parser descriptor IF */
2647#define NIG_REG_PRS_EOP_OUT_EN                                   0x10104
2648/* [RW 1] Input enable for RX parser request IF */
2649#define NIG_REG_PRS_REQ_IN_EN                                    0x100b8
2650/* [RW 5] control to serdes - CL45 DEVAD */
2651#define NIG_REG_SERDES0_CTRL_MD_DEVAD                            0x10370
2652/* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2653#define NIG_REG_SERDES0_CTRL_MD_ST                               0x1036c
2654/* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
2655#define NIG_REG_SERDES0_CTRL_PHY_ADDR                            0x10374
2656/* [R 1] status from serdes0 that inputs to interrupt logic of link status */
2657#define NIG_REG_SERDES0_STATUS_LINK_STATUS                       0x10578
2658/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2659   for port0 */
2660#define NIG_REG_STAT0_BRB_DISCARD                                0x105f0
2661/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
2662   for port0 */
2663#define NIG_REG_STAT0_BRB_TRUNCATE                               0x105f8
2664/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2665   between 1024 and 1522 bytes for port0 */
2666#define NIG_REG_STAT0_EGRESS_MAC_PKT0                            0x10750
2667/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2668   between 1523 bytes and above for port0 */
2669#define NIG_REG_STAT0_EGRESS_MAC_PKT1                            0x10760
2670/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2671   for port1 */
2672#define NIG_REG_STAT1_BRB_DISCARD                                0x10628
2673/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2674   between 1024 and 1522 bytes for port1 */
2675#define NIG_REG_STAT1_EGRESS_MAC_PKT0                            0x107a0
2676/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2677   between 1523 bytes and above for port1 */
2678#define NIG_REG_STAT1_EGRESS_MAC_PKT1                            0x107b0
2679/* [WB_R 64] Rx statistics : User octets received for LP */
2680#define NIG_REG_STAT2_BRB_OCTET                                  0x107e0
2681#define NIG_REG_STATUS_INTERRUPT_PORT0                           0x10328
2682#define NIG_REG_STATUS_INTERRUPT_PORT1                           0x1032c
2683/* [RW 1] port swap mux selection. If this register equal to 0 then port
2684   swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
2685   ort swap is equal to ~nig_registers_port_swap.port_swap */
2686#define NIG_REG_STRAP_OVERRIDE                                   0x10398
2687/* [WB 64] Addresses for TimeSync related registers in the timesync
2688 * generator sub-module.
2689 */
2690#define NIG_REG_TIMESYNC_GEN_REG                                 0x18800
2691/* [RW 1] output enable for RX_XCM0 IF */
2692#define NIG_REG_XCM0_OUT_EN                                      0x100f0
2693/* [RW 1] output enable for RX_XCM1 IF */
2694#define NIG_REG_XCM1_OUT_EN                                      0x100f4
2695/* [RW 1] control to xgxs - remote PHY in-band MDIO */
2696#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST                       0x10348
2697/* [RW 5] control to xgxs - CL45 DEVAD */
2698#define NIG_REG_XGXS0_CTRL_MD_DEVAD                              0x1033c
2699/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2700#define NIG_REG_XGXS0_CTRL_MD_ST                                 0x10338
2701/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2702#define NIG_REG_XGXS0_CTRL_PHY_ADDR                              0x10340
2703/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
2704#define NIG_REG_XGXS0_STATUS_LINK10G                             0x10680
2705/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
2706#define NIG_REG_XGXS0_STATUS_LINK_STATUS                         0x10684
2707/* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
2708#define NIG_REG_XGXS_LANE_SEL_P0                                 0x102e8
2709/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
2710#define NIG_REG_XGXS_SERDES0_MODE_SEL                            0x102e0
2711#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT  (0x1<<0)
2712#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
2713#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G      (0x1<<15)
2714#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS  (0xf<<18)
2715#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
2716/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
2717#define PBF_REG_COS0_UPPER_BOUND                                 0x15c05c
2718/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2719 * of port 0. */
2720#define PBF_REG_COS0_UPPER_BOUND_P0                              0x15c2cc
2721/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2722 * of port 1. */
2723#define PBF_REG_COS0_UPPER_BOUND_P1                              0x15c2e4
2724/* [RW 31] The weight of COS0 in the ETS command arbiter. */
2725#define PBF_REG_COS0_WEIGHT                                      0x15c054
2726/* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
2727#define PBF_REG_COS0_WEIGHT_P0                                   0x15c2a8
2728/* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
2729#define PBF_REG_COS0_WEIGHT_P1                                   0x15c2c0
2730/* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2731#define PBF_REG_COS1_UPPER_BOUND                                 0x15c060
2732/* [RW 31] The weight of COS1 in the ETS command arbiter. */
2733#define PBF_REG_COS1_WEIGHT                                      0x15c058
2734/* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
2735#define PBF_REG_COS1_WEIGHT_P0                                   0x15c2ac
2736/* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
2737#define PBF_REG_COS1_WEIGHT_P1                                   0x15c2c4
2738/* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
2739#define PBF_REG_COS2_WEIGHT_P0                                   0x15c2b0
2740/* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
2741#define PBF_REG_COS2_WEIGHT_P1                                   0x15c2c8
2742/* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
2743#define PBF_REG_COS3_WEIGHT_P0                                   0x15c2b4
2744/* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
2745#define PBF_REG_COS4_WEIGHT_P0                                   0x15c2b8
2746/* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
2747#define PBF_REG_COS5_WEIGHT_P0                                   0x15c2bc
2748/* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
2749 * lines. */
2750#define PBF_REG_CREDIT_LB_Q                                      0x140338
2751/* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
2752 * lines. */
2753#define PBF_REG_CREDIT_Q0                                        0x14033c
2754/* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
2755 * lines. */
2756#define PBF_REG_CREDIT_Q1                                        0x140340
2757/* [RW 1] Disable processing further tasks from port 0 (after ending the
2758   current task in process). */
2759#define PBF_REG_DISABLE_NEW_TASK_PROC_P0                         0x14005c
2760/* [RW 1] Disable processing further tasks from port 1 (after ending the
2761   current task in process). */
2762#define PBF_REG_DISABLE_NEW_TASK_PROC_P1                         0x140060
2763/* [RW 1] Disable processing further tasks from port 4 (after ending the
2764   current task in process). */
2765#define PBF_REG_DISABLE_NEW_TASK_PROC_P4                         0x14006c
2766#define PBF_REG_DISABLE_PF                                       0x1402e8
2767#define PBF_REG_DISABLE_VF                                       0x1402ec
2768/* [RW 18] For port 0: For each client that is subject to WFQ (the
2769 * corresponding bit is 1); indicates to which of the credit registers this
2770 * client is mapped. For clients which are not credit blocked; their mapping
2771 * is dont care. */
2772#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0                     0x15c288
2773/* [RW 9] For port 1: For each client that is subject to WFQ (the
2774 * corresponding bit is 1); indicates to which of the credit registers this
2775 * client is mapped. For clients which are not credit blocked; their mapping
2776 * is dont care. */
2777#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1                     0x15c28c
2778/* [RW 6] For port 0: Bit per client to indicate if the client competes in
2779 * the strict priority arbiter directly (corresponding bit = 1); or first
2780 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2781 * lowest priority in the strict-priority arbiter. */
2782#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0                      0x15c278
2783/* [RW 3] For port 1: Bit per client to indicate if the client competes in
2784 * the strict priority arbiter directly (corresponding bit = 1); or first
2785 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2786 * lowest priority in the strict-priority arbiter. */
2787#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1                      0x15c27c
2788/* [RW 6] For port 0: Bit per client to indicate if the client is subject to
2789 * WFQ credit blocking (corresponding bit = 1). */
2790#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0                 0x15c280
2791/* [RW 3] For port 0: Bit per client to indicate if the client is subject to
2792 * WFQ credit blocking (corresponding bit = 1). */
2793#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1                 0x15c284
2794/* [RW 16] For port 0: The number of strict priority arbitration slots
2795 * between 2 RR arbitration slots. A value of 0 means no strict priority
2796 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2797 * arbiter. */
2798#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0                  0x15c2a0
2799/* [RW 16] For port 1: The number of strict priority arbitration slots
2800 * between 2 RR arbitration slots. A value of 0 means no strict priority
2801 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2802 * arbiter. */
2803#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1                  0x15c2a4
2804/* [RW 18] For port 0: Indicates which client is connected to each priority
2805 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2806 * priority 5 is the lowest; to which the RR output is connected to (this is
2807 * not configurable). */
2808#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0                       0x15c270
2809/* [RW 9] For port 1: Indicates which client is connected to each priority
2810 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2811 * priority 5 is the lowest; to which the RR output is connected to (this is
2812 * not configurable). */
2813#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1                       0x15c274
2814/* [RW 1] Indicates that ETS is performed between the COSes in the command
2815 * arbiter. If reset strict priority w/ anti-starvation will be performed
2816 * w/o WFQ. */
2817#define PBF_REG_ETS_ENABLED                                      0x15c050
2818/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2819 * Ethernet header. */
2820#define PBF_REG_HDRS_AFTER_BASIC                                 0x15c0a8
2821/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2822#define PBF_REG_HDRS_AFTER_TAG_0                                 0x15c0b8
2823/* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
2824 * priority in the command arbiter. */
2825#define PBF_REG_HIGH_PRIORITY_COS_NUM                            0x15c04c
2826#define PBF_REG_IF_ENABLE_REG                                    0x140044
2827/* [RW 1] Init bit. When set the initial credits are copied to the credit
2828   registers (except the port credits). Should be set and then reset after
2829   the configuration of the block has ended. */
2830#define PBF_REG_INIT                                             0x140000
2831/* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
2832 * lines. */
2833#define PBF_REG_INIT_CRD_LB_Q                                    0x15c248
2834/* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
2835 * lines. */
2836#define PBF_REG_INIT_CRD_Q0                                      0x15c230
2837/* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
2838 * lines. */
2839#define PBF_REG_INIT_CRD_Q1                                      0x15c234
2840/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2841   copied to the credit register. Should be set and then reset after the
2842   configuration of the port has ended. */
2843#define PBF_REG_INIT_P0                                          0x140004
2844/* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
2845   copied to the credit register. Should be set and then reset after the
2846   configuration of the port has ended. */
2847#define PBF_REG_INIT_P1                                          0x140008
2848/* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
2849   copied to the credit register. Should be set and then reset after the
2850   configuration of the port has ended. */
2851#define PBF_REG_INIT_P4                                          0x14000c
2852/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2853 * the LB queue. Reset upon init. */
2854#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q                      0x140354
2855/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2856 * queue 0. Reset upon init. */
2857#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0                        0x140358
2858/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2859 * queue 1. Reset upon init. */
2860#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1                        0x14035c
2861/* [RW 1] Enable for mac interface 0. */
2862#define PBF_REG_MAC_IF0_ENABLE                                   0x140030
2863/* [RW 1] Enable for mac interface 1. */
2864#define PBF_REG_MAC_IF1_ENABLE                                   0x140034
2865/* [RW 1] Enable for the loopback interface. */
2866#define PBF_REG_MAC_LB_ENABLE                                    0x140040
2867/* [RW 6] Bit-map indicating which headers must appear in the packet */
2868#define PBF_REG_MUST_HAVE_HDRS                                   0x15c0c4
2869/* [RW 16] The number of strict priority arbitration slots between 2 RR
2870 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
2871 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2872#define PBF_REG_NUM_STRICT_ARB_SLOTS                             0x15c064
2873/* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2874   not suppoterd. */
2875#define PBF_REG_P0_ARB_THRSH                                     0x1400e4
2876/* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
2877#define PBF_REG_P0_CREDIT                                        0x140200
2878/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2879   lines. */
2880#define PBF_REG_P0_INIT_CRD                                      0x1400d0
2881/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2882 * port 0. Reset upon init. */
2883#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT                        0x140308
2884/* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2885#define PBF_REG_P0_PAUSE_ENABLE                                  0x140014
2886/* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
2887#define PBF_REG_P0_TASK_CNT                                      0x140204
2888/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2889 * freed from the task queue of port 0. Reset upon init. */
2890#define PBF_REG_P0_TQ_LINES_FREED_CNT                            0x1402f0
2891/* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
2892#define PBF_REG_P0_TQ_OCCUPANCY                                  0x1402fc
2893/* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
2894 * buffers in 16 byte lines. */
2895#define PBF_REG_P1_CREDIT                                        0x140208
2896/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2897 * buffers in 16 byte lines. */
2898#define PBF_REG_P1_INIT_CRD                                      0x1400d4
2899/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2900 * port 1. Reset upon init. */
2901#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT                        0x14030c
2902/* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
2903#define PBF_REG_P1_TASK_CNT                                      0x14020c
2904/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2905 * freed from the task queue of port 1. Reset upon init. */
2906#define PBF_REG_P1_TQ_LINES_FREED_CNT                            0x1402f4
2907/* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
2908#define PBF_REG_P1_TQ_OCCUPANCY                                  0x140300
2909/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
2910#define PBF_REG_P4_CREDIT                                        0x140210
2911/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2912   lines. */
2913#define PBF_REG_P4_INIT_CRD                                      0x1400e0
2914/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2915 * port 4. Reset upon init. */
2916#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT                        0x140310
2917/* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
2918#define PBF_REG_P4_TASK_CNT                                      0x140214
2919/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2920 * freed from the task queue of port 4. Reset upon init. */
2921#define PBF_REG_P4_TQ_LINES_FREED_CNT                            0x1402f8
2922/* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
2923#define PBF_REG_P4_TQ_OCCUPANCY                                  0x140304
2924/* [RW 5] Interrupt mask register #0 read/write */
2925#define PBF_REG_PBF_INT_MASK                                     0x1401d4
2926/* [R 5] Interrupt register #0 read */
2927#define PBF_REG_PBF_INT_STS                                      0x1401c8
2928/* [RW 20] Parity mask register #0 read/write */
2929#define PBF_REG_PBF_PRTY_MASK                                    0x1401e4
2930/* [R 28] Parity register #0 read */
2931#define PBF_REG_PBF_PRTY_STS                                     0x1401d8
2932/* [RC 20] Parity register #0 read clear */
2933#define PBF_REG_PBF_PRTY_STS_CLR                                 0x1401dc
2934/* [RW 16] The Ethernet type value for L2 tag 0 */
2935#define PBF_REG_TAG_ETHERTYPE_0                                  0x15c090
2936/* [RW 4] The length of the info field for L2 tag 0. The length is between
2937 * 2B and 14B; in 2B granularity */
2938#define PBF_REG_TAG_LEN_0                                        0x15c09c
2939/* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
2940 * queue. Reset upon init. */
2941#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q                          0x14038c
2942/* [R 32] Cyclic counter for number of 8 byte lines freed from the task
2943 * queue 0. Reset upon init. */
2944#define PBF_REG_TQ_LINES_FREED_CNT_Q0                            0x140390
2945/* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
2946 * Reset upon init. */
2947#define PBF_REG_TQ_LINES_FREED_CNT_Q1                            0x140394
2948/* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
2949 * queue. */
2950#define PBF_REG_TQ_OCCUPANCY_LB_Q                                0x1403a8
2951/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
2952#define PBF_REG_TQ_OCCUPANCY_Q0                                  0x1403ac
2953/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
2954#define PBF_REG_TQ_OCCUPANCY_Q1                                  0x1403b0
2955#define PB_REG_CONTROL                                           0
2956/* [RW 2] Interrupt mask register #0 read/write */
2957#define PB_REG_PB_INT_MASK                                       0x28
2958/* [R 2] Interrupt register #0 read */
2959#define PB_REG_PB_INT_STS                                        0x1c
2960/* [RW 4] Parity mask register #0 read/write */
2961#define PB_REG_PB_PRTY_MASK                                      0x38
2962/* [R 4] Parity register #0 read */
2963#define PB_REG_PB_PRTY_STS                                       0x2c
2964/* [RC 4] Parity register #0 read clear */
2965#define PB_REG_PB_PRTY_STS_CLR                                   0x30
2966#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR                (0x1<<0)
2967#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW        (0x1<<8)
2968#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR       (0x1<<1)
2969#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN              (0x1<<6)
2970#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN        (0x1<<7)
2971#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN  (0x1<<4)
2972#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN     (0x1<<3)
2973#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN   (0x1<<5)
2974#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN               (0x1<<2)
2975/* [R 8] Config space A attention dirty bits. Each bit indicates that the
2976 * corresponding PF generates config space A attention. Set by PXP. Reset by
2977 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
2978 * from both paths. */
2979#define PGLUE_B_REG_CFG_SPACE_A_REQUEST                  0x9010
2980/* [R 8] Config space B attention dirty bits. Each bit indicates that the
2981 * corresponding PF generates config space B attention. Set by PXP. Reset by
2982 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
2983 * from both paths. */
2984#define PGLUE_B_REG_CFG_SPACE_B_REQUEST                  0x9014
2985/* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2986 * - enable. */
2987#define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE                     0x9194
2988/* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
2989 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
2990#define PGLUE_B_REG_CSDM_INB_INT_B_VF                            0x916c
2991/* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
2992 * - enable. */
2993#define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE                     0x919c
2994/* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
2995#define PGLUE_B_REG_CSDM_START_OFFSET_A                  0x9100
2996/* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
2997#define PGLUE_B_REG_CSDM_START_OFFSET_B                  0x9108
2998/* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
2999#define PGLUE_B_REG_CSDM_VF_SHIFT_B                              0x9110
3000/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3001#define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF                  0x91ac
3002/* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
3003 * that the FLR register of the corresponding PF was set. Set by PXP. Reset
3004 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
3005 * from both paths. */
3006#define PGLUE_B_REG_FLR_REQUEST_PF_7_0                           0x9028
3007/* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
3008 * to a bit in this register in order to clear the corresponding bit in
3009 * flr_request_pf_7_0 register. Note: register contains bits from both
3010 * paths. */
3011#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR                       0x9418
3012/* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
3013 * indicates that the FLR register of the corresponding VF was set. Set by
3014 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
3015#define PGLUE_B_REG_FLR_REQUEST_VF_127_96                        0x9024
3016/* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
3017 * indicates that the FLR register of the corresponding VF was set. Set by
3018 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
3019#define PGLUE_B_REG_FLR_REQUEST_VF_31_0                  0x9018
3020/* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
3021 * indicates that the FLR register of the corresponding VF was set. Set by
3022 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
3023#define PGLUE_B_REG_FLR_REQUEST_VF_63_32                         0x901c
3024/* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
3025 * indicates that the FLR register of the corresponding VF was set. Set by
3026 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
3027#define PGLUE_B_REG_FLR_REQUEST_VF_95_64                         0x9020
3028/* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
3029 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
3030 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
3031 * arrived with a correctable error. Bit 3 - Configuration RW arrived with
3032 * an uncorrectable error. Bit 4 - Completion with Configuration Request
3033 * Retry Status. Bit 5 - Expansion ROM access received with a write request.
3034 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
3035 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
3036 * and pcie_rx_last not asserted. */
3037#define PGLUE_B_REG_INCORRECT_RCV_DETAILS                        0x9068
3038#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER          0x942c
3039#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ             0x9430
3040#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE            0x9434
3041#define PGLUE_B_REG_INTERNAL_VFID_ENABLE                         0x9438
3042/* [W 7] Writing 1 to each bit in this register clears a corresponding error
3043 * details register and enables logging new error details. Bit 0 - clears
3044 * INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears
3045 * TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS
3046 * TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32
3047 * TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 -
3048 * clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears
3049 * VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6
3050 * - clears TCPL_IN_TWO_RCBS_DETAILS. */
3051#define PGLUE_B_REG_LATCHED_ERRORS_CLR                           0x943c
3052
3053/* [R 9] Interrupt register #0 read */
3054#define PGLUE_B_REG_PGLUE_B_INT_STS                              0x9298
3055/* [RC 9] Interrupt register #0 read clear */
3056#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR                  0x929c
3057/* [RW 2] Parity mask register #0 read/write */
3058#define PGLUE_B_REG_PGLUE_B_PRTY_MASK                            0x92b4
3059/* [R 2] Parity register #0 read */
3060#define PGLUE_B_REG_PGLUE_B_PRTY_STS                             0x92a8
3061/* [RC 2] Parity register #0 read clear */
3062#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR                         0x92ac
3063/* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
3064 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
3065 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
3066 * completer abort. 3 - Illegal value for this field. [12] valid - indicates
3067 * if there was a completion error since the last time this register was
3068 * cleared. */
3069#define PGLUE_B_REG_RX_ERR_DETAILS                               0x9080
3070/* [R 18] Details of first ATS Translation Completion request received with
3071 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
3072 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
3073 * unsupported request. 2 - completer abort. 3 - Illegal value for this
3074 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
3075 * completion error since the last time this register was cleared. */
3076#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS                  0x9084
3077/* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
3078 * a bit in this register in order to clear the corresponding bit in
3079 * shadow_bme_pf_7_0 register. MCP should never use this unless a
3080 * work-around is needed. Note: register contains bits from both paths. */
3081#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR                        0x9458
3082/* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
3083 * VF enable register of the corresponding PF is written to 0 and was
3084 * previously 1. Set by PXP. Reset by MCP writing 1 to
3085 * sr_iov_disabled_request_clr. Note: register contains bits from both
3086 * paths. */
3087#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST                      0x9030
3088/* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
3089 * completion did not return yet. 1 - tag is unused. Same functionality as
3090 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
3091#define PGLUE_B_REG_TAGS_63_32                                   0x9244
3092/* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
3093 * - enable. */
3094#define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE                     0x9170
3095/* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
3096#define PGLUE_B_REG_TSDM_START_OFFSET_A                  0x90c4
3097/* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
3098#define PGLUE_B_REG_TSDM_START_OFFSET_B                  0x90cc
3099/* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
3100#define PGLUE_B_REG_TSDM_VF_SHIFT_B                              0x90d4
3101/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3102#define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF                  0x91a0
3103/* [R 32] Address [31:0] of first read request not submitted due to error */
3104#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0                           0x9098
3105/* [R 32] Address [63:32] of first read request not submitted due to error */
3106#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32                  0x909c
3107/* [R 31] Details of first read request not submitted due to error. [4:0]
3108 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
3109 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
3110 * VFID. */
3111#define PGLUE_B_REG_TX_ERR_RD_DETAILS                            0x90a0
3112/* [R 26] Details of first read request not submitted due to error. [15:0]
3113 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
3114 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
3115 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
3116 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
3117 * indicates if there was a request not submitted due to error since the
3118 * last time this register was cleared. */
3119#define PGLUE_B_REG_TX_ERR_RD_DETAILS2                           0x90a4
3120/* [R 32] Address [31:0] of first write request not submitted due to error */
3121#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0                           0x9088
3122/* [R 32] Address [63:32] of first write request not submitted due to error */
3123#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32                  0x908c
3124/* [R 31] Details of first write request not submitted due to error. [4:0]
3125 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
3126 * - VFID. */
3127#define PGLUE_B_REG_TX_ERR_WR_DETAILS                            0x9090
3128/* [R 26] Details of first write request not submitted due to error. [15:0]
3129 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
3130 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
3131 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
3132 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
3133 * indicates if there was a request not submitted due to error since the
3134 * last time this register was cleared. */
3135#define PGLUE_B_REG_TX_ERR_WR_DETAILS2                           0x9094
3136/* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
3137 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
3138 * value (Byte resolution address). */
3139#define PGLUE_B_REG_USDM_INB_INT_A_0                             0x9128
3140#define PGLUE_B_REG_USDM_INB_INT_A_1                             0x912c
3141#define PGLUE_B_REG_USDM_INB_INT_A_2                             0x9130
3142#define PGLUE_B_REG_USDM_INB_INT_A_3                             0x9134
3143#define PGLUE_B_REG_USDM_INB_INT_A_4                             0x9138
3144#define PGLUE_B_REG_USDM_INB_INT_A_5                             0x913c
3145#define PGLUE_B_REG_USDM_INB_INT_A_6                             0x9140
3146/* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
3147 * - enable. */
3148#define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE                     0x917c
3149/* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
3150 * - enable. */
3151#define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE                     0x9180
3152/* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
3153 * - enable. */
3154#define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE                     0x9184
3155/* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
3156#define PGLUE_B_REG_USDM_START_OFFSET_A                  0x90d8
3157/* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
3158#define PGLUE_B_REG_USDM_START_OFFSET_B                  0x90e0
3159/* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
3160#define PGLUE_B_REG_USDM_VF_SHIFT_B                              0x90e8
3161/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3162#define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF                  0x91a4
3163/* [R 26] Details of first target VF request accessing VF GRC space that
3164 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
3165 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
3166 * request accessing VF GRC space that failed permission check since the
3167 * last time this register was cleared. Permission checks are: function
3168 * permission; R/W permission; address range permission. */
3169#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS               0x9234
3170/* [R 31] Details of first target VF request with length violation (too many
3171 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
3172 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
3173 * valid - indicates if there was a request with length violation since the
3174 * last time this register was cleared. Length violations: length of more
3175 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
3176 * length is more than 1 DW. */
3177#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS          0x9230
3178/* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
3179 * that there was a completion with uncorrectable error for the
3180 * corresponding PF. Set by PXP. Reset by MCP writing 1 to
3181 * was_error_pf_7_0_clr. */
3182#define PGLUE_B_REG_WAS_ERROR_PF_7_0                             0x907c
3183/* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
3184 * to a bit in this register in order to clear the corresponding bit in
3185 * flr_request_pf_7_0 register. */
3186#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR                         0x9470
3187/* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
3188 * indicates that there was a completion with uncorrectable error for the
3189 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
3190 * was_error_vf_127_96_clr. */
3191#define PGLUE_B_REG_WAS_ERROR_VF_127_96                  0x9078
3192/* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
3193 * writes 1 to a bit in this register in order to clear the corresponding
3194 * bit in was_error_vf_127_96 register. */
3195#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR                      0x9474
3196/* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
3197 * indicates that there was a completion with uncorrectable error for the
3198 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
3199 * was_error_vf_31_0_clr. */
3200#define PGLUE_B_REG_WAS_ERROR_VF_31_0                            0x906c
3201/* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
3202 * 1 to a bit in this register in order to clear the corresponding bit in
3203 * was_error_vf_31_0 register. */
3204#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR                        0x9478
3205/* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
3206 * indicates that there was a completion with uncorrectable error for the
3207 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
3208 * was_error_vf_63_32_clr. */
3209#define PGLUE_B_REG_WAS_ERROR_VF_63_32                           0x9070
3210/* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
3211 * 1 to a bit in this register in order to clear the corresponding bit in
3212 * was_error_vf_63_32 register. */
3213#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR                       0x947c
3214/* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
3215 * indicates that there was a completion with uncorrectable error for the
3216 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
3217 * was_error_vf_95_64_clr. */
3218#define PGLUE_B_REG_WAS_ERROR_VF_95_64                           0x9074
3219/* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
3220 * 1 to a bit in this register in order to clear the corresponding bit in
3221 * was_error_vf_95_64 register. */
3222#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR                       0x9480
3223/* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
3224 * - enable. */
3225#define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE                     0x9188
3226/* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
3227#define PGLUE_B_REG_XSDM_START_OFFSET_A                  0x90ec
3228/* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
3229#define PGLUE_B_REG_XSDM_START_OFFSET_B                  0x90f4
3230/* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
3231#define PGLUE_B_REG_XSDM_VF_SHIFT_B                              0x90fc
3232/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3233#define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF                  0x91a8
3234#define PRS_REG_A_PRSU_20                                        0x40134
3235/* [R 8] debug only: CFC load request current credit. Transaction based. */
3236#define PRS_REG_CFC_LD_CURRENT_CREDIT                            0x40164
3237/* [R 8] debug only: CFC search request current credit. Transaction based. */
3238#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT                        0x40168
3239/* [RW 6] The initial credit for the search message to the CFC interface.
3240   Credit is transaction based. */
3241#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT                        0x4011c
3242/* [RW 24] CID for port 0 if no match */
3243#define PRS_REG_CID_PORT_0                                       0x400fc
3244/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
3245   load response is reset and packet type is 0. Used in packet start message
3246   to TCM. */
3247#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0                         0x400dc
3248#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1                         0x400e0
3249#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2                         0x400e4
3250#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3                         0x400e8
3251#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4                         0x400ec
3252#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5                         0x400f0
3253/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
3254   load response is set and packet type is 0. Used in packet start message
3255   to TCM. */
3256#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0                      0x400bc
3257#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1                      0x400c0
3258#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2                      0x400c4
3259#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3                      0x400c8
3260#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4                      0x400cc
3261#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5                      0x400d0
3262/* [RW 32] The CM header for a match and packet type 1 for loopback port.
3263   Used in packet start message to TCM. */
3264#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1                           0x4009c
3265#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2                           0x400a0
3266#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3                           0x400a4
3267#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4                           0x400a8
3268/* [RW 32] The CM header for a match and packet type 0. Used in packet start
3269   message to TCM. */
3270#define PRS_REG_CM_HDR_TYPE_0                                    0x40078
3271#define PRS_REG_CM_HDR_TYPE_1                                    0x4007c
3272#define PRS_REG_CM_HDR_TYPE_2                                    0x40080
3273#define PRS_REG_CM_HDR_TYPE_3                                    0x40084
3274#define PRS_REG_CM_HDR_TYPE_4                                    0x40088
3275/* [RW 32] The CM header in case there was not a match on the connection */
3276#define PRS_REG_CM_NO_MATCH_HDR                                  0x400b8
3277/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
3278#define PRS_REG_E1HOV_MODE                                       0x401c8
3279/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
3280   start message to TCM. */
3281#define PRS_REG_EVENT_ID_1                                       0x40054
3282#define PRS_REG_EVENT_ID_2                                       0x40058
3283#define PRS_REG_EVENT_ID_3                                       0x4005c
3284/* [RW 16] The Ethernet type value for FCoE */
3285#define PRS_REG_FCOE_TYPE                                        0x401d0
3286/* [RW 8] Context region for flush packet with packet type 0. Used in CFC
3287   load request message. */
3288#define PRS_REG_FLUSH_REGIONS_TYPE_0                             0x40004
3289#define PRS_REG_FLUSH_REGIONS_TYPE_1                             0x40008
3290#define PRS_REG_FLUSH_REGIONS_TYPE_2                             0x4000c
3291#define PRS_REG_FLUSH_REGIONS_TYPE_3                             0x40010
3292#define PRS_REG_FLUSH_REGIONS_TYPE_4                             0x40014
3293#define PRS_REG_FLUSH_REGIONS_TYPE_5                             0x40018
3294#define PRS_REG_FLUSH_REGIONS_TYPE_6                             0x4001c
3295#define PRS_REG_FLUSH_REGIONS_TYPE_7                             0x40020
3296/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3297 * Ethernet header. */
3298#define PRS_REG_HDRS_AFTER_BASIC                                 0x40238
3299/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3300 * Ethernet header for port 0 packets. */
3301#define PRS_REG_HDRS_AFTER_BASIC_PORT_0                          0x40270
3302#define PRS_REG_HDRS_AFTER_BASIC_PORT_1                          0x40290
3303/* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
3304#define PRS_REG_HDRS_AFTER_TAG_0                                 0x40248
3305/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
3306 * port 0 packets */
3307#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0                          0x40280
3308#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1                          0x402a0
3309/* [RW 4] The increment value to send in the CFC load request message */
3310#define PRS_REG_INC_VALUE                                        0x40048
3311/* [RW 6] Bit-map indicating which headers must appear in the packet */
3312#define PRS_REG_MUST_HAVE_HDRS                                   0x40254
3313/* [RW 6] Bit-map indicating which headers must appear in the packet for
3314 * port 0 packets */
3315#define PRS_REG_MUST_HAVE_HDRS_PORT_0                            0x4028c
3316#define PRS_REG_MUST_HAVE_HDRS_PORT_1                            0x402ac
3317#define PRS_REG_NIC_MODE                                         0x40138
3318/* [RW 8] The 8-bit event ID for cases where there is no match on the
3319   connection. Used in packet start message to TCM. */
3320#define PRS_REG_NO_MATCH_EVENT_ID                                0x40070
3321/* [ST 24] The number of input CFC flush packets */
3322#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES                        0x40128
3323/* [ST 32] The number of cycles the Parser halted its operation since it
3324   could not allocate the next serial number */
3325#define PRS_REG_NUM_OF_DEAD_CYCLES                               0x40130
3326/* [ST 24] The number of input packets */
3327#define PRS_REG_NUM_OF_PACKETS                                   0x40124
3328/* [ST 24] The number of input transparent flush packets */
3329#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES                0x4012c
3330/* [RW 8] Context region for received Ethernet packet with a match and
3331   packet type 0. Used in CFC load request message */
3332#define PRS_REG_PACKET_REGIONS_TYPE_0                            0x40028
3333#define PRS_REG_PACKET_REGIONS_TYPE_1                            0x4002c
3334#define PRS_REG_PACKET_REGIONS_TYPE_2                            0x40030
3335#define PRS_REG_PACKET_REGIONS_TYPE_3                            0x40034
3336#define PRS_REG_PACKET_REGIONS_TYPE_4                            0x40038
3337#define PRS_REG_PACKET_REGIONS_TYPE_5                            0x4003c
3338#define PRS_REG_PACKET_REGIONS_TYPE_6                            0x40040
3339#define PRS_REG_PACKET_REGIONS_TYPE_7                            0x40044
3340/* [R 2] debug only: Number of pending requests for CAC on port 0. */
3341#define PRS_REG_PENDING_BRB_CAC0_RQ                              0x40174
3342/* [R 2] debug only: Number of pending requests for header parsing. */
3343#define PRS_REG_PENDING_BRB_PRS_RQ                               0x40170
3344/* [R 1] Interrupt register #0 read */
3345#define PRS_REG_PRS_INT_STS                                      0x40188
3346/* [RW 8] Parity mask register #0 read/write */
3347#define PRS_REG_PRS_PRTY_MASK                                    0x401a4
3348/* [R 8] Parity register #0 read */
3349#define PRS_REG_PRS_PRTY_STS                                     0x40198
3350/* [RC 8] Parity register #0 read clear */
3351#define PRS_REG_PRS_PRTY_STS_CLR                                 0x4019c
3352/* [RW 8] Context region for pure acknowledge packets. Used in CFC load
3353   request message */
3354#define PRS_REG_PURE_REGIONS                                     0x40024
3355/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
3356   serail number was released by SDM but cannot be used because a previous
3357   serial number was not released. */
3358#define PRS_REG_SERIAL_NUM_STATUS_LSB                            0x40154
3359/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
3360   serail number was released by SDM but cannot be used because a previous
3361   serial number was not released. */
3362#define PRS_REG_SERIAL_NUM_STATUS_MSB                            0x40158
3363/* [R 4] debug only: SRC current credit. Transaction based. */
3364#define PRS_REG_SRC_CURRENT_CREDIT                               0x4016c
3365/* [RW 16] The Ethernet type value for L2 tag 0 */
3366#define PRS_REG_TAG_ETHERTYPE_0                                  0x401d4
3367/* [RW 4] The length of the info field for L2 tag 0. The length is between
3368 * 2B and 14B; in 2B granularity */
3369#define PRS_REG_TAG_LEN_0                                        0x4022c
3370/* [R 8] debug only: TCM current credit. Cycle based. */
3371#define PRS_REG_TCM_CURRENT_CREDIT                               0x40160
3372/* [R 8] debug only: TSDM current credit. Transaction based. */
3373#define PRS_REG_TSDM_CURRENT_CREDIT                              0x4015c
3374#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT                     (0x1<<19)
3375#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF                      (0x1<<20)
3376#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN                   (0x1<<22)
3377#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED                (0x1<<23)
3378#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED               (0x1<<24)
3379#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR               (0x1<<7)
3380#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR           (0x1<<7)
3381/* [R 6] Debug only: Number of used entries in the data FIFO */
3382#define PXP2_REG_HST_DATA_FIFO_STATUS                            0x12047c
3383/* [R 7] Debug only: Number of used entries in the header FIFO */
3384#define PXP2_REG_HST_HEADER_FIFO_STATUS                          0x120478
3385#define PXP2_REG_PGL_ADDR_88_F0                                  0x120534
3386/* [R 32] GRC address for configuration access to PCIE config address 0x88.
3387 * any write to this PCIE address will cause a GRC write access to the
3388 * address that's in t this register */
3389#define PXP2_REG_PGL_ADDR_88_F1                                  0x120544
3390#define PXP2_REG_PGL_ADDR_8C_F0                                  0x120538
3391/* [R 32] GRC address for configuration access to PCIE config address 0x8c.
3392 * any write to this PCIE address will cause a GRC write access to the
3393 * address that's in t this register */
3394#define PXP2_REG_PGL_ADDR_8C_F1                                  0x120548
3395#define PXP2_REG_PGL_ADDR_90_F0                                  0x12053c
3396/* [R 32] GRC address for configuration access to PCIE config address 0x90.
3397 * any write to this PCIE address will cause a GRC write access to the
3398 * address that's in t this register */
3399#define PXP2_REG_PGL_ADDR_90_F1                                  0x12054c
3400#define PXP2_REG_PGL_ADDR_94_F0                                  0x120540
3401/* [R 32] GRC address for configuration access to PCIE config address 0x94.
3402 * any write to this PCIE address will cause a GRC write access to the
3403 * address that's in t this register */
3404#define PXP2_REG_PGL_ADDR_94_F1                                  0x120550
3405#define PXP2_REG_PGL_CONTROL0                                    0x120490
3406#define PXP2_REG_PGL_CONTROL1                                    0x120514
3407#define PXP2_REG_PGL_DEBUG                                       0x120520
3408/* [RW 32] third dword data of expansion rom request. this register is
3409   special. reading from it provides a vector outstanding read requests. if
3410   a bit is zero it means that a read request on the corresponding tag did
3411   not finish yet (not all completions have arrived for it) */
3412#define PXP2_REG_PGL_EXP_ROM2                                    0x120808
3413/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
3414   its[15:0]-address */
3415#define PXP2_REG_PGL_INT_CSDM_0                                  0x1204f4
3416#define PXP2_REG_PGL_INT_CSDM_1                                  0x1204f8
3417#define PXP2_REG_PGL_INT_CSDM_2                                  0x1204fc
3418#define PXP2_REG_PGL_INT_CSDM_3                                  0x120500
3419#define PXP2_REG_PGL_INT_CSDM_4                                  0x120504
3420#define PXP2_REG_PGL_INT_CSDM_5                                  0x120508
3421#define PXP2_REG_PGL_INT_CSDM_6                                  0x12050c
3422#define PXP2_REG_PGL_INT_CSDM_7                                  0x120510
3423/* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
3424   its[15:0]-address */
3425#define PXP2_REG_PGL_INT_TSDM_0                                  0x120494
3426#define PXP2_REG_PGL_INT_TSDM_1                                  0x120498
3427#define PXP2_REG_PGL_INT_TSDM_2                                  0x12049c
3428#define PXP2_REG_PGL_INT_TSDM_3                                  0x1204a0
3429#define PXP2_REG_PGL_INT_TSDM_4                                  0x1204a4
3430#define PXP2_REG_PGL_INT_TSDM_5                                  0x1204a8
3431#define PXP2_REG_PGL_INT_TSDM_6                                  0x1204ac
3432#define PXP2_REG_PGL_INT_TSDM_7                                  0x1204b0
3433/* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
3434   its[15:0]-address */
3435#define PXP2_REG_PGL_INT_USDM_0                                  0x1204b4
3436#define PXP2_REG_PGL_INT_USDM_1                                  0x1204b8
3437#define PXP2_REG_PGL_INT_USDM_2                                  0x1204bc
3438#define PXP2_REG_PGL_INT_USDM_3                                  0x1204c0
3439#define PXP2_REG_PGL_INT_USDM_4                                  0x1204c4
3440#define PXP2_REG_PGL_INT_USDM_5                                  0x1204c8
3441#define PXP2_REG_PGL_INT_USDM_6                                  0x1204cc
3442#define PXP2_REG_PGL_INT_USDM_7                                  0x1204d0
3443/* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
3444   its[15:0]-address */
3445#define PXP2_REG_PGL_INT_XSDM_0                                  0x1204d4
3446#define PXP2_REG_PGL_INT_XSDM_1                                  0x1204d8
3447#define PXP2_REG_PGL_INT_XSDM_2                                  0x1204dc
3448#define PXP2_REG_PGL_INT_XSDM_3                                  0x1204e0
3449#define PXP2_REG_PGL_INT_XSDM_4                                  0x1204e4
3450#define PXP2_REG_PGL_INT_XSDM_5                                  0x1204e8
3451#define PXP2_REG_PGL_INT_XSDM_6                                  0x1204ec
3452#define PXP2_REG_PGL_INT_XSDM_7                                  0x1204f0
3453/* [RW 3] this field allows one function to pretend being another function
3454   when accessing any BAR mapped resource within the device. the value of
3455   the field is the number of the function that will be accessed
3456   effectively. after software write to this bit it must read it in order to
3457   know that the new value is updated */
3458#define PXP2_REG_PGL_PRETEND_FUNC_F0                             0x120674
3459#define PXP2_REG_PGL_PRETEND_FUNC_F1                             0x120678
3460#define PXP2_REG_PGL_PRETEND_FUNC_F2                             0x12067c
3461#define PXP2_REG_PGL_PRETEND_FUNC_F3                             0x120680
3462#define PXP2_REG_PGL_PRETEND_FUNC_F4                             0x120684
3463#define PXP2_REG_PGL_PRETEND_FUNC_F5                             0x120688
3464#define PXP2_REG_PGL_PRETEND_FUNC_F6                             0x12068c
3465#define PXP2_REG_PGL_PRETEND_FUNC_F7                             0x120690
3466/* [R 1] this bit indicates that a read request was blocked because of
3467   bus_master_en was deasserted */
3468#define PXP2_REG_PGL_READ_BLOCKED                                0x120568
3469#define PXP2_REG_PGL_TAGS_LIMIT                                  0x1205a8
3470/* [R 18] debug only */
3471#define PXP2_REG_PGL_TXW_CDTS                                    0x12052c
3472/* [R 1] this bit indicates that a write request was blocked because of
3473   bus_master_en was deasserted */
3474#define PXP2_REG_PGL_WRITE_BLOCKED                               0x120564
3475#define PXP2_REG_PSWRQ_BW_ADD1                                   0x1201c0
3476#define PXP2_REG_PSWRQ_BW_ADD10                                  0x1201e4
3477#define PXP2_REG_PSWRQ_BW_ADD11                                  0x1201e8
3478#define PXP2_REG_PSWRQ_BW_ADD2                                   0x1201c4
3479#define PXP2_REG_PSWRQ_BW_ADD28                                  0x120228
3480#define PXP2_REG_PSWRQ_BW_ADD3                                   0x1201c8
3481#define PXP2_REG_PSWRQ_BW_ADD6                                   0x1201d4
3482#define PXP2_REG_PSWRQ_BW_ADD7                                   0x1201d8
3483#define PXP2_REG_PSWRQ_BW_ADD8                                   0x1201dc
3484#define PXP2_REG_PSWRQ_BW_ADD9                                   0x1201e0
3485#define PXP2_REG_PSWRQ_BW_CREDIT                                 0x12032c
3486#define PXP2_REG_PSWRQ_BW_L1                                     0x1202b0
3487#define PXP2_REG_PSWRQ_BW_L10                                    0x1202d4
3488#define PXP2_REG_PSWRQ_BW_L11                                    0x1202d8
3489#define PXP2_REG_PSWRQ_BW_L2                                     0x1202b4
3490#define PXP2_REG_PSWRQ_BW_L28                                    0x120318
3491#define PXP2_REG_PSWRQ_BW_L3                                     0x1202b8
3492#define PXP2_REG_PSWRQ_BW_L6                                     0x1202c4
3493#define PXP2_REG_PSWRQ_BW_L7                                     0x1202c8
3494#define PXP2_REG_PSWRQ_BW_L8                                     0x1202cc
3495#define PXP2_REG_PSWRQ_BW_L9                                     0x1202d0
3496#define PXP2_REG_PSWRQ_BW_RD                                     0x120324
3497#define PXP2_REG_PSWRQ_BW_UB1                                    0x120238
3498#define PXP2_REG_PSWRQ_BW_UB10                                   0x12025c
3499#define PXP2_REG_PSWRQ_BW_UB11                                   0x120260
3500#define PXP2_REG_PSWRQ_BW_UB2                                    0x12023c
3501#define PXP2_REG_PSWRQ_BW_UB28                                   0x1202a0
3502#define PXP2_REG_PSWRQ_BW_UB3                                    0x120240
3503#define PXP2_REG_PSWRQ_BW_UB6                                    0x12024c
3504#define PXP2_REG_PSWRQ_BW_UB7                                    0x120250
3505#define PXP2_REG_PSWRQ_BW_UB8                                    0x120254
3506#define PXP2_REG_PSWRQ_BW_UB9                                    0x120258
3507#define PXP2_REG_PSWRQ_BW_WR                                     0x120328
3508#define PXP2_REG_PSWRQ_CDU0_L2P                                  0x120000
3509#define PXP2_REG_PSWRQ_QM0_L2P                                   0x120038
3510#define PXP2_REG_PSWRQ_SRC0_L2P                                  0x120054
3511#define PXP2_REG_PSWRQ_TM0_L2P                                   0x12001c
3512#define PXP2_REG_PSWRQ_TSDM0_L2P                                 0x1200e0
3513/* [RW 32] Interrupt mask register #0 read/write */
3514#define PXP2_REG_PXP2_INT_MASK_0                                 0x120578
3515/* [R 32] Interrupt register #0 read */
3516#define PXP2_REG_PXP2_INT_STS_0                                  0x12056c
3517#define PXP2_REG_PXP2_INT_STS_1                                  0x120608
3518/* [RC 32] Interrupt register #0 read clear */
3519#define PXP2_REG_PXP2_INT_STS_CLR_0                              0x120570
3520/* [RW 32] Parity mask register #0 read/write */
3521#define PXP2_REG_PXP2_PRTY_MASK_0                                0x120588
3522#define PXP2_REG_PXP2_PRTY_MASK_1                                0x120598
3523/* [R 32] Parity register #0 read */
3524#define PXP2_REG_PXP2_PRTY_STS_0                                 0x12057c
3525#define PXP2_REG_PXP2_PRTY_STS_1                                 0x12058c
3526/* [RC 32] Parity register #0 read clear */
3527#define PXP2_REG_PXP2_PRTY_STS_CLR_0                             0x120580
3528#define PXP2_REG_PXP2_PRTY_STS_CLR_1                             0x120590
3529/* [R 1] Debug only: The 'almost full' indication from each fifo (gives
3530   indication about backpressure) */
3531#define PXP2_REG_RD_ALMOST_FULL_0                                0x120424
3532/* [R 8] Debug only: The blocks counter - number of unused block ids */
3533#define PXP2_REG_RD_BLK_CNT                                      0x120418
3534/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
3535   Must be bigger than 6. Normally should not be changed. */
3536#define PXP2_REG_RD_BLK_NUM_CFG                                  0x12040c
3537/* [RW 2] CDU byte swapping mode configuration for master read requests */
3538#define PXP2_REG_RD_CDURD_SWAP_MODE                              0x120404
3539/* [RW 1] When '1'; inputs to the PSWRD block are ignored */
3540#define PXP2_REG_RD_DISABLE_INPUTS                               0x120374
3541/* [R 1] PSWRD internal memories initialization is done */
3542#define PXP2_REG_RD_INIT_DONE                                    0x120370
3543/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3544   allocated for vq10 */
3545#define PXP2_REG_RD_MAX_BLKS_VQ10                                0x1203a0
3546/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3547   allocated for vq11 */
3548#define PXP2_REG_RD_MAX_BLKS_VQ11                                0x1203a4
3549/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3550   allocated for vq17 */
3551#define PXP2_REG_RD_MAX_BLKS_VQ17                                0x1203bc
3552/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3553   allocated for vq18 */
3554#define PXP2_REG_RD_MAX_BLKS_VQ18                                0x1203c0
3555/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3556   allocated for vq19 */
3557#define PXP2_REG_RD_MAX_BLKS_VQ19                                0x1203c4
3558/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3559   allocated for vq22 */
3560#define PXP2_REG_RD_MAX_BLKS_VQ22                                0x1203d0
3561/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3562   allocated for vq25 */
3563#define PXP2_REG_RD_MAX_BLKS_VQ25                                0x1203dc
3564/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3565   allocated for vq6 */
3566#define PXP2_REG_RD_MAX_BLKS_VQ6                                 0x120390
3567/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3568   allocated for vq9 */
3569#define PXP2_REG_RD_MAX_BLKS_VQ9                                 0x12039c
3570/* [RW 2] PBF byte swapping mode configuration for master read requests */
3571#define PXP2_REG_RD_PBF_SWAP_MODE                                0x1203f4
3572/* [R 1] Debug only: Indication if delivery ports are idle */
3573#define PXP2_REG_RD_PORT_IS_IDLE_0                               0x12041c
3574#define PXP2_REG_RD_PORT_IS_IDLE_1                               0x120420
3575/* [RW 2] QM byte swapping mode configuration for master read requests */
3576#define PXP2_REG_RD_QM_SWAP_MODE                                 0x1203f8
3577/* [R 7] Debug only: The SR counter - number of unused sub request ids */
3578#define PXP2_REG_RD_SR_CNT                                       0x120414
3579/* [RW 2] SRC byte swapping mode configuration for master read requests */
3580#define PXP2_REG_RD_SRC_SWAP_MODE                                0x120400
3581/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
3582   be bigger than 1. Normally should not be changed. */
3583#define PXP2_REG_RD_SR_NUM_CFG                                   0x120408
3584/* [RW 1] Signals the PSWRD block to start initializing internal memories */
3585#define PXP2_REG_RD_START_INIT                                   0x12036c
3586/* [RW 2] TM byte swapping mode configuration for master read requests */
3587#define PXP2_REG_RD_TM_SWAP_MODE                                 0x1203fc
3588/* [RW 10] Bandwidth addition to VQ0 write requests */
3589#define PXP2_REG_RQ_BW_RD_ADD0                                   0x1201bc
3590/* [RW 10] Bandwidth addition to VQ12 read requests */
3591#define PXP2_REG_RQ_BW_RD_ADD12                                  0x1201ec
3592/* [RW 10] Bandwidth addition to VQ13 read requests */
3593#define PXP2_REG_RQ_BW_RD_ADD13                                  0x1201f0
3594/* [RW 10] Bandwidth addition to VQ14 read requests */
3595#define PXP2_REG_RQ_BW_RD_ADD14                                  0x1201f4
3596/* [RW 10] Bandwidth addition to VQ15 read requests */
3597#define PXP2_REG_RQ_BW_RD_ADD15                                  0x1201f8
3598/* [RW 10] Bandwidth addition to VQ16 read requests */
3599#define PXP2_REG_RQ_BW_RD_ADD16                                  0x1201fc
3600/* [RW 10] Bandwidth addition to VQ17 read requests */
3601#define PXP2_REG_RQ_BW_RD_ADD17                                  0x120200
3602/* [RW 10] Bandwidth addition to VQ18 read requests */
3603#define PXP2_REG_RQ_BW_RD_ADD18                                  0x120204
3604/* [RW 10] Bandwidth addition to VQ19 read requests */
3605#define PXP2_REG_RQ_BW_RD_ADD19                                  0x120208
3606/* [RW 10] Bandwidth addition to VQ20 read requests */
3607#define PXP2_REG_RQ_BW_RD_ADD20                                  0x12020c
3608/* [RW 10] Bandwidth addition to VQ22 read requests */
3609#define PXP2_REG_RQ_BW_RD_ADD22                                  0x120210
3610/* [RW 10] Bandwidth addition to VQ23 read requests */
3611#define PXP2_REG_RQ_BW_RD_ADD23                                  0x120214
3612/* [RW 10] Bandwidth addition to VQ24 read requests */
3613#define PXP2_REG_RQ_BW_RD_ADD24                                  0x120218
3614/* [RW 10] Bandwidth addition to VQ25 read requests */
3615#define PXP2_REG_RQ_BW_RD_ADD25                                  0x12021c
3616/* [RW 10] Bandwidth addition to VQ26 read requests */
3617#define PXP2_REG_RQ_BW_RD_ADD26                                  0x120220
3618/* [RW 10] Bandwidth addition to VQ27 read requests */
3619#define PXP2_REG_RQ_BW_RD_ADD27                                  0x120224
3620/* [RW 10] Bandwidth addition to VQ4 read requests */
3621#define PXP2_REG_RQ_BW_RD_ADD4                                   0x1201cc
3622/* [RW 10] Bandwidth addition to VQ5 read requests */
3623#define PXP2_REG_RQ_BW_RD_ADD5                                   0x1201d0
3624/* [RW 10] Bandwidth Typical L for VQ0 Read requests */
3625#define PXP2_REG_RQ_BW_RD_L0                                     0x1202ac
3626/* [RW 10] Bandwidth Typical L for VQ12 Read requests */
3627#define PXP2_REG_RQ_BW_RD_L12                                    0x1202dc
3628/* [RW 10] Bandwidth Typical L for VQ13 Read requests */
3629#define PXP2_REG_RQ_BW_RD_L13                                    0x1202e0
3630/* [RW 10] Bandwidth Typical L for VQ14 Read requests */
3631#define PXP2_REG_RQ_BW_RD_L14                                    0x1202e4
3632/* [RW 10] Bandwidth Typical L for VQ15 Read requests */
3633#define PXP2_REG_RQ_BW_RD_L15                                    0x1202e8
3634/* [RW 10] Bandwidth Typical L for VQ16 Read requests */
3635#define PXP2_REG_RQ_BW_RD_L16                                    0x1202ec
3636/* [RW 10] Bandwidth Typical L for VQ17 Read requests */
3637#define PXP2_REG_RQ_BW_RD_L17                                    0x1202f0
3638/* [RW 10] Bandwidth Typical L for VQ18 Read requests */
3639#define PXP2_REG_RQ_BW_RD_L18                                    0x1202f4
3640/* [RW 10] Bandwidth Typical L for VQ19 Read requests */
3641#define PXP2_REG_RQ_BW_RD_L19                                    0x1202f8
3642/* [RW 10] Bandwidth Typical L for VQ20 Read requests */
3643#define PXP2_REG_RQ_BW_RD_L20                                    0x1202fc
3644/* [RW 10] Bandwidth Typical L for VQ22 Read requests */
3645#define PXP2_REG_RQ_BW_RD_L22                                    0x120300
3646/* [RW 10] Bandwidth Typical L for VQ23 Read requests */
3647#define PXP2_REG_RQ_BW_RD_L23                                    0x120304
3648/* [RW 10] Bandwidth Typical L for VQ24 Read requests */
3649#define PXP2_REG_RQ_BW_RD_L24                                    0x120308
3650/* [RW 10] Bandwidth Typical L for VQ25 Read requests */
3651#define PXP2_REG_RQ_BW_RD_L25                                    0x12030c
3652/* [RW 10] Bandwidth Typical L for VQ26 Read requests */
3653#define PXP2_REG_RQ_BW_RD_L26                                    0x120310
3654/* [RW 10] Bandwidth Typical L for VQ27 Read requests */
3655#define PXP2_REG_RQ_BW_RD_L27                                    0x120314
3656/* [RW 10] Bandwidth Typical L for VQ4 Read requests */
3657#define PXP2_REG_RQ_BW_RD_L4                                     0x1202bc
3658/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
3659#define PXP2_REG_RQ_BW_RD_L5                                     0x1202c0
3660/* [RW 7] Bandwidth upper bound for VQ0 read requests */
3661#define PXP2_REG_RQ_BW_RD_UBOUND0                                0x120234
3662/* [RW 7] Bandwidth upper bound for VQ12 read requests */
3663#define PXP2_REG_RQ_BW_RD_UBOUND12                               0x120264
3664/* [RW 7] Bandwidth upper bound for VQ13 read requests */
3665#define PXP2_REG_RQ_BW_RD_UBOUND13                               0x120268
3666/* [RW 7] Bandwidth upper bound for VQ14 read requests */
3667#define PXP2_REG_RQ_BW_RD_UBOUND14                               0x12026c
3668/* [RW 7] Bandwidth upper bound for VQ15 read requests */
3669#define PXP2_REG_RQ_BW_RD_UBOUND15                               0x120270
3670/* [RW 7] Bandwidth upper bound for VQ16 read requests */
3671#define PXP2_REG_RQ_BW_RD_UBOUND16                               0x120274
3672/* [RW 7] Bandwidth upper bound for VQ17 read requests */
3673#define PXP2_REG_RQ_BW_RD_UBOUND17                               0x120278
3674/* [RW 7] Bandwidth upper bound for VQ18 read requests */
3675#define PXP2_REG_RQ_BW_RD_UBOUND18                               0x12027c
3676/* [RW 7] Bandwidth upper bound for VQ19 read requests */
3677#define PXP2_REG_RQ_BW_RD_UBOUND19                               0x120280
3678/* [RW 7] Bandwidth upper bound for VQ20 read requests */
3679#define PXP2_REG_RQ_BW_RD_UBOUND20                               0x120284
3680/* [RW 7] Bandwidth upper bound for VQ22 read requests */
3681#define PXP2_REG_RQ_BW_RD_UBOUND22                               0x120288
3682/* [RW 7] Bandwidth upper bound for VQ23 read requests */
3683#define PXP2_REG_RQ_BW_RD_UBOUND23                               0x12028c
3684/* [RW 7] Bandwidth upper bound for VQ24 read requests */
3685#define PXP2_REG_RQ_BW_RD_UBOUND24                               0x120290
3686/* [RW 7] Bandwidth upper bound for VQ25 read requests */
3687#define PXP2_REG_RQ_BW_RD_UBOUND25                               0x120294
3688/* [RW 7] Bandwidth upper bound for VQ26 read requests */
3689#define PXP2_REG_RQ_BW_RD_UBOUND26                               0x120298
3690/* [RW 7] Bandwidth upper bound for VQ27 read requests */
3691#define PXP2_REG_RQ_BW_RD_UBOUND27                               0x12029c
3692/* [RW 7] Bandwidth upper bound for VQ4 read requests */
3693#define PXP2_REG_RQ_BW_RD_UBOUND4                                0x120244
3694/* [RW 7] Bandwidth upper bound for VQ5 read requests */
3695#define PXP2_REG_RQ_BW_RD_UBOUND5                                0x120248
3696/* [RW 10] Bandwidth addition to VQ29 write requests */
3697#define PXP2_REG_RQ_BW_WR_ADD29                                  0x12022c
3698/* [RW 10] Bandwidth addition to VQ30 write requests */
3699#define PXP2_REG_RQ_BW_WR_ADD30                                  0x120230
3700/* [RW 10] Bandwidth Typical L for VQ29 Write requests */
3701#define PXP2_REG_RQ_BW_WR_L29                                    0x12031c
3702/* [RW 10] Bandwidth Typical L for VQ30 Write requests */
3703#define PXP2_REG_RQ_BW_WR_L30                                    0x120320
3704/* [RW 7] Bandwidth upper bound for VQ29 */
3705#define PXP2_REG_RQ_BW_WR_UBOUND29                               0x1202a4
3706/* [RW 7] Bandwidth upper bound for VQ30 */
3707#define PXP2_REG_RQ_BW_WR_UBOUND30                               0x1202a8
3708/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
3709#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR                         0x120008
3710/* [RW 2] Endian mode for cdu */
3711#define PXP2_REG_RQ_CDU_ENDIAN_M                                 0x1201a0
3712#define PXP2_REG_RQ_CDU_FIRST_ILT                                0x12061c
3713#define PXP2_REG_RQ_CDU_LAST_ILT                                 0x120620
3714/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
3715   -128k */
3716#define PXP2_REG_RQ_CDU_P_SIZE                                   0x120018
3717/* [R 1] 1' indicates that the requester has finished its internal
3718   configuration */
3719#define PXP2_REG_RQ_CFG_DONE                                     0x1201b4
3720/* [RW 2] Endian mode for debug */
3721#define PXP2_REG_RQ_DBG_ENDIAN_M                                 0x1201a4
3722/* [RW 1] When '1'; requests will enter input buffers but wont get out
3723   towards the glue */
3724#define PXP2_REG_RQ_DISABLE_INPUTS                               0x120330
3725/* [RW 4] Determines alignment of write SRs when a request is split into
3726 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3727 * aligned. 4 - 512B aligned. */
3728#define PXP2_REG_RQ_DRAM_ALIGN                                   0x1205b0
3729/* [RW 4] Determines alignment of read SRs when a request is split into
3730 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3731 * aligned. 4 - 512B aligned. */
3732#define PXP2_REG_RQ_DRAM_ALIGN_RD                                0x12092c
3733/* [RW 1] when set the new alignment method (E2) will be applied; when reset
3734 * the original alignment method (E1 E1H) will be applied */
3735#define PXP2_REG_RQ_DRAM_ALIGN_SEL                               0x120930
3736/* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
3737   be asserted */
3738#define PXP2_REG_RQ_ELT_DISABLE                                  0x12066c
3739/* [RW 2] Endian mode for hc */
3740#define PXP2_REG_RQ_HC_ENDIAN_M                                  0x1201a8
3741/* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
3742   compatibility needs; Note that different registers are used per mode */
3743#define PXP2_REG_RQ_ILT_MODE                                     0x1205b4
3744/* [WB 53] Onchip address table */
3745#define PXP2_REG_RQ_ONCHIP_AT                                    0x122000
3746/* [WB 53] Onchip address table - B0 */
3747#define PXP2_REG_RQ_ONCHIP_AT_B0                                 0x128000
3748/* [RW 13] Pending read limiter threshold; in Dwords */
3749#define PXP2_REG_RQ_PDR_LIMIT                                    0x12033c
3750/* [RW 2] Endian mode for qm */
3751#define PXP2_REG_RQ_QM_ENDIAN_M                                  0x120194
3752#define PXP2_REG_RQ_QM_FIRST_ILT                                 0x120634
3753#define PXP2_REG_RQ_QM_LAST_ILT                                  0x120638
3754/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
3755   -128k */
3756#define PXP2_REG_RQ_QM_P_SIZE                                    0x120050
3757/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
3758#define PXP2_REG_RQ_RBC_DONE                                     0x1201b0
3759/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3760   001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3761#define PXP2_REG_RQ_RD_MBS0                                      0x120160
3762/* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
3763   001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3764#define PXP2_REG_RQ_RD_MBS1                                      0x120168
3765/* [RW 2] Endian mode for src */
3766#define PXP2_REG_RQ_SRC_ENDIAN_M                                 0x12019c
3767#define PXP2_REG_RQ_SRC_FIRST_ILT                                0x12063c
3768#define PXP2_REG_RQ_SRC_LAST_ILT                                 0x120640
3769/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
3770   -128k */
3771#define PXP2_REG_RQ_SRC_P_SIZE                                   0x12006c
3772/* [RW 2] Endian mode for tm */
3773#define PXP2_REG_RQ_TM_ENDIAN_M                                  0x120198
3774#define PXP2_REG_RQ_TM_FIRST_ILT                                 0x120644
3775#define PXP2_REG_RQ_TM_LAST_ILT                                  0x120648
3776/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
3777   -128k */
3778#define PXP2_REG_RQ_TM_P_SIZE                                    0x120034
3779/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
3780#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY                           0x12080c
3781/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
3782#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR                        0x120094
3783/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
3784#define PXP2_REG_RQ_VQ0_ENTRY_CNT                                0x120810
3785/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
3786#define PXP2_REG_RQ_VQ10_ENTRY_CNT                               0x120818
3787/* [R 8] Number of entries occupied by vq 11 in pswrq memory */
3788#define PXP2_REG_RQ_VQ11_ENTRY_CNT                               0x120820
3789/* [R 8] Number of entries occupied by vq 12 in pswrq memory */
3790#define PXP2_REG_RQ_VQ12_ENTRY_CNT                               0x120828
3791/* [R 8] Number of entries occupied by vq 13 in pswrq memory */
3792#define PXP2_REG_RQ_VQ13_ENTRY_CNT                               0x120830
3793/* [R 8] Number of entries occupied by vq 14 in pswrq memory */
3794#define PXP2_REG_RQ_VQ14_ENTRY_CNT                               0x120838
3795/* [R 8] Number of entries occupied by vq 15 in pswrq memory */
3796#define PXP2_REG_RQ_VQ15_ENTRY_CNT                               0x120840
3797/* [R 8] Number of entries occupied by vq 16 in pswrq memory */
3798#define PXP2_REG_RQ_VQ16_ENTRY_CNT                               0x120848
3799/* [R 8] Number of entries occupied by vq 17 in pswrq memory */
3800#define PXP2_REG_RQ_VQ17_ENTRY_CNT                               0x120850
3801/* [R 8] Number of entries occupied by vq 18 in pswrq memory */
3802#define PXP2_REG_RQ_VQ18_ENTRY_CNT                               0x120858
3803/* [R 8] Number of entries occupied by vq 19 in pswrq memory */
3804#define PXP2_REG_RQ_VQ19_ENTRY_CNT                               0x120860
3805/* [R 8] Number of entries occupied by vq 1 in pswrq memory */
3806#define PXP2_REG_RQ_VQ1_ENTRY_CNT                                0x120868
3807/* [R 8] Number of entries occupied by vq 20 in pswrq memory */
3808#define PXP2_REG_RQ_VQ20_ENTRY_CNT                               0x120870
3809/* [R 8] Number of entries occupied by vq 21 in pswrq memory */
3810#define PXP2_REG_RQ_VQ21_ENTRY_CNT                               0x120878
3811/* [R 8] Number of entries occupied by vq 22 in pswrq memory */
3812#define PXP2_REG_RQ_VQ22_ENTRY_CNT                               0x120880
3813/* [R 8] Number of entries occupied by vq 23 in pswrq memory */
3814#define PXP2_REG_RQ_VQ23_ENTRY_CNT                               0x120888
3815/* [R 8] Number of entries occupied by vq 24 in pswrq memory */
3816#define PXP2_REG_RQ_VQ24_ENTRY_CNT                               0x120890
3817/* [R 8] Number of entries occupied by vq 25 in pswrq memory */
3818#define PXP2_REG_RQ_VQ25_ENTRY_CNT                               0x120898
3819/* [R 8] Number of entries occupied by vq 26 in pswrq memory */
3820#define PXP2_REG_RQ_VQ26_ENTRY_CNT                               0x1208a0
3821/* [R 8] Number of entries occupied by vq 27 in pswrq memory */
3822#define PXP2_REG_RQ_VQ27_ENTRY_CNT                               0x1208a8
3823/* [R 8] Number of entries occupied by vq 28 in pswrq memory */
3824#define PXP2_REG_RQ_VQ28_ENTRY_CNT                               0x1208b0
3825/* [R 8] Number of entries occupied by vq 29 in pswrq memory */
3826#define PXP2_REG_RQ_VQ29_ENTRY_CNT                               0x1208b8
3827/* [R 8] Number of entries occupied by vq 2 in pswrq memory */
3828#define PXP2_REG_RQ_VQ2_ENTRY_CNT                                0x1208c0
3829/* [R 8] Number of entries occupied by vq 30 in pswrq memory */
3830#define PXP2_REG_RQ_VQ30_ENTRY_CNT                               0x1208c8
3831/* [R 8] Number of entries occupied by vq 31 in pswrq memory */
3832#define PXP2_REG_RQ_VQ31_ENTRY_CNT                               0x1208d0
3833/* [R 8] Number of entries occupied by vq 3 in pswrq memory */
3834#define PXP2_REG_RQ_VQ3_ENTRY_CNT                                0x1208d8
3835/* [R 8] Number of entries occupied by vq 4 in pswrq memory */
3836#define PXP2_REG_RQ_VQ4_ENTRY_CNT                                0x1208e0
3837/* [R 8] Number of entries occupied by vq 5 in pswrq memory */
3838#define PXP2_REG_RQ_VQ5_ENTRY_CNT                                0x1208e8
3839/* [R 8] Number of entries occupied by vq 6 in pswrq memory */
3840#define PXP2_REG_RQ_VQ6_ENTRY_CNT                                0x1208f0
3841/* [R 8] Number of entries occupied by vq 7 in pswrq memory */
3842#define PXP2_REG_RQ_VQ7_ENTRY_CNT                                0x1208f8
3843/* [R 8] Number of entries occupied by vq 8 in pswrq memory */
3844#define PXP2_REG_RQ_VQ8_ENTRY_CNT                                0x120900
3845/* [R 8] Number of entries occupied by vq 9 in pswrq memory */
3846#define PXP2_REG_RQ_VQ9_ENTRY_CNT                                0x120908
3847/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3848   001:256B; 010: 512B; */
3849#define PXP2_REG_RQ_WR_MBS0                                      0x12015c
3850/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
3851   001:256B; 010: 512B; */
3852#define PXP2_REG_RQ_WR_MBS1                                      0x120164
3853/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3854   buffer reaches this number has_payload will be asserted */
3855#define PXP2_REG_WR_CDU_MPS                                      0x1205f0
3856/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3857   buffer reaches this number has_payload will be asserted */
3858#define PXP2_REG_WR_CSDM_MPS                                     0x1205d0
3859/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3860   buffer reaches this number has_payload will be asserted */
3861#define PXP2_REG_WR_DBG_MPS                                      0x1205e8
3862/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3863   buffer reaches this number has_payload will be asserted */
3864#define PXP2_REG_WR_DMAE_MPS                                     0x1205ec
3865/* [RW 10] if Number of entries in dmae fifo will be higher than this
3866   threshold then has_payload indication will be asserted; the default value
3867   should be equal to &gt;  write MBS size! */
3868#define PXP2_REG_WR_DMAE_TH                                      0x120368
3869/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3870   buffer reaches this number has_payload will be asserted */
3871#define PXP2_REG_WR_HC_MPS                                       0x1205c8
3872/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3873   buffer reaches this number has_payload will be asserted */
3874#define PXP2_REG_WR_QM_MPS                                       0x1205dc
3875/* [RW 1] 0 - working in A0 mode;  - working in B0 mode */
3876#define PXP2_REG_WR_REV_MODE                                     0x120670
3877/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3878   buffer reaches this number has_payload will be asserted */
3879#define PXP2_REG_WR_SRC_MPS                                      0x1205e4
3880/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3881   buffer reaches this number has_payload will be asserted */
3882#define PXP2_REG_WR_TM_MPS                                       0x1205e0
3883/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3884   buffer reaches this number has_payload will be asserted */
3885#define PXP2_REG_WR_TSDM_MPS                                     0x1205d4
3886/* [RW 10] if Number of entries in usdmdp fifo will be higher than this
3887   threshold then has_payload indication will be asserted; the default value
3888   should be equal to &gt;  write MBS size! */
3889#define PXP2_REG_WR_USDMDP_TH                                    0x120348
3890/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3891   buffer reaches this number has_payload will be asserted */
3892#define PXP2_REG_WR_USDM_MPS                                     0x1205cc
3893/* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3894   buffer reaches this number has_payload will be asserted */
3895#define PXP2_REG_WR_XSDM_MPS                                     0x1205d8
3896/* [R 1] debug only: Indication if PSWHST arbiter is idle */
3897#define PXP_REG_HST_ARB_IS_IDLE                                  0x103004
3898/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
3899   this client is waiting for the arbiter. */
3900#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB                       0x103008
3901/* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
3902   block. Should be used for close the gates. */
3903#define PXP_REG_HST_DISCARD_DOORBELLS                            0x1030a4
3904/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
3905   should update according to 'hst_discard_doorbells' register when the state
3906   machine is idle */
3907#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS                     0x1030a0
3908/* [RW 1] When 1; new internal writes arriving to the block are discarded.
3909   Should be used for close the gates. */
3910#define PXP_REG_HST_DISCARD_INTERNAL_WRITES                      0x1030a8
3911/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
3912   means this PSWHST is discarding inputs from this client. Each bit should
3913   update according to 'hst_discard_internal_writes' register when the state
3914   machine is idle. */
3915#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS               0x10309c
3916/* [WB 160] Used for initialization of the inbound interrupts memory */
3917#define PXP_REG_HST_INBOUND_INT                                  0x103800
3918/* [RW 7] Indirect access to the permission table. The fields are : {Valid;
3919 * VFID[5:0]}
3920 */
3921#define PXP_REG_HST_ZONE_PERMISSION_TABLE                        0x103400
3922/* [RW 32] Interrupt mask register #0 read/write */
3923#define PXP_REG_PXP_INT_MASK_0                                   0x103074
3924#define PXP_REG_PXP_INT_MASK_1                                   0x103084
3925/* [R 32] Interrupt register #0 read */
3926#define PXP_REG_PXP_INT_STS_0                                    0x103068
3927#define PXP_REG_PXP_INT_STS_1                                    0x103078
3928/* [RC 32] Interrupt register #0 read clear */
3929#define PXP_REG_PXP_INT_STS_CLR_0                                0x10306c
3930#define PXP_REG_PXP_INT_STS_CLR_1                                0x10307c
3931/* [RW 27] Parity mask register #0 read/write */
3932#define PXP_REG_PXP_PRTY_MASK                                    0x103094
3933/* [R 26] Parity register #0 read */
3934#define PXP_REG_PXP_PRTY_STS                                     0x103088
3935/* [RC 27] Parity register #0 read clear */
3936#define PXP_REG_PXP_PRTY_STS_CLR                                 0x10308c
3937/* [RW 4] The activity counter initial increment value sent in the load
3938   request */
3939#define QM_REG_ACTCTRINITVAL_0                                   0x168040
3940#define QM_REG_ACTCTRINITVAL_1                                   0x168044
3941#define QM_REG_ACTCTRINITVAL_2                                   0x168048
3942#define QM_REG_ACTCTRINITVAL_3                                   0x16804c
3943/* [RW 32] The base logical address (in bytes) of each physical queue. The
3944   index I represents the physical queue number. The 12 lsbs are ignore and
3945   considered zero so practically there are only 20 bits in this register;
3946   queues 63-0 */
3947#define QM_REG_BASEADDR                                          0x168900
3948/* [RW 32] The base logical address (in bytes) of each physical queue. The
3949   index I represents the physical queue number. The 12 lsbs are ignore and
3950   considered zero so practically there are only 20 bits in this register;
3951   queues 127-64 */
3952#define QM_REG_BASEADDR_EXT_A                                    0x16e100
3953/* [RW 16] The byte credit cost for each task. This value is for both ports */
3954#define QM_REG_BYTECRDCOST                                       0x168234
3955/* [RW 16] The initial byte credit value for both ports. */
3956#define QM_REG_BYTECRDINITVAL                                    0x168238
3957/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3958   queue uses port 0 else it uses port 1; queues 31-0 */
3959#define QM_REG_BYTECRDPORT_LSB                                   0x168228
3960/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3961   queue uses port 0 else it uses port 1; queues 95-64 */
3962#define QM_REG_BYTECRDPORT_LSB_EXT_A                             0x16e520
3963/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3964   queue uses port 0 else it uses port 1; queues 63-32 */
3965#define QM_REG_BYTECRDPORT_MSB                                   0x168224
3966/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3967   queue uses port 0 else it uses port 1; queues 127-96 */
3968#define QM_REG_BYTECRDPORT_MSB_EXT_A                             0x16e51c
3969/* [RW 16] The byte credit value that if above the QM is considered almost
3970   full */
3971#define QM_REG_BYTECREDITAFULLTHR                                0x168094
3972/* [RW 4] The initial credit for interface */
3973#define QM_REG_CMINITCRD_0                                       0x1680cc
3974#define QM_REG_BYTECRDCMDQ_0                                     0x16e6e8
3975#define QM_REG_CMINITCRD_1                                       0x1680d0
3976#define QM_REG_CMINITCRD_2                                       0x1680d4
3977#define QM_REG_CMINITCRD_3                                       0x1680d8
3978#define QM_REG_CMINITCRD_4                                       0x1680dc
3979#define QM_REG_CMINITCRD_5                                       0x1680e0
3980#define QM_REG_CMINITCRD_6                                       0x1680e4
3981#define QM_REG_CMINITCRD_7                                       0x1680e8
3982/* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
3983   is masked */
3984#define QM_REG_CMINTEN                                           0x1680ec
3985/* [RW 12] A bit vector which indicates which one of the queues are tied to
3986   interface 0 */
3987#define QM_REG_CMINTVOQMASK_0                                    0x1681f4
3988#define QM_REG_CMINTVOQMASK_1                                    0x1681f8
3989#define QM_REG_CMINTVOQMASK_2                                    0x1681fc
3990#define QM_REG_CMINTVOQMASK_3                                    0x168200
3991#define QM_REG_CMINTVOQMASK_4                                    0x168204
3992#define QM_REG_CMINTVOQMASK_5                                    0x168208
3993#define QM_REG_CMINTVOQMASK_6                                    0x16820c
3994#define QM_REG_CMINTVOQMASK_7                                    0x168210
3995/* [RW 20] The number of connections divided by 16 which dictates the size
3996   of each queue which belongs to even function number. */
3997#define QM_REG_CONNNUM_0                                         0x168020
3998/* [R 6] Keep the fill level of the fifo from write client 4 */
3999#define QM_REG_CQM_WRC_FIFOLVL                                   0x168018
4000/* [RW 8] The context regions sent in the CFC load request */
4001#define QM_REG_CTXREG_0                                          0x168030
4002#define QM_REG_CTXREG_1                                          0x168034
4003#define QM_REG_CTXREG_2                                          0x168038
4004#define QM_REG_CTXREG_3                                          0x16803c
4005/* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
4006   bypass enable */
4007#define QM_REG_ENBYPVOQMASK                                      0x16823c
4008/* [RW 32] A bit mask per each physical queue. If a bit is set then the
4009   physical queue uses the byte credit; queues 31-0 */
4010#define QM_REG_ENBYTECRD_LSB                                     0x168220
4011/* [RW 32] A bit mask per each physical queue. If a bit is set then the
4012   physical queue uses the byte credit; queues 95-64 */
4013#define QM_REG_ENBYTECRD_LSB_EXT_A                               0x16e518
4014/* [RW 32] A bit mask per each physical queue. If a bit is set then the
4015   physical queue uses the byte credit; queues 63-32 */
4016#define QM_REG_ENBYTECRD_MSB                                     0x16821c
4017/* [RW 32] A bit mask per each physical queue. If a bit is set then the
4018   physical queue uses the byte credit; queues 127-96 */
4019#define QM_REG_ENBYTECRD_MSB_EXT_A                               0x16e514
4020/* [RW 4] If cleared then the secondary interface will not be served by the
4021   RR arbiter */
4022#define QM_REG_ENSEC                                             0x1680f0
4023/* [RW 32] NA */
4024#define QM_REG_FUNCNUMSEL_LSB                                    0x168230
4025/* [RW 32] NA */
4026#define QM_REG_FUNCNUMSEL_MSB                                    0x16822c
4027/* [RW 32] A mask register to mask the Almost empty signals which will not
4028   be use for the almost empty indication to the HW block; queues 31:0 */
4029#define QM_REG_HWAEMPTYMASK_LSB                                  0x168218
4030/* [RW 32] A mask register to mask the Almost empty signals which will not
4031   be use for the almost empty indication to the HW block; queues 95-64 */
4032#define QM_REG_HWAEMPTYMASK_LSB_EXT_A                            0x16e510
4033/* [RW 32] A mask register to mask the Almost empty signals which will not
4034   be use for the almost empty indication to the HW block; queues 63:32 */
4035#define QM_REG_HWAEMPTYMASK_MSB                                  0x168214
4036/* [RW 32] A mask register to mask the Almost empty signals which will not
4037   be use for the almost empty indication to the HW block; queues 127-96 */
4038#define QM_REG_HWAEMPTYMASK_MSB_EXT_A                            0x16e50c
4039/* [RW 4] The number of outstanding request to CFC */
4040#define QM_REG_OUTLDREQ                                          0x168804
4041/* [RC 1] A flag to indicate that overflow error occurred in one of the
4042   queues. */
4043#define QM_REG_OVFERROR                                          0x16805c
4044/* [RC 7] the Q where the overflow occurs */
4045#define QM_REG_OVFQNUM                                           0x168058
4046/* [R 16] Pause state for physical queues 15-0 */
4047#define QM_REG_PAUSESTATE0                                       0x168410
4048/* [R 16] Pause state for physical queues 31-16 */
4049#define QM_REG_PAUSESTATE1                                       0x168414
4050/* [R 16] Pause state for physical queues 47-32 */
4051#define QM_REG_PAUSESTATE2                                       0x16e684
4052/* [R 16] Pause state for physical queues 63-48 */
4053#define QM_REG_PAUSESTATE3                                       0x16e688
4054/* [R 16] Pause state for physical queues 79-64 */
4055#define QM_REG_PAUSESTATE4                                       0x16e68c
4056/* [R 16] Pause state for physical queues 95-80 */
4057#define QM_REG_PAUSESTATE5                                       0x16e690
4058/* [R 16] Pause state for physical queues 111-96 */
4059#define QM_REG_PAUSESTATE6                                       0x16e694
4060/* [R 16] Pause state for physical queues 127-112 */
4061#define QM_REG_PAUSESTATE7                                       0x16e698
4062/* [RW 2] The PCI attributes field used in the PCI request. */
4063#define QM_REG_PCIREQAT                                          0x168054
4064#define QM_REG_PF_EN                                             0x16e70c
4065/* [R 24] The number of tasks stored in the QM for the PF. only even
4066 * functions are valid in E2 (odd I registers will be hard wired to 0) */
4067#define QM_REG_PF_USG_CNT_0                                      0x16e040
4068/* [R 16] NOT USED */
4069#define QM_REG_PORT0BYTECRD                                      0x168300
4070/* [R 16] The byte credit of port 1 */
4071#define QM_REG_PORT1BYTECRD                                      0x168304
4072/* [RW 3] pci function number of queues 15-0 */
4073#define QM_REG_PQ2PCIFUNC_0                                      0x16e6bc
4074#define QM_REG_PQ2PCIFUNC_1                                      0x16e6c0
4075#define QM_REG_PQ2PCIFUNC_2                                      0x16e6c4
4076#define QM_REG_PQ2PCIFUNC_3                                      0x16e6c8
4077#define QM_REG_PQ2PCIFUNC_4                                      0x16e6cc
4078#define QM_REG_PQ2PCIFUNC_5                                      0x16e6d0
4079#define QM_REG_PQ2PCIFUNC_6                                      0x16e6d4
4080#define QM_REG_PQ2PCIFUNC_7                                      0x16e6d8
4081/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
4082   ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
4083   bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
4084#define QM_REG_PTRTBL                                            0x168a00
4085/* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
4086   ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
4087   bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
4088#define QM_REG_PTRTBL_EXT_A                                      0x16e200
4089/* [RW 2] Interrupt mask register #0 read/write */
4090#define QM_REG_QM_INT_MASK                                       0x168444
4091/* [R 2] Interrupt register #0 read */
4092#define QM_REG_QM_INT_STS                                        0x168438
4093/* [RW 12] Parity mask register #0 read/write */
4094#define QM_REG_QM_PRTY_MASK                                      0x168454
4095/* [R 12] Parity register #0 read */
4096#define QM_REG_QM_PRTY_STS                                       0x168448
4097/* [RC 12] Parity register #0 read clear */
4098#define QM_REG_QM_PRTY_STS_CLR                                   0x16844c
4099/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
4100#define QM_REG_QSTATUS_HIGH                                      0x16802c
4101/* [R 32] Current queues in pipeline: Queues from 96 to 127 */
4102#define QM_REG_QSTATUS_HIGH_EXT_A                                0x16e408
4103/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
4104#define QM_REG_QSTATUS_LOW                                       0x168028
4105/* [R 32] Current queues in pipeline: Queues from 64 to 95 */
4106#define QM_REG_QSTATUS_LOW_EXT_A                                 0x16e404
4107/* [R 24] The number of tasks queued for each queue; queues 63-0 */
4108#define QM_REG_QTASKCTR_0                                        0x168308
4109/* [R 24] The number of tasks queued for each queue; queues 127-64 */
4110#define QM_REG_QTASKCTR_EXT_A_0                                  0x16e584
4111/* [RW 4] Queue tied to VOQ */
4112#define QM_REG_QVOQIDX_0                                         0x1680f4
4113#define QM_REG_QVOQIDX_10                                        0x16811c
4114#define QM_REG_QVOQIDX_100                                       0x16e49c
4115#define QM_REG_QVOQIDX_101                                       0x16e4a0
4116#define QM_REG_QVOQIDX_102                                       0x16e4a4
4117#define QM_REG_QVOQIDX_103                                       0x16e4a8
4118#define QM_REG_QVOQIDX_104                                       0x16e4ac
4119#define QM_REG_QVOQIDX_105                                       0x16e4b0
4120#define QM_REG_QVOQIDX_106                                       0x16e4b4
4121#define QM_REG_QVOQIDX_107                                       0x16e4b8
4122#define QM_REG_QVOQIDX_108                                       0x16e4bc
4123#define QM_REG_QVOQIDX_109                                       0x16e4c0
4124#define QM_REG_QVOQIDX_11                                        0x168120
4125#define QM_REG_QVOQIDX_110                                       0x16e4c4
4126#define QM_REG_QVOQIDX_111                                       0x16e4c8
4127#define QM_REG_QVOQIDX_112                                       0x16e4cc
4128#define QM_REG_QVOQIDX_113                                       0x16e4d0
4129#define QM_REG_QVOQIDX_114                                       0x16e4d4
4130#define QM_REG_QVOQIDX_115                                       0x16e4d8
4131#define QM_REG_QVOQIDX_116                                       0x16e4dc
4132#define QM_REG_QVOQIDX_117                                       0x16e4e0
4133#define QM_REG_QVOQIDX_118                                       0x16e4e4
4134#define QM_REG_QVOQIDX_119                                       0x16e4e8
4135#define QM_REG_QVOQIDX_12                                        0x168124
4136#define QM_REG_QVOQIDX_120                                       0x16e4ec
4137#define QM_REG_QVOQIDX_121                                       0x16e4f0
4138#define QM_REG_QVOQIDX_122                                       0x16e4f4
4139#define QM_REG_QVOQIDX_123                                       0x16e4f8
4140#define QM_REG_QVOQIDX_124                                       0x16e4fc
4141#define QM_REG_QVOQIDX_125                                       0x16e500
4142#define QM_REG_QVOQIDX_126                                       0x16e504
4143#define QM_REG_QVOQIDX_127                                       0x16e508
4144#define QM_REG_QVOQIDX_13                                        0x168128
4145#define QM_REG_QVOQIDX_14                                        0x16812c
4146#define QM_REG_QVOQIDX_15                                        0x168130
4147#define QM_REG_QVOQIDX_16                                        0x168134
4148#define QM_REG_QVOQIDX_17                                        0x168138
4149#define QM_REG_QVOQIDX_21                                        0x168148
4150#define QM_REG_QVOQIDX_22                                        0x16814c
4151#define QM_REG_QVOQIDX_23                                        0x168150
4152#define QM_REG_QVOQIDX_24                                        0x168154
4153#define QM_REG_QVOQIDX_25                                        0x168158
4154#define QM_REG_QVOQIDX_26                                        0x16815c
4155#define QM_REG_QVOQIDX_27                                        0x168160
4156#define QM_REG_QVOQIDX_28                                        0x168164
4157#define QM_REG_QVOQIDX_29                                        0x168168
4158#define QM_REG_QVOQIDX_30                                        0x16816c
4159#define QM_REG_QVOQIDX_31                                        0x168170
4160#define QM_REG_QVOQIDX_32                                        0x168174
4161#define QM_REG_QVOQIDX_33                                        0x168178
4162#define QM_REG_QVOQIDX_34                                        0x16817c
4163#define QM_REG_QVOQIDX_35                                        0x168180
4164#define QM_REG_QVOQIDX_36                                        0x168184
4165#define QM_REG_QVOQIDX_37                                        0x168188
4166#define QM_REG_QVOQIDX_38                                        0x16818c
4167#define QM_REG_QVOQIDX_39                                        0x168190
4168#define QM_REG_QVOQIDX_40                                        0x168194
4169#define QM_REG_QVOQIDX_41                                        0x168198
4170#define QM_REG_QVOQIDX_42                                        0x16819c
4171#define QM_REG_QVOQIDX_43                                        0x1681a0
4172#define QM_REG_QVOQIDX_44                                        0x1681a4
4173#define QM_REG_QVOQIDX_45                                        0x1681a8
4174#define QM_REG_QVOQIDX_46                                        0x1681ac
4175#define QM_REG_QVOQIDX_47                                        0x1681b0
4176#define QM_REG_QVOQIDX_48                                        0x1681b4
4177#define QM_REG_QVOQIDX_49                                        0x1681b8
4178#define QM_REG_QVOQIDX_5                                         0x168108
4179#define QM_REG_QVOQIDX_50                                        0x1681bc
4180#define QM_REG_QVOQIDX_51                                        0x1681c0
4181#define QM_REG_QVOQIDX_52                                        0x1681c4
4182#define QM_REG_QVOQIDX_53                                        0x1681c8
4183#define QM_REG_QVOQIDX_54                                        0x1681cc
4184#define QM_REG_QVOQIDX_55                                        0x1681d0
4185#define QM_REG_QVOQIDX_56                                        0x1681d4
4186#define QM_REG_QVOQIDX_57                                        0x1681d8
4187#define QM_REG_QVOQIDX_58                                        0x1681dc
4188#define QM_REG_QVOQIDX_59                                        0x1681e0
4189#define QM_REG_QVOQIDX_6                                         0x16810c
4190#define QM_REG_QVOQIDX_60                                        0x1681e4
4191#define QM_REG_QVOQIDX_61                                        0x1681e8
4192#define QM_REG_QVOQIDX_62                                        0x1681ec
4193#define QM_REG_QVOQIDX_63                                        0x1681f0
4194#define QM_REG_QVOQIDX_64                                        0x16e40c
4195#define QM_REG_QVOQIDX_65                                        0x16e410
4196#define QM_REG_QVOQIDX_69                                        0x16e420
4197#define QM_REG_QVOQIDX_7                                         0x168110
4198#define QM_REG_QVOQIDX_70                                        0x16e424
4199#define QM_REG_QVOQIDX_71                                        0x16e428
4200#define QM_REG_QVOQIDX_72                                        0x16e42c
4201#define QM_REG_QVOQIDX_73                                        0x16e430
4202#define QM_REG_QVOQIDX_74                                        0x16e434
4203#define QM_REG_QVOQIDX_75                                        0x16e438
4204#define QM_REG_QVOQIDX_76                                        0x16e43c
4205#define QM_REG_QVOQIDX_77                                        0x16e440
4206#define QM_REG_QVOQIDX_78                                        0x16e444
4207#define QM_REG_QVOQIDX_79                                        0x16e448
4208#define QM_REG_QVOQIDX_8                                         0x168114
4209#define QM_REG_QVOQIDX_80                                        0x16e44c
4210#define QM_REG_QVOQIDX_81                                        0x16e450
4211#define QM_REG_QVOQIDX_85                                        0x16e460
4212#define QM_REG_QVOQIDX_86                                        0x16e464
4213#define QM_REG_QVOQIDX_87                                        0x16e468
4214#define QM_REG_QVOQIDX_88                                        0x16e46c
4215#define QM_REG_QVOQIDX_89                                        0x16e470
4216#define QM_REG_QVOQIDX_9                                         0x168118
4217#define QM_REG_QVOQIDX_90                                        0x16e474
4218#define QM_REG_QVOQIDX_91                                        0x16e478
4219#define QM_REG_QVOQIDX_92                                        0x16e47c
4220#define QM_REG_QVOQIDX_93                                        0x16e480
4221#define QM_REG_QVOQIDX_94                                        0x16e484
4222#define QM_REG_QVOQIDX_95                                        0x16e488
4223#define QM_REG_QVOQIDX_96                                        0x16e48c
4224#define QM_REG_QVOQIDX_97                                        0x16e490
4225#define QM_REG_QVOQIDX_98                                        0x16e494
4226#define QM_REG_QVOQIDX_99                                        0x16e498
4227/* [RW 1] Initialization bit command */
4228#define QM_REG_SOFT_RESET                                        0x168428
4229/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
4230#define QM_REG_TASKCRDCOST_0                                     0x16809c
4231#define QM_REG_TASKCRDCOST_1                                     0x1680a0
4232#define QM_REG_TASKCRDCOST_2                                     0x1680a4
4233#define QM_REG_TASKCRDCOST_4                                     0x1680ac
4234#define QM_REG_TASKCRDCOST_5                                     0x1680b0
4235/* [R 6] Keep the fill level of the fifo from write client 3 */
4236#define QM_REG_TQM_WRC_FIFOLVL                                   0x168010
4237/* [R 6] Keep the fill level of the fifo from write client 2 */
4238#define QM_REG_UQM_WRC_FIFOLVL                                   0x168008
4239/* [RC 32] Credit update error register */
4240#define QM_REG_VOQCRDERRREG                                      0x168408
4241/* [R 16] The credit value for each VOQ */
4242#define QM_REG_VOQCREDIT_0                                       0x1682d0
4243#define QM_REG_VOQCREDIT_1                                       0x1682d4
4244#define QM_REG_VOQCREDIT_4                                       0x1682e0
4245/* [RW 16] The credit value that if above the QM is considered almost full */
4246#define QM_REG_VOQCREDITAFULLTHR                                 0x168090
4247/* [RW 16] The init and maximum credit for each VoQ */
4248#define QM_REG_VOQINITCREDIT_0                                   0x168060
4249#define QM_REG_VOQINITCREDIT_1                                   0x168064
4250#define QM_REG_VOQINITCREDIT_2                                   0x168068
4251#define QM_REG_VOQINITCREDIT_4                                   0x168070
4252#define QM_REG_VOQINITCREDIT_5                                   0x168074
4253/* [RW 1] The port of which VOQ belongs */
4254#define QM_REG_VOQPORT_0                                         0x1682a0
4255#define QM_REG_VOQPORT_1                                         0x1682a4
4256#define QM_REG_VOQPORT_2                                         0x1682a8
4257/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4258#define QM_REG_VOQQMASK_0_LSB                                    0x168240
4259/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4260#define QM_REG_VOQQMASK_0_LSB_EXT_A                              0x16e524
4261/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4262#define QM_REG_VOQQMASK_0_MSB                                    0x168244
4263/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4264#define QM_REG_VOQQMASK_0_MSB_EXT_A                              0x16e528
4265/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4266#define QM_REG_VOQQMASK_10_LSB                                   0x168290
4267/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4268#define QM_REG_VOQQMASK_10_LSB_EXT_A                             0x16e574
4269/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4270#define QM_REG_VOQQMASK_10_MSB                                   0x168294
4271/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4272#define QM_REG_VOQQMASK_10_MSB_EXT_A                             0x16e578
4273/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4274#define QM_REG_VOQQMASK_11_LSB                                   0x168298
4275/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4276#define QM_REG_VOQQMASK_11_LSB_EXT_A                             0x16e57c
4277/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4278#define QM_REG_VOQQMASK_11_MSB                                   0x16829c
4279/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4280#define QM_REG_VOQQMASK_11_MSB_EXT_A                             0x16e580
4281/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4282#define QM_REG_VOQQMASK_1_LSB                                    0x168248
4283/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4284#define QM_REG_VOQQMASK_1_LSB_EXT_A                              0x16e52c
4285/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4286#define QM_REG_VOQQMASK_1_MSB                                    0x16824c
4287/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4288#define QM_REG_VOQQMASK_1_MSB_EXT_A                              0x16e530
4289/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4290#define QM_REG_VOQQMASK_2_LSB                                    0x168250
4291/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4292#define QM_REG_VOQQMASK_2_LSB_EXT_A                              0x16e534
4293/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4294#define QM_REG_VOQQMASK_2_MSB                                    0x168254
4295/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4296#define QM_REG_VOQQMASK_2_MSB_EXT_A                              0x16e538
4297/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4298#define QM_REG_VOQQMASK_3_LSB                                    0x168258
4299/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4300#define QM_REG_VOQQMASK_3_LSB_EXT_A                              0x16e53c
4301/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4302#define QM_REG_VOQQMASK_3_MSB_EXT_A                              0x16e540
4303/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4304#define QM_REG_VOQQMASK_4_LSB                                    0x168260
4305/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4306#define QM_REG_VOQQMASK_4_LSB_EXT_A                              0x16e544
4307/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4308#define QM_REG_VOQQMASK_4_MSB                                    0x168264
4309/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4310#define QM_REG_VOQQMASK_4_MSB_EXT_A                              0x16e548
4311/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4312#define QM_REG_VOQQMASK_5_LSB                                    0x168268
4313/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4314#define QM_REG_VOQQMASK_5_LSB_EXT_A                              0x16e54c
4315/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4316#define QM_REG_VOQQMASK_5_MSB                                    0x16826c
4317/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4318#define QM_REG_VOQQMASK_5_MSB_EXT_A                              0x16e550
4319/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4320#define QM_REG_VOQQMASK_6_LSB                                    0x168270
4321/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4322#define QM_REG_VOQQMASK_6_LSB_EXT_A                              0x16e554
4323/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4324#define QM_REG_VOQQMASK_6_MSB                                    0x168274
4325/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4326#define QM_REG_VOQQMASK_6_MSB_EXT_A                              0x16e558
4327/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4328#define QM_REG_VOQQMASK_7_LSB                                    0x168278
4329/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4330#define QM_REG_VOQQMASK_7_LSB_EXT_A                              0x16e55c
4331/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4332#define QM_REG_VOQQMASK_7_MSB                                    0x16827c
4333/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4334#define QM_REG_VOQQMASK_7_MSB_EXT_A                              0x16e560
4335/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4336#define QM_REG_VOQQMASK_8_LSB                                    0x168280
4337/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4338#define QM_REG_VOQQMASK_8_LSB_EXT_A                              0x16e564
4339/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4340#define QM_REG_VOQQMASK_8_MSB                                    0x168284
4341/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4342#define QM_REG_VOQQMASK_8_MSB_EXT_A                              0x16e568
4343/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4344#define QM_REG_VOQQMASK_9_LSB                                    0x168288
4345/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4346#define QM_REG_VOQQMASK_9_LSB_EXT_A                              0x16e56c
4347/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4348#define QM_REG_VOQQMASK_9_MSB_EXT_A                              0x16e570
4349/* [RW 32] Wrr weights */
4350#define QM_REG_WRRWEIGHTS_0                                      0x16880c
4351#define QM_REG_WRRWEIGHTS_1                                      0x168810
4352#define QM_REG_WRRWEIGHTS_10                                     0x168814
4353#define QM_REG_WRRWEIGHTS_11                                     0x168818
4354#define QM_REG_WRRWEIGHTS_12                                     0x16881c
4355#define QM_REG_WRRWEIGHTS_13                                     0x168820
4356#define QM_REG_WRRWEIGHTS_14                                     0x168824
4357#define QM_REG_WRRWEIGHTS_15                                     0x168828
4358#define QM_REG_WRRWEIGHTS_16                                     0x16e000
4359#define QM_REG_WRRWEIGHTS_17                                     0x16e004
4360#define QM_REG_WRRWEIGHTS_18                                     0x16e008
4361#define QM_REG_WRRWEIGHTS_19                                     0x16e00c
4362#define QM_REG_WRRWEIGHTS_2                                      0x16882c
4363#define QM_REG_WRRWEIGHTS_20                                     0x16e010
4364#define QM_REG_WRRWEIGHTS_21                                     0x16e014
4365#define QM_REG_WRRWEIGHTS_22                                     0x16e018
4366#define QM_REG_WRRWEIGHTS_23                                     0x16e01c
4367#define QM_REG_WRRWEIGHTS_24                                     0x16e020
4368#define QM_REG_WRRWEIGHTS_25                                     0x16e024
4369#define QM_REG_WRRWEIGHTS_26                                     0x16e028
4370#define QM_REG_WRRWEIGHTS_27                                     0x16e02c
4371#define QM_REG_WRRWEIGHTS_28                                     0x16e030
4372#define QM_REG_WRRWEIGHTS_29                                     0x16e034
4373#define QM_REG_WRRWEIGHTS_3                                      0x168830
4374#define QM_REG_WRRWEIGHTS_30                                     0x16e038
4375#define QM_REG_WRRWEIGHTS_31                                     0x16e03c
4376#define QM_REG_WRRWEIGHTS_4                                      0x168834
4377#define QM_REG_WRRWEIGHTS_5                                      0x168838
4378#define QM_REG_WRRWEIGHTS_6                                      0x16883c
4379#define QM_REG_WRRWEIGHTS_7                                      0x168840
4380#define QM_REG_WRRWEIGHTS_8                                      0x168844
4381#define QM_REG_WRRWEIGHTS_9                                      0x168848
4382/* [R 6] Keep the fill level of the fifo from write client 1 */
4383#define QM_REG_XQM_WRC_FIFOLVL                                   0x168000
4384/* [W 1] reset to parity interrupt */
4385#define SEM_FAST_REG_PARITY_RST                                  0x18840
4386#define SRC_REG_COUNTFREE0                                       0x40500
4387/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
4388   ports. If set the searcher support 8 functions. */
4389#define SRC_REG_E1HMF_ENABLE                                     0x404cc
4390#define SRC_REG_FIRSTFREE0                                       0x40510
4391#define SRC_REG_KEYRSS0_0                                        0x40408
4392#define SRC_REG_KEYRSS0_7                                        0x40424
4393#define SRC_REG_KEYRSS1_9                                        0x40454
4394#define SRC_REG_KEYSEARCH_0                                      0x40458
4395#define SRC_REG_KEYSEARCH_1                                      0x4045c
4396#define SRC_REG_KEYSEARCH_2                                      0x40460
4397#define SRC_REG_KEYSEARCH_3                                      0x40464
4398#define SRC_REG_KEYSEARCH_4                                      0x40468
4399#define SRC_REG_KEYSEARCH_5                                      0x4046c
4400#define SRC_REG_KEYSEARCH_6                                      0x40470
4401#define SRC_REG_KEYSEARCH_7                                      0x40474
4402#define SRC_REG_KEYSEARCH_8                                      0x40478
4403#define SRC_REG_KEYSEARCH_9                                      0x4047c
4404#define SRC_REG_LASTFREE0                                        0x40530
4405#define SRC_REG_NUMBER_HASH_BITS0                                0x40400
4406/* [RW 1] Reset internal state machines. */
4407#define SRC_REG_SOFT_RST                                         0x4049c
4408/* [R 3] Interrupt register #0 read */
4409#define SRC_REG_SRC_INT_STS                                      0x404ac
4410/* [RW 3] Parity mask register #0 read/write */
4411#define SRC_REG_SRC_PRTY_MASK                                    0x404c8
4412/* [R 3] Parity register #0 read */
4413#define SRC_REG_SRC_PRTY_STS                                     0x404bc
4414/* [RC 3] Parity register #0 read clear */
4415#define SRC_REG_SRC_PRTY_STS_CLR                                 0x404c0
4416/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
4417#define TCM_REG_CAM_OCCUP                                        0x5017c
4418/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4419   disregarded; valid output is deasserted; all other signals are treated as
4420   usual; if 1 - normal activity. */
4421#define TCM_REG_CDU_AG_RD_IFEN                                   0x50034
4422/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4423   are disregarded; all other signals are treated as usual; if 1 - normal
4424   activity. */
4425#define TCM_REG_CDU_AG_WR_IFEN                                   0x50030
4426/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4427   disregarded; valid output is deasserted; all other signals are treated as
4428   usual; if 1 - normal activity. */
4429#define TCM_REG_CDU_SM_RD_IFEN                                   0x5003c
4430/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4431   input is disregarded; all other signals are treated as usual; if 1 -
4432   normal activity. */
4433#define TCM_REG_CDU_SM_WR_IFEN                                   0x50038
4434/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4435   the initial credit value; read returns the current value of the credit
4436   counter. Must be initialized to 1 at start-up. */
4437#define TCM_REG_CFC_INIT_CRD                                     0x50204
4438/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4439   weight 8 (the most prioritised); 1 stands for weight 1(least
4440   prioritised); 2 stands for weight 2; tc. */
4441#define TCM_REG_CP_WEIGHT                                        0x500c0
4442/* [RW 1] Input csem Interface enable. If 0 - the valid input is
4443   disregarded; acknowledge output is deasserted; all other signals are
4444   treated as usual; if 1 - normal activity. */
4445#define TCM_REG_CSEM_IFEN                                        0x5002c
4446/* [RC 1] Message length mismatch (relative to last indication) at the In#9
4447   interface. */
4448#define TCM_REG_CSEM_LENGTH_MIS                                  0x50174
4449/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4450   weight 8 (the most prioritised); 1 stands for weight 1(least
4451   prioritised); 2 stands for weight 2; tc. */
4452#define TCM_REG_CSEM_WEIGHT                                      0x500bc
4453/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
4454#define TCM_REG_ERR_EVNT_ID                                      0x500a0
4455/* [RW 28] The CM erroneous header for QM and Timers formatting. */
4456#define TCM_REG_ERR_TCM_HDR                                      0x5009c
4457/* [RW 8] The Event ID for Timers expiration. */
4458#define TCM_REG_EXPR_EVNT_ID                                     0x500a4
4459/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4460   writes the initial credit value; read returns the current value of the
4461   credit counter. Must be initialized to 64 at start-up. */
4462#define TCM_REG_FIC0_INIT_CRD                                    0x5020c
4463/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4464   writes the initial credit value; read returns the current value of the
4465   credit counter. Must be initialized to 64 at start-up. */
4466#define TCM_REG_FIC1_INIT_CRD                                    0x50210
4467/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4468   - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
4469   ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
4470   ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
4471#define TCM_REG_GR_ARB_TYPE                                      0x50114
4472/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4473   highest priority is 3. It is supposed that the Store channel is the
4474   compliment of the other 3 groups. */
4475#define TCM_REG_GR_LD0_PR                                        0x5011c
4476/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4477   highest priority is 3. It is supposed that the Store channel is the
4478   compliment of the other 3 groups. */
4479#define TCM_REG_GR_LD1_PR                                        0x50120
4480/* [RW 4] The number of double REG-pairs; loaded from the STORM context and
4481   sent to STORM; for a specific connection type. The double REG-pairs are
4482   used to align to STORM context row size of 128 bits. The offset of these
4483   data in the STORM context is always 0. Index _i stands for the connection
4484   type (one of 16). */
4485#define TCM_REG_N_SM_CTX_LD_0                                    0x50050
4486#define TCM_REG_N_SM_CTX_LD_1                                    0x50054
4487#define TCM_REG_N_SM_CTX_LD_2                                    0x50058
4488#define TCM_REG_N_SM_CTX_LD_3                                    0x5005c
4489#define TCM_REG_N_SM_CTX_LD_4                                    0x50060
4490#define TCM_REG_N_SM_CTX_LD_5                                    0x50064
4491/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4492   acknowledge output is deasserted; all other signals are treated as usual;
4493   if 1 - normal activity. */
4494#define TCM_REG_PBF_IFEN                                         0x50024
4495/* [RC 1] Message length mismatch (relative to last indication) at the In#7
4496   interface. */
4497#define TCM_REG_PBF_LENGTH_MIS                                   0x5016c
4498/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4499   weight 8 (the most prioritised); 1 stands for weight 1(least
4500   prioritised); 2 stands for weight 2; tc. */
4501#define TCM_REG_PBF_WEIGHT                                       0x500b4
4502#define TCM_REG_PHYS_QNUM0_0                                     0x500e0
4503#define TCM_REG_PHYS_QNUM0_1                                     0x500e4
4504#define TCM_REG_PHYS_QNUM1_0                                     0x500e8
4505#define TCM_REG_PHYS_QNUM1_1                                     0x500ec
4506#define TCM_REG_PHYS_QNUM2_0                                     0x500f0
4507#define TCM_REG_PHYS_QNUM2_1                                     0x500f4
4508#define TCM_REG_PHYS_QNUM3_0                                     0x500f8
4509#define TCM_REG_PHYS_QNUM3_1                                     0x500fc
4510/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
4511   acknowledge output is deasserted; all other signals are treated as usual;
4512   if 1 - normal activity. */
4513#define TCM_REG_PRS_IFEN                                         0x50020
4514/* [RC 1] Message length mismatch (relative to last indication) at the In#6
4515   interface. */
4516#define TCM_REG_PRS_LENGTH_MIS                                   0x50168
4517/* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
4518   weight 8 (the most prioritised); 1 stands for weight 1(least
4519   prioritised); 2 stands for weight 2; tc. */
4520#define TCM_REG_PRS_WEIGHT                                       0x500b0
4521/* [RW 8] The Event ID for Timers formatting in case of stop done. */
4522#define TCM_REG_STOP_EVNT_ID                                     0x500a8
4523/* [RC 1] Message length mismatch (relative to last indication) at the STORM
4524   interface. */
4525#define TCM_REG_STORM_LENGTH_MIS                                 0x50160
4526/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4527   disregarded; acknowledge output is deasserted; all other signals are
4528   treated as usual; if 1 - normal activity. */
4529#define TCM_REG_STORM_TCM_IFEN                                   0x50010
4530/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4531   weight 8 (the most prioritised); 1 stands for weight 1(least
4532   prioritised); 2 stands for weight 2; tc. */
4533#define TCM_REG_STORM_WEIGHT                                     0x500ac
4534/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4535   acknowledge output is deasserted; all other signals are treated as usual;
4536   if 1 - normal activity. */
4537#define TCM_REG_TCM_CFC_IFEN                                     0x50040
4538/* [RW 11] Interrupt mask register #0 read/write */
4539#define TCM_REG_TCM_INT_MASK                                     0x501dc
4540/* [R 11] Interrupt register #0 read */
4541#define TCM_REG_TCM_INT_STS                                      0x501d0
4542/* [RW 27] Parity mask register #0 read/write */
4543#define TCM_REG_TCM_PRTY_MASK                                    0x501ec
4544/* [R 27] Parity register #0 read */
4545#define TCM_REG_TCM_PRTY_STS                                     0x501e0
4546/* [RC 27] Parity register #0 read clear */
4547#define TCM_REG_TCM_PRTY_STS_CLR                                 0x501e4
4548/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
4549   REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4550   Is used to determine the number of the AG context REG-pairs written back;
4551   when the input message Reg1WbFlg isn't set. */
4552#define TCM_REG_TCM_REG0_SZ                                      0x500d8
4553/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4554   disregarded; valid is deasserted; all other signals are treated as usual;
4555   if 1 - normal activity. */
4556#define TCM_REG_TCM_STORM0_IFEN                                  0x50004
4557/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4558   disregarded; valid is deasserted; all other signals are treated as usual;
4559   if 1 - normal activity. */
4560#define TCM_REG_TCM_STORM1_IFEN                                  0x50008
4561/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4562   disregarded; valid is deasserted; all other signals are treated as usual;
4563   if 1 - normal activity. */
4564#define TCM_REG_TCM_TQM_IFEN                                     0x5000c
4565/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4566#define TCM_REG_TCM_TQM_USE_Q                                    0x500d4
4567/* [RW 28] The CM header for Timers expiration command. */
4568#define TCM_REG_TM_TCM_HDR                                       0x50098
4569/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4570   disregarded; acknowledge output is deasserted; all other signals are
4571   treated as usual; if 1 - normal activity. */
4572#define TCM_REG_TM_TCM_IFEN                                      0x5001c
4573/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4574   weight 8 (the most prioritised); 1 stands for weight 1(least
4575   prioritised); 2 stands for weight 2; tc. */
4576#define TCM_REG_TM_WEIGHT                                        0x500d0
4577/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4578   the initial credit value; read returns the current value of the credit
4579   counter. Must be initialized to 32 at start-up. */
4580#define TCM_REG_TQM_INIT_CRD                                     0x5021c
4581/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4582   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4583   prioritised); 2 stands for weight 2; tc. */
4584#define TCM_REG_TQM_P_WEIGHT                                     0x500c8
4585/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4586   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4587   prioritised); 2 stands for weight 2; tc. */
4588#define TCM_REG_TQM_S_WEIGHT                                     0x500cc
4589/* [RW 28] The CM header value for QM request (primary). */
4590#define TCM_REG_TQM_TCM_HDR_P                                    0x50090
4591/* [RW 28] The CM header value for QM request (secondary). */
4592#define TCM_REG_TQM_TCM_HDR_S                                    0x50094
4593/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4594   acknowledge output is deasserted; all other signals are treated as usual;
4595   if 1 - normal activity. */
4596#define TCM_REG_TQM_TCM_IFEN                                     0x50014
4597/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4598   acknowledge output is deasserted; all other signals are treated as usual;
4599   if 1 - normal activity. */
4600#define TCM_REG_TSDM_IFEN                                        0x50018
4601/* [RC 1] Message length mismatch (relative to last indication) at the SDM
4602   interface. */
4603#define TCM_REG_TSDM_LENGTH_MIS                                  0x50164
4604/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4605   weight 8 (the most prioritised); 1 stands for weight 1(least
4606   prioritised); 2 stands for weight 2; tc. */
4607#define TCM_REG_TSDM_WEIGHT                                      0x500c4
4608/* [RW 1] Input usem Interface enable. If 0 - the valid input is
4609   disregarded; acknowledge output is deasserted; all other signals are
4610   treated as usual; if 1 - normal activity. */
4611#define TCM_REG_USEM_IFEN                                        0x50028
4612/* [RC 1] Message length mismatch (relative to last indication) at the In#8
4613   interface. */
4614#define TCM_REG_USEM_LENGTH_MIS                                  0x50170
4615/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4616   weight 8 (the most prioritised); 1 stands for weight 1(least
4617   prioritised); 2 stands for weight 2; tc. */
4618#define TCM_REG_USEM_WEIGHT                                      0x500b8
4619/* [RW 21] Indirect access to the descriptor table of the XX protection
4620   mechanism. The fields are: [5:0] - length of the message; 15:6] - message
4621   pointer; 20:16] - next pointer. */
4622#define TCM_REG_XX_DESCR_TABLE                                   0x50280
4623#define TCM_REG_XX_DESCR_TABLE_SIZE                              29
4624/* [R 6] Use to read the value of XX protection Free counter. */
4625#define TCM_REG_XX_FREE                                          0x50178
4626/* [RW 6] Initial value for the credit counter; responsible for fulfilling
4627   of the Input Stage XX protection buffer by the XX protection pending
4628   messages. Max credit available - 127.Write writes the initial credit
4629   value; read returns the current value of the credit counter. Must be
4630   initialized to 19 at start-up. */
4631#define TCM_REG_XX_INIT_CRD                                      0x50220
4632/* [RW 6] Maximum link list size (messages locked) per connection in the XX
4633   protection. */
4634#define TCM_REG_XX_MAX_LL_SZ                                     0x50044
4635/* [RW 6] The maximum number of pending messages; which may be stored in XX
4636   protection. ~tcm_registers_xx_free.xx_free is read on read. */
4637#define TCM_REG_XX_MSG_NUM                                       0x50224
4638/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4639#define TCM_REG_XX_OVFL_EVNT_ID                                  0x50048
4640/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4641   The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
4642   header pointer. */
4643#define TCM_REG_XX_TABLE                                         0x50240
4644/* [RW 4] Load value for cfc ac credit cnt. */
4645#define TM_REG_CFC_AC_CRDCNT_VAL                                 0x164208
4646/* [RW 4] Load value for cfc cld credit cnt. */
4647#define TM_REG_CFC_CLD_CRDCNT_VAL                                0x164210
4648/* [RW 8] Client0 context region. */
4649#define TM_REG_CL0_CONT_REGION                                   0x164030
4650/* [RW 8] Client1 context region. */
4651#define TM_REG_CL1_CONT_REGION                                   0x164034
4652/* [RW 8] Client2 context region. */
4653#define TM_REG_CL2_CONT_REGION                                   0x164038
4654/* [RW 2] Client in High priority client number. */
4655#define TM_REG_CLIN_PRIOR0_CLIENT                                0x164024
4656/* [RW 4] Load value for clout0 cred cnt. */
4657#define TM_REG_CLOUT_CRDCNT0_VAL                                 0x164220
4658/* [RW 4] Load value for clout1 cred cnt. */
4659#define TM_REG_CLOUT_CRDCNT1_VAL                                 0x164228
4660/* [RW 4] Load value for clout2 cred cnt. */
4661#define TM_REG_CLOUT_CRDCNT2_VAL                                 0x164230
4662/* [RW 1] Enable client0 input. */
4663#define TM_REG_EN_CL0_INPUT                                      0x164008
4664/* [RW 1] Enable client1 input. */
4665#define TM_REG_EN_CL1_INPUT                                      0x16400c
4666/* [RW 1] Enable client2 input. */
4667#define TM_REG_EN_CL2_INPUT                                      0x164010
4668#define TM_REG_EN_LINEAR0_TIMER                                  0x164014
4669/* [RW 1] Enable real time counter. */
4670#define TM_REG_EN_REAL_TIME_CNT                                  0x1640d8
4671/* [RW 1] Enable for Timers state machines. */
4672#define TM_REG_EN_TIMERS                                         0x164000
4673/* [RW 4] Load value for expiration credit cnt. CFC max number of
4674   outstanding load requests for timers (expiration) context loading. */
4675#define TM_REG_EXP_CRDCNT_VAL                                    0x164238
4676/* [RW 32] Linear0 logic address. */
4677#define TM_REG_LIN0_LOGIC_ADDR                                   0x164240
4678/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
4679#define TM_REG_LIN0_MAX_ACTIVE_CID                               0x164048
4680/* [ST 16] Linear0 Number of scans counter. */
4681#define TM_REG_LIN0_NUM_SCANS                                    0x1640a0
4682/* [WB 64] Linear0 phy address. */
4683#define TM_REG_LIN0_PHY_ADDR                                     0x164270
4684/* [RW 1] Linear0 physical address valid. */
4685#define TM_REG_LIN0_PHY_ADDR_VALID                               0x164248
4686#define TM_REG_LIN0_SCAN_ON                                      0x1640d0
4687/* [RW 24] Linear0 array scan timeout. */
4688#define TM_REG_LIN0_SCAN_TIME                                    0x16403c
4689#define TM_REG_LIN0_VNIC_UC                                      0x164128
4690/* [RW 32] Linear1 logic address. */
4691#define TM_REG_LIN1_LOGIC_ADDR                                   0x164250
4692/* [WB 64] Linear1 phy address. */
4693#define TM_REG_LIN1_PHY_ADDR                                     0x164280
4694/* [RW 1] Linear1 physical address valid. */
4695#define TM_REG_LIN1_PHY_ADDR_VALID                               0x164258
4696/* [RW 6] Linear timer set_clear fifo threshold. */
4697#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR                        0x164070
4698/* [RW 2] Load value for pci arbiter credit cnt. */
4699#define TM_REG_PCIARB_CRDCNT_VAL                                 0x164260
4700/* [RW 20] The amount of hardware cycles for each timer tick. */
4701#define TM_REG_TIMER_TICK_SIZE                                   0x16401c
4702/* [RW 8] Timers Context region. */
4703#define TM_REG_TM_CONTEXT_REGION                                 0x164044
4704/* [RW 1] Interrupt mask register #0 read/write */
4705#define TM_REG_TM_INT_MASK                                       0x1640fc
4706/* [R 1] Interrupt register #0 read */
4707#define TM_REG_TM_INT_STS                                        0x1640f0
4708/* [RW 7] Parity mask register #0 read/write */
4709#define TM_REG_TM_PRTY_MASK                                      0x16410c
4710/* [R 7] Parity register #0 read */
4711#define TM_REG_TM_PRTY_STS                                       0x164100
4712/* [RC 7] Parity register #0 read clear */
4713#define TM_REG_TM_PRTY_STS_CLR                                   0x164104
4714/* [RW 8] The event id for aggregated interrupt 0 */
4715#define TSDM_REG_AGG_INT_EVENT_0                                 0x42038
4716#define TSDM_REG_AGG_INT_EVENT_1                                 0x4203c
4717#define TSDM_REG_AGG_INT_EVENT_2                                 0x42040
4718#define TSDM_REG_AGG_INT_EVENT_3                                 0x42044
4719#define TSDM_REG_AGG_INT_EVENT_4                                 0x42048
4720/* [RW 1] The T bit for aggregated interrupt 0 */
4721#define TSDM_REG_AGG_INT_T_0                                     0x420b8
4722#define TSDM_REG_AGG_INT_T_1                                     0x420bc
4723/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4724#define TSDM_REG_CFC_RSP_START_ADDR                              0x42008
4725/* [RW 16] The maximum value of the completion counter #0 */
4726#define TSDM_REG_CMP_COUNTER_MAX0                                0x4201c
4727/* [RW 16] The maximum value of the completion counter #1 */
4728#define TSDM_REG_CMP_COUNTER_MAX1                                0x42020
4729/* [RW 16] The maximum value of the completion counter #2 */
4730#define TSDM_REG_CMP_COUNTER_MAX2                                0x42024
4731/* [RW 16] The maximum value of the completion counter #3 */
4732#define TSDM_REG_CMP_COUNTER_MAX3                                0x42028
4733/* [RW 13] The start address in the internal RAM for the completion
4734   counters. */
4735#define TSDM_REG_CMP_COUNTER_START_ADDR                          0x4200c
4736#define TSDM_REG_ENABLE_IN1                                      0x42238
4737#define TSDM_REG_ENABLE_IN2                                      0x4223c
4738#define TSDM_REG_ENABLE_OUT1                                     0x42240
4739#define TSDM_REG_ENABLE_OUT2                                     0x42244
4740/* [RW 4] The initial number of messages that can be sent to the pxp control
4741   interface without receiving any ACK. */
4742#define TSDM_REG_INIT_CREDIT_PXP_CTRL                            0x424bc
4743/* [ST 32] The number of ACK after placement messages received */
4744#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE                          0x4227c
4745/* [ST 32] The number of packet end messages received from the parser */
4746#define TSDM_REG_NUM_OF_PKT_END_MSG                              0x42274
4747/* [ST 32] The number of requests received from the pxp async if */
4748#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ                            0x42278
4749/* [ST 32] The number of commands received in queue 0 */
4750#define TSDM_REG_NUM_OF_Q0_CMD                                   0x42248
4751/* [ST 32] The number of commands received in queue 10 */
4752#define TSDM_REG_NUM_OF_Q10_CMD                                  0x4226c
4753/* [ST 32] The number of commands received in queue 11 */
4754#define TSDM_REG_NUM_OF_Q11_CMD                                  0x42270
4755/* [ST 32] The number of commands received in queue 1 */
4756#define TSDM_REG_NUM_OF_Q1_CMD                                   0x4224c
4757/* [ST 32] The number of commands received in queue 3 */
4758#define TSDM_REG_NUM_OF_Q3_CMD                                   0x42250
4759/* [ST 32] The number of commands received in queue 4 */
4760#define TSDM_REG_NUM_OF_Q4_CMD                                   0x42254
4761/* [ST 32] The number of commands received in queue 5 */
4762#define TSDM_REG_NUM_OF_Q5_CMD                                   0x42258
4763/* [ST 32] The number of commands received in queue 6 */
4764#define TSDM_REG_NUM_OF_Q6_CMD                                   0x4225c
4765/* [ST 32] The number of commands received in queue 7 */
4766#define TSDM_REG_NUM_OF_Q7_CMD                                   0x42260
4767/* [ST 32] The number of commands received in queue 8 */
4768#define TSDM_REG_NUM_OF_Q8_CMD                                   0x42264
4769/* [ST 32] The number of commands received in queue 9 */
4770#define TSDM_REG_NUM_OF_Q9_CMD                                   0x42268
4771/* [RW 13] The start address in the internal RAM for the packet end message */
4772#define TSDM_REG_PCK_END_MSG_START_ADDR                          0x42014
4773/* [RW 13] The start address in the internal RAM for queue counters */
4774#define TSDM_REG_Q_COUNTER_START_ADDR                            0x42010
4775/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4776#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY                        0x42548
4777/* [R 1] parser fifo empty in sdm_sync block */
4778#define TSDM_REG_SYNC_PARSER_EMPTY                               0x42550
4779/* [R 1] parser serial fifo empty in sdm_sync block */
4780#define TSDM_REG_SYNC_SYNC_EMPTY                                 0x42558
4781/* [RW 32] Tick for timer counter. Applicable only when
4782   ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4783#define TSDM_REG_TIMER_TICK                                      0x42000
4784/* [RW 32] Interrupt mask register #0 read/write */
4785#define TSDM_REG_TSDM_INT_MASK_0                                 0x4229c
4786#define TSDM_REG_TSDM_INT_MASK_1                                 0x422ac
4787/* [R 32] Interrupt register #0 read */
4788#define TSDM_REG_TSDM_INT_STS_0                                  0x42290
4789#define TSDM_REG_TSDM_INT_STS_1                                  0x422a0
4790/* [RW 11] Parity mask register #0 read/write */
4791#define TSDM_REG_TSDM_PRTY_MASK                                  0x422bc
4792/* [R 11] Parity register #0 read */
4793#define TSDM_REG_TSDM_PRTY_STS                                   0x422b0
4794/* [RC 11] Parity register #0 read clear */
4795#define TSDM_REG_TSDM_PRTY_STS_CLR                               0x422b4
4796/* [RW 5] The number of time_slots in the arbitration cycle */
4797#define TSEM_REG_ARB_CYCLE_SIZE                                  0x180034
4798/* [RW 3] The source that is associated with arbitration element 0. Source
4799   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4800   sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4801#define TSEM_REG_ARB_ELEMENT0                                    0x180020
4802/* [RW 3] The source that is associated with arbitration element 1. Source
4803   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4804   sleeping thread with priority 1; 4- sleeping thread with priority 2.
4805   Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
4806#define TSEM_REG_ARB_ELEMENT1                                    0x180024
4807/* [RW 3] The source that is associated with arbitration element 2. Source
4808   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4809   sleeping thread with priority 1; 4- sleeping thread with priority 2.
4810   Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4811   and ~tsem_registers_arb_element1.arb_element1 */
4812#define TSEM_REG_ARB_ELEMENT2                                    0x180028
4813/* [RW 3] The source that is associated with arbitration element 3. Source
4814   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4815   sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4816   not be equal to register ~tsem_registers_arb_element0.arb_element0 and
4817   ~tsem_registers_arb_element1.arb_element1 and
4818   ~tsem_registers_arb_element2.arb_element2 */
4819#define TSEM_REG_ARB_ELEMENT3                                    0x18002c
4820/* [RW 3] The source that is associated with arbitration element 4. Source
4821   decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4822   sleeping thread with priority 1; 4- sleeping thread with priority 2.
4823   Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4824   and ~tsem_registers_arb_element1.arb_element1 and
4825   ~tsem_registers_arb_element2.arb_element2 and
4826   ~tsem_registers_arb_element3.arb_element3 */
4827#define TSEM_REG_ARB_ELEMENT4                                    0x180030
4828#define TSEM_REG_ENABLE_IN                                       0x1800a4
4829#define TSEM_REG_ENABLE_OUT                                      0x1800a8
4830/* [RW 32] This address space contains all registers and memories that are
4831   placed in SEM_FAST block. The SEM_FAST registers are described in
4832   appendix B. In order to access the sem_fast registers the base address
4833   ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4834#define TSEM_REG_FAST_MEMORY                                     0x1a0000
4835/* [RW 1] Disables input messages from FIC0 May be updated during run_time
4836   by the microcode */
4837#define TSEM_REG_FIC0_DISABLE                                    0x180224
4838/* [RW 1] Disables input messages from FIC1 May be updated during run_time
4839   by the microcode */
4840#define TSEM_REG_FIC1_DISABLE                                    0x180234
4841/* [RW 15] Interrupt table Read and write access to it is not possible in
4842   the middle of the work */
4843#define TSEM_REG_INT_TABLE                                       0x180400
4844/* [ST 24] Statistics register. The number of messages that entered through
4845   FIC0 */
4846#define TSEM_REG_MSG_NUM_FIC0                                    0x180000
4847/* [ST 24] Statistics register. The number of messages that entered through
4848   FIC1 */
4849#define TSEM_REG_MSG_NUM_FIC1                                    0x180004
4850/* [ST 24] Statistics register. The number of messages that were sent to
4851   FOC0 */
4852#define TSEM_REG_MSG_NUM_FOC0                                    0x180008
4853/* [ST 24] Statistics register. The number of messages that were sent to
4854   FOC1 */
4855#define TSEM_REG_MSG_NUM_FOC1                                    0x18000c
4856/* [ST 24] Statistics register. The number of messages that were sent to
4857   FOC2 */
4858#define TSEM_REG_MSG_NUM_FOC2                                    0x180010
4859/* [ST 24] Statistics register. The number of messages that were sent to
4860   FOC3 */
4861#define TSEM_REG_MSG_NUM_FOC3                                    0x180014
4862/* [RW 1] Disables input messages from the passive buffer May be updated
4863   during run_time by the microcode */
4864#define TSEM_REG_PAS_DISABLE                                     0x18024c
4865/* [WB 128] Debug only. Passive buffer memory */
4866#define TSEM_REG_PASSIVE_BUFFER                                  0x181000
4867/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4868#define TSEM_REG_PRAM                                            0x1c0000
4869/* [R 8] Valid sleeping threads indication have bit per thread */
4870#define TSEM_REG_SLEEP_THREADS_VALID                             0x18026c
4871/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4872#define TSEM_REG_SLOW_EXT_STORE_EMPTY                            0x1802a0
4873/* [RW 8] List of free threads . There is a bit per thread. */
4874#define TSEM_REG_THREADS_LIST                                    0x1802e4
4875/* [RC 32] Parity register #0 read clear */
4876#define TSEM_REG_TSEM_PRTY_STS_CLR_0                             0x180118
4877#define TSEM_REG_TSEM_PRTY_STS_CLR_1                             0x180128
4878/* [RW 3] The arbitration scheme of time_slot 0 */
4879#define TSEM_REG_TS_0_AS                                         0x180038
4880/* [RW 3] The arbitration scheme of time_slot 10 */
4881#define TSEM_REG_TS_10_AS                                        0x180060
4882/* [RW 3] The arbitration scheme of time_slot 11 */
4883#define TSEM_REG_TS_11_AS                                        0x180064
4884/* [RW 3] The arbitration scheme of time_slot 12 */
4885#define TSEM_REG_TS_12_AS                                        0x180068
4886/* [RW 3] The arbitration scheme of time_slot 13 */
4887#define TSEM_REG_TS_13_AS                                        0x18006c
4888/* [RW 3] The arbitration scheme of time_slot 14 */
4889#define TSEM_REG_TS_14_AS                                        0x180070
4890/* [RW 3] The arbitration scheme of time_slot 15 */
4891#define TSEM_REG_TS_15_AS                                        0x180074
4892/* [RW 3] The arbitration scheme of time_slot 16 */
4893#define TSEM_REG_TS_16_AS                                        0x180078
4894/* [RW 3] The arbitration scheme of time_slot 17 */
4895#define TSEM_REG_TS_17_AS                                        0x18007c
4896/* [RW 3] The arbitration scheme of time_slot 18 */
4897#define TSEM_REG_TS_18_AS                                        0x180080
4898/* [RW 3] The arbitration scheme of time_slot 1 */
4899#define TSEM_REG_TS_1_AS                                         0x18003c
4900/* [RW 3] The arbitration scheme of time_slot 2 */
4901#define TSEM_REG_TS_2_AS                                         0x180040
4902/* [RW 3] The arbitration scheme of time_slot 3 */
4903#define TSEM_REG_TS_3_AS                                         0x180044
4904/* [RW 3] The arbitration scheme of time_slot 4 */
4905#define TSEM_REG_TS_4_AS                                         0x180048
4906/* [RW 3] The arbitration scheme of time_slot 5 */
4907#define TSEM_REG_TS_5_AS                                         0x18004c
4908/* [RW 3] The arbitration scheme of time_slot 6 */
4909#define TSEM_REG_TS_6_AS                                         0x180050
4910/* [RW 3] The arbitration scheme of time_slot 7 */
4911#define TSEM_REG_TS_7_AS                                         0x180054
4912/* [RW 3] The arbitration scheme of time_slot 8 */
4913#define TSEM_REG_TS_8_AS                                         0x180058
4914/* [RW 3] The arbitration scheme of time_slot 9 */
4915#define TSEM_REG_TS_9_AS                                         0x18005c
4916/* [RW 32] Interrupt mask register #0 read/write */
4917#define TSEM_REG_TSEM_INT_MASK_0                                 0x180100
4918#define TSEM_REG_TSEM_INT_MASK_1                                 0x180110
4919/* [R 32] Interrupt register #0 read */
4920#define TSEM_REG_TSEM_INT_STS_0                                  0x1800f4
4921#define TSEM_REG_TSEM_INT_STS_1                                  0x180104
4922/* [RW 32] Parity mask register #0 read/write */
4923#define TSEM_REG_TSEM_PRTY_MASK_0                                0x180120
4924#define TSEM_REG_TSEM_PRTY_MASK_1                                0x180130
4925/* [R 32] Parity register #0 read */
4926#define TSEM_REG_TSEM_PRTY_STS_0                                 0x180114
4927#define TSEM_REG_TSEM_PRTY_STS_1                                 0x180124
4928/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4929 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4930#define TSEM_REG_VFPF_ERR_NUM                                    0x180380
4931/* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4932 * [10:8] of the address should be the offset within the accessed LCID
4933 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4934 * LCID100. The RBC address should be 12'ha64. */
4935#define UCM_REG_AG_CTX                                           0xe2000
4936/* [R 5] Used to read the XX protection CAM occupancy counter. */
4937#define UCM_REG_CAM_OCCUP                                        0xe0170
4938/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4939   disregarded; valid output is deasserted; all other signals are treated as
4940   usual; if 1 - normal activity. */
4941#define UCM_REG_CDU_AG_RD_IFEN                                   0xe0038
4942/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4943   are disregarded; all other signals are treated as usual; if 1 - normal
4944   activity. */
4945#define UCM_REG_CDU_AG_WR_IFEN                                   0xe0034
4946/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4947   disregarded; valid output is deasserted; all other signals are treated as
4948   usual; if 1 - normal activity. */
4949#define UCM_REG_CDU_SM_RD_IFEN                                   0xe0040
4950/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4951   input is disregarded; all other signals are treated as usual; if 1 -
4952   normal activity. */
4953#define UCM_REG_CDU_SM_WR_IFEN                                   0xe003c
4954/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4955   the initial credit value; read returns the current value of the credit
4956   counter. Must be initialized to 1 at start-up. */
4957#define UCM_REG_CFC_INIT_CRD                                     0xe0204
4958/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4959   weight 8 (the most prioritised); 1 stands for weight 1(least
4960   prioritised); 2 stands for weight 2; tc. */
4961#define UCM_REG_CP_WEIGHT                                        0xe00c4
4962/* [RW 1] Input csem Interface enable. If 0 - the valid input is
4963   disregarded; acknowledge output is deasserted; all other signals are
4964   treated as usual; if 1 - normal activity. */
4965#define UCM_REG_CSEM_IFEN                                        0xe0028
4966/* [RC 1] Set when the message length mismatch (relative to last indication)
4967   at the csem interface is detected. */
4968#define UCM_REG_CSEM_LENGTH_MIS                                  0xe0160
4969/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4970   weight 8 (the most prioritised); 1 stands for weight 1(least
4971   prioritised); 2 stands for weight 2; tc. */
4972#define UCM_REG_CSEM_WEIGHT                                      0xe00b8
4973/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4974   disregarded; acknowledge output is deasserted; all other signals are
4975   treated as usual; if 1 - normal activity. */
4976#define UCM_REG_DORQ_IFEN                                        0xe0030
4977/* [RC 1] Set when the message length mismatch (relative to last indication)
4978   at the dorq interface is detected. */
4979#define UCM_REG_DORQ_LENGTH_MIS                                  0xe0168
4980/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4981   weight 8 (the most prioritised); 1 stands for weight 1(least
4982   prioritised); 2 stands for weight 2; tc. */
4983#define UCM_REG_DORQ_WEIGHT                                      0xe00c0
4984/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4985#define UCM_REG_ERR_EVNT_ID                                      0xe00a4
4986/* [RW 28] The CM erroneous header for QM and Timers formatting. */
4987#define UCM_REG_ERR_UCM_HDR                                      0xe00a0
4988/* [RW 8] The Event ID for Timers expiration. */
4989#define UCM_REG_EXPR_EVNT_ID                                     0xe00a8
4990/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4991   writes the initial credit value; read returns the current value of the
4992   credit counter. Must be initialized to 64 at start-up. */
4993#define UCM_REG_FIC0_INIT_CRD                                    0xe020c
4994/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4995   writes the initial credit value; read returns the current value of the
4996   credit counter. Must be initialized to 64 at start-up. */
4997#define UCM_REG_FIC1_INIT_CRD                                    0xe0210
4998/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4999   - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
5000   ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
5001   ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
5002#define UCM_REG_GR_ARB_TYPE                                      0xe0144
5003/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
5004   highest priority is 3. It is supposed that the Store channel group is
5005   compliment to the others. */
5006#define UCM_REG_GR_LD0_PR                                        0xe014c
5007/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
5008   highest priority is 3. It is supposed that the Store channel group is
5009   compliment to the others. */
5010#define UCM_REG_GR_LD1_PR                                        0xe0150
5011/* [RW 2] The queue index for invalidate counter flag decision. */
5012#define UCM_REG_INV_CFLG_Q                                       0xe00e4
5013/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5014   sent to STORM; for a specific connection type. the double REG-pairs are
5015   used in order to align to STORM context row size of 128 bits. The offset
5016   of these data in the STORM context is always 0. Index _i stands for the
5017   connection type (one of 16). */
5018#define UCM_REG_N_SM_CTX_LD_0                                    0xe0054
5019#define UCM_REG_N_SM_CTX_LD_1                                    0xe0058
5020#define UCM_REG_N_SM_CTX_LD_2                                    0xe005c
5021#define UCM_REG_N_SM_CTX_LD_3                                    0xe0060
5022#define UCM_REG_N_SM_CTX_LD_4                                    0xe0064
5023#define UCM_REG_N_SM_CTX_LD_5                                    0xe0068
5024#define UCM_REG_PHYS_QNUM0_0                                     0xe0110
5025#define UCM_REG_PHYS_QNUM0_1                                     0xe0114
5026#define UCM_REG_PHYS_QNUM1_0                                     0xe0118
5027#define UCM_REG_PHYS_QNUM1_1                                     0xe011c
5028#define UCM_REG_PHYS_QNUM2_0                                     0xe0120
5029#define UCM_REG_PHYS_QNUM2_1                                     0xe0124
5030#define UCM_REG_PHYS_QNUM3_0                                     0xe0128
5031#define UCM_REG_PHYS_QNUM3_1                                     0xe012c
5032/* [RW 8] The Event ID for Timers formatting in case of stop done. */
5033#define UCM_REG_STOP_EVNT_ID                                     0xe00ac
5034/* [RC 1] Set when the message length mismatch (relative to last indication)
5035   at the STORM interface is detected. */
5036#define UCM_REG_STORM_LENGTH_MIS                                 0xe0154
5037/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5038   disregarded; acknowledge output is deasserted; all other signals are
5039   treated as usual; if 1 - normal activity. */
5040#define UCM_REG_STORM_UCM_IFEN                                   0xe0010
5041/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5042   weight 8 (the most prioritised); 1 stands for weight 1(least
5043   prioritised); 2 stands for weight 2; tc. */
5044#define UCM_REG_STORM_WEIGHT                                     0xe00b0
5045/* [RW 4] Timers output initial credit. Max credit available - 15.Write
5046   writes the initial credit value; read returns the current value of the
5047   credit counter. Must be initialized to 4 at start-up. */
5048#define UCM_REG_TM_INIT_CRD                                      0xe021c
5049/* [RW 28] The CM header for Timers expiration command. */
5050#define UCM_REG_TM_UCM_HDR                                       0xe009c
5051/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5052   disregarded; acknowledge output is deasserted; all other signals are
5053   treated as usual; if 1 - normal activity. */
5054#define UCM_REG_TM_UCM_IFEN                                      0xe001c
5055/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5056   weight 8 (the most prioritised); 1 stands for weight 1(least
5057   prioritised); 2 stands for weight 2; tc. */
5058#define UCM_REG_TM_WEIGHT                                        0xe00d4
5059/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5060   disregarded; acknowledge output is deasserted; all other signals are
5061   treated as usual; if 1 - normal activity. */
5062#define UCM_REG_TSEM_IFEN                                        0xe0024
5063/* [RC 1] Set when the message length mismatch (relative to last indication)
5064   at the tsem interface is detected. */
5065#define UCM_REG_TSEM_LENGTH_MIS                                  0xe015c
5066/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5067   weight 8 (the most prioritised); 1 stands for weight 1(least
5068   prioritised); 2 stands for weight 2; tc. */
5069#define UCM_REG_TSEM_WEIGHT                                      0xe00b4
5070/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5071   acknowledge output is deasserted; all other signals are treated as usual;
5072   if 1 - normal activity. */
5073#define UCM_REG_UCM_CFC_IFEN                                     0xe0044
5074/* [RW 11] Interrupt mask register #0 read/write */
5075#define UCM_REG_UCM_INT_MASK                                     0xe01d4
5076/* [R 11] Interrupt register #0 read */
5077#define UCM_REG_UCM_INT_STS                                      0xe01c8
5078/* [RW 27] Parity mask register #0 read/write */
5079#define UCM_REG_UCM_PRTY_MASK                                    0xe01e4
5080/* [R 27] Parity register #0 read */
5081#define UCM_REG_UCM_PRTY_STS                                     0xe01d8
5082/* [RC 27] Parity register #0 read clear */
5083#define UCM_REG_UCM_PRTY_STS_CLR                                 0xe01dc
5084/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
5085   REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5086   Is used to determine the number of the AG context REG-pairs written back;
5087   when the Reg1WbFlg isn't set. */
5088#define UCM_REG_UCM_REG0_SZ                                      0xe00dc
5089/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5090   disregarded; valid is deasserted; all other signals are treated as usual;
5091   if 1 - normal activity. */
5092#define UCM_REG_UCM_STORM0_IFEN                                  0xe0004
5093/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5094   disregarded; valid is deasserted; all other signals are treated as usual;
5095   if 1 - normal activity. */
5096#define UCM_REG_UCM_STORM1_IFEN                                  0xe0008
5097/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5098   disregarded; acknowledge output is deasserted; all other signals are
5099   treated as usual; if 1 - normal activity. */
5100#define UCM_REG_UCM_TM_IFEN                                      0xe0020
5101/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5102   disregarded; valid is deasserted; all other signals are treated as usual;
5103   if 1 - normal activity. */
5104#define UCM_REG_UCM_UQM_IFEN                                     0xe000c
5105/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
5106#define UCM_REG_UCM_UQM_USE_Q                                    0xe00d8
5107/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5108   the initial credit value; read returns the current value of the credit
5109   counter. Must be initialized to 32 at start-up. */
5110#define UCM_REG_UQM_INIT_CRD                                     0xe0220
5111/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5112   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5113   prioritised); 2 stands for weight 2; tc. */
5114#define UCM_REG_UQM_P_WEIGHT                                     0xe00cc
5115/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5116   stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5117   prioritised); 2 stands for weight 2; tc. */
5118#define UCM_REG_UQM_S_WEIGHT                                     0xe00d0
5119/* [RW 28] The CM header value for QM request (primary). */
5120#define UCM_REG_UQM_UCM_HDR_P                                    0xe0094
5121/* [RW 28] The CM header value for QM request (secondary). */
5122#define UCM_REG_UQM_UCM_HDR_S                                    0xe0098
5123/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5124   acknowledge output is deasserted; all other signals are treated as usual;
5125   if 1 - normal activity. */
5126#define UCM_REG_UQM_UCM_IFEN                                     0xe0014
5127/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5128   acknowledge output is deasserted; all other signals are treated as usual;
5129   if 1 - norm