akaros/kern/drivers/net/bnx2x/bnx2x_link.h
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   1/* Copyright 2008-2013 Broadcom Corporation
   2 *
   3 * Unless you and Broadcom execute a separate written software license
   4 * agreement governing use of this software, this software is licensed to you
   5 * under the terms of the GNU General Public License version 2, available
   6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7 *
   8 * Notwithstanding the above, under no circumstances may you combine this
   9 * software in any way with any other Broadcom software provided under a
  10 * license other than the GPL, without Broadcom's express prior written
  11 * consent.
  12 *
  13 * Written by Yaniv Rosner
  14 *
  15 */
  16
  17#pragma once
  18
  19
  20
  21/***********************************************************/
  22/*                         Defines                         */
  23/***********************************************************/
  24#define DEFAULT_PHY_DEV_ADDR    3
  25#define E2_DEFAULT_PHY_DEV_ADDR 5
  26
  27
  28
  29#define BNX2X_FLOW_CTRL_AUTO            PORT_FEATURE_FLOW_CONTROL_AUTO
  30#define BNX2X_FLOW_CTRL_TX              PORT_FEATURE_FLOW_CONTROL_TX
  31#define BNX2X_FLOW_CTRL_RX              PORT_FEATURE_FLOW_CONTROL_RX
  32#define BNX2X_FLOW_CTRL_BOTH            PORT_FEATURE_FLOW_CONTROL_BOTH
  33#define BNX2X_FLOW_CTRL_NONE            PORT_FEATURE_FLOW_CONTROL_NONE
  34
  35#define NET_SERDES_IF_XFI               1
  36#define NET_SERDES_IF_SFI               2
  37#define NET_SERDES_IF_KR                3
  38#define NET_SERDES_IF_DXGXS     4
  39
  40#define SPEED_AUTO_NEG          0
  41#define SPEED_20000             20000
  42
  43#define I2C_DEV_ADDR_A0                 0xa0
  44#define I2C_DEV_ADDR_A2                 0xa2
  45
  46#define SFP_EEPROM_PAGE_SIZE                    16
  47#define SFP_EEPROM_VENDOR_NAME_ADDR             0x14
  48#define SFP_EEPROM_VENDOR_NAME_SIZE             16
  49#define SFP_EEPROM_VENDOR_OUI_ADDR              0x25
  50#define SFP_EEPROM_VENDOR_OUI_SIZE              3
  51#define SFP_EEPROM_PART_NO_ADDR                 0x28
  52#define SFP_EEPROM_PART_NO_SIZE                 16
  53#define SFP_EEPROM_REVISION_ADDR                0x38
  54#define SFP_EEPROM_REVISION_SIZE                4
  55#define SFP_EEPROM_SERIAL_ADDR                  0x44
  56#define SFP_EEPROM_SERIAL_SIZE                  16
  57#define SFP_EEPROM_DATE_ADDR                    0x54 /* ASCII YYMMDD */
  58#define SFP_EEPROM_DATE_SIZE                    6
  59#define SFP_EEPROM_DIAG_TYPE_ADDR               0x5c
  60#define SFP_EEPROM_DIAG_TYPE_SIZE               1
  61#define SFP_EEPROM_DIAG_ADDR_CHANGE_REQ         (1<<2)
  62#define SFP_EEPROM_SFF_8472_COMP_ADDR           0x5e
  63#define SFP_EEPROM_SFF_8472_COMP_SIZE           1
  64
  65#define SFP_EEPROM_A2_CHECKSUM_RANGE            0x5e
  66#define SFP_EEPROM_A2_CC_DMI_ADDR               0x5f
  67
  68#define PWR_FLT_ERR_MSG_LEN                     250
  69
  70#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
  71                ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
  72#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
  73                (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
  74                 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
  75#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
  76                ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
  77
  78/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
  79#define SINGLE_MEDIA_DIRECT(params)     (params->num_phys == 1)
  80/* Single Media board contains single external phy */
  81#define SINGLE_MEDIA(params)            (params->num_phys == 2)
  82/* Dual Media board contains two external phy with different media */
  83#define DUAL_MEDIA(params)              (params->num_phys == 3)
  84
  85#define FW_PARAM_PHY_ADDR_MASK          0x000000FF
  86#define FW_PARAM_PHY_TYPE_MASK          0x0000FF00
  87#define FW_PARAM_MDIO_CTRL_MASK         0xFFFF0000
  88#define FW_PARAM_MDIO_CTRL_OFFSET               16
  89#define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
  90                                           FW_PARAM_PHY_ADDR_MASK)
  91#define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
  92                                           FW_PARAM_PHY_TYPE_MASK)
  93#define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
  94                                            FW_PARAM_MDIO_CTRL_MASK) >> \
  95                                            FW_PARAM_MDIO_CTRL_OFFSET)
  96#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
  97        (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
  98
  99
 100#define PFC_BRB_FULL_LB_XOFF_THRESHOLD                          170
 101#define PFC_BRB_FULL_LB_XON_THRESHOLD                           250
 102
 103#define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
 104
 105#define BMAC_CONTROL_RX_ENABLE          2
 106/***********************************************************/
 107/*                         Structs                         */
 108/***********************************************************/
 109#define INT_PHY         0
 110#define EXT_PHY1        1
 111#define EXT_PHY2        2
 112#define MAX_PHYS        3
 113
 114/* Same configuration is shared between the XGXS and the first external phy */
 115#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
 116#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
 117                                         0 : (_phy_idx - 1))
 118/***********************************************************/
 119/*                      bnx2x_phy struct                     */
 120/*  Defines the required arguments and function per phy    */
 121/***********************************************************/
 122struct link_vars;
 123struct link_params;
 124struct bnx2x_phy;
 125
 126typedef uint8_t (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
 127                            struct link_vars *vars);
 128typedef uint8_t (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
 129                            struct link_vars *vars);
 130typedef void (*link_reset_t)(struct bnx2x_phy *phy,
 131                             struct link_params *params);
 132typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
 133                                  struct link_params *params);
 134typedef uint8_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len);
 135typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
 136typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
 137                               struct link_params *params, uint8_t mode);
 138typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
 139                                    struct link_params *params,
 140                                    uint32_t action);
 141struct bnx2x_reg_set {
 142        uint8_t  devad;
 143        uint16_t reg;
 144        uint16_t val;
 145};
 146
 147struct bnx2x_phy {
 148        uint32_t type;
 149
 150        /* Loaded during init */
 151        uint8_t addr;
 152        uint8_t def_md_devad;
 153        uint16_t flags;
 154        /* No Over-Current detection */
 155#define FLAGS_NOC                       (1<<1)
 156        /* Fan failure detection required */
 157#define FLAGS_FAN_FAILURE_DET_REQ       (1<<2)
 158        /* Initialize first the XGXS and only then the phy itself */
 159#define FLAGS_INIT_XGXS_FIRST           (1<<3)
 160#define FLAGS_WC_DUAL_MODE              (1<<4)
 161#define FLAGS_4_PORT_MODE               (1<<5)
 162#define FLAGS_REARM_LATCH_SIGNAL        (1<<6)
 163#define FLAGS_SFP_NOT_APPROVED          (1<<7)
 164#define FLAGS_MDC_MDIO_WA               (1<<8)
 165#define FLAGS_DUMMY_READ                (1<<9)
 166#define FLAGS_MDC_MDIO_WA_B0            (1<<10)
 167#define FLAGS_TX_ERROR_CHECK            (1<<12)
 168#define FLAGS_EEE                       (1<<13)
 169#define FLAGS_MDC_MDIO_WA_G             (1<<15)
 170
 171        /* preemphasis values for the rx side */
 172        uint16_t rx_preemphasis[4];
 173
 174        /* preemphasis values for the tx side */
 175        uint16_t tx_preemphasis[4];
 176
 177        /* EMAC address for access MDIO */
 178        uint32_t mdio_ctrl;
 179
 180        uint32_t supported;
 181
 182        uint32_t media_type;
 183#define ETH_PHY_UNSPECIFIED     0x0
 184#define ETH_PHY_SFPP_10G_FIBER  0x1
 185#define ETH_PHY_XFP_FIBER               0x2
 186#define ETH_PHY_DA_TWINAX               0x3
 187#define ETH_PHY_BASE_T          0x4
 188#define ETH_PHY_SFP_1G_FIBER    0x5
 189#define ETH_PHY_KR              0xf0
 190#define ETH_PHY_CX4             0xf1
 191#define ETH_PHY_NOT_PRESENT     0xff
 192
 193        /* The address in which version is located*/
 194        uint32_t ver_addr;
 195
 196        uint16_t req_flow_ctrl;
 197
 198        uint16_t req_line_speed;
 199
 200        uint32_t speed_cap_mask;
 201
 202        uint16_t req_duplex;
 203        uint16_t rsrv;
 204        /* Called per phy/port init, and it configures LASI, speed, autoneg,
 205         duplex, flow control negotiation, etc. */
 206        config_init_t config_init;
 207
 208        /* Called due to interrupt. It determines the link, speed */
 209        read_status_t read_status;
 210
 211        /* Called when driver is unloading. Should reset the phy */
 212        link_reset_t link_reset;
 213
 214        /* Set the loopback configuration for the phy */
 215        config_loopback_t config_loopback;
 216
 217        /* Format the given raw number into str up to len */
 218        format_fw_ver_t format_fw_ver;
 219
 220        /* Reset the phy (both ports) */
 221        hw_reset_t hw_reset;
 222
 223        /* Set link led mode (on/off/oper)*/
 224        set_link_led_t set_link_led;
 225
 226        /* PHY Specific tasks */
 227        phy_specific_func_t phy_specific_func;
 228#define DISABLE_TX      1
 229#define ENABLE_TX       2
 230#define PHY_INIT        3
 231};
 232
 233/* Inputs parameters to the CLC */
 234struct link_params {
 235
 236        uint8_t port;
 237
 238        /* Default / User Configuration */
 239        uint8_t loopback_mode;
 240#define LOOPBACK_NONE           0
 241#define LOOPBACK_EMAC           1
 242#define LOOPBACK_BMAC           2
 243#define LOOPBACK_XGXS           3
 244#define LOOPBACK_EXT_PHY        4
 245#define LOOPBACK_EXT            5
 246#define LOOPBACK_UMAC           6
 247#define LOOPBACK_XMAC           7
 248
 249        /* Device parameters */
 250        uint8_t mac_addr[6];
 251
 252        uint16_t req_duplex[LINK_CONFIG_SIZE];
 253        uint16_t req_flow_ctrl[LINK_CONFIG_SIZE];
 254
 255        uint16_t req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
 256
 257        /* shmem parameters */
 258        uint32_t shmem_base;
 259        uint32_t shmem2_base;
 260        uint32_t speed_cap_mask[LINK_CONFIG_SIZE];
 261        uint32_t switch_cfg;
 262#define SWITCH_CFG_1G           PORT_FEATURE_CON_SWITCH_1G_SWITCH
 263#define SWITCH_CFG_10G          PORT_FEATURE_CON_SWITCH_10G_SWITCH
 264#define SWITCH_CFG_AUTO_DETECT  PORT_FEATURE_CON_SWITCH_AUTO_DETECT
 265
 266        uint32_t lane_config;
 267
 268        /* Phy register parameter */
 269        uint32_t chip_id;
 270
 271        /* features */
 272        uint32_t feature_config_flags;
 273#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED     (1<<0)
 274#define FEATURE_CONFIG_PFC_ENABLED                      (1<<1)
 275#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY         (1<<2)
 276#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY        (1<<3)
 277#define FEATURE_CONFIG_BC_SUPPORTS_AFEX                 (1<<8)
 278#define FEATURE_CONFIG_AUTOGREEEN_ENABLED                       (1<<9)
 279#define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED              (1<<10)
 280#define FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET         (1<<11)
 281#define FEATURE_CONFIG_MT_SUPPORT                       (1<<13)
 282#define FEATURE_CONFIG_BOOT_FROM_SAN                    (1<<14)
 283
 284        /* Will be populated during common init */
 285        struct bnx2x_phy phy[MAX_PHYS];
 286
 287        /* Will be populated during common init */
 288        uint8_t num_phys;
 289
 290        uint8_t rsrv;
 291
 292        /* Used to configure the EEE Tx LPI timer, has several modes of
 293         * operation, according to bits 29:28 -
 294         * 2'b00: Timer will be configured by nvram, output will be the value
 295         *        from nvram.
 296         * 2'b01: Timer will be configured by nvram, output will be in
 297         *        microseconds.
 298         * 2'b10: bits 1:0 contain an nvram value which will be used instead
 299         *        of the one located in the nvram. Output will be that value.
 300         * 2'b11: bits 19:0 contain the idle timer in microseconds; output
 301         *        will be in microseconds.
 302         * Bits 31:30 should be 2'b11 in order for EEE to be enabled.
 303         */
 304        uint32_t eee_mode;
 305#define EEE_MODE_NVRAM_BALANCED_TIME            (0xa00)
 306#define EEE_MODE_NVRAM_AGGRESSIVE_TIME          (0x100)
 307#define EEE_MODE_NVRAM_LATENCY_TIME             (0x6000)
 308#define EEE_MODE_NVRAM_MASK             (0x3)
 309#define EEE_MODE_TIMER_MASK             (0xfffff)
 310#define EEE_MODE_OUTPUT_TIME            (1<<28)
 311#define EEE_MODE_OVERRIDE_NVRAM         (1<<29)
 312#define EEE_MODE_ENABLE_LPI             (1<<30)
 313#define EEE_MODE_ADV_LPI                        (1<<31)
 314
 315        uint16_t hw_led_mode; /* part of the hw_config read from the shmem */
 316        uint32_t multi_phy_config;
 317
 318        /* Device pointer passed to all callback functions */
 319        struct bnx2x *bp;
 320        uint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when
 321                                req_flow_ctrl is set to AUTO */
 322        uint16_t link_flags;
 323#define LINK_FLAGS_INT_DISABLED         (1<<0)
 324#define PHY_INITIALIZED         (1<<1)
 325        uint32_t lfa_base;
 326
 327        /* The same definitions as the shmem2 parameter */
 328        uint32_t link_attr_sync;
 329};
 330
 331/* Output parameters */
 332struct link_vars {
 333        uint8_t phy_flags;
 334#define PHY_XGXS_FLAG                   (1<<0)
 335#define PHY_SGMII_FLAG                  (1<<1)
 336#define PHY_PHYSICAL_LINK_FLAG          (1<<2)
 337#define PHY_HALF_OPEN_CONN_FLAG         (1<<3)
 338#define PHY_OVER_CURRENT_FLAG           (1<<4)
 339#define PHY_SFP_TX_FAULT_FLAG           (1<<5)
 340
 341        uint8_t mac_type;
 342#define MAC_TYPE_NONE           0
 343#define MAC_TYPE_EMAC           1
 344#define MAC_TYPE_BMAC           2
 345#define MAC_TYPE_UMAC           3
 346#define MAC_TYPE_XMAC           4
 347
 348        uint8_t phy_link_up; /* internal phy link indication */
 349        uint8_t link_up;
 350
 351        uint16_t line_speed;
 352        uint16_t duplex;
 353
 354        uint16_t flow_ctrl;
 355        uint16_t ieee_fc;
 356
 357        /* The same definitions as the shmem parameter */
 358        uint32_t link_status;
 359        uint32_t eee_status;
 360        uint8_t fault_detected;
 361        uint8_t check_kr2_recovery_cnt;
 362#define CHECK_KR2_RECOVERY_CNT  5
 363        uint16_t periodic_flags;
 364#define PERIODIC_FLAGS_LINK_EVENT       0x0001
 365
 366        uint32_t aeu_int_mask;
 367        uint8_t rx_tx_asic_rst;
 368        uint8_t turn_to_run_wc_rt;
 369        uint16_t rsrv2;
 370};
 371
 372/***********************************************************/
 373/*                         Functions                       */
 374/***********************************************************/
 375int bnx2x_phy_init(struct link_params *params, struct link_vars *vars);
 376
 377/* Reset the link. Should be called when driver or interface goes down
 378   Before calling phy firmware upgrade, the reset_ext_phy should be set
 379   to 0 */
 380int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
 381                     uint8_t reset_ext_phy);
 382int bnx2x_lfa_reset(struct link_params *params, struct link_vars *vars);
 383/* bnx2x_link_update should be called upon link interrupt */
 384int bnx2x_link_update(struct link_params *params, struct link_vars *vars);
 385
 386/* use the following phy functions to read/write from external_phy
 387  In order to use it to read/write internal phy registers, use
 388  DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
 389  the register */
 390int bnx2x_phy_read(struct link_params *params, uint8_t phy_addr,
 391                   uint8_t devad, uint16_t reg, uint16_t *ret_val);
 392
 393int bnx2x_phy_write(struct link_params *params, uint8_t phy_addr,
 394                    uint8_t devad, uint16_t reg, uint16_t val);
 395
 396/* Reads the link_status from the shmem,
 397   and update the link vars accordingly */
 398void bnx2x_link_status_update(struct link_params *input,
 399                            struct link_vars *output);
 400/* returns string representing the fw_version of the external phy */
 401int bnx2x_get_ext_phy_fw_version(struct link_params *params, uint8_t *version,
 402                                 uint16_t len);
 403
 404/* Set/Unset the led
 405   Basically, the CLC takes care of the led for the link, but in case one needs
 406   to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
 407   blink the led, and LED_MODE_OFF to set the led off.*/
 408int bnx2x_set_led(struct link_params *params,
 409                  struct link_vars *vars, uint8_t mode, uint32_t speed);
 410#define LED_MODE_OFF                    0
 411#define LED_MODE_ON                     1
 412#define LED_MODE_OPER                   2
 413#define LED_MODE_FRONT_PANEL_OFF        3
 414
 415/* bnx2x_handle_module_detect_int should be called upon module detection
 416   interrupt */
 417void bnx2x_handle_module_detect_int(struct link_params *params);
 418
 419/* Get the actual link status. In case it returns 0, link is up,
 420        otherwise link is down*/
 421int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
 422                    uint8_t is_serdes);
 423
 424/* One-time initialization for external phy after power up */
 425int bnx2x_common_init_phy(struct bnx2x *bp, uint32_t shmem_base_path[],
 426                          uint32_t shmem2_base_path[], uint32_t chip_id);
 427
 428/* Reset the external PHY using GPIO */
 429void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, uint8_t port);
 430
 431/* Reset the external of SFX7101 */
 432void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
 433
 434/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
 435int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
 436                                 struct link_params *params, uint8_t dev_addr,
 437                                 uint16_t addr, uint16_t byte_cnt,
 438                                 uint8_t *o_buf);
 439
 440void bnx2x_hw_reset_phy(struct link_params *params);
 441
 442/* Check swap bit and adjust PHY order */
 443uint32_t bnx2x_phy_selection(struct link_params *params);
 444
 445/* Probe the phys on board, and populate them in "params" */
 446int bnx2x_phy_probe(struct link_params *params);
 447
 448/* Checks if fan failure detection is required on one of the phys on board */
 449uint8_t bnx2x_fan_failure_det_req(struct bnx2x *bp, uint32_t shmem_base,
 450                             uint32_t shmem2_base, uint8_t port);
 451
 452/* Open / close the gate between the NIG and the BRB */
 453void bnx2x_set_rx_filter(struct link_params *params, uint8_t en);
 454
 455/* DCBX structs */
 456
 457/* Number of maximum COS per chip */
 458#define DCBX_E2E3_MAX_NUM_COS           (2)
 459#define DCBX_E3B0_MAX_NUM_COS_PORT0     (6)
 460#define DCBX_E3B0_MAX_NUM_COS_PORT1     (3)
 461#define DCBX_E3B0_MAX_NUM_COS           ( \
 462                        MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
 463                            DCBX_E3B0_MAX_NUM_COS_PORT1))
 464
 465#define DCBX_MAX_NUM_COS                        ( \
 466                        MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
 467                            DCBX_E2E3_MAX_NUM_COS))
 468
 469/* PFC port configuration params */
 470struct bnx2x_nig_brb_pfc_port_params {
 471        /* NIG */
 472        uint32_t pause_enable;
 473        uint32_t llfc_out_en;
 474        uint32_t llfc_enable;
 475        uint32_t pkt_priority_to_cos;
 476        uint8_t num_of_rx_cos_priority_mask;
 477        uint32_t rx_cos_priority_mask[DCBX_MAX_NUM_COS];
 478        uint32_t llfc_high_priority_classes;
 479        uint32_t llfc_low_priority_classes;
 480};
 481
 482
 483/* ETS port configuration params */
 484struct bnx2x_ets_bw_params {
 485        uint8_t bw;
 486};
 487
 488struct bnx2x_ets_sp_params {
 489        /**
 490         * valid values are 0 - 5. 0 is highest strict priority.
 491         * There can't be two COS's with the same pri.
 492         */
 493        uint8_t pri;
 494};
 495
 496enum bnx2x_cos_state {
 497        bnx2x_cos_state_strict = 0,
 498        bnx2x_cos_state_bw = 1,
 499};
 500
 501struct bnx2x_ets_cos_params {
 502        enum bnx2x_cos_state state ;
 503        union {
 504                struct bnx2x_ets_bw_params bw_params;
 505                struct bnx2x_ets_sp_params sp_params;
 506        } params;
 507};
 508
 509struct bnx2x_ets_params {
 510        uint8_t num_of_cos; /* Number of valid COS entries*/
 511        struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS];
 512};
 513
 514/* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
 515 * when link is already up
 516 */
 517int bnx2x_update_pfc(struct link_params *params,
 518                      struct link_vars *vars,
 519                      struct bnx2x_nig_brb_pfc_port_params *pfc_params);
 520
 521
 522/* Used to configure the ETS to disable */
 523int bnx2x_ets_disabled(struct link_params *params,
 524                       struct link_vars *vars);
 525
 526/* Used to configure the ETS to BW limited */
 527void bnx2x_ets_bw_limit(const struct link_params *params,
 528                        const uint32_t cos0_bw,
 529                        const uint32_t cos1_bw);
 530
 531/* Used to configure the ETS to strict */
 532int bnx2x_ets_strict(const struct link_params *params,
 533                     const uint8_t strict_cos);
 534
 535
 536/*  Configure the COS to ETS according to BW and SP settings.*/
 537int bnx2x_ets_e3b0_config(const struct link_params *params,
 538                         const struct link_vars *vars,
 539                         struct bnx2x_ets_params *ets_params);
 540
 541void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
 542                            uint32_t chip_id, uint32_t shmem_base,
 543                            uint32_t shmem2_base,
 544                            uint8_t port);
 545
 546void bnx2x_period_func(struct link_params *params, struct link_vars *vars);
 547