akaros/kern/drivers/net/bnx2x/bnx2x_init.h
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   1/* bnx2x_init.h: Broadcom Everest network driver.
   2 *               Structures and macroes needed during the initialization.
   3 *
   4 * Copyright (c) 2007-2013 Broadcom Corporation
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation.
   9 *
  10 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  11 * Written by: Eliezer Tamir
  12 * Modified by: Vladislav Zolotarov
  13 */
  14
  15#pragma once
  16
  17/* Init operation types and structures */
  18enum {
  19        OP_RD = 0x1,    /* read a single register */
  20        OP_WR,          /* write a single register */
  21        OP_SW,          /* copy a string to the device */
  22        OP_ZR,          /* clear memory */
  23        OP_ZP,          /* unzip then copy with DMAE */
  24        OP_WR_64,       /* write 64 bit pattern */
  25        OP_WB,          /* copy a string using DMAE */
  26        OP_WB_ZR,       /* Clear a string using DMAE or indirect-wr */
  27        /* Skip the following ops if all of the init modes don't match */
  28        OP_IF_MODE_OR,
  29        /* Skip the following ops if any of the init modes don't match */
  30        OP_IF_MODE_AND,
  31        OP_MAX
  32};
  33
  34enum {
  35        STAGE_START,
  36        STAGE_END,
  37};
  38
  39/* Returns the index of start or end of a specific block stage in ops array*/
  40#define BLOCK_OPS_IDX(block, stage, end) \
  41        (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
  42
  43
  44/* structs for the various opcodes */
  45struct raw_op {
  46        uint32_t op:8;
  47        uint32_t offset:24;
  48        uint32_t raw_data;
  49};
  50
  51struct op_read {
  52        uint32_t op:8;
  53        uint32_t offset:24;
  54        uint32_t val;
  55};
  56
  57struct op_write {
  58        uint32_t op:8;
  59        uint32_t offset:24;
  60        uint32_t val;
  61};
  62
  63struct op_arr_write {
  64        uint32_t op:8;
  65        uint32_t offset:24;
  66#ifdef __BIG_ENDIAN
  67        uint16_t data_len;
  68        uint16_t data_off;
  69#else /* __LITTLE_ENDIAN */
  70        uint16_t data_off;
  71        uint16_t data_len;
  72#endif
  73};
  74
  75struct op_zero {
  76        uint32_t op:8;
  77        uint32_t offset:24;
  78        uint32_t len;
  79};
  80
  81struct op_if_mode {
  82        uint32_t op:8;
  83        uint32_t cmd_offset:24;
  84        uint32_t mode_bit_map;
  85};
  86
  87
  88union init_op {
  89        struct op_read          read;
  90        struct op_write         write;
  91        struct op_arr_write     arr_wr;
  92        struct op_zero          zero;
  93        struct raw_op           raw;
  94        struct op_if_mode       if_mode;
  95};
  96
  97
  98/* Init Phases */
  99enum {
 100        PHASE_COMMON,
 101        PHASE_PORT0,
 102        PHASE_PORT1,
 103        PHASE_PF0,
 104        PHASE_PF1,
 105        PHASE_PF2,
 106        PHASE_PF3,
 107        PHASE_PF4,
 108        PHASE_PF5,
 109        PHASE_PF6,
 110        PHASE_PF7,
 111        NUM_OF_INIT_PHASES
 112};
 113
 114/* Init Modes */
 115enum {
 116        MODE_ASIC                      = 0x00000001,
 117        MODE_FPGA                      = 0x00000002,
 118        MODE_EMUL                      = 0x00000004,
 119        MODE_E2                        = 0x00000008,
 120        MODE_E3                        = 0x00000010,
 121        MODE_PORT2                     = 0x00000020,
 122        MODE_PORT4                     = 0x00000040,
 123        MODE_SF                        = 0x00000080,
 124        MODE_MF                        = 0x00000100,
 125        MODE_MF_SD                     = 0x00000200,
 126        MODE_MF_SI                     = 0x00000400,
 127        MODE_MF_AFEX                   = 0x00000800,
 128        MODE_E3_A0                     = 0x00001000,
 129        MODE_E3_B0                     = 0x00002000,
 130        MODE_COS3                      = 0x00004000,
 131        MODE_COS6                      = 0x00008000,
 132        MODE_LITTLE_ENDIAN             = 0x00010000,
 133        MODE_BIG_ENDIAN                = 0x00020000,
 134};
 135
 136/* Init Blocks */
 137enum {
 138        BLOCK_ATC,
 139        BLOCK_BRB1,
 140        BLOCK_CCM,
 141        BLOCK_CDU,
 142        BLOCK_CFC,
 143        BLOCK_CSDM,
 144        BLOCK_CSEM,
 145        BLOCK_DBG,
 146        BLOCK_DMAE,
 147        BLOCK_DORQ,
 148        BLOCK_HC,
 149        BLOCK_IGU,
 150        BLOCK_MISC,
 151        BLOCK_NIG,
 152        BLOCK_PBF,
 153        BLOCK_PGLUE_B,
 154        BLOCK_PRS,
 155        BLOCK_PXP2,
 156        BLOCK_PXP,
 157        BLOCK_QM,
 158        BLOCK_SRC,
 159        BLOCK_TCM,
 160        BLOCK_TM,
 161        BLOCK_TSDM,
 162        BLOCK_TSEM,
 163        BLOCK_UCM,
 164        BLOCK_UPB,
 165        BLOCK_USDM,
 166        BLOCK_USEM,
 167        BLOCK_XCM,
 168        BLOCK_XPB,
 169        BLOCK_XSDM,
 170        BLOCK_XSEM,
 171        BLOCK_MISC_AEU,
 172        NUM_OF_INIT_BLOCKS
 173};
 174
 175/* QM queue numbers */
 176#define BNX2X_ETH_Q             0
 177#define BNX2X_TOE_Q             3
 178#define BNX2X_TOE_ACK_Q         6
 179#define BNX2X_ISCSI_Q           9
 180#define BNX2X_ISCSI_ACK_Q       11
 181#define BNX2X_FCOE_Q            10
 182
 183/* Vnics per mode */
 184#define BNX2X_PORT2_MODE_NUM_VNICS 4
 185#define BNX2X_PORT4_MODE_NUM_VNICS 2
 186
 187/* COS offset for port1 in E3 B0 4port mode */
 188#define BNX2X_E3B0_PORT1_COS_OFFSET 3
 189
 190/* QM Register addresses */
 191#define BNX2X_Q_VOQ_REG_ADDR(pf_q_num)\
 192        (QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
 193#define BNX2X_VOQ_Q_REG_ADDR(cos, pf_q_num)\
 194        (QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
 195#define BNX2X_Q_CMDQ_REG_ADDR(pf_q_num)\
 196        (QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
 197
 198/* extracts the QM queue number for the specified port and vnic */
 199#define BNX2X_PF_Q_NUM(q_num, port, vnic)\
 200        ((((port) << 1) | (vnic)) * 16 + (q_num))
 201
 202
 203/* Maps the specified queue to the specified COS */
 204static inline void bnx2x_map_q_cos(struct bnx2x *bp, uint32_t q_num,
 205                                   uint32_t new_cos)
 206{
 207        /* find current COS mapping */
 208        uint32_t curr_cos = REG_RD(bp, QM_REG_QVOQIDX_0 + q_num * 4);
 209
 210        /* check if queue->COS mapping has changed */
 211        if (curr_cos != new_cos) {
 212                uint32_t num_vnics = BNX2X_PORT2_MODE_NUM_VNICS;
 213                uint32_t reg_addr, reg_bit_map, vnic;
 214
 215                /* update parameters for 4port mode */
 216                if (INIT_MODE_FLAGS(bp) & MODE_PORT4) {
 217                        num_vnics = BNX2X_PORT4_MODE_NUM_VNICS;
 218                        if (BP_PORT(bp)) {
 219                                curr_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
 220                                new_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
 221                        }
 222                }
 223
 224                /* change queue mapping for each VNIC */
 225                for (vnic = 0; vnic < num_vnics; vnic++) {
 226                        uint32_t pf_q_num =
 227                                BNX2X_PF_Q_NUM(q_num, BP_PORT(bp), vnic);
 228                        uint32_t q_bit_map = 1 << (pf_q_num & 0x1f);
 229
 230                        /* overwrite queue->VOQ mapping */
 231                        REG_WR(bp, BNX2X_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
 232
 233                        /* clear queue bit from current COS bit map */
 234                        reg_addr = BNX2X_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
 235                        reg_bit_map = REG_RD(bp, reg_addr);
 236                        REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map));
 237
 238                        /* set queue bit in new COS bit map */
 239                        reg_addr = BNX2X_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
 240                        reg_bit_map = REG_RD(bp, reg_addr);
 241                        REG_WR(bp, reg_addr, reg_bit_map | q_bit_map);
 242
 243                        /* set/clear queue bit in command-queue bit map
 244                         * (E2/E3A0 only, valid COS values are 0/1)
 245                         */
 246                        if (!(INIT_MODE_FLAGS(bp) & MODE_E3_B0)) {
 247                                reg_addr = BNX2X_Q_CMDQ_REG_ADDR(pf_q_num);
 248                                reg_bit_map = REG_RD(bp, reg_addr);
 249                                q_bit_map = 1 << (2 * (pf_q_num & 0xf));
 250                                reg_bit_map = new_cos ?
 251                                              (reg_bit_map | q_bit_map) :
 252                                              (reg_bit_map & (~q_bit_map));
 253                                REG_WR(bp, reg_addr, reg_bit_map);
 254                        }
 255                }
 256        }
 257}
 258
 259/* Configures the QM according to the specified per-traffic-type COSes */
 260static inline void bnx2x_dcb_config_qm(struct bnx2x *bp, enum cos_mode mode,
 261                                       struct priority_cos *traffic_cos)
 262{
 263        bnx2x_map_q_cos(bp, BNX2X_FCOE_Q,
 264                        traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);
 265        bnx2x_map_q_cos(bp, BNX2X_ISCSI_Q,
 266                        traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
 267        bnx2x_map_q_cos(bp, BNX2X_ISCSI_ACK_Q,
 268                traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
 269        if (mode != STATIC_COS) {
 270                /* required only in backward compatible COS mode */
 271                bnx2x_map_q_cos(bp, BNX2X_ETH_Q,
 272                                traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
 273                bnx2x_map_q_cos(bp, BNX2X_TOE_Q,
 274                                traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
 275                bnx2x_map_q_cos(bp, BNX2X_TOE_ACK_Q,
 276                                traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
 277        }
 278}
 279
 280
 281/* congestion managment port init api description
 282 * the api works as follows:
 283 * the driver should pass the cmng_init_input struct, the port_init function
 284 * will prepare the required internal ram structure which will be passed back
 285 * to the driver (cmng_init) that will write it into the internal ram.
 286 *
 287 * IMPORTANT REMARKS:
 288 * 1. the cmng_init struct does not represent the contiguous internal ram
 289 *    structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET
 290 *    offset in order to write the port sub struct and the
 291 *    PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other
 292 *    words - don't use memcpy!).
 293 * 2. although the cmng_init struct is filled for the maximal vnic number
 294 *    possible, the driver should only write the valid vnics into the internal
 295 *    ram according to the appropriate port mode.
 296 */
 297#define BITS_TO_BYTES(x) ((x)/8)
 298
 299/* CMNG constants, as derived from system spec calculations */
 300
 301/* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */
 302#define DEF_MIN_RATE 100
 303
 304/* resolution of the rate shaping timer - 400 usec */
 305#define RS_PERIODIC_TIMEOUT_USEC 400
 306
 307/* number of bytes in single QM arbitration cycle -
 308 * coefficient for calculating the fairness timer
 309 */
 310#define QM_ARB_BYTES 160000
 311
 312/* resolution of Min algorithm 1:100 */
 313#define MIN_RES 100
 314
 315/* how many bytes above threshold for
 316 * the minimal credit of Min algorithm
 317 */
 318#define MIN_ABOVE_THRESH 32768
 319
 320/* Fairness algorithm integration time coefficient -
 321 * for calculating the actual Tfair
 322 */
 323#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
 324
 325/* Memory of fairness algorithm - 2 cycles */
 326#define FAIR_MEM 2
 327#define SAFC_TIMEOUT_USEC 52
 328
 329#define SDM_TICKS 4
 330
 331
 332static inline void bnx2x_init_max(const struct cmng_init_input *input_data,
 333                                  uint32_t r_param,
 334                                  struct cmng_init *ram_data)
 335{
 336        uint32_t vnic;
 337        struct cmng_vnic *vdata = &ram_data->vnic;
 338        struct cmng_struct_per_port *pdata = &ram_data->port;
 339        /* rate shaping per-port variables
 340         * 100 micro seconds in SDM ticks = 25
 341         * since each tick is 4 microSeconds
 342         */
 343
 344        pdata->rs_vars.rs_periodic_timeout =
 345        RS_PERIODIC_TIMEOUT_USEC / SDM_TICKS;
 346
 347        /* this is the threshold below which no timer arming will occur.
 348         * 1.25 coefficient is for the threshold to be a little bigger
 349         * then the real time to compensate for timer in-accuracy
 350         */
 351        pdata->rs_vars.rs_threshold =
 352        (5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4;
 353
 354        /* rate shaping per-vnic variables */
 355        for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++) {
 356                /* global vnic counter */
 357                vdata->vnic_max_rate[vnic].vn_counter.rate =
 358                input_data->vnic_max_rate[vnic];
 359                /* maximal Mbps for this vnic
 360                 * the quota in each timer period - number of bytes
 361                 * transmitted in this period
 362                 */
 363                vdata->vnic_max_rate[vnic].vn_counter.quota =
 364                        RS_PERIODIC_TIMEOUT_USEC *
 365                        (uint32_t)vdata->vnic_max_rate[vnic].vn_counter.rate / 8;
 366        }
 367
 368}
 369
 370static inline void bnx2x_init_min(const struct cmng_init_input *input_data,
 371                                  uint32_t r_param,
 372                                  struct cmng_init *ram_data)
 373{
 374        uint32_t vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair;
 375        struct cmng_vnic *vdata = &ram_data->vnic;
 376        struct cmng_struct_per_port *pdata = &ram_data->port;
 377
 378        /* this is the resolution of the fairness timer */
 379        fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
 380
 381        /* fairness per-port variables
 382         * for 10G it is 1000usec. for 1G it is 10000usec.
 383         */
 384        tFair = T_FAIR_COEF / input_data->port_rate;
 385
 386        /* this is the threshold below which we won't arm the timer anymore */
 387        pdata->fair_vars.fair_threshold = QM_ARB_BYTES;
 388
 389        /* we multiply by 1e3/8 to get bytes/msec. We don't want the credits
 390         * to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution)
 391         */
 392        pdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM;
 393
 394        /* since each tick is 4 microSeconds */
 395        pdata->fair_vars.fairness_timeout =
 396                                fair_periodic_timeout_usec / SDM_TICKS;
 397
 398        /* calculate sum of weights */
 399        vnicWeightSum = 0;
 400
 401        for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++)
 402                vnicWeightSum += input_data->vnic_min_rate[vnic];
 403
 404        /* global vnic counter */
 405        if (vnicWeightSum > 0) {
 406                /* fairness per-vnic variables */
 407                for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++) {
 408                        /* this is the credit for each period of the fairness
 409                         * algorithm - number of bytes in T_FAIR (this vnic
 410                         * share of the port rate)
 411                         */
 412                        vdata->vnic_min_rate[vnic].vn_credit_delta =
 413                                (uint32_t)input_data->vnic_min_rate[vnic] * 100 *
 414                                (T_FAIR_COEF / (8 * 100 * vnicWeightSum));
 415                        if (vdata->vnic_min_rate[vnic].vn_credit_delta <
 416                            pdata->fair_vars.fair_threshold +
 417                            MIN_ABOVE_THRESH) {
 418                                vdata->vnic_min_rate[vnic].vn_credit_delta =
 419                                        pdata->fair_vars.fair_threshold +
 420                                        MIN_ABOVE_THRESH;
 421                        }
 422                }
 423        }
 424}
 425
 426static inline void bnx2x_init_fw_wrr(const struct cmng_init_input *input_data,
 427                                     uint32_t r_param,
 428                                     struct cmng_init *ram_data)
 429{
 430        uint32_t vnic, cos;
 431        uint32_t cosWeightSum = 0;
 432        struct cmng_vnic *vdata = &ram_data->vnic;
 433        struct cmng_struct_per_port *pdata = &ram_data->port;
 434
 435        for (cos = 0; cos < MAX_COS_NUMBER; cos++)
 436                cosWeightSum += input_data->cos_min_rate[cos];
 437
 438        if (cosWeightSum > 0) {
 439
 440                for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++) {
 441                        /* Since cos and vnic shouldn't work together the rate
 442                         * to divide between the coses is the port rate.
 443                         */
 444                        uint32_t *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta;
 445                        for (cos = 0; cos < MAX_COS_NUMBER; cos++) {
 446                                /* this is the credit for each period of
 447                                 * the fairness algorithm - number of bytes
 448                                 * in T_FAIR (this cos share of the vnic rate)
 449                                 */
 450                                ccd[cos] =
 451                                    (uint32_t)input_data->cos_min_rate[cos] * 100 *
 452                                    (T_FAIR_COEF / (8 * 100 * cosWeightSum));
 453                                 if (ccd[cos] < pdata->fair_vars.fair_threshold
 454                                                + MIN_ABOVE_THRESH) {
 455                                        ccd[cos] =
 456                                            pdata->fair_vars.fair_threshold +
 457                                            MIN_ABOVE_THRESH;
 458                                }
 459                        }
 460                }
 461        }
 462}
 463
 464static inline void bnx2x_init_safc(const struct cmng_init_input *input_data,
 465                                   struct cmng_init *ram_data)
 466{
 467        /* in microSeconds */
 468        ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;
 469}
 470
 471/* Congestion management port init */
 472static inline void bnx2x_init_cmng(const struct cmng_init_input *input_data,
 473                                   struct cmng_init *ram_data)
 474{
 475        uint32_t r_param;
 476        memset(ram_data, 0, sizeof(struct cmng_init));
 477
 478        ram_data->port.flags = input_data->flags;
 479
 480        /* number of bytes transmitted in a rate of 10Gbps
 481         * in one usec = 1.25KB.
 482         */
 483        r_param = BITS_TO_BYTES(input_data->port_rate);
 484        bnx2x_init_max(input_data, r_param, ram_data);
 485        bnx2x_init_min(input_data, r_param, ram_data);
 486        bnx2x_init_fw_wrr(input_data, r_param, ram_data);
 487        bnx2x_init_safc(input_data, ram_data);
 488}
 489
 490
 491
 492/* Returns the index of start or end of a specific block stage in ops array */
 493#define BLOCK_OPS_IDX(block, stage, end) \
 494                        (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
 495
 496
 497#define INITOP_SET              0       /* set the HW directly */
 498#define INITOP_CLEAR            1       /* clear the HW directly */
 499#define INITOP_INIT             2       /* set the init-value array */
 500
 501/****************************************************************************
 502* ILT management
 503****************************************************************************/
 504struct ilt_line {
 505        dma_addr_t page_mapping;
 506        void *page;
 507        uint32_t size;
 508};
 509
 510struct ilt_client_info {
 511        uint32_t page_size;
 512        uint16_t start;
 513        uint16_t end;
 514        uint16_t client_num;
 515        uint16_t flags;
 516#define ILT_CLIENT_SKIP_INIT    0x1
 517#define ILT_CLIENT_SKIP_MEM     0x2
 518};
 519
 520struct bnx2x_ilt {
 521        uint32_t start_line;
 522        struct ilt_line         *lines;
 523        struct ilt_client_info  clients[4];
 524#define ILT_CLIENT_CDU  0
 525#define ILT_CLIENT_QM   1
 526#define ILT_CLIENT_SRC  2
 527#define ILT_CLIENT_TM   3
 528};
 529
 530/****************************************************************************
 531* SRC configuration
 532****************************************************************************/
 533struct src_ent {
 534        uint8_t opaque[56];
 535        uint64_t next;
 536};
 537
 538/****************************************************************************
 539* Parity configuration
 540****************************************************************************/
 541#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
 542{ \
 543        block##_REG_##block##_PRTY_MASK, \
 544        block##_REG_##block##_PRTY_STS_CLR, \
 545        en_mask, {m1, m1h, m2, m3}, #block \
 546}
 547
 548#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
 549{ \
 550        block##_REG_##block##_PRTY_MASK_0, \
 551        block##_REG_##block##_PRTY_STS_CLR_0, \
 552        en_mask, {m1, m1h, m2, m3}, #block"_0" \
 553}
 554
 555#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
 556{ \
 557        block##_REG_##block##_PRTY_MASK_1, \
 558        block##_REG_##block##_PRTY_STS_CLR_1, \
 559        en_mask, {m1, m1h, m2, m3}, #block"_1" \
 560}
 561
 562static const struct {
 563        uint32_t mask_addr;
 564        uint32_t sts_clr_addr;
 565        uint32_t en_mask;               /* Mask to enable parity attentions */
 566        struct {
 567                uint32_t e1;            /* 57710 */
 568                uint32_t e1h;   /* 57711 */
 569                uint32_t e2;            /* 57712 */
 570                uint32_t e3;            /* 578xx */
 571        } reg_mask;             /* Register mask (all valid bits) */
 572        char name[8];           /* Block's longest name is 7 characters long
 573                                 * (name + suffix)
 574                                 */
 575} bnx2x_blocks_parity_data[] = {
 576        /* bit 19 masked */
 577        /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
 578        /* bit 5,18,20-31 */
 579        /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
 580        /* bit 5 */
 581        /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
 582        /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
 583        /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
 584
 585        /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
 586         * want to handle "system kill" flow at the moment.
 587         */
 588        BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
 589                        0x7ffffff),
 590        BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 591                          0xffffffff),
 592        BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
 593        BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
 594        BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
 595        BLOCK_PRTY_INFO_0(NIG,  0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
 596        BLOCK_PRTY_INFO_1(NIG,  0xffff, 0, 0, 0xff, 0xffff),
 597        BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
 598        BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
 599        BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
 600        BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
 601        BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
 602        BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
 603        {GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
 604                GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
 605                {0xf, 0xf, 0xf, 0xf}, "UPB"},
 606        {GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
 607                GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
 608                {0xf, 0xf, 0xf, 0xf}, "XPB"},
 609        BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
 610        BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
 611        BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
 612        BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
 613        BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
 614        BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
 615        BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff),
 616        BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
 617        BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
 618        BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
 619        BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
 620        BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
 621        BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
 622        BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
 623        BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
 624        BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
 625        BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
 626        BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
 627                          0xffffffff),
 628        BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
 629        BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
 630                          0xffffffff),
 631        BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
 632        BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
 633                          0xffffffff),
 634        BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
 635        BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
 636                          0xffffffff),
 637        BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
 638};
 639
 640
 641/* [28] MCP Latched rom_parity
 642 * [29] MCP Latched ump_rx_parity
 643 * [30] MCP Latched ump_tx_parity
 644 * [31] MCP Latched scpad_parity
 645 */
 646#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS       \
 647        (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
 648         AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
 649         AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
 650
 651#define MISC_AEU_ENABLE_MCP_PRTY_BITS   \
 652        (MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
 653         AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
 654
 655/* Below registers control the MCP parity attention output. When
 656 * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
 657 * enabled, when cleared - disabled.
 658 */
 659static const struct {
 660        uint32_t addr;
 661        uint32_t bits;
 662} mcp_attn_ctl_regs[] = {
 663        { MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
 664                MISC_AEU_ENABLE_MCP_PRTY_BITS },
 665        { MISC_REG_AEU_ENABLE4_NIG_0,
 666                MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
 667        { MISC_REG_AEU_ENABLE4_PXP_0,
 668                MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
 669        { MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
 670                MISC_AEU_ENABLE_MCP_PRTY_BITS },
 671        { MISC_REG_AEU_ENABLE4_NIG_1,
 672                MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
 673        { MISC_REG_AEU_ENABLE4_PXP_1,
 674                MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }
 675};
 676
 677static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, uint8_t enable)
 678{
 679        int i;
 680        uint32_t reg_val;
 681
 682        for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
 683                reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr);
 684
 685                if (enable)
 686                        reg_val |= mcp_attn_ctl_regs[i].bits;
 687                else
 688                        reg_val &= ~mcp_attn_ctl_regs[i].bits;
 689
 690                REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val);
 691        }
 692}
 693
 694static inline uint32_t bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)
 695{
 696        if (CHIP_IS_E1(bp))
 697                return bnx2x_blocks_parity_data[idx].reg_mask.e1;
 698        else if (CHIP_IS_E1H(bp))
 699                return bnx2x_blocks_parity_data[idx].reg_mask.e1h;
 700        else if (CHIP_IS_E2(bp))
 701                return bnx2x_blocks_parity_data[idx].reg_mask.e2;
 702        else /* CHIP_IS_E3 */
 703                return bnx2x_blocks_parity_data[idx].reg_mask.e3;
 704}
 705
 706static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)
 707{
 708        int i;
 709
 710        for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
 711                uint32_t dis_mask = bnx2x_parity_reg_mask(bp, i);
 712
 713                if (dis_mask) {
 714                        REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
 715                               dis_mask);
 716                        DP(NETIF_MSG_HW, "Setting parity mask "
 717                                                 "for %s to\t\t0x%x\n",
 718                                    bnx2x_blocks_parity_data[i].name, dis_mask);
 719                }
 720        }
 721
 722        /* Disable MCP parity attentions */
 723        bnx2x_set_mcp_parity(bp, false);
 724}
 725
 726/* Clear the parity error status registers. */
 727static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp)
 728{
 729        int i;
 730        uint32_t reg_val, mcp_aeu_bits =
 731                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
 732                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
 733                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
 734                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
 735
 736        /* Clear SEM_FAST parities */
 737        REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
 738        REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
 739        REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
 740        REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
 741
 742        for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
 743                uint32_t reg_mask = bnx2x_parity_reg_mask(bp, i);
 744
 745                if (reg_mask) {
 746                        reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].
 747                                         sts_clr_addr);
 748                        if (reg_val & reg_mask)
 749                                DP(NETIF_MSG_HW,
 750                                            "Parity errors in %s: 0x%x\n",
 751                                            bnx2x_blocks_parity_data[i].name,
 752                                            reg_val & reg_mask);
 753                }
 754        }
 755
 756        /* Check if there were parity attentions in MCP */
 757        reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);
 758        if (reg_val & mcp_aeu_bits)
 759                DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n",
 760                   reg_val & mcp_aeu_bits);
 761
 762        /* Clear parity attentions in MCP:
 763         * [7]  clears Latched rom_parity
 764         * [8]  clears Latched ump_rx_parity
 765         * [9]  clears Latched ump_tx_parity
 766         * [10] clears Latched scpad_parity (both ports)
 767         */
 768        REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
 769}
 770
 771static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp)
 772{
 773        int i;
 774
 775        for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
 776                uint32_t reg_mask = bnx2x_parity_reg_mask(bp, i);
 777
 778                if (reg_mask)
 779                        REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
 780                                bnx2x_blocks_parity_data[i].en_mask & reg_mask);
 781        }
 782
 783        /* Enable MCP parity attentions */
 784        bnx2x_set_mcp_parity(bp, true);
 785}
 786