akaros/kern/drivers/net/bnx2x/bnx2x_hsi.h
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   1/* bnx2x_hsi.h: Broadcom Everest network driver.
   2 *
   3 * Copyright (c) 2007-2013 Broadcom Corporation
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation.
   8 */
   9#pragma once
  10
  11#include "bnx2x_fw_defs.h"
  12#include "bnx2x_mfw_req.h"
  13
  14#define FW_ENCODE_32BIT_PATTERN         0x1e1e1e1e
  15
  16struct license_key {
  17        uint32_t reserved[6];
  18
  19        uint32_t max_iscsi_conn;
  20#define BNX2X_MAX_ISCSI_TRGT_CONN_MASK  0xFFFF
  21#define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
  22#define BNX2X_MAX_ISCSI_INIT_CONN_MASK  0xFFFF0000
  23#define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
  24
  25        uint32_t reserved_a;
  26
  27        uint32_t max_fcoe_conn;
  28#define BNX2X_MAX_FCOE_TRGT_CONN_MASK   0xFFFF
  29#define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT  0
  30#define BNX2X_MAX_FCOE_INIT_CONN_MASK   0xFFFF0000
  31#define BNX2X_MAX_FCOE_INIT_CONN_SHIFT  16
  32
  33        uint32_t reserved_b[4];
  34};
  35
  36/****************************************************************************
  37 * Shared HW configuration                                                  *
  38 ****************************************************************************/
  39#define PIN_CFG_NA                          0x00000000
  40#define PIN_CFG_GPIO0_P0                    0x00000001
  41#define PIN_CFG_GPIO1_P0                    0x00000002
  42#define PIN_CFG_GPIO2_P0                    0x00000003
  43#define PIN_CFG_GPIO3_P0                    0x00000004
  44#define PIN_CFG_GPIO0_P1                    0x00000005
  45#define PIN_CFG_GPIO1_P1                    0x00000006
  46#define PIN_CFG_GPIO2_P1                    0x00000007
  47#define PIN_CFG_GPIO3_P1                    0x00000008
  48#define PIN_CFG_EPIO0                       0x00000009
  49#define PIN_CFG_EPIO1                       0x0000000a
  50#define PIN_CFG_EPIO2                       0x0000000b
  51#define PIN_CFG_EPIO3                       0x0000000c
  52#define PIN_CFG_EPIO4                       0x0000000d
  53#define PIN_CFG_EPIO5                       0x0000000e
  54#define PIN_CFG_EPIO6                       0x0000000f
  55#define PIN_CFG_EPIO7                       0x00000010
  56#define PIN_CFG_EPIO8                       0x00000011
  57#define PIN_CFG_EPIO9                       0x00000012
  58#define PIN_CFG_EPIO10                      0x00000013
  59#define PIN_CFG_EPIO11                      0x00000014
  60#define PIN_CFG_EPIO12                      0x00000015
  61#define PIN_CFG_EPIO13                      0x00000016
  62#define PIN_CFG_EPIO14                      0x00000017
  63#define PIN_CFG_EPIO15                      0x00000018
  64#define PIN_CFG_EPIO16                      0x00000019
  65#define PIN_CFG_EPIO17                      0x0000001a
  66#define PIN_CFG_EPIO18                      0x0000001b
  67#define PIN_CFG_EPIO19                      0x0000001c
  68#define PIN_CFG_EPIO20                      0x0000001d
  69#define PIN_CFG_EPIO21                      0x0000001e
  70#define PIN_CFG_EPIO22                      0x0000001f
  71#define PIN_CFG_EPIO23                      0x00000020
  72#define PIN_CFG_EPIO24                      0x00000021
  73#define PIN_CFG_EPIO25                      0x00000022
  74#define PIN_CFG_EPIO26                      0x00000023
  75#define PIN_CFG_EPIO27                      0x00000024
  76#define PIN_CFG_EPIO28                      0x00000025
  77#define PIN_CFG_EPIO29                      0x00000026
  78#define PIN_CFG_EPIO30                      0x00000027
  79#define PIN_CFG_EPIO31                      0x00000028
  80
  81/* EPIO definition */
  82#define EPIO_CFG_NA                         0x00000000
  83#define EPIO_CFG_EPIO0                      0x00000001
  84#define EPIO_CFG_EPIO1                      0x00000002
  85#define EPIO_CFG_EPIO2                      0x00000003
  86#define EPIO_CFG_EPIO3                      0x00000004
  87#define EPIO_CFG_EPIO4                      0x00000005
  88#define EPIO_CFG_EPIO5                      0x00000006
  89#define EPIO_CFG_EPIO6                      0x00000007
  90#define EPIO_CFG_EPIO7                      0x00000008
  91#define EPIO_CFG_EPIO8                      0x00000009
  92#define EPIO_CFG_EPIO9                      0x0000000a
  93#define EPIO_CFG_EPIO10                     0x0000000b
  94#define EPIO_CFG_EPIO11                     0x0000000c
  95#define EPIO_CFG_EPIO12                     0x0000000d
  96#define EPIO_CFG_EPIO13                     0x0000000e
  97#define EPIO_CFG_EPIO14                     0x0000000f
  98#define EPIO_CFG_EPIO15                     0x00000010
  99#define EPIO_CFG_EPIO16                     0x00000011
 100#define EPIO_CFG_EPIO17                     0x00000012
 101#define EPIO_CFG_EPIO18                     0x00000013
 102#define EPIO_CFG_EPIO19                     0x00000014
 103#define EPIO_CFG_EPIO20                     0x00000015
 104#define EPIO_CFG_EPIO21                     0x00000016
 105#define EPIO_CFG_EPIO22                     0x00000017
 106#define EPIO_CFG_EPIO23                     0x00000018
 107#define EPIO_CFG_EPIO24                     0x00000019
 108#define EPIO_CFG_EPIO25                     0x0000001a
 109#define EPIO_CFG_EPIO26                     0x0000001b
 110#define EPIO_CFG_EPIO27                     0x0000001c
 111#define EPIO_CFG_EPIO28                     0x0000001d
 112#define EPIO_CFG_EPIO29                     0x0000001e
 113#define EPIO_CFG_EPIO30                     0x0000001f
 114#define EPIO_CFG_EPIO31                     0x00000020
 115
 116struct mac_addr {
 117        uint32_t upper;
 118        uint32_t lower;
 119};
 120
 121struct shared_hw_cfg {                   /* NVRAM Offset */
 122        /* Up to 16 bytes of NULL-terminated string */
 123        uint8_t  part_num[16];              /* 0x104 */
 124
 125        uint32_t config;                        /* 0x114 */
 126        #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
 127                #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT             0
 128                #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V              0x00000000
 129                #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V              0x00000001
 130        #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
 131
 132        #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
 133
 134        #define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
 135
 136        #define SHARED_HW_CFG_PCIE_GEN3_DISABLED            0x00000000
 137        #define SHARED_HW_CFG_PCIE_GEN3_ENABLED             0x00000010
 138
 139        #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
 140                #define SHARED_HW_CFG_MFW_SELECT_SHIFT               8
 141        /* Whatever MFW found in NVM
 142           (if multiple found, priority order is: NC-SI, UMP, IPMI) */
 143                #define SHARED_HW_CFG_MFW_SELECT_DEFAULT             0x00000000
 144                #define SHARED_HW_CFG_MFW_SELECT_NC_SI               0x00000100
 145                #define SHARED_HW_CFG_MFW_SELECT_UMP                 0x00000200
 146                #define SHARED_HW_CFG_MFW_SELECT_IPMI                0x00000300
 147        /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
 148          (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
 149                #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI    0x00000400
 150        /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
 151          (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
 152                #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI      0x00000500
 153        /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
 154          (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
 155                #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP     0x00000600
 156
 157        #define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
 158                #define SHARED_HW_CFG_LED_MODE_SHIFT                 16
 159                #define SHARED_HW_CFG_LED_MAC1                       0x00000000
 160                #define SHARED_HW_CFG_LED_PHY1                       0x00010000
 161                #define SHARED_HW_CFG_LED_PHY2                       0x00020000
 162                #define SHARED_HW_CFG_LED_PHY3                       0x00030000
 163                #define SHARED_HW_CFG_LED_MAC2                       0x00040000
 164                #define SHARED_HW_CFG_LED_PHY4                       0x00050000
 165                #define SHARED_HW_CFG_LED_PHY5                       0x00060000
 166                #define SHARED_HW_CFG_LED_PHY6                       0x00070000
 167                #define SHARED_HW_CFG_LED_MAC3                       0x00080000
 168                #define SHARED_HW_CFG_LED_PHY7                       0x00090000
 169                #define SHARED_HW_CFG_LED_PHY9                       0x000a0000
 170                #define SHARED_HW_CFG_LED_PHY11                      0x000b0000
 171                #define SHARED_HW_CFG_LED_MAC4                       0x000c0000
 172                #define SHARED_HW_CFG_LED_PHY8                       0x000d0000
 173                #define SHARED_HW_CFG_LED_EXTPHY1                    0x000e0000
 174                #define SHARED_HW_CFG_LED_EXTPHY2                    0x000f0000
 175
 176
 177        #define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
 178                #define SHARED_HW_CFG_AN_ENABLE_SHIFT                24
 179                #define SHARED_HW_CFG_AN_ENABLE_CL37                 0x01000000
 180                #define SHARED_HW_CFG_AN_ENABLE_CL73                 0x02000000
 181                #define SHARED_HW_CFG_AN_ENABLE_BAM                  0x04000000
 182                #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION   0x08000000
 183                #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT  0x10000000
 184                #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY           0x20000000
 185
 186        #define SHARED_HW_CFG_SRIOV_MASK                    0x40000000
 187                #define SHARED_HW_CFG_SRIOV_DISABLED                 0x00000000
 188                #define SHARED_HW_CFG_SRIOV_ENABLED                  0x40000000
 189
 190        #define SHARED_HW_CFG_ATC_MASK                      0x80000000
 191                #define SHARED_HW_CFG_ATC_DISABLED                   0x00000000
 192                #define SHARED_HW_CFG_ATC_ENABLED                    0x80000000
 193
 194        uint32_t config2;                           /* 0x118 */
 195        /* one time auto detect grace period (in sec) */
 196        #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
 197        #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT                     0
 198
 199        #define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
 200        #define SHARED_HW_CFG_PCIE_GEN2_DISABLED            0x00000000
 201
 202        /* The default value for the core clock is 250MHz and it is
 203           achieved by setting the clock change to 4 */
 204        #define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
 205        #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT                     9
 206
 207        #define SHARED_HW_CFG_SMBUS_TIMING_MASK             0x00001000
 208                #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ            0x00000000
 209                #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ            0x00001000
 210
 211        #define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
 212
 213        #define SHARED_HW_CFG_WOL_CAPABLE_MASK              0x00004000
 214                #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED           0x00000000
 215                #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED            0x00004000
 216
 217                /* Output low when PERST is asserted */
 218        #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK       0x00008000
 219                #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED    0x00000000
 220                #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED     0x00008000
 221
 222        #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK    0x00070000
 223                #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT    16
 224                #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW       0x00000000
 225                #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB      0x00010000
 226                #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB    0x00020000
 227                #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB    0x00030000
 228
 229        /*  The fan failure mechanism is usually related to the PHY type
 230              since the power consumption of the board is determined by the PHY.
 231              Currently, fan is required for most designs with SFX7101, BCM8727
 232              and BCM8481. If a fan is not required for a board which uses one
 233              of those PHYs, this field should be set to "Disabled". If a fan is
 234              required for a different PHY type, this option should be set to
 235              "Enabled". The fan failure indication is expected on SPIO5 */
 236        #define SHARED_HW_CFG_FAN_FAILURE_MASK              0x00180000
 237                #define SHARED_HW_CFG_FAN_FAILURE_SHIFT              19
 238                #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE           0x00000000
 239                #define SHARED_HW_CFG_FAN_FAILURE_DISABLED           0x00080000
 240                #define SHARED_HW_CFG_FAN_FAILURE_ENABLED            0x00100000
 241
 242                /* ASPM Power Management support */
 243        #define SHARED_HW_CFG_ASPM_SUPPORT_MASK             0x00600000
 244                #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT             21
 245                #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED    0x00000000
 246                #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED      0x00200000
 247                #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED       0x00400000
 248                #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED   0x00600000
 249
 250        /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
 251           tl_control_0 (register 0x2800) */
 252        #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK         0x00800000
 253                #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED      0x00000000
 254                #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED       0x00800000
 255
 256        #define SHARED_HW_CFG_PORT_MODE_MASK                0x01000000
 257                #define SHARED_HW_CFG_PORT_MODE_2                    0x00000000
 258                #define SHARED_HW_CFG_PORT_MODE_4                    0x01000000
 259
 260        #define SHARED_HW_CFG_PATH_SWAP_MASK                0x02000000
 261                #define SHARED_HW_CFG_PATH_SWAP_DISABLED             0x00000000
 262                #define SHARED_HW_CFG_PATH_SWAP_ENABLED              0x02000000
 263
 264        /*  Set the MDC/MDIO access for the first external phy */
 265        #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK         0x1C000000
 266                #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT         26
 267                #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE      0x00000000
 268                #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0         0x04000000
 269                #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1         0x08000000
 270                #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH          0x0c000000
 271                #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED       0x10000000
 272
 273        /*  Set the MDC/MDIO access for the second external phy */
 274        #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK         0xE0000000
 275                #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT         29
 276                #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE      0x00000000
 277                #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0         0x20000000
 278                #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1         0x40000000
 279                #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH          0x60000000
 280                #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED       0x80000000
 281
 282        uint32_t config_3;                              /* 0x11C */
 283        #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK         0x00000F00
 284                #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT              8
 285                #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5        0x00000000
 286                #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0        0x00000100
 287
 288        uint32_t ump_nc_si_config;                      /* 0x120 */
 289        #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
 290                #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT       0
 291                #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC         0x00000000
 292                #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY         0x00000001
 293                #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII         0x00000000
 294                #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII        0x00000002
 295
 296        #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
 297                #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT       8
 298
 299        #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
 300                #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT   16
 301                #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE    0x00000000
 302                #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
 303
 304        uint32_t board;                 /* 0x124 */
 305        #define SHARED_HW_CFG_E3_I2C_MUX0_MASK              0x0000003F
 306        #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT                      0
 307        #define SHARED_HW_CFG_E3_I2C_MUX1_MASK              0x00000FC0
 308        #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT                      6
 309        /* Use the PIN_CFG_XXX defines on top */
 310        #define SHARED_HW_CFG_BOARD_REV_MASK                0x00ff0000
 311        #define SHARED_HW_CFG_BOARD_REV_SHIFT                        16
 312
 313        #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0f000000
 314        #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT                  24
 315
 316        #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xf0000000
 317        #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT                  28
 318
 319        uint32_t wc_lane_config;                                    /* 0x128 */
 320        #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK            0x0000FFFF
 321                #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT            0
 322                #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210         0x00001b1b
 323                #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123         0x00001be4
 324                #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210         0x0000e41b
 325                #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123         0x0000e4e4
 326        #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK         0x000000FF
 327        #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                 0
 328        #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK         0x0000FF00
 329        #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                 8
 330
 331        /* TX lane Polarity swap */
 332        #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED     0x00010000
 333        #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED     0x00020000
 334        #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED     0x00040000
 335        #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED     0x00080000
 336        /* TX lane Polarity swap */
 337        #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED     0x00100000
 338        #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED     0x00200000
 339        #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED     0x00400000
 340        #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED     0x00800000
 341
 342        /*  Selects the port layout of the board */
 343        #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK           0x0F000000
 344                #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT           24
 345                #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01           0x00000000
 346                #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10           0x01000000
 347                #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123         0x02000000
 348                #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032         0x03000000
 349                #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301         0x04000000
 350                #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210         0x05000000
 351};
 352
 353
 354/****************************************************************************
 355 * Port HW configuration                                                    *
 356 ****************************************************************************/
 357struct port_hw_cfg {                /* port 0: 0x12c  port 1: 0x2bc */
 358
 359        uint32_t pci_id;
 360        #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
 361        #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
 362
 363        uint32_t pci_sub_id;
 364        #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
 365        #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
 366
 367        uint32_t power_dissipated;
 368        #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
 369        #define PORT_HW_CFG_POWER_DIS_D0_SHIFT                       0
 370        #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
 371        #define PORT_HW_CFG_POWER_DIS_D1_SHIFT                       8
 372        #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
 373        #define PORT_HW_CFG_POWER_DIS_D2_SHIFT                       16
 374        #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
 375        #define PORT_HW_CFG_POWER_DIS_D3_SHIFT                       24
 376
 377        uint32_t power_consumed;
 378        #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
 379        #define PORT_HW_CFG_POWER_CONS_D0_SHIFT                      0
 380        #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
 381        #define PORT_HW_CFG_POWER_CONS_D1_SHIFT                      8
 382        #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
 383        #define PORT_HW_CFG_POWER_CONS_D2_SHIFT                      16
 384        #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
 385        #define PORT_HW_CFG_POWER_CONS_D3_SHIFT                      24
 386
 387        uint32_t mac_upper;
 388        #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
 389        #define PORT_HW_CFG_UPPERMAC_SHIFT                           0
 390        uint32_t mac_lower;
 391
 392        uint32_t iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
 393        uint32_t iscsi_mac_lower;
 394
 395        uint32_t rdma_mac_upper;   /* Upper 16 bits are always zeroes */
 396        uint32_t rdma_mac_lower;
 397
 398        uint32_t serdes_config;
 399        #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
 400        #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT         0
 401
 402        #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0xffff0000
 403        #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT            16
 404
 405
 406        /*  Default values: 2P-64, 4P-32 */
 407        uint32_t pf_config;                                         /* 0x158 */
 408        #define PORT_HW_CFG_PF_NUM_VF_MASK                  0x0000007F
 409        #define PORT_HW_CFG_PF_NUM_VF_SHIFT                          0
 410
 411        /*  Default values: 17 */
 412        #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK        0x00007F00
 413        #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT                8
 414
 415        #define PORT_HW_CFG_ENABLE_FLR_MASK                 0x00010000
 416        #define PORT_HW_CFG_FLR_ENABLED                     0x00010000
 417
 418        uint32_t vf_config;                                         /* 0x15C */
 419        #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK        0x0000007F
 420        #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT                0
 421
 422        #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK           0xFFFF0000
 423        #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT                   16
 424
 425        uint32_t mf_pci_id;                                         /* 0x160 */
 426        #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK           0x0000FFFF
 427        #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT                   0
 428
 429        /*  Controls the TX laser of the SFP+ module */
 430        uint32_t sfp_ctrl;                                          /* 0x164 */
 431        #define PORT_HW_CFG_TX_LASER_MASK                   0x000000FF
 432                #define PORT_HW_CFG_TX_LASER_SHIFT                   0
 433                #define PORT_HW_CFG_TX_LASER_MDIO                    0x00000000
 434                #define PORT_HW_CFG_TX_LASER_GPIO0                   0x00000001
 435                #define PORT_HW_CFG_TX_LASER_GPIO1                   0x00000002
 436                #define PORT_HW_CFG_TX_LASER_GPIO2                   0x00000003
 437                #define PORT_HW_CFG_TX_LASER_GPIO3                   0x00000004
 438
 439        /*  Controls the fault module LED of the SFP+ */
 440        #define PORT_HW_CFG_FAULT_MODULE_LED_MASK           0x0000FF00
 441                #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT           8
 442                #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0           0x00000000
 443                #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1           0x00000100
 444                #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2           0x00000200
 445                #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3           0x00000300
 446                #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED        0x00000400
 447
 448        /*  The output pin TX_DIS that controls the TX laser of the SFP+
 449          module. Use the PIN_CFG_XXX defines on top */
 450        uint32_t e3_sfp_ctrl;                               /* 0x168 */
 451        #define PORT_HW_CFG_E3_TX_LASER_MASK                0x000000FF
 452        #define PORT_HW_CFG_E3_TX_LASER_SHIFT                        0
 453
 454        /*  The output pin for SFPP_TYPE which turns on the Fault module LED */
 455        #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK           0x0000FF00
 456        #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT                   8
 457
 458        /*  The input pin MOD_ABS that indicates whether SFP+ module is
 459          present or not. Use the PIN_CFG_XXX defines on top */
 460        #define PORT_HW_CFG_E3_MOD_ABS_MASK                 0x00FF0000
 461        #define PORT_HW_CFG_E3_MOD_ABS_SHIFT                         16
 462
 463        /*  The output pin PWRDIS_SFP_X which disable the power of the SFP+
 464          module. Use the PIN_CFG_XXX defines on top */
 465        #define PORT_HW_CFG_E3_PWR_DIS_MASK                 0xFF000000
 466        #define PORT_HW_CFG_E3_PWR_DIS_SHIFT                         24
 467
 468        /*
 469         * The input pin which signals module transmit fault. Use the
 470         * PIN_CFG_XXX defines on top
 471         */
 472        uint32_t e3_cmn_pin_cfg;                                    /* 0x16C */
 473        #define PORT_HW_CFG_E3_TX_FAULT_MASK                0x000000FF
 474        #define PORT_HW_CFG_E3_TX_FAULT_SHIFT                        0
 475
 476        /*  The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
 477         top */
 478        #define PORT_HW_CFG_E3_PHY_RESET_MASK               0x0000FF00
 479        #define PORT_HW_CFG_E3_PHY_RESET_SHIFT                       8
 480
 481        /*
 482         * The output pin which powers down the PHY. Use the PIN_CFG_XXX
 483         * defines on top
 484         */
 485        #define PORT_HW_CFG_E3_PWR_DOWN_MASK                0x00FF0000
 486        #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT                        16
 487
 488        /*  The output pin values BSC_SEL which selects the I2C for this port
 489          in the I2C Mux */
 490        #define PORT_HW_CFG_E3_I2C_MUX0_MASK                0x01000000
 491        #define PORT_HW_CFG_E3_I2C_MUX1_MASK                0x02000000
 492
 493
 494        /*
 495         * The input pin I_FAULT which indicate over-current has occurred.
 496         * Use the PIN_CFG_XXX defines on top
 497         */
 498        uint32_t e3_cmn_pin_cfg1;                                   /* 0x170 */
 499        #define PORT_HW_CFG_E3_OVER_CURRENT_MASK            0x000000FF
 500        #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT                    0
 501
 502        /*  pause on host ring */
 503        uint32_t generic_features;                               /* 0x174 */
 504        #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK                   0x00000001
 505        #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT                  0
 506        #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED               0x00000000
 507        #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED                0x00000001
 508
 509        /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2
 510         * LOM recommended and tested value is 0xBEB2. Using a different
 511         * value means using a value not tested by BRCM
 512         */
 513        uint32_t sfi_tap_values;                                 /* 0x178 */
 514        #define PORT_HW_CFG_TX_EQUALIZATION_MASK                      0x0000FFFF
 515        #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT                     0
 516
 517        /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested
 518         * value is 0x2. LOM recommended and tested value is 0x2. Using a
 519         * different value means using a value not tested by BRCM
 520         */
 521        #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK                     0x000F0000
 522        #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT                    16
 523
 524        uint32_t reserved0[5];                              /* 0x17c */
 525
 526        uint32_t aeu_int_mask;                              /* 0x190 */
 527
 528        uint32_t media_type;                                        /* 0x194 */
 529        #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK            0x000000FF
 530        #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT                    0
 531
 532        #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK            0x0000FF00
 533        #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT                    8
 534
 535        #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK            0x00FF0000
 536        #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT                    16
 537
 538        /*  4 times 16 bits for all 4 lanes. In case external PHY is present
 539              (not direct mode), those values will not take effect on the 4 XGXS
 540              lanes. For some external PHYs (such as 8706 and 8726) the values
 541              will be used to configure the external PHY  in those cases, not
 542              all 4 values are needed. */
 543        uint16_t xgxs_config_rx[4];                     /* 0x198 */
 544        uint16_t xgxs_config_tx[4];                     /* 0x1A0 */
 545
 546        /* For storing FCOE mac on shared memory */
 547        uint32_t fcoe_fip_mac_upper;
 548        #define PORT_HW_CFG_FCOE_UPPERMAC_MASK              0x0000ffff
 549        #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT                      0
 550        uint32_t fcoe_fip_mac_lower;
 551
 552        uint32_t fcoe_wwn_port_name_upper;
 553        uint32_t fcoe_wwn_port_name_lower;
 554
 555        uint32_t fcoe_wwn_node_name_upper;
 556        uint32_t fcoe_wwn_node_name_lower;
 557
 558        uint32_t Reserved1[49];                             /* 0x1C0 */
 559
 560        /*  Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
 561              84833 only */
 562        uint32_t xgbt_phy_cfg;                              /* 0x284 */
 563        #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK             0x000000FF
 564        #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT                     0
 565
 566                uint32_t default_cfg;                       /* 0x288 */
 567        #define PORT_HW_CFG_GPIO0_CONFIG_MASK               0x00000003
 568                #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT               0
 569                #define PORT_HW_CFG_GPIO0_CONFIG_NA                  0x00000000
 570                #define PORT_HW_CFG_GPIO0_CONFIG_LOW                 0x00000001
 571                #define PORT_HW_CFG_GPIO0_CONFIG_HIGH                0x00000002
 572                #define PORT_HW_CFG_GPIO0_CONFIG_INPUT               0x00000003
 573
 574        #define PORT_HW_CFG_GPIO1_CONFIG_MASK               0x0000000C
 575                #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT               2
 576                #define PORT_HW_CFG_GPIO1_CONFIG_NA                  0x00000000
 577                #define PORT_HW_CFG_GPIO1_CONFIG_LOW                 0x00000004
 578                #define PORT_HW_CFG_GPIO1_CONFIG_HIGH                0x00000008
 579                #define PORT_HW_CFG_GPIO1_CONFIG_INPUT               0x0000000c
 580
 581        #define PORT_HW_CFG_GPIO2_CONFIG_MASK               0x00000030
 582                #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT               4
 583                #define PORT_HW_CFG_GPIO2_CONFIG_NA                  0x00000000
 584                #define PORT_HW_CFG_GPIO2_CONFIG_LOW                 0x00000010
 585                #define PORT_HW_CFG_GPIO2_CONFIG_HIGH                0x00000020
 586                #define PORT_HW_CFG_GPIO2_CONFIG_INPUT               0x00000030
 587
 588        #define PORT_HW_CFG_GPIO3_CONFIG_MASK               0x000000C0
 589                #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT               6
 590                #define PORT_HW_CFG_GPIO3_CONFIG_NA                  0x00000000
 591                #define PORT_HW_CFG_GPIO3_CONFIG_LOW                 0x00000040
 592                #define PORT_HW_CFG_GPIO3_CONFIG_HIGH                0x00000080
 593                #define PORT_HW_CFG_GPIO3_CONFIG_INPUT               0x000000c0
 594
 595        /*  When KR link is required to be set to force which is not
 596              KR-compliant, this parameter determine what is the trigger for it.
 597              When GPIO is selected, low input will force the speed. Currently
 598              default speed is 1G. In the future, it may be widen to select the
 599              forced speed in with another parameter. Note when force-1G is
 600              enabled, it override option 56: Link Speed option. */
 601        #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK           0x00000F00
 602                #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT           8
 603                #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED      0x00000000
 604                #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0        0x00000100
 605                #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0        0x00000200
 606                #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0        0x00000300
 607                #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0        0x00000400
 608                #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1        0x00000500
 609                #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1        0x00000600
 610                #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1        0x00000700
 611                #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1        0x00000800
 612                #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED          0x00000900
 613        /*  Enable to determine with which GPIO to reset the external phy */
 614        #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK           0x000F0000
 615                #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT           16
 616                #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE        0x00000000
 617                #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0        0x00010000
 618                #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0        0x00020000
 619                #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0        0x00030000
 620                #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0        0x00040000
 621                #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1        0x00050000
 622                #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1        0x00060000
 623                #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1        0x00070000
 624                #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1        0x00080000
 625
 626        /*  Enable BAM on KR */
 627        #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK           0x00100000
 628        #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT                   20
 629        #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED                0x00000000
 630        #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED                 0x00100000
 631
 632        /*  Enable Common Mode Sense */
 633        #define PORT_HW_CFG_ENABLE_CMS_MASK                 0x00200000
 634        #define PORT_HW_CFG_ENABLE_CMS_SHIFT                         21
 635        #define PORT_HW_CFG_ENABLE_CMS_DISABLED                      0x00000000
 636        #define PORT_HW_CFG_ENABLE_CMS_ENABLED                       0x00200000
 637
 638        /*  Determine the Serdes electrical interface   */
 639        #define PORT_HW_CFG_NET_SERDES_IF_MASK              0x0F000000
 640        #define PORT_HW_CFG_NET_SERDES_IF_SHIFT                      24
 641        #define PORT_HW_CFG_NET_SERDES_IF_SGMII                      0x00000000
 642        #define PORT_HW_CFG_NET_SERDES_IF_XFI                        0x01000000
 643        #define PORT_HW_CFG_NET_SERDES_IF_SFI                        0x02000000
 644        #define PORT_HW_CFG_NET_SERDES_IF_KR                         0x03000000
 645        #define PORT_HW_CFG_NET_SERDES_IF_DXGXS                      0x04000000
 646        #define PORT_HW_CFG_NET_SERDES_IF_KR2                        0x05000000
 647
 648
 649        uint32_t speed_capability_mask2;                            /* 0x28C */
 650        #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK       0x0000FFFF
 651                #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT       0
 652                #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL    0x00000001
 653                #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__           0x00000002
 654                #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___          0x00000004
 655                #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL   0x00000008
 656                #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G          0x00000010
 657                #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G    0x00000020
 658                #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G         0x00000040
 659                #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G         0x00000080
 660
 661        #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK       0xFFFF0000
 662                #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT       16
 663                #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL    0x00010000
 664                #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__           0x00020000
 665                #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___          0x00040000
 666                #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL   0x00080000
 667                #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G          0x00100000
 668                #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G    0x00200000
 669                #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G         0x00400000
 670                #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G         0x00800000
 671
 672
 673        /*  In the case where two media types (e.g. copper and fiber) are
 674              present and electrically active at the same time, PHY Selection
 675              will determine which of the two PHYs will be designated as the
 676              Active PHY and used for a connection to the network.  */
 677        uint32_t multi_phy_config;                                  /* 0x290 */
 678        #define PORT_HW_CFG_PHY_SELECTION_MASK              0x00000007
 679                #define PORT_HW_CFG_PHY_SELECTION_SHIFT              0
 680                #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT   0x00000000
 681                #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY          0x00000001
 682                #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY         0x00000002
 683                #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
 684                #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
 685
 686        /*  When enabled, all second phy nvram parameters will be swapped
 687              with the first phy parameters */
 688        #define PORT_HW_CFG_PHY_SWAPPED_MASK                0x00000008
 689                #define PORT_HW_CFG_PHY_SWAPPED_SHIFT                3
 690                #define PORT_HW_CFG_PHY_SWAPPED_DISABLED             0x00000000
 691                #define PORT_HW_CFG_PHY_SWAPPED_ENABLED              0x00000008
 692
 693
 694        /*  Address of the second external phy */
 695        uint32_t external_phy_config2;                      /* 0x294 */
 696        #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK         0x000000FF
 697        #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT                 0
 698
 699        /*  The second XGXS external PHY type */
 700        #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK         0x0000FF00
 701                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT         8
 702                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT        0x00000000
 703                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071       0x00000100
 704                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072       0x00000200
 705                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073       0x00000300
 706                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705       0x00000400
 707                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706       0x00000500
 708                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726       0x00000600
 709                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481       0x00000700
 710                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101       0x00000800
 711                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727       0x00000900
 712                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC   0x00000a00
 713                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823      0x00000b00
 714                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640      0x00000c00
 715                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833      0x00000d00
 716                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE    0x00000e00
 717                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722       0x00000f00
 718                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616      0x00001000
 719                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834      0x00001100
 720                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE       0x0000fd00
 721                #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN      0x0000ff00
 722
 723
 724        /*  4 times 16 bits for all 4 lanes. For some external PHYs (such as
 725              8706, 8726 and 8727) not all 4 values are needed. */
 726        uint16_t xgxs_config2_rx[4];                                /* 0x296 */
 727        uint16_t xgxs_config2_tx[4];                                /* 0x2A0 */
 728
 729        uint32_t lane_config;
 730        #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
 731                #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT              0
 732                /* AN and forced */
 733                #define PORT_HW_CFG_LANE_SWAP_CFG_01230123           0x00001b1b
 734                /* forced only */
 735                #define PORT_HW_CFG_LANE_SWAP_CFG_01233210           0x00001be4
 736                /* forced only */
 737                #define PORT_HW_CFG_LANE_SWAP_CFG_31203120           0x0000d8d8
 738                /* forced only */
 739                #define PORT_HW_CFG_LANE_SWAP_CFG_32103210           0x0000e4e4
 740        #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
 741        #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                   0
 742        #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
 743        #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                   8
 744        #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
 745        #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT               14
 746
 747        /*  Indicate whether to swap the external phy polarity */
 748        #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK          0x00010000
 749                #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED       0x00000000
 750                #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED        0x00010000
 751
 752
 753        uint32_t external_phy_config;
 754        #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
 755        #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT                  0
 756
 757        #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
 758                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT          8
 759                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT         0x00000000
 760                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071        0x00000100
 761                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072        0x00000200
 762                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073        0x00000300
 763                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705        0x00000400
 764                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706        0x00000500
 765                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726        0x00000600
 766                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481        0x00000700
 767                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101        0x00000800
 768                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727        0x00000900
 769                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC    0x00000a00
 770                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823       0x00000b00
 771                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640       0x00000c00
 772                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833       0x00000d00
 773                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE     0x00000e00
 774                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722        0x00000f00
 775                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616       0x00001000
 776                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834       0x00001100
 777                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC      0x0000fc00
 778                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE        0x0000fd00
 779                #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN       0x0000ff00
 780
 781        #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
 782        #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT                16
 783
 784        #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
 785                #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT        24
 786                #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT       0x00000000
 787                #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482      0x01000000
 788                #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD    0x02000000
 789                #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN     0xff000000
 790
 791        uint32_t speed_capability_mask;
 792        #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
 793                #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT        0
 794                #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL     0x00000001
 795                #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF     0x00000002
 796                #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF    0x00000004
 797                #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL    0x00000008
 798                #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G           0x00000010
 799                #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G         0x00000020
 800                #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G          0x00000040
 801                #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G          0x00000080
 802                #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED     0x0000f000
 803
 804        #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
 805                #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT        16
 806                #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL     0x00010000
 807                #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF     0x00020000
 808                #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF    0x00040000
 809                #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL    0x00080000
 810                #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G           0x00100000
 811                #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G         0x00200000
 812                #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G          0x00400000
 813                #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G          0x00800000
 814                #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED     0xf0000000
 815
 816        /*  A place to hold the original MAC address as a backup */
 817        uint32_t backup_mac_upper;                      /* 0x2B4 */
 818        uint32_t backup_mac_lower;                      /* 0x2B8 */
 819
 820};
 821
 822
 823/****************************************************************************
 824 * Shared Feature configuration                                             *
 825 ****************************************************************************/
 826struct shared_feat_cfg {                 /* NVRAM Offset */
 827
 828        uint32_t config;                        /* 0x450 */
 829        #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
 830
 831        /* Use NVRAM values instead of HW default values */
 832        #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
 833                                                            0x00000002
 834                #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
 835                                                                     0x00000000
 836                #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
 837                                                                     0x00000002
 838
 839        #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK         0x00000008
 840                #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO          0x00000000
 841                #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM         0x00000008
 842
 843        #define SHARED_FEAT_CFG_NCSI_ID_MASK                0x00000030
 844        #define SHARED_FEAT_CFG_NCSI_ID_SHIFT                        4
 845
 846        /*  Override the OTP back to single function mode. When using GPIO,
 847              high means only SF, 0 is according to CLP configuration */
 848        #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK          0x00000700
 849                #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT          8
 850                #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED     0x00000000
 851                #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF      0x00000100
 852                #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4          0x00000200
 853                #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT  0x00000300
 854                #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE      0x00000400
 855                #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE       0x00000600
 856                #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE  0x00000700
 857
 858        /* The interval in seconds between sending LLDP packets. Set to zero
 859           to disable the feature */
 860        #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK     0x00ff0000
 861        #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT             16
 862
 863        /* The assigned device type ID for LLDP usage */
 864        #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK    0xff000000
 865        #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT            24
 866
 867};
 868
 869
 870/****************************************************************************
 871 * Port Feature configuration                                               *
 872 ****************************************************************************/
 873struct port_feat_cfg {              /* port 0: 0x454  port 1: 0x4c8 */
 874
 875        uint32_t config;
 876        #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
 877                #define PORT_FEATURE_BAR1_SIZE_SHIFT                 0
 878                #define PORT_FEATURE_BAR1_SIZE_DISABLED              0x00000000
 879                #define PORT_FEATURE_BAR1_SIZE_64K                   0x00000001
 880                #define PORT_FEATURE_BAR1_SIZE_128K                  0x00000002
 881                #define PORT_FEATURE_BAR1_SIZE_256K                  0x00000003
 882                #define PORT_FEATURE_BAR1_SIZE_512K                  0x00000004
 883                #define PORT_FEATURE_BAR1_SIZE_1M                    0x00000005
 884                #define PORT_FEATURE_BAR1_SIZE_2M                    0x00000006
 885                #define PORT_FEATURE_BAR1_SIZE_4M                    0x00000007
 886                #define PORT_FEATURE_BAR1_SIZE_8M                    0x00000008
 887                #define PORT_FEATURE_BAR1_SIZE_16M                   0x00000009
 888                #define PORT_FEATURE_BAR1_SIZE_32M                   0x0000000a
 889                #define PORT_FEATURE_BAR1_SIZE_64M                   0x0000000b
 890                #define PORT_FEATURE_BAR1_SIZE_128M                  0x0000000c
 891                #define PORT_FEATURE_BAR1_SIZE_256M                  0x0000000d
 892                #define PORT_FEATURE_BAR1_SIZE_512M                  0x0000000e
 893                #define PORT_FEATURE_BAR1_SIZE_1G                    0x0000000f
 894        #define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
 895                #define PORT_FEATURE_BAR2_SIZE_SHIFT                 4
 896                #define PORT_FEATURE_BAR2_SIZE_DISABLED              0x00000000
 897                #define PORT_FEATURE_BAR2_SIZE_64K                   0x00000010
 898                #define PORT_FEATURE_BAR2_SIZE_128K                  0x00000020
 899                #define PORT_FEATURE_BAR2_SIZE_256K                  0x00000030
 900                #define PORT_FEATURE_BAR2_SIZE_512K                  0x00000040
 901                #define PORT_FEATURE_BAR2_SIZE_1M                    0x00000050
 902                #define PORT_FEATURE_BAR2_SIZE_2M                    0x00000060
 903                #define PORT_FEATURE_BAR2_SIZE_4M                    0x00000070
 904                #define PORT_FEATURE_BAR2_SIZE_8M                    0x00000080
 905                #define PORT_FEATURE_BAR2_SIZE_16M                   0x00000090
 906                #define PORT_FEATURE_BAR2_SIZE_32M                   0x000000a0
 907                #define PORT_FEATURE_BAR2_SIZE_64M                   0x000000b0
 908                #define PORT_FEATURE_BAR2_SIZE_128M                  0x000000c0
 909                #define PORT_FEATURE_BAR2_SIZE_256M                  0x000000d0
 910                #define PORT_FEATURE_BAR2_SIZE_512M                  0x000000e0
 911                #define PORT_FEATURE_BAR2_SIZE_1G                    0x000000f0
 912
 913        #define PORT_FEAT_CFG_DCBX_MASK                     0x00000100
 914                #define PORT_FEAT_CFG_DCBX_DISABLED                  0x00000000
 915                #define PORT_FEAT_CFG_DCBX_ENABLED                   0x00000100
 916
 917                #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK        0x00000C00
 918                #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE        0x00000400
 919                #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI       0x00000800
 920
 921        #define PORT_FEATURE_EN_SIZE_MASK                   0x0f000000
 922        #define PORT_FEATURE_EN_SIZE_SHIFT                           24
 923        #define PORT_FEATURE_WOL_ENABLED                             0x01000000
 924        #define PORT_FEATURE_MBA_ENABLED                             0x02000000
 925        #define PORT_FEATURE_MFW_ENABLED                             0x04000000
 926
 927        /* Advertise expansion ROM even if MBA is disabled */
 928        #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK        0x08000000
 929                #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED     0x00000000
 930                #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED      0x08000000
 931
 932        /* Check the optic vendor via i2c against a list of approved modules
 933           in a separate nvram image */
 934        #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK         0xe0000000
 935                #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT         29
 936                #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
 937                                                                     0x00000000
 938                #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
 939                                                                     0x20000000
 940                #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG   0x40000000
 941                #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN    0x60000000
 942
 943        uint32_t wol_config;
 944        /* Default is used when driver sets to "auto" mode */
 945        #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
 946                #define PORT_FEATURE_WOL_DEFAULT_SHIFT               0
 947                #define PORT_FEATURE_WOL_DEFAULT_DISABLE             0x00000000
 948                #define PORT_FEATURE_WOL_DEFAULT_MAGIC               0x00000001
 949                #define PORT_FEATURE_WOL_DEFAULT_ACPI                0x00000002
 950                #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI      0x00000003
 951        #define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
 952        #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
 953        #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
 954
 955        uint32_t mba_config;
 956        #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000007
 957                #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT       0
 958                #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE         0x00000000
 959                #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL         0x00000001
 960                #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP       0x00000002
 961                #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB      0x00000003
 962                #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT   0x00000004
 963                #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE        0x00000007
 964
 965        #define PORT_FEATURE_MBA_BOOT_RETRY_MASK            0x00000038
 966        #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT                    3
 967
 968        #define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
 969        #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
 970        #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
 971        #define PORT_FEATURE_MBA_HOTKEY_MASK                0x00000800
 972                #define PORT_FEATURE_MBA_HOTKEY_CTRL_S               0x00000000
 973                #define PORT_FEATURE_MBA_HOTKEY_CTRL_B               0x00000800
 974        #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
 975                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT          12
 976                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED       0x00000000
 977                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K             0x00001000
 978                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K             0x00002000
 979                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K             0x00003000
 980                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K            0x00004000
 981                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K            0x00005000
 982                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K            0x00006000
 983                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K           0x00007000
 984                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K           0x00008000
 985                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K           0x00009000
 986                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M             0x0000a000
 987                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M             0x0000b000
 988                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M             0x0000c000
 989                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M             0x0000d000
 990                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M            0x0000e000
 991                #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M            0x0000f000
 992        #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
 993        #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT                   20
 994        #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
 995                #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT        24
 996                #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO         0x00000000
 997                #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS          0x01000000
 998                #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H       0x02000000
 999                #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H       0x03000000
1000        #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
1001                #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT            26
1002                #define PORT_FEATURE_MBA_LINK_SPEED_AUTO             0x00000000
1003                #define PORT_FEATURE_MBA_LINK_SPEED_10HD             0x04000000
1004                #define PORT_FEATURE_MBA_LINK_SPEED_10FD             0x08000000
1005                #define PORT_FEATURE_MBA_LINK_SPEED_100HD            0x0c000000
1006                #define PORT_FEATURE_MBA_LINK_SPEED_100FD            0x10000000
1007                #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS            0x14000000
1008                #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS          0x18000000
1009                #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4       0x1c000000
1010                #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS           0x20000000
1011        uint32_t bmc_config;
1012        #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK         0x00000001
1013                #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT       0x00000000
1014                #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN            0x00000001
1015
1016        uint32_t mba_vlan_cfg;
1017        #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
1018        #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT                      0
1019        #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
1020
1021        uint32_t resource_cfg;
1022        #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
1023        #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
1024        #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
1025        #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
1026        #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
1027
1028        uint32_t smbus_config;
1029        #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
1030        #define PORT_FEATURE_SMBUS_ADDR_SHIFT                        1
1031
1032        uint32_t vf_config;
1033        #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK             0x0000000f
1034                #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT             0
1035                #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED          0x00000000
1036                #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K                0x00000001
1037                #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K                0x00000002
1038                #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K               0x00000003
1039                #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K               0x00000004
1040                #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K               0x00000005
1041                #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K              0x00000006
1042                #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K              0x00000007
1043                #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K              0x00000008
1044                #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M                0x00000009
1045                #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M                0x0000000a
1046                #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M                0x0000000b
1047                #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M                0x0000000c
1048                #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M               0x0000000d
1049                #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M               0x0000000e
1050                #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M               0x0000000f
1051
1052        uint32_t link_config;    /* Used as HW defaults for the driver */
1053        #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
1054                #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT          24
1055                /* (forced) low speed switch (< 10G) */
1056                #define PORT_FEATURE_CON_SWITCH_1G_SWITCH            0x00000000
1057                /* (forced) high speed switch (>= 10G) */
1058                #define PORT_FEATURE_CON_SWITCH_10G_SWITCH           0x01000000
1059                #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT          0x02000000
1060                #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT      0x03000000
1061
1062        #define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
1063                #define PORT_FEATURE_LINK_SPEED_SHIFT                16
1064                #define PORT_FEATURE_LINK_SPEED_AUTO                 0x00000000
1065                #define PORT_FEATURE_LINK_SPEED_10M_FULL             0x00010000
1066                #define PORT_FEATURE_LINK_SPEED_10M_HALF             0x00020000
1067                #define PORT_FEATURE_LINK_SPEED_100M_HALF            0x00030000
1068                #define PORT_FEATURE_LINK_SPEED_100M_FULL            0x00040000
1069                #define PORT_FEATURE_LINK_SPEED_1G                   0x00050000
1070                #define PORT_FEATURE_LINK_SPEED_2_5G                 0x00060000
1071                #define PORT_FEATURE_LINK_SPEED_10G_CX4              0x00070000
1072                #define PORT_FEATURE_LINK_SPEED_20G                  0x00080000
1073
1074        #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
1075                #define PORT_FEATURE_FLOW_CONTROL_SHIFT              8
1076                #define PORT_FEATURE_FLOW_CONTROL_AUTO               0x00000000
1077                #define PORT_FEATURE_FLOW_CONTROL_TX                 0x00000100
1078                #define PORT_FEATURE_FLOW_CONTROL_RX                 0x00000200
1079                #define PORT_FEATURE_FLOW_CONTROL_BOTH               0x00000300
1080                #define PORT_FEATURE_FLOW_CONTROL_NONE               0x00000400
1081
1082        /* The default for MCP link configuration,
1083           uses the same defines as link_config */
1084        uint32_t mfw_wol_link_cfg;
1085
1086        /* The default for the driver of the second external phy,
1087           uses the same defines as link_config */
1088        uint32_t link_config2;                              /* 0x47C */
1089
1090        /* The default for MCP of the second external phy,
1091           uses the same defines as link_config */
1092        uint32_t mfw_wol_link_cfg2;                                 /* 0x480 */
1093
1094
1095        /*  EEE power saving mode */
1096        uint32_t eee_power_mode;                                 /* 0x484 */
1097        #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK                     0x000000FF
1098        #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT                    0
1099        #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED                 0x00000000
1100        #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED                 0x00000001
1101        #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE               0x00000002
1102        #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY              0x00000003
1103
1104
1105        uint32_t Reserved2[16];                                  /* 0x488 */
1106};
1107
1108
1109/****************************************************************************
1110 * Device Information                                                       *
1111 ****************************************************************************/
1112struct shm_dev_info {                           /* size */
1113
1114        uint32_t    bc_rev; /* 8 bits each: major, minor, build */             /* 4 */
1115
1116        struct shared_hw_cfg     shared_hw_config;            /* 40 */
1117
1118        struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
1119
1120        struct shared_feat_cfg   shared_feature_config;            /* 4 */
1121
1122        struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
1123
1124};
1125
1126
1127#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1128        #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1129#endif
1130
1131#define FUNC_0              0
1132#define FUNC_1              1
1133#define FUNC_2              2
1134#define FUNC_3              3
1135#define FUNC_4              4
1136#define FUNC_5              5
1137#define FUNC_6              6
1138#define FUNC_7              7
1139#define E1_FUNC_MAX         2
1140#define E1H_FUNC_MAX            8
1141#define E2_FUNC_MAX         4   /* per path */
1142
1143#define VN_0                0
1144#define VN_1                1
1145#define VN_2                2
1146#define VN_3                3
1147#define E1VN_MAX            1
1148#define E1HVN_MAX           4
1149
1150#define E2_VF_MAX           64  /* HC_REG_VF_CONFIGURATION_SIZE */
1151/* This value (in milliseconds) determines the frequency of the driver
1152 * issuing the PULSE message code.  The firmware monitors this periodic
1153 * pulse to determine when to switch to an OS-absent mode. */
1154#define DRV_PULSE_PERIOD_MS     250
1155
1156/* This value (in milliseconds) determines how long the driver should
1157 * wait for an acknowledgement from the firmware before timing out.  Once
1158 * the firmware has timed out, the driver will assume there is no firmware
1159 * running and there won't be any firmware-driver synchronization during a
1160 * driver reset. */
1161#define FW_ACK_TIME_OUT_MS      5000
1162
1163#define FW_ACK_POLL_TIME_MS     1
1164
1165#define FW_ACK_NUM_OF_POLL  (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1166
1167#define MFW_TRACE_SIGNATURE     0x54524342
1168
1169/****************************************************************************
1170 * Driver <-> FW Mailbox                                                    *
1171 ****************************************************************************/
1172struct drv_port_mb {
1173
1174        uint32_t link_status;
1175        /* Driver should update this field on any link change event */
1176
1177        #define LINK_STATUS_NONE                                (0<<0)
1178        #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
1179        #define LINK_STATUS_LINK_UP                             0x00000001
1180        #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
1181        #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
1182        #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
1183        #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
1184        #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
1185        #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
1186        #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
1187        #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
1188        #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
1189        #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
1190        #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
1191        #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
1192        #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
1193        #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
1194        #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
1195        #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD             (11<<1)
1196        #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD             (11<<1)
1197
1198        #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
1199        #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
1200
1201        #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
1202        #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
1203        #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
1204
1205        #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
1206        #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
1207        #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
1208        #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
1209        #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
1210        #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
1211        #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
1212
1213        #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
1214        #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
1215
1216        #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
1217        #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
1218
1219        #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
1220        #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
1221        #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
1222        #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
1223        #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
1224
1225        #define LINK_STATUS_SERDES_LINK                         0x00100000
1226
1227        #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
1228        #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
1229        #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
1230        #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE         0x10000000
1231
1232        #define LINK_STATUS_PFC_ENABLED                         0x20000000
1233
1234        #define LINK_STATUS_PHYSICAL_LINK_FLAG                  0x40000000
1235        #define LINK_STATUS_SFP_TX_FAULT                        0x80000000
1236
1237        uint32_t port_stx;
1238
1239        uint32_t stat_nig_timer;
1240
1241        /* MCP firmware does not use this field */
1242        uint32_t ext_phy_fw_version;
1243
1244};
1245
1246
1247struct drv_func_mb {
1248
1249        uint32_t drv_mb_header;
1250        #define DRV_MSG_CODE_MASK                       0xffff0000
1251        #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
1252        #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
1253        #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN          0x20000000
1254        #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS         0x20010000
1255        #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP         0x20020000
1256        #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
1257        #define DRV_MSG_CODE_DCC_OK                     0x30000000
1258        #define DRV_MSG_CODE_DCC_FAILURE                0x31000000
1259        #define DRV_MSG_CODE_DIAG_ENTER_REQ             0x50000000
1260        #define DRV_MSG_CODE_DIAG_EXIT_REQ              0x60000000
1261        #define DRV_MSG_CODE_VALIDATE_KEY               0x70000000
1262        #define DRV_MSG_CODE_GET_CURR_KEY               0x80000000
1263        #define DRV_MSG_CODE_GET_UPGRADE_KEY            0x81000000
1264        #define DRV_MSG_CODE_GET_MANUF_KEY              0x82000000
1265        #define DRV_MSG_CODE_LOAD_L2B_PRAM              0x90000000
1266        #define DRV_MSG_CODE_OEM_OK                     0x00010000
1267        #define DRV_MSG_CODE_OEM_FAILURE                0x00020000
1268        #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK         0x00030000
1269        #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE    0x00040000
1270        /*
1271         * The optic module verification command requires bootcode
1272         * v5.0.6 or later, te specific optic module verification command
1273         * requires bootcode v5.2.12 or later
1274         */
1275        #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL     0xa0000000
1276        #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL     0x00050006
1277        #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL  0xa1000000
1278        #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL  0x00050234
1279        #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED        0xa2000000
1280        #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED        0x00070002
1281        #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED   0x00070014
1282        #define REQ_BC_VER_4_MT_SUPPORTED               0x00070201
1283        #define REQ_BC_VER_4_PFC_STATS_SUPPORTED        0x00070201
1284        #define REQ_BC_VER_4_FCOE_FEATURES              0x00070209
1285
1286        #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG         0xb0000000
1287        #define DRV_MSG_CODE_DCBX_PMF_DRV_OK            0xb2000000
1288        #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF     0x00070401
1289
1290        #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
1291
1292        #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC         0xd0000000
1293        #define DRV_MSG_CODE_AFEX_LISTGET_ACK           0xd1000000
1294        #define DRV_MSG_CODE_AFEX_LISTSET_ACK           0xd2000000
1295        #define DRV_MSG_CODE_AFEX_STATSGET_ACK          0xd3000000
1296        #define DRV_MSG_CODE_AFEX_VIFSET_ACK            0xd4000000
1297
1298        #define DRV_MSG_CODE_DRV_INFO_ACK               0xd8000000
1299        #define DRV_MSG_CODE_DRV_INFO_NACK              0xd9000000
1300
1301        #define DRV_MSG_CODE_EEE_RESULTS_ACK            0xda000000
1302
1303        #define DRV_MSG_CODE_RMMOD                      0xdb000000
1304        #define REQ_BC_VER_4_RMMOD_CMD                  0x0007080f
1305
1306        #define DRV_MSG_CODE_SET_MF_BW                  0xe0000000
1307        #define REQ_BC_VER_4_SET_MF_BW                  0x00060202
1308        #define DRV_MSG_CODE_SET_MF_BW_ACK              0xe1000000
1309
1310        #define DRV_MSG_CODE_LINK_STATUS_CHANGED        0x01000000
1311
1312        #define DRV_MSG_CODE_INITIATE_FLR               0x02000000
1313        #define REQ_BC_VER_4_INITIATE_FLR               0x00070213
1314
1315        #define BIOS_MSG_CODE_LIC_CHALLENGE             0xff010000
1316        #define BIOS_MSG_CODE_LIC_RESPONSE              0xff020000
1317        #define BIOS_MSG_CODE_VIRT_MAC_PRIM             0xff030000
1318        #define BIOS_MSG_CODE_VIRT_MAC_ISCSI            0xff040000
1319
1320        #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
1321
1322        uint32_t drv_mb_param;
1323        #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK         0x00ff0000
1324        #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK         0xff000000
1325
1326        #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET     0x00000002
1327
1328        #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA          0x0000100a
1329        #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA         0x00002000
1330
1331        uint32_t fw_mb_header;
1332        #define FW_MSG_CODE_MASK                        0xffff0000
1333        #define FW_MSG_CODE_DRV_LOAD_COMMON             0x10100000
1334        #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
1335        #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
1336        /* Load common chip is supported from bc 6.0.0  */
1337        #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP       0x00060000
1338        #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP        0x10130000
1339
1340        #define FW_MSG_CODE_DRV_LOAD_REFUSED            0x10200000
1341        #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
1342        #define FW_MSG_CODE_DRV_UNLOAD_COMMON           0x20100000
1343        #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20110000
1344        #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20120000
1345        #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
1346        #define FW_MSG_CODE_DCC_DONE                    0x30100000
1347        #define FW_MSG_CODE_LLDP_DONE                   0x40100000
1348        #define FW_MSG_CODE_DIAG_ENTER_DONE             0x50100000
1349        #define FW_MSG_CODE_DIAG_REFUSE                 0x50200000
1350        #define FW_MSG_CODE_DIAG_EXIT_DONE              0x60100000
1351        #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS        0x70100000
1352        #define FW_MSG_CODE_VALIDATE_KEY_FAILURE        0x70200000
1353        #define FW_MSG_CODE_GET_KEY_DONE                0x80100000
1354        #define FW_MSG_CODE_NO_KEY                      0x80f00000
1355        #define FW_MSG_CODE_LIC_INFO_NOT_READY          0x80f80000
1356        #define FW_MSG_CODE_L2B_PRAM_LOADED             0x90100000
1357        #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE     0x90210000
1358        #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE     0x90220000
1359        #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE     0x90230000
1360        #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE     0x90240000
1361        #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS        0xa0100000
1362        #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG      0xa0200000
1363        #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED     0xa0300000
1364        #define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
1365        #define FW_MSG_CODE_HW_SET_INVALID_IMAGE        0xb0100000
1366
1367        #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE     0xd0100000
1368        #define FW_MSG_CODE_AFEX_LISTGET_ACK            0xd1100000
1369        #define FW_MSG_CODE_AFEX_LISTSET_ACK            0xd2100000
1370        #define FW_MSG_CODE_AFEX_STATSGET_ACK           0xd3100000
1371        #define FW_MSG_CODE_AFEX_VIFSET_ACK             0xd4100000
1372
1373        #define FW_MSG_CODE_DRV_INFO_ACK                0xd8100000
1374        #define FW_MSG_CODE_DRV_INFO_NACK               0xd9100000
1375
1376        #define FW_MSG_CODE_EEE_RESULS_ACK              0xda100000
1377
1378        #define FW_MSG_CODE_RMMOD_ACK                   0xdb100000
1379
1380        #define FW_MSG_CODE_SET_MF_BW_SENT              0xe0000000
1381        #define FW_MSG_CODE_SET_MF_BW_DONE              0xe1000000
1382
1383        #define FW_MSG_CODE_LINK_CHANGED_ACK            0x01100000
1384
1385        #define FW_MSG_CODE_LIC_CHALLENGE               0xff010000
1386        #define FW_MSG_CODE_LIC_RESPONSE                0xff020000
1387        #define FW_MSG_CODE_VIRT_MAC_PRIM               0xff030000
1388        #define FW_MSG_CODE_VIRT_MAC_ISCSI              0xff040000
1389
1390        #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
1391
1392        uint32_t fw_mb_param;
1393
1394        uint32_t drv_pulse_mb;
1395        #define DRV_PULSE_SEQ_MASK                      0x00007fff
1396        #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
1397        /*
1398         * The system time is in the format of
1399         * (year-2001)*12*32 + month*32 + day.
1400         */
1401        #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
1402        /*
1403         * Indicate to the firmware not to go into the
1404         * OS-absent when it is not getting driver pulse.
1405         * This is used for debugging as well for PXE(MBA).
1406         */
1407
1408        uint32_t mcp_pulse_mb;
1409        #define MCP_PULSE_SEQ_MASK                      0x00007fff
1410        #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
1411        /* Indicates to the driver not to assert due to lack
1412         * of MCP response */
1413        #define MCP_EVENT_MASK                          0xffff0000
1414        #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
1415
1416        uint32_t iscsi_boot_signature;
1417        uint32_t iscsi_boot_block_offset;
1418
1419        uint32_t drv_status;
1420        #define DRV_STATUS_PMF                          0x00000001
1421        #define DRV_STATUS_VF_DISABLED                  0x00000002
1422        #define DRV_STATUS_SET_MF_BW                    0x00000004
1423        #define DRV_STATUS_LINK_EVENT                   0x00000008
1424
1425        #define DRV_STATUS_OEM_EVENT_MASK               0x00000070
1426        #define DRV_STATUS_OEM_DISABLE_ENABLE_PF        0x00000010
1427        #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION     0x00000020
1428
1429        #define DRV_STATUS_OEM_UPDATE_SVID              0x00000080
1430
1431        #define DRV_STATUS_DCC_EVENT_MASK               0x0000ff00
1432        #define DRV_STATUS_DCC_DISABLE_ENABLE_PF        0x00000100
1433        #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION     0x00000200
1434        #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS       0x00000400
1435        #define DRV_STATUS_DCC_RESERVED1                0x00000800
1436        #define DRV_STATUS_DCC_SET_PROTOCOL             0x00001000
1437        #define DRV_STATUS_DCC_SET_PRIORITY             0x00002000
1438
1439        #define DRV_STATUS_DCBX_EVENT_MASK              0x000f0000
1440        #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS     0x00010000
1441        #define DRV_STATUS_AFEX_EVENT_MASK              0x03f00000
1442        #define DRV_STATUS_AFEX_LISTGET_REQ             0x00100000
1443        #define DRV_STATUS_AFEX_LISTSET_REQ             0x00200000
1444        #define DRV_STATUS_AFEX_STATSGET_REQ            0x00400000
1445        #define DRV_STATUS_AFEX_VIFSET_REQ              0x00800000
1446
1447        #define DRV_STATUS_DRV_INFO_REQ                 0x04000000
1448
1449        #define DRV_STATUS_EEE_NEGOTIATION_RESULTS      0x08000000
1450
1451        uint32_t virt_mac_upper;
1452        #define VIRT_MAC_SIGN_MASK                      0xffff0000
1453        #define VIRT_MAC_SIGNATURE                      0x564d0000
1454        uint32_t virt_mac_lower;
1455
1456};
1457
1458
1459/****************************************************************************
1460 * Management firmware state                                                *
1461 ****************************************************************************/
1462/* Allocate 440 bytes for management firmware */
1463#define MGMTFW_STATE_WORD_SIZE                          110
1464
1465struct mgmtfw_state {
1466        uint32_t opaque[MGMTFW_STATE_WORD_SIZE];
1467};
1468
1469
1470/****************************************************************************
1471 * Multi-Function configuration                                             *
1472 ****************************************************************************/
1473struct shared_mf_cfg {
1474
1475        uint32_t clp_mb;
1476        #define SHARED_MF_CLP_SET_DEFAULT               0x00000000
1477        /* set by CLP */
1478        #define SHARED_MF_CLP_EXIT                      0x00000001
1479        /* set by MCP */
1480        #define SHARED_MF_CLP_EXIT_DONE                 0x00010000
1481
1482};
1483
1484struct port_mf_cfg {
1485
1486        uint32_t dynamic_cfg;    /* device control channel */
1487        #define PORT_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1488        #define PORT_MF_CFG_E1HOV_TAG_SHIFT             0
1489        #define PORT_MF_CFG_E1HOV_TAG_DEFAULT         PORT_MF_CFG_E1HOV_TAG_MASK
1490
1491        uint32_t reserved[1];
1492
1493};
1494
1495struct func_mf_cfg {
1496
1497        uint32_t config;
1498        /* E/R/I/D */
1499        /* function 0 of each port cannot be hidden */
1500        #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
1501
1502        #define FUNC_MF_CFG_PROTOCOL_MASK               0x00000006
1503        #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000000
1504        #define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000002
1505        #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1506        #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000006
1507        #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1508                                FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1509
1510        #define FUNC_MF_CFG_FUNC_DISABLED               0x00000008
1511        #define FUNC_MF_CFG_FUNC_DELETED                0x00000010
1512
1513        /* PRI */
1514        /* 0 - low priority, 3 - high priority */
1515        #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK      0x00000300
1516        #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT     8
1517        #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT   0x00000000
1518
1519        /* MINBW, MAXBW */
1520        /* value range - 0..100, increments in 100Mbps */
1521        #define FUNC_MF_CFG_MIN_BW_MASK                 0x00ff0000
1522        #define FUNC_MF_CFG_MIN_BW_SHIFT                16
1523        #define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
1524        #define FUNC_MF_CFG_MAX_BW_MASK                 0xff000000
1525        #define FUNC_MF_CFG_MAX_BW_SHIFT                24
1526        #define FUNC_MF_CFG_MAX_BW_DEFAULT              0x64000000
1527
1528        uint32_t mac_upper;         /* MAC */
1529        #define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
1530        #define FUNC_MF_CFG_UPPERMAC_SHIFT              0
1531        #define FUNC_MF_CFG_UPPERMAC_DEFAULT           FUNC_MF_CFG_UPPERMAC_MASK
1532        uint32_t mac_lower;
1533        #define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
1534
1535        uint32_t e1hov_tag;     /* VNI */
1536        #define FUNC_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1537        #define FUNC_MF_CFG_E1HOV_TAG_SHIFT             0
1538        #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT         FUNC_MF_CFG_E1HOV_TAG_MASK
1539
1540        /* afex default VLAN ID - 12 bits */
1541        #define FUNC_MF_CFG_AFEX_VLAN_MASK              0x0fff0000
1542        #define FUNC_MF_CFG_AFEX_VLAN_SHIFT             16
1543
1544        uint32_t afex_config;
1545        #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK                     0x000000ff
1546        #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT                    0
1547        #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK                    0x0000ff00
1548        #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT                   8
1549        #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL                     0x00000100
1550        #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK                      0x000f0000
1551        #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT                     16
1552
1553        uint32_t reserved;
1554};
1555
1556enum mf_cfg_afex_vlan_mode {
1557        FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1558        FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
1559        FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
1560};
1561
1562/* This structure is not applicable and should not be accessed on 57711 */
1563struct func_ext_cfg {
1564        uint32_t func_cfg;
1565        #define MACP_FUNC_CFG_FLAGS_MASK                0x0000007F
1566        #define MACP_FUNC_CFG_FLAGS_SHIFT               0
1567        #define MACP_FUNC_CFG_FLAGS_ENABLED             0x00000001
1568        #define MACP_FUNC_CFG_FLAGS_ETHERNET            0x00000002
1569        #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD       0x00000004
1570        #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD        0x00000008
1571        #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING        0x00000080
1572
1573        uint32_t iscsi_mac_addr_upper;
1574        uint32_t iscsi_mac_addr_lower;
1575
1576        uint32_t fcoe_mac_addr_upper;
1577        uint32_t fcoe_mac_addr_lower;
1578
1579        uint32_t fcoe_wwn_port_name_upper;
1580        uint32_t fcoe_wwn_port_name_lower;
1581
1582        uint32_t fcoe_wwn_node_name_upper;
1583        uint32_t fcoe_wwn_node_name_lower;
1584
1585        uint32_t preserve_data;
1586        #define MF_FUNC_CFG_PRESERVE_L2_MAC             (1<<0)
1587        #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC          (1<<1)
1588        #define MF_FUNC_CFG_PRESERVE_FCOE_MAC           (1<<2)
1589        #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P         (1<<3)
1590        #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N         (1<<4)
1591        #define MF_FUNC_CFG_PRESERVE_TX_BW              (1<<5)
1592};
1593
1594struct mf_cfg {
1595
1596        struct shared_mf_cfg    shared_mf_config;       /* 0x4 */
1597                                                        /* 0x8*2*2=0x20 */
1598        struct port_mf_cfg  port_mf_config[NVM_PATH_MAX][PORT_MAX];
1599        /* for all chips, there are 8 mf functions */
1600        struct func_mf_cfg  func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1601        /*
1602         * Extended configuration per function  - this array does not exist and
1603         * should not be accessed on 57711
1604         */
1605        struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1606}; /* 0x224 */
1607
1608/****************************************************************************
1609 * Shared Memory Region                                                     *
1610 ****************************************************************************/
1611struct shmem_region {                  /*   SharedMem Offset (size) */
1612
1613        uint32_t         validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
1614        #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
1615        #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
1616        /* validity bits */
1617        #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
1618        #define SHR_MEM_VALIDITY_MB                         0x00200000
1619        #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
1620        #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
1621        /* One licensing bit should be set */
1622        #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
1623        #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
1624        #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
1625        #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
1626        /* Active MFW */
1627        #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
1628        #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
1629        #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
1630        #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
1631        #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
1632        #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
1633
1634        struct shm_dev_info dev_info;        /* 0x8     (0x438) */
1635
1636        struct license_key       drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1637
1638        /* FW information (for internal FW use) */
1639        uint32_t         fw_info_fio_offset;            /* 0x4a8       (0x4) */
1640        struct mgmtfw_state mgmtfw_state;       /* 0x4ac     (0x1b8) */
1641
1642        struct drv_port_mb  port_mb[PORT_MAX];  /* 0x664 (16*2=0x20) */
1643
1644#ifdef BMAPI
1645        /* This is a variable length array */
1646        /* the number of function depends on the chip type */
1647        struct drv_func_mb func_mb[1];  /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1648#else
1649        /* the number of function depends on the chip type */
1650        struct drv_func_mb  func_mb[];  /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1651#endif /* BMAPI */
1652
1653}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1654
1655/****************************************************************************
1656 * Shared Memory 2 Region                                                   *
1657 ****************************************************************************/
1658/* The fw_flr_ack is actually built in the following way:                   */
1659/* 8 bit:  PF ack                                                           */
1660/* 64 bit: VF ack                                                           */
1661/* 8 bit:  ios_dis_ack                                                      */
1662/* In order to maintain endianity in the mailbox hsi, we want to keep using */
1663/* u32. The fw must have the VF right after the PF since this is how it     */
1664/* access arrays(it expects always the VF to reside after the PF, and that  */
1665/* makes the calculation much easier for it. )                              */
1666/* In order to answer both limitations, and keep the struct small, the code */
1667/* will abuse the structure defined here to achieve the actual partition    */
1668/* above                                                                    */
1669/****************************************************************************/
1670struct fw_flr_ack {
1671        uint32_t         pf_ack;
1672        uint32_t         vf_ack[1];
1673        uint32_t         iov_dis_ack;
1674};
1675
1676struct fw_flr_mb {
1677        uint32_t         aggint;
1678        uint32_t         opgen_addr;
1679        struct fw_flr_ack ack;
1680};
1681
1682struct eee_remote_vals {
1683        uint32_t         tx_tw;
1684        uint32_t         rx_tw;
1685};
1686
1687/**** SUPPORT FOR SHMEM ARRRAYS ***
1688 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1689 * define arrays with storage types smaller then unsigned dwords.
1690 * The macros below add generic support for SHMEM arrays with numeric elements
1691 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1692 * array with individual bit-filed elements accessed using shifts and masks.
1693 *
1694 */
1695
1696/* eb is the bitwidth of a single element */
1697#define SHMEM_ARRAY_MASK(eb)            ((1<<(eb))-1)
1698#define SHMEM_ARRAY_ENTRY(i, eb)        ((i)/(32/(eb)))
1699
1700/* the bit-position macro allows the used to flip the order of the arrays
1701 * elements on a per byte or word boundary.
1702 *
1703 * example: an array with 8 entries each 4 bit wide. This array will fit into
1704 * a single dword. The diagrmas below show the array order of the nibbles.
1705 *
1706 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1707 *
1708 *                |                |                |               |
1709 *   0    |   1   |   2    |   3   |   4    |   5   |   6   |   7   |
1710 *                |                |                |               |
1711 *
1712 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1713 *
1714 *                |                |                |               |
1715 *   1   |   0    |   3    |   2   |   5    |   4   |   7   |   6   |
1716 *                |                |                |               |
1717 *
1718 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1719 *
1720 *                |                |                |               |
1721 *   3   |   2    |   1   |   0    |   7   |   6    |   5   |   4   |
1722 *                |                |                |               |
1723 */
1724#define SHMEM_ARRAY_BITPOS(i, eb, fb)   \
1725        ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1726        (((i)%((fb)/(eb))) * (eb)))
1727
1728#define SHMEM_ARRAY_GET(a, i, eb, fb)                                   \
1729        ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) &  \
1730        SHMEM_ARRAY_MASK(eb))
1731
1732#define SHMEM_ARRAY_SET(a, i, eb, fb, val)                              \
1733do {                                                                       \
1734        a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<           \
1735        SHMEM_ARRAY_BITPOS(i, eb, fb));                                    \
1736        a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) <<  \
1737        SHMEM_ARRAY_BITPOS(i, eb, fb));                                    \
1738} while (0)
1739
1740
1741/****START OF DCBX STRUCTURES DECLARATIONS****/
1742#define DCBX_MAX_NUM_PRI_PG_ENTRIES     8
1743#define DCBX_PRI_PG_BITWIDTH            4
1744#define DCBX_PRI_PG_FBITS               8
1745#define DCBX_PRI_PG_GET(a, i)           \
1746        SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1747#define DCBX_PRI_PG_SET(a, i, val)      \
1748        SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1749#define DCBX_MAX_NUM_PG_BW_ENTRIES      8
1750#define DCBX_BW_PG_BITWIDTH             8
1751#define DCBX_PG_BW_GET(a, i)            \
1752        SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1753#define DCBX_PG_BW_SET(a, i, val)       \
1754        SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1755#define DCBX_STRICT_PRI_PG              15
1756#define DCBX_MAX_APP_PROTOCOL           16
1757#define FCOE_APP_IDX                    0
1758#define ISCSI_APP_IDX                   1
1759#define PREDEFINED_APP_IDX_MAX          2
1760
1761
1762/* Big/Little endian have the same representation. */
1763struct dcbx_ets_feature {
1764        /*
1765         * For Admin MIB - is this feature supported by the
1766         * driver | For Local MIB - should this feature be enabled.
1767         */
1768        uint32_t enabled;
1769        uint32_t  pg_bw_tbl[2];
1770        uint32_t  pri_pg_tbl[1];
1771};
1772
1773/* Driver structure in LE */
1774struct dcbx_pfc_feature {
1775#ifdef __BIG_ENDIAN
1776        uint8_t pri_en_bitmap;
1777        #define DCBX_PFC_PRI_0 0x01
1778        #define DCBX_PFC_PRI_1 0x02
1779        #define DCBX_PFC_PRI_2 0x04
1780        #define DCBX_PFC_PRI_3 0x08
1781        #define DCBX_PFC_PRI_4 0x10
1782        #define DCBX_PFC_PRI_5 0x20
1783        #define DCBX_PFC_PRI_6 0x40
1784        #define DCBX_PFC_PRI_7 0x80
1785        uint8_t pfc_caps;
1786        uint8_t reserved;
1787        uint8_t enabled;
1788#elif defined(__LITTLE_ENDIAN)
1789        uint8_t enabled;
1790        uint8_t reserved;
1791        uint8_t pfc_caps;
1792        uint8_t pri_en_bitmap;
1793        #define DCBX_PFC_PRI_0 0x01
1794        #define DCBX_PFC_PRI_1 0x02
1795        #define DCBX_PFC_PRI_2 0x04
1796        #define DCBX_PFC_PRI_3 0x08
1797        #define DCBX_PFC_PRI_4 0x10
1798        #define DCBX_PFC_PRI_5 0x20
1799        #define DCBX_PFC_PRI_6 0x40
1800        #define DCBX_PFC_PRI_7 0x80
1801#endif
1802};
1803
1804struct dcbx_app_priority_entry {
1805#ifdef __BIG_ENDIAN
1806        uint16_t  app_id;
1807        uint8_t  pri_bitmap;
1808        uint8_t  appBitfield;
1809        #define DCBX_APP_ENTRY_VALID         0x01
1810        #define DCBX_APP_ENTRY_SF_MASK       0x30
1811        #define DCBX_APP_ENTRY_SF_SHIFT      4
1812        #define DCBX_APP_SF_ETH_TYPE         0x10
1813        #define DCBX_APP_SF_PORT             0x20
1814#elif defined(__LITTLE_ENDIAN)
1815        uint8_t appBitfield;
1816        #define DCBX_APP_ENTRY_VALID         0x01
1817        #define DCBX_APP_ENTRY_SF_MASK       0x30
1818        #define DCBX_APP_ENTRY_SF_SHIFT      4
1819        #define DCBX_APP_SF_ETH_TYPE         0x10
1820        #define DCBX_APP_SF_PORT             0x20
1821        uint8_t  pri_bitmap;
1822        uint16_t  app_id;
1823#endif
1824};
1825
1826
1827/* FW structure in BE */
1828struct dcbx_app_priority_feature {
1829#ifdef __BIG_ENDIAN
1830        uint8_t reserved;
1831        uint8_t default_pri;
1832        uint8_t tc_supported;
1833        uint8_t enabled;
1834#elif defined(__LITTLE_ENDIAN)
1835        uint8_t enabled;
1836        uint8_t tc_supported;
1837        uint8_t default_pri;
1838        uint8_t reserved;
1839#endif
1840        struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1841};
1842
1843/* FW structure in BE */
1844struct dcbx_features {
1845        /* PG feature */
1846        struct dcbx_ets_feature ets;
1847        /* PFC feature */
1848        struct dcbx_pfc_feature pfc;
1849        /* APP feature */
1850        struct dcbx_app_priority_feature app;
1851};
1852
1853/* LLDP protocol parameters */
1854/* FW structure in BE */
1855struct lldp_params {
1856#ifdef __BIG_ENDIAN
1857        uint8_t  msg_fast_tx_interval;
1858        uint8_t  msg_tx_hold;
1859        uint8_t  msg_tx_interval;
1860        uint8_t  admin_status;
1861        #define LLDP_TX_ONLY  0x01
1862        #define LLDP_RX_ONLY  0x02
1863        #define LLDP_TX_RX    0x03
1864        #define LLDP_DISABLED 0x04
1865        uint8_t  reserved1;
1866        uint8_t  tx_fast;
1867        uint8_t  tx_crd_max;
1868        uint8_t  tx_crd;
1869#elif defined(__LITTLE_ENDIAN)
1870        uint8_t  admin_status;
1871        #define LLDP_TX_ONLY  0x01
1872        #define LLDP_RX_ONLY  0x02
1873        #define LLDP_TX_RX    0x03
1874        #define LLDP_DISABLED 0x04
1875        uint8_t  msg_tx_interval;
1876        uint8_t  msg_tx_hold;
1877        uint8_t  msg_fast_tx_interval;
1878        uint8_t  tx_crd;
1879        uint8_t  tx_crd_max;
1880        uint8_t  tx_fast;
1881        uint8_t  reserved1;
1882#endif
1883        #define REM_CHASSIS_ID_STAT_LEN 4
1884        #define REM_PORT_ID_STAT_LEN 4
1885        /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1886        uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1887        /* Holds remote Port ID TLV header, subtype and 9B of payload. */
1888        uint32_t peer_port_id[REM_PORT_ID_STAT_LEN];
1889};
1890
1891struct lldp_dcbx_stat {
1892        #define LOCAL_CHASSIS_ID_STAT_LEN 2
1893        #define LOCAL_PORT_ID_STAT_LEN 2
1894        /* Holds local Chassis ID 8B payload of constant subtype 4. */
1895        uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1896        /* Holds local Port ID 8B payload of constant subtype 3. */
1897        uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN];
1898        /* Number of DCBX frames transmitted. */
1899        uint32_t num_tx_dcbx_pkts;
1900        /* Number of DCBX frames received. */
1901        uint32_t num_rx_dcbx_pkts;
1902};
1903
1904/* ADMIN MIB - DCBX local machine default configuration. */
1905struct lldp_admin_mib {
1906        uint32_t     ver_cfg_flags;
1907        #define DCBX_ETS_CONFIG_TX_ENABLED       0x00000001
1908        #define DCBX_PFC_CONFIG_TX_ENABLED       0x00000002
1909        #define DCBX_APP_CONFIG_TX_ENABLED       0x00000004
1910        #define DCBX_ETS_RECO_TX_ENABLED         0x00000008
1911        #define DCBX_ETS_RECO_VALID              0x00000010
1912        #define DCBX_ETS_WILLING                 0x00000020
1913        #define DCBX_PFC_WILLING                 0x00000040
1914        #define DCBX_APP_WILLING                 0x00000080
1915        #define DCBX_VERSION_CEE                 0x00000100
1916        #define DCBX_VERSION_IEEE                0x00000200
1917        #define DCBX_DCBX_ENABLED                0x00000400
1918        #define DCBX_CEE_VERSION_MASK            0x0000f000
1919        #define DCBX_CEE_VERSION_SHIFT           12
1920        #define DCBX_CEE_MAX_VERSION_MASK        0x000f0000
1921        #define DCBX_CEE_MAX_VERSION_SHIFT       16
1922        struct dcbx_features     features;
1923};
1924
1925/* REMOTE MIB - remote machine DCBX configuration. */
1926struct lldp_remote_mib {
1927        uint32_t prefix_seq_num;
1928        uint32_t flags;
1929        #define DCBX_ETS_TLV_RX                  0x00000001
1930        #define DCBX_PFC_TLV_RX                  0x00000002
1931        #define DCBX_APP_TLV_RX                  0x00000004
1932        #define DCBX_ETS_RX_ERROR                0x00000010
1933        #define DCBX_PFC_RX_ERROR                0x00000020
1934        #define DCBX_APP_RX_ERROR                0x00000040
1935        #define DCBX_ETS_REM_WILLING             0x00000100
1936        #define DCBX_PFC_REM_WILLING             0x00000200
1937        #define DCBX_APP_REM_WILLING             0x00000400
1938        #define DCBX_REMOTE_ETS_RECO_VALID       0x00001000
1939        #define DCBX_REMOTE_MIB_VALID            0x00002000
1940        struct dcbx_features features;
1941        uint32_t suffix_seq_num;
1942};
1943
1944/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1945struct lldp_local_mib {
1946        uint32_t prefix_seq_num;
1947        /* Indicates if there is mismatch with negotiation results. */
1948        uint32_t error;
1949        #define DCBX_LOCAL_ETS_ERROR             0x00000001
1950        #define DCBX_LOCAL_PFC_ERROR             0x00000002
1951        #define DCBX_LOCAL_APP_ERROR             0x00000004
1952        #define DCBX_LOCAL_PFC_MISMATCH          0x00000010
1953        #define DCBX_LOCAL_APP_MISMATCH          0x00000020
1954        #define DCBX_REMOTE_MIB_ERROR            0x00000040
1955        #define DCBX_REMOTE_ETS_TLV_NOT_FOUND    0x00000080
1956        #define DCBX_REMOTE_PFC_TLV_NOT_FOUND    0x00000100
1957        #define DCBX_REMOTE_APP_TLV_NOT_FOUND    0x00000200
1958        struct dcbx_features   features;
1959        uint32_t suffix_seq_num;
1960};
1961/***END OF DCBX STRUCTURES DECLARATIONS***/
1962
1963/***********************************************************/
1964/*                         Elink section                   */
1965/***********************************************************/
1966#define SHMEM_LINK_CONFIG_SIZE 2
1967struct shmem_lfa {
1968        uint32_t req_duplex;
1969        #define REQ_DUPLEX_PHY0_MASK        0x0000ffff
1970        #define REQ_DUPLEX_PHY0_SHIFT       0
1971        #define REQ_DUPLEX_PHY1_MASK        0xffff0000
1972        #define REQ_DUPLEX_PHY1_SHIFT       16
1973        uint32_t req_flow_ctrl;
1974        #define REQ_FLOW_CTRL_PHY0_MASK     0x0000ffff
1975        #define REQ_FLOW_CTRL_PHY0_SHIFT    0
1976        #define REQ_FLOW_CTRL_PHY1_MASK     0xffff0000
1977        #define REQ_FLOW_CTRL_PHY1_SHIFT    16
1978        uint32_t req_line_speed; /* Also determine AutoNeg */
1979        #define REQ_LINE_SPD_PHY0_MASK      0x0000ffff
1980        #define REQ_LINE_SPD_PHY0_SHIFT     0
1981        #define REQ_LINE_SPD_PHY1_MASK      0xffff0000
1982        #define REQ_LINE_SPD_PHY1_SHIFT     16
1983        uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
1984        uint32_t additional_config;
1985        #define REQ_FC_AUTO_ADV_MASK        0x0000ffff
1986        #define REQ_FC_AUTO_ADV0_SHIFT      0
1987        #define NO_LFA_DUE_TO_DCC_MASK      0x00010000
1988        uint32_t lfa_sts;
1989        #define LFA_LINK_FLAP_REASON_OFFSET             0
1990        #define LFA_LINK_FLAP_REASON_MASK               0x000000ff
1991                #define LFA_LINK_DOWN                       0x1
1992                #define LFA_LOOPBACK_ENABLED            0x2
1993                #define LFA_DUPLEX_MISMATCH                 0x3
1994                #define LFA_MFW_IS_TOO_OLD                  0x4
1995                #define LFA_LINK_SPEED_MISMATCH         0x5
1996                #define LFA_FLOW_CTRL_MISMATCH          0x6
1997                #define LFA_SPEED_CAP_MISMATCH          0x7
1998                #define LFA_DCC_LFA_DISABLED            0x8
1999                #define LFA_EEE_MISMATCH                0x9
2000
2001        #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET        8
2002        #define LINK_FLAP_AVOIDANCE_COUNT_MASK          0x0000ff00
2003
2004        #define LINK_FLAP_COUNT_OFFSET                  16
2005        #define LINK_FLAP_COUNT_MASK                    0x00ff0000
2006
2007        #define LFA_FLAGS_MASK                          0xff000000
2008        #define SHMEM_LFA_DONT_CLEAR_STAT               (1<<24)
2009};
2010
2011/* Used to support NSCI get OS driver version
2012 * on driver load the version value will be set
2013 * on driver unload driver value of 0x0 will be set.
2014 */
2015struct os_drv_ver {
2016#define DRV_VER_NOT_LOADED                      0
2017
2018        /* personalties order is important */
2019#define DRV_PERS_ETHERNET                       0
2020#define DRV_PERS_ISCSI                          1
2021#define DRV_PERS_FCOE                           2
2022
2023        /* shmem2 struct is constant can't add more personalties here */
2024#define MAX_DRV_PERS                            3
2025        uint32_t versions[MAX_DRV_PERS];
2026};
2027
2028struct ncsi_oem_fcoe_features {
2029        uint32_t fcoe_features1;
2030        #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK          0x0000FFFF
2031        #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET        0
2032
2033        #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK             0xFFFF0000
2034        #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET           16
2035
2036        uint32_t fcoe_features2;
2037        #define FCOE_FEATURES2_EXCHANGES_MASK                   0x0000FFFF
2038        #define FCOE_FEATURES2_EXCHANGES_OFFSET                 0
2039
2040        #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK           0xFFFF0000
2041        #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET         16
2042
2043        uint32_t fcoe_features3;
2044        #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK           0x0000FFFF
2045        #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET         0
2046
2047        #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK        0xFFFF0000
2048        #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET      16
2049
2050        uint32_t fcoe_features4;
2051        #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK            0x0000000F
2052        #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET          0
2053};
2054
2055struct ncsi_oem_data {
2056        uint32_t driver_version[4];
2057        struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
2058};
2059
2060struct shmem2_region {
2061
2062        uint32_t size;                                  /* 0x0000 */
2063
2064        uint32_t dcc_support;                           /* 0x0004 */
2065        #define SHMEM_DCC_SUPPORT_NONE                      0x00000000
2066        #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
2067        #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
2068        #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
2069        #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
2070        #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080
2071
2072        uint32_t ext_phy_fw_version2[PORT_MAX];         /* 0x0008 */
2073        /*
2074         * For backwards compatibility, if the mf_cfg_addr does not exist
2075         * (the size filed is smaller than 0xc) the mf_cfg resides at the
2076         * end of struct shmem_region
2077         */
2078        uint32_t mf_cfg_addr;                           /* 0x0010 */
2079        #define SHMEM_MF_CFG_ADDR_NONE                  0x00000000
2080
2081        struct fw_flr_mb flr_mb;                        /* 0x0014 */
2082        uint32_t dcbx_lldp_params_offset;                       /* 0x0028 */
2083        #define SHMEM_LLDP_DCBX_PARAMS_NONE             0x00000000
2084        uint32_t dcbx_neg_res_offset;                   /* 0x002c */
2085        #define SHMEM_DCBX_NEG_RES_NONE                 0x00000000
2086        uint32_t dcbx_remote_mib_offset;                        /* 0x0030 */
2087        #define SHMEM_DCBX_REMOTE_MIB_NONE              0x00000000
2088        /*
2089         * The other shmemX_base_addr holds the other path's shmem address
2090         * required for example in case of common phy init, or for path1 to know
2091         * the address of mcp debug trace which is located in offset from shmem
2092         * of path0
2093         */
2094        uint32_t other_shmem_base_addr;                 /* 0x0034 */
2095        uint32_t other_shmem2_base_addr;                        /* 0x0038 */
2096        /*
2097         * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
2098         * which were disabled/flred
2099         */
2100        uint32_t mcp_vf_disabled[E2_VF_MAX / 32];               /* 0x003c */
2101
2102        /*
2103         * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
2104         * VFs
2105         */
2106        uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
2107
2108        uint32_t dcbx_lldp_dcbx_stat_offset;                    /* 0x0064 */
2109        #define SHMEM_LLDP_DCBX_STAT_NONE               0x00000000
2110
2111        /*
2112         * edebug_driver_if field is used to transfer messages between edebug
2113         * app to the driver through shmem2.
2114         *
2115         * message format:
2116         * bits 0-2 -  function number / instance of driver to perform request
2117         * bits 3-5 -  op code / is_ack?
2118         * bits 6-63 - data
2119         */
2120        uint32_t edebug_driver_if[2];                   /* 0x0068 */
2121        #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR  1
2122        #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR   2
2123        #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT   3
2124
2125        uint32_t nvm_retain_bitmap_addr;                        /* 0x0070 */
2126
2127        /* afex support of that driver */
2128        uint32_t afex_driver_support;                   /* 0x0074 */
2129        #define SHMEM_AFEX_VERSION_MASK                  0x100f
2130        #define SHMEM_AFEX_SUPPORTED_VERSION_ONE         0x1001
2131        #define SHMEM_AFEX_REDUCED_DRV_LOADED            0x8000
2132
2133        /* driver receives addr in scratchpad to which it should respond */
2134        uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2135
2136        /* generic params from MCP to driver (value depends on the msg sent
2137         * to driver
2138         */
2139        uint32_t afex_param1_to_driver[E2_FUNC_MAX];            /* 0x0088 */
2140        uint32_t afex_param2_to_driver[E2_FUNC_MAX];            /* 0x0098 */
2141
2142        uint32_t swim_base_addr;                                /* 0x0108 */
2143        uint32_t swim_funcs;
2144        uint32_t swim_main_cb;
2145
2146        /* bitmap notifying which VIF profiles stored in nvram are enabled by
2147         * switch
2148         */
2149        uint32_t afex_profiles_enabled[2];
2150
2151        /* generic flags controlled by the driver */
2152        uint32_t drv_flags;
2153        #define DRV_FLAGS_DCB_CONFIGURED                0x0
2154        #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED     0x1
2155        #define DRV_FLAGS_DCB_MFW_CONFIGURED    0x2
2156
2157        #define DRV_FLAGS_PORT_MASK     ((1 << DRV_FLAGS_DCB_CONFIGURED) | \
2158                        (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
2159                        (1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
2160        /* pointer to extended dev_info shared data copied from nvm image */
2161        uint32_t extended_dev_info_shared_addr;
2162        uint32_t ncsi_oem_data_addr;
2163
2164        uint32_t ocsd_host_addr; /* initialized by option ROM */
2165        uint32_t ocbb_host_addr; /* initialized by option ROM */
2166        uint32_t ocsd_req_update_interval; /* initialized by option ROM */
2167        uint32_t temperature_in_half_celsius;
2168        uint32_t glob_struct_in_host;
2169
2170        uint32_t dcbx_neg_res_ext_offset;
2171#define SHMEM_DCBX_NEG_RES_EXT_NONE                     0x00000000
2172
2173        uint32_t drv_capabilities_flag[E2_FUNC_MAX];
2174#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2175#define DRV_FLAGS_CAPABILITIES_LOADED_L2        0x00000002
2176#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE      0x00000004
2177#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI     0x00000008
2178
2179        uint32_t extended_dev_info_shared_cfg_size;
2180
2181        uint32_t dcbx_en[PORT_MAX];
2182
2183        /* The offset points to the multi threaded meta structure */
2184        uint32_t multi_thread_data_offset;
2185
2186        /* address of DMAable host address holding values from the drivers */
2187        uint32_t drv_info_host_addr_lo;
2188        uint32_t drv_info_host_addr_hi;
2189
2190        /* general values written by the MFW (such as current version) */
2191        uint32_t drv_info_control;
2192#define DRV_INFO_CONTROL_VER_MASK          0x000000ff
2193#define DRV_INFO_CONTROL_VER_SHIFT         0
2194#define DRV_INFO_CONTROL_OP_CODE_MASK      0x0000ff00
2195#define DRV_INFO_CONTROL_OP_CODE_SHIFT     8
2196        uint32_t ibft_host_addr; /* initialized by option ROM */
2197        struct eee_remote_vals eee_remote_vals[PORT_MAX];
2198        uint32_t reserved[E2_FUNC_MAX];
2199
2200
2201        /* the status of EEE auto-negotiation
2202         * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2203         * bits 19:16 the supported modes for EEE.
2204         * bits 23:20 the speeds advertised for EEE.
2205         * bits 27:24 the speeds the Link partner advertised for EEE.
2206         * The supported/adv. modes in bits 27:19 originate from the
2207         * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
2208         * bit 28 when 1'b1 EEE was requested.
2209         * bit 29 when 1'b1 tx lpi was requested.
2210         * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
2211         * 30:29 are 2'b11.
2212         * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2213         * value. When 1'b1 those bits contains a value times 16 microseconds.
2214         */
2215        uint32_t eee_status[PORT_MAX];
2216        #define SHMEM_EEE_TIMER_MASK               0x0000ffff
2217        #define SHMEM_EEE_SUPPORTED_MASK           0x000f0000
2218        #define SHMEM_EEE_SUPPORTED_SHIFT          16
2219        #define SHMEM_EEE_ADV_STATUS_MASK          0x00f00000
2220                #define SHMEM_EEE_100M_ADV         (1<<0)
2221                #define SHMEM_EEE_1G_ADV           (1<<1)
2222                #define SHMEM_EEE_10G_ADV          (1<<2)
2223        #define SHMEM_EEE_ADV_STATUS_SHIFT         20
2224        #define SHMEM_EEE_LP_ADV_STATUS_MASK       0x0f000000
2225        #define SHMEM_EEE_LP_ADV_STATUS_SHIFT      24
2226        #define SHMEM_EEE_REQUESTED_BIT            0x10000000
2227        #define SHMEM_EEE_LPI_REQUESTED_BIT        0x20000000
2228        #define SHMEM_EEE_ACTIVE_BIT               0x40000000
2229        #define SHMEM_EEE_TIME_OUTPUT_BIT          0x80000000
2230
2231        uint32_t sizeof_port_stats;
2232
2233        /* Link Flap Avoidance */
2234        uint32_t lfa_host_addr[PORT_MAX];
2235        uint32_t reserved1;
2236
2237        uint32_t reserved2;                             /* Offset 0x148 */
2238        uint32_t reserved3;                             /* Offset 0x14C */
2239        uint32_t reserved4;                             /* Offset 0x150 */
2240        uint32_t link_attr_sync[PORT_MAX];              /* Offset 0x154 */
2241        #define LINK_ATTR_SYNC_KR2_ENABLE       0x00000001
2242        #define LINK_SFP_EEPROM_COMP_CODE_MASK  0x0000ff00
2243        #define LINK_SFP_EEPROM_COMP_CODE_SHIFT          8
2244        #define LINK_SFP_EEPROM_COMP_CODE_SR    0x00001000
2245        #define LINK_SFP_EEPROM_COMP_CODE_LR    0x00002000
2246        #define LINK_SFP_EEPROM_COMP_CODE_LRM   0x00004000
2247
2248        uint32_t reserved5[2];
2249        uint32_t reserved6[PORT_MAX];
2250
2251        /* driver version for each personality */
2252        struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */
2253
2254        /* Flag to the driver that PF's drv_info_host_addr buffer was read  */
2255        uint32_t mfw_drv_indication;
2256
2257        /* We use indication for each PF (0..3) */
2258#define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))
2259};
2260
2261
2262struct emac_stats {
2263        uint32_t     rx_stat_ifhcinoctets;
2264        uint32_t     rx_stat_ifhcinbadoctets;
2265        uint32_t     rx_stat_etherstatsfragments;
2266        uint32_t     rx_stat_ifhcinucastpkts;
2267        uint32_t     rx_stat_ifhcinmulticastpkts;
2268        uint32_t     rx_stat_ifhcinbroadcastpkts;
2269        uint32_t     rx_stat_dot3statsfcserrors;
2270        uint32_t     rx_stat_dot3statsalignmenterrors;
2271        uint32_t     rx_stat_dot3statscarriersenseerrors;
2272        uint32_t     rx_stat_xonpauseframesreceived;
2273        uint32_t     rx_stat_xoffpauseframesreceived;
2274        uint32_t     rx_stat_maccontrolframesreceived;
2275        uint32_t     rx_stat_xoffstateentered;
2276        uint32_t     rx_stat_dot3statsframestoolong;
2277        uint32_t     rx_stat_etherstatsjabbers;
2278        uint32_t     rx_stat_etherstatsundersizepkts;
2279        uint32_t     rx_stat_etherstatspkts64octets;
2280        uint32_t     rx_stat_etherstatspkts65octetsto127octets;
2281        uint32_t     rx_stat_etherstatspkts128octetsto255octets;
2282        uint32_t     rx_stat_etherstatspkts256octetsto511octets;
2283        uint32_t     rx_stat_etherstatspkts512octetsto1023octets;
2284        uint32_t     rx_stat_etherstatspkts1024octetsto1522octets;
2285        uint32_t     rx_stat_etherstatspktsover1522octets;
2286
2287        uint32_t     rx_stat_falsecarriererrors;
2288
2289        uint32_t     tx_stat_ifhcoutoctets;
2290        uint32_t     tx_stat_ifhcoutbadoctets;
2291        uint32_t     tx_stat_etherstatscollisions;
2292        uint32_t     tx_stat_outxonsent;
2293        uint32_t     tx_stat_outxoffsent;
2294        uint32_t     tx_stat_flowcontroldone;
2295        uint32_t     tx_stat_dot3statssinglecollisionframes;
2296        uint32_t     tx_stat_dot3statsmultiplecollisionframes;
2297        uint32_t     tx_stat_dot3statsdeferredtransmissions;
2298        uint32_t     tx_stat_dot3statsexcessivecollisions;
2299        uint32_t     tx_stat_dot3statslatecollisions;
2300        uint32_t     tx_stat_ifhcoutucastpkts;
2301        uint32_t     tx_stat_ifhcoutmulticastpkts;
2302        uint32_t     tx_stat_ifhcoutbroadcastpkts;
2303        uint32_t     tx_stat_etherstatspkts64octets;
2304        uint32_t     tx_stat_etherstatspkts65octetsto127octets;
2305        uint32_t     tx_stat_etherstatspkts128octetsto255octets;
2306        uint32_t     tx_stat_etherstatspkts256octetsto511octets;
2307        uint32_t     tx_stat_etherstatspkts512octetsto1023octets;
2308        uint32_t     tx_stat_etherstatspkts1024octetsto1522octets;
2309        uint32_t     tx_stat_etherstatspktsover1522octets;
2310        uint32_t     tx_stat_dot3statsinternalmactransmiterrors;
2311};
2312
2313
2314struct bmac1_stats {
2315        uint32_t        tx_stat_gtpkt_lo;
2316        uint32_t        tx_stat_gtpkt_hi;
2317        uint32_t        tx_stat_gtxpf_lo;
2318        uint32_t        tx_stat_gtxpf_hi;
2319        uint32_t        tx_stat_gtfcs_lo;
2320        uint32_t        tx_stat_gtfcs_hi;
2321        uint32_t        tx_stat_gtmca_lo;
2322        uint32_t        tx_stat_gtmca_hi;
2323        uint32_t        tx_stat_gtbca_lo;
2324        uint32_t        tx_stat_gtbca_hi;
2325        uint32_t        tx_stat_gtfrg_lo;
2326        uint32_t        tx_stat_gtfrg_hi;
2327        uint32_t        tx_stat_gtovr_lo;
2328        uint32_t        tx_stat_gtovr_hi;
2329        uint32_t        tx_stat_gt64_lo;
2330        uint32_t        tx_stat_gt64_hi;
2331        uint32_t        tx_stat_gt127_lo;
2332        uint32_t        tx_stat_gt127_hi;
2333        uint32_t        tx_stat_gt255_lo;
2334        uint32_t        tx_stat_gt255_hi;
2335        uint32_t        tx_stat_gt511_lo;
2336        uint32_t        tx_stat_gt511_hi;
2337        uint32_t        tx_stat_gt1023_lo;
2338        uint32_t        tx_stat_gt1023_hi;
2339        uint32_t        tx_stat_gt1518_lo;
2340        uint32_t        tx_stat_gt1518_hi;
2341        uint32_t        tx_stat_gt2047_lo;
2342        uint32_t        tx_stat_gt2047_hi;
2343        uint32_t        tx_stat_gt4095_lo;
2344        uint32_t        tx_stat_gt4095_hi;
2345        uint32_t        tx_stat_gt9216_lo;
2346        uint32_t        tx_stat_gt9216_hi;
2347        uint32_t        tx_stat_gt16383_lo;
2348        uint32_t        tx_stat_gt16383_hi;
2349        uint32_t        tx_stat_gtmax_lo;
2350        uint32_t        tx_stat_gtmax_hi;
2351        uint32_t        tx_stat_gtufl_lo;
2352        uint32_t        tx_stat_gtufl_hi;
2353        uint32_t        tx_stat_gterr_lo;
2354        uint32_t        tx_stat_gterr_hi;
2355        uint32_t        tx_stat_gtbyt_lo;
2356        uint32_t        tx_stat_gtbyt_hi;
2357
2358        uint32_t        rx_stat_gr64_lo;
2359        uint32_t        rx_stat_gr64_hi;
2360        uint32_t        rx_stat_gr127_lo;
2361        uint32_t        rx_stat_gr127_hi;
2362        uint32_t        rx_stat_gr255_lo;
2363        uint32_t        rx_stat_gr255_hi;
2364        uint32_t        rx_stat_gr511_lo;
2365        uint32_t        rx_stat_gr511_hi;
2366        uint32_t        rx_stat_gr1023_lo;
2367        uint32_t        rx_stat_gr1023_hi;
2368        uint32_t        rx_stat_gr1518_lo;
2369        uint32_t        rx_stat_gr1518_hi;
2370        uint32_t        rx_stat_gr2047_lo;
2371        uint32_t        rx_stat_gr2047_hi;
2372        uint32_t        rx_stat_gr4095_lo;
2373        uint32_t        rx_stat_gr4095_hi;
2374        uint32_t        rx_stat_gr9216_lo;
2375        uint32_t        rx_stat_gr9216_hi;
2376        uint32_t        rx_stat_gr16383_lo;
2377        uint32_t        rx_stat_gr16383_hi;
2378        uint32_t        rx_stat_grmax_lo;
2379        uint32_t        rx_stat_grmax_hi;
2380        uint32_t        rx_stat_grpkt_lo;
2381        uint32_t        rx_stat_grpkt_hi;
2382        uint32_t        rx_stat_grfcs_lo;
2383        uint32_t        rx_stat_grfcs_hi;
2384        uint32_t        rx_stat_grmca_lo;
2385        uint32_t        rx_stat_grmca_hi;
2386        uint32_t        rx_stat_grbca_lo;
2387        uint32_t        rx_stat_grbca_hi;
2388        uint32_t        rx_stat_grxcf_lo;
2389        uint32_t        rx_stat_grxcf_hi;
2390        uint32_t        rx_stat_grxpf_lo;
2391        uint32_t        rx_stat_grxpf_hi;
2392        uint32_t        rx_stat_grxuo_lo;
2393        uint32_t        rx_stat_grxuo_hi;
2394        uint32_t        rx_stat_grjbr_lo;
2395        uint32_t        rx_stat_grjbr_hi;
2396        uint32_t        rx_stat_grovr_lo;
2397        uint32_t        rx_stat_grovr_hi;
2398        uint32_t        rx_stat_grflr_lo;
2399        uint32_t        rx_stat_grflr_hi;
2400        uint32_t        rx_stat_grmeg_lo;
2401        uint32_t        rx_stat_grmeg_hi;
2402        uint32_t        rx_stat_grmeb_lo;
2403        uint32_t        rx_stat_grmeb_hi;
2404        uint32_t        rx_stat_grbyt_lo;
2405        uint32_t        rx_stat_grbyt_hi;
2406        uint32_t        rx_stat_grund_lo;
2407        uint32_t        rx_stat_grund_hi;
2408        uint32_t        rx_stat_grfrg_lo;
2409        uint32_t        rx_stat_grfrg_hi;
2410        uint32_t        rx_stat_grerb_lo;
2411        uint32_t        rx_stat_grerb_hi;
2412        uint32_t        rx_stat_grfre_lo;
2413        uint32_t        rx_stat_grfre_hi;
2414        uint32_t        rx_stat_gripj_lo;
2415        uint32_t        rx_stat_gripj_hi;
2416};
2417
2418struct bmac2_stats {
2419        uint32_t        tx_stat_gtpk_lo; /* gtpok */
2420        uint32_t        tx_stat_gtpk_hi; /* gtpok */
2421        uint32_t        tx_stat_gtxpf_lo; /* gtpf */
2422        uint32_t        tx_stat_gtxpf_hi; /* gtpf */
2423        uint32_t        tx_stat_gtpp_lo; /* NEW BMAC2 */
2424        uint32_t        tx_stat_gtpp_hi; /* NEW BMAC2 */
2425        uint32_t        tx_stat_gtfcs_lo;
2426        uint32_t        tx_stat_gtfcs_hi;
2427        uint32_t        tx_stat_gtuca_lo; /* NEW BMAC2 */
2428        uint32_t        tx_stat_gtuca_hi; /* NEW BMAC2 */
2429        uint32_t        tx_stat_gtmca_lo;
2430        uint32_t        tx_stat_gtmca_hi;
2431        uint32_t        tx_stat_gtbca_lo;
2432        uint32_t        tx_stat_gtbca_hi;
2433        uint32_t        tx_stat_gtovr_lo;
2434        uint32_t        tx_stat_gtovr_hi;
2435        uint32_t        tx_stat_gtfrg_lo;
2436        uint32_t        tx_stat_gtfrg_hi;
2437        uint32_t        tx_stat_gtpkt1_lo; /* gtpkt */
2438        uint32_t        tx_stat_gtpkt1_hi; /* gtpkt */
2439        uint32_t        tx_stat_gt64_lo;
2440        uint32_t        tx_stat_gt64_hi;
2441        uint32_t        tx_stat_gt127_lo;
2442        uint32_t        tx_stat_gt127_hi;
2443        uint32_t        tx_stat_gt255_lo;
2444        uint32_t        tx_stat_gt255_hi;
2445        uint32_t        tx_stat_gt511_lo;
2446        uint32_t        tx_stat_gt511_hi;
2447        uint32_t        tx_stat_gt1023_lo;
2448        uint32_t        tx_stat_gt1023_hi;
2449        uint32_t        tx_stat_gt1518_lo;
2450        uint32_t        tx_stat_gt1518_hi;
2451        uint32_t        tx_stat_gt2047_lo;
2452        uint32_t        tx_stat_gt2047_hi;
2453        uint32_t        tx_stat_gt4095_lo;
2454        uint32_t        tx_stat_gt4095_hi;
2455        uint32_t        tx_stat_gt9216_lo;
2456        uint32_t        tx_stat_gt9216_hi;
2457        uint32_t        tx_stat_gt16383_lo;
2458        uint32_t        tx_stat_gt16383_hi;
2459        uint32_t        tx_stat_gtmax_lo;
2460        uint32_t        tx_stat_gtmax_hi;
2461        uint32_t        tx_stat_gtufl_lo;
2462        uint32_t        tx_stat_gtufl_hi;
2463        uint32_t        tx_stat_gterr_lo;
2464        uint32_t        tx_stat_gterr_hi;
2465        uint32_t        tx_stat_gtbyt_lo;
2466        uint32_t        tx_stat_gtbyt_hi;
2467
2468        uint32_t        rx_stat_gr64_lo;
2469        uint32_t        rx_stat_gr64_hi;
2470        uint32_t        rx_stat_gr127_lo;
2471        uint32_t        rx_stat_gr127_hi;
2472        uint32_t        rx_stat_gr255_lo;
2473        uint32_t        rx_stat_gr255_hi;
2474        uint32_t        rx_stat_gr511_lo;
2475        uint32_t        rx_stat_gr511_hi;
2476        uint32_t        rx_stat_gr1023_lo;
2477        uint32_t        rx_stat_gr1023_hi;
2478        uint32_t        rx_stat_gr1518_lo;
2479        uint32_t        rx_stat_gr1518_hi;
2480        uint32_t        rx_stat_gr2047_lo;
2481        uint32_t        rx_stat_gr2047_hi;
2482        uint32_t        rx_stat_gr4095_lo;
2483        uint32_t        rx_stat_gr4095_hi;
2484        uint32_t        rx_stat_gr9216_lo;
2485        uint32_t        rx_stat_gr9216_hi;
2486        uint32_t        rx_stat_gr16383_lo;
2487        uint32_t        rx_stat_gr16383_hi;
2488        uint32_t        rx_stat_grmax_lo;
2489        uint32_t        rx_stat_grmax_hi;
2490        uint32_t        rx_stat_grpkt_lo;
2491        uint32_t        rx_stat_grpkt_hi;
2492        uint32_t        rx_stat_grfcs_lo;
2493        uint32_t        rx_stat_grfcs_hi;
2494        uint32_t        rx_stat_gruca_lo;
2495        uint32_t        rx_stat_gruca_hi;
2496        uint32_t        rx_stat_grmca_lo;
2497        uint32_t        rx_stat_grmca_hi;
2498        uint32_t        rx_stat_grbca_lo;
2499        uint32_t        rx_stat_grbca_hi;
2500        uint32_t        rx_stat_grxpf_lo; /* grpf */
2501        uint32_t        rx_stat_grxpf_hi; /* grpf */
2502        uint32_t        rx_stat_grpp_lo;
2503        uint32_t        rx_stat_grpp_hi;
2504        uint32_t        rx_stat_grxuo_lo; /* gruo */
2505        uint32_t        rx_stat_grxuo_hi; /* gruo */
2506        uint32_t        rx_stat_grjbr_lo;
2507        uint32_t        rx_stat_grjbr_hi;
2508        uint32_t        rx_stat_grovr_lo;
2509        uint32_t        rx_stat_grovr_hi;
2510        uint32_t        rx_stat_grxcf_lo; /* grcf */
2511        uint32_t        rx_stat_grxcf_hi; /* grcf */
2512        uint32_t        rx_stat_grflr_lo;
2513        uint32_t        rx_stat_grflr_hi;
2514        uint32_t        rx_stat_grpok_lo;
2515        uint32_t        rx_stat_grpok_hi;
2516        uint32_t        rx_stat_grmeg_lo;
2517        uint32_t        rx_stat_grmeg_hi;
2518        uint32_t        rx_stat_grmeb_lo;
2519        uint32_t        rx_stat_grmeb_hi;
2520        uint32_t        rx_stat_grbyt_lo;
2521        uint32_t        rx_stat_grbyt_hi;
2522        uint32_t        rx_stat_grund_lo;
2523        uint32_t        rx_stat_grund_hi;
2524        uint32_t        rx_stat_grfrg_lo;
2525        uint32_t        rx_stat_grfrg_hi;
2526        uint32_t        rx_stat_grerb_lo; /* grerrbyt */
2527        uint32_t        rx_stat_grerb_hi; /* grerrbyt */
2528        uint32_t        rx_stat_grfre_lo; /* grfrerr */
2529        uint32_t        rx_stat_grfre_hi; /* grfrerr */
2530        uint32_t        rx_stat_gripj_lo;
2531        uint32_t        rx_stat_gripj_hi;
2532};
2533
2534struct mstat_stats {
2535        struct {
2536                /* OTE MSTAT on E3 has a bug where this register's contents are
2537                 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2538                 */
2539                uint32_t tx_gtxpok_lo;
2540                uint32_t tx_gtxpok_hi;
2541                uint32_t tx_gtxpf_lo;
2542                uint32_t tx_gtxpf_hi;
2543                uint32_t tx_gtxpp_lo;
2544                uint32_t tx_gtxpp_hi;
2545                uint32_t tx_gtfcs_lo;
2546                uint32_t tx_gtfcs_hi;
2547                uint32_t tx_gtuca_lo;
2548                uint32_t tx_gtuca_hi;
2549                uint32_t tx_gtmca_lo;
2550                uint32_t tx_gtmca_hi;
2551                uint32_t tx_gtgca_lo;
2552                uint32_t tx_gtgca_hi;
2553                uint32_t tx_gtpkt_lo;
2554                uint32_t tx_gtpkt_hi;
2555                uint32_t tx_gt64_lo;
2556                uint32_t tx_gt64_hi;
2557                uint32_t tx_gt127_lo;
2558                uint32_t tx_gt127_hi;
2559                uint32_t tx_gt255_lo;
2560                uint32_t tx_gt255_hi;
2561                uint32_t tx_gt511_lo;
2562                uint32_t tx_gt511_hi;
2563                uint32_t tx_gt1023_lo;
2564                uint32_t tx_gt1023_hi;
2565                uint32_t tx_gt1518_lo;
2566                uint32_t tx_gt1518_hi;
2567                uint32_t tx_gt2047_lo;
2568                uint32_t tx_gt2047_hi;
2569                uint32_t tx_gt4095_lo;
2570                uint32_t tx_gt4095_hi;
2571                uint32_t tx_gt9216_lo;
2572                uint32_t tx_gt9216_hi;
2573                uint32_t tx_gt16383_lo;
2574                uint32_t tx_gt16383_hi;
2575                uint32_t tx_gtufl_lo;
2576                uint32_t tx_gtufl_hi;
2577                uint32_t tx_gterr_lo;
2578                uint32_t tx_gterr_hi;
2579                uint32_t tx_gtbyt_lo;
2580                uint32_t tx_gtbyt_hi;
2581                uint32_t tx_collisions_lo;
2582                uint32_t tx_collisions_hi;
2583                uint32_t tx_singlecollision_lo;
2584                uint32_t tx_singlecollision_hi;
2585                uint32_t tx_multiplecollisions_lo;
2586                uint32_t tx_multiplecollisions_hi;
2587                uint32_t tx_deferred_lo;
2588                uint32_t tx_deferred_hi;
2589                uint32_t tx_excessivecollisions_lo;
2590                uint32_t tx_excessivecollisions_hi;
2591                uint32_t tx_latecollisions_lo;
2592                uint32_t tx_latecollisions_hi;
2593        } stats_tx;
2594
2595        struct {
2596                uint32_t rx_gr64_lo;
2597                uint32_t rx_gr64_hi;
2598                uint32_t rx_gr127_lo;
2599                uint32_t rx_gr127_hi;
2600                uint32_t rx_gr255_lo;
2601                uint32_t rx_gr255_hi;
2602                uint32_t rx_gr511_lo;
2603                uint32_t rx_gr511_hi;
2604                uint32_t rx_gr1023_lo;
2605                uint32_t rx_gr1023_hi;
2606                uint32_t rx_gr1518_lo;
2607                uint32_t rx_gr1518_hi;
2608                uint32_t rx_gr2047_lo;
2609                uint32_t rx_gr2047_hi;
2610                uint32_t rx_gr4095_lo;
2611                uint32_t rx_gr4095_hi;
2612                uint32_t rx_gr9216_lo;
2613                uint32_t rx_gr9216_hi;
2614                uint32_t rx_gr16383_lo;
2615                uint32_t rx_gr16383_hi;
2616                uint32_t rx_grpkt_lo;
2617                uint32_t rx_grpkt_hi;
2618                uint32_t rx_grfcs_lo;
2619                uint32_t rx_grfcs_hi;
2620                uint32_t rx_gruca_lo;
2621                uint32_t rx_gruca_hi;
2622                uint32_t rx_grmca_lo;
2623                uint32_t rx_grmca_hi;
2624                uint32_t rx_grbca_lo;
2625                uint32_t rx_grbca_hi;
2626                uint32_t rx_grxpf_lo;
2627                uint32_t rx_grxpf_hi;
2628                uint32_t rx_grxpp_lo;
2629                uint32_t rx_grxpp_hi;
2630                uint32_t rx_grxuo_lo;
2631                uint32_t rx_grxuo_hi;
2632                uint32_t rx_grovr_lo;
2633                uint32_t rx_grovr_hi;
2634                uint32_t rx_grxcf_lo;
2635                uint32_t rx_grxcf_hi;
2636                uint32_t rx_grflr_lo;
2637                uint32_t rx_grflr_hi;
2638                uint32_t rx_grpok_lo;
2639                uint32_t rx_grpok_hi;
2640                uint32_t rx_grbyt_lo;
2641                uint32_t rx_grbyt_hi;
2642                uint32_t rx_grund_lo;
2643                uint32_t rx_grund_hi;
2644                uint32_t rx_grfrg_lo;
2645                uint32_t rx_grfrg_hi;
2646                uint32_t rx_grerb_lo;
2647                uint32_t rx_grerb_hi;
2648                uint32_t rx_grfre_lo;
2649                uint32_t rx_grfre_hi;
2650
2651                uint32_t rx_alignmenterrors_lo;
2652                uint32_t rx_alignmenterrors_hi;
2653                uint32_t rx_falsecarrier_lo;
2654                uint32_t rx_falsecarrier_hi;
2655                uint32_t rx_llfcmsgcnt_lo;
2656                uint32_t rx_llfcmsgcnt_hi;
2657        } stats_rx;
2658};
2659
2660union mac_stats {
2661        struct emac_stats       emac_stats;
2662        struct bmac1_stats      bmac1_stats;
2663        struct bmac2_stats      bmac2_stats;
2664        struct mstat_stats      mstat_stats;
2665};
2666
2667
2668struct mac_stx {
2669        /* in_bad_octets */
2670        uint32_t     rx_stat_ifhcinbadoctets_hi;
2671        uint32_t     rx_stat_ifhcinbadoctets_lo;
2672
2673        /* out_bad_octets */
2674        uint32_t     tx_stat_ifhcoutbadoctets_hi;
2675        uint32_t     tx_stat_ifhcoutbadoctets_lo;
2676
2677        /* crc_receive_errors */
2678        uint32_t     rx_stat_dot3statsfcserrors_hi;
2679        uint32_t     rx_stat_dot3statsfcserrors_lo;
2680        /* alignment_errors */
2681        uint32_t     rx_stat_dot3statsalignmenterrors_hi;
2682        uint32_t     rx_stat_dot3statsalignmenterrors_lo;
2683        /* carrier_sense_errors */
2684        uint32_t     rx_stat_dot3statscarriersenseerrors_hi;
2685        uint32_t     rx_stat_dot3statscarriersenseerrors_lo;
2686        /* false_carrier_detections */
2687        uint32_t     rx_stat_falsecarriererrors_hi;
2688        uint32_t     rx_stat_falsecarriererrors_lo;
2689
2690        /* runt_packets_received */
2691        uint32_t     rx_stat_etherstatsundersizepkts_hi;
2692        uint32_t     rx_stat_etherstatsundersizepkts_lo;
2693        /* jabber_packets_received */
2694        uint32_t     rx_stat_dot3statsframestoolong_hi;
2695        uint32_t     rx_stat_dot3statsframestoolong_lo;
2696
2697        /* error_runt_packets_received */
2698        uint32_t     rx_stat_etherstatsfragments_hi;
2699        uint32_t     rx_stat_etherstatsfragments_lo;
2700        /* error_jabber_packets_received */
2701        uint32_t     rx_stat_etherstatsjabbers_hi;
2702        uint32_t     rx_stat_etherstatsjabbers_lo;
2703
2704        /* control_frames_received */
2705        uint32_t     rx_stat_maccontrolframesreceived_hi;
2706        uint32_t     rx_stat_maccontrolframesreceived_lo;
2707        uint32_t     rx_stat_mac_xpf_hi;
2708        uint32_t     rx_stat_mac_xpf_lo;
2709        uint32_t     rx_stat_mac_xcf_hi;
2710        uint32_t     rx_stat_mac_xcf_lo;
2711
2712        /* xoff_state_entered */
2713        uint32_t     rx_stat_xoffstateentered_hi;
2714        uint32_t     rx_stat_xoffstateentered_lo;
2715        /* pause_xon_frames_received */
2716        uint32_t     rx_stat_xonpauseframesreceived_hi;
2717        uint32_t     rx_stat_xonpauseframesreceived_lo;
2718        /* pause_xoff_frames_received */
2719        uint32_t     rx_stat_xoffpauseframesreceived_hi;
2720        uint32_t     rx_stat_xoffpauseframesreceived_lo;
2721        /* pause_xon_frames_transmitted */
2722        uint32_t     tx_stat_outxonsent_hi;
2723        uint32_t     tx_stat_outxonsent_lo;
2724        /* pause_xoff_frames_transmitted */
2725        uint32_t     tx_stat_outxoffsent_hi;
2726        uint32_t     tx_stat_outxoffsent_lo;
2727        /* flow_control_done */
2728        uint32_t     tx_stat_flowcontroldone_hi;
2729        uint32_t     tx_stat_flowcontroldone_lo;
2730
2731        /* ether_stats_collisions */
2732        uint32_t     tx_stat_etherstatscollisions_hi;
2733        uint32_t     tx_stat_etherstatscollisions_lo;
2734        /* single_collision_transmit_frames */
2735        uint32_t     tx_stat_dot3statssinglecollisionframes_hi;
2736        uint32_t     tx_stat_dot3statssinglecollisionframes_lo;
2737        /* multiple_collision_transmit_frames */
2738        uint32_t     tx_stat_dot3statsmultiplecollisionframes_hi;
2739        uint32_t     tx_stat_dot3statsmultiplecollisionframes_lo;
2740        /* deferred_transmissions */
2741        uint32_t     tx_stat_dot3statsdeferredtransmissions_hi;
2742        uint32_t     tx_stat_dot3statsdeferredtransmissions_lo;
2743        /* excessive_collision_frames */
2744        uint32_t     tx_stat_dot3statsexcessivecollisions_hi;
2745        uint32_t     tx_stat_dot3statsexcessivecollisions_lo;
2746        /* late_collision_frames */
2747        uint32_t     tx_stat_dot3statslatecollisions_hi;
2748        uint32_t     tx_stat_dot3statslatecollisions_lo;
2749
2750        /* frames_transmitted_64_bytes */
2751        uint32_t     tx_stat_etherstatspkts64octets_hi;
2752        uint32_t     tx_stat_etherstatspkts64octets_lo;
2753        /* frames_transmitted_65_127_bytes */
2754        uint32_t     tx_stat_etherstatspkts65octetsto127octets_hi;
2755        uint32_t     tx_stat_etherstatspkts65octetsto127octets_lo;
2756        /* frames_transmitted_128_255_bytes */
2757        uint32_t     tx_stat_etherstatspkts128octetsto255octets_hi;
2758        uint32_t     tx_stat_etherstatspkts128octetsto255octets_lo;
2759        /* frames_transmitted_256_511_bytes */
2760        uint32_t     tx_stat_etherstatspkts256octetsto511octets_hi;
2761        uint32_t     tx_stat_etherstatspkts256octetsto511octets_lo;
2762        /* frames_transmitted_512_1023_bytes */
2763        uint32_t     tx_stat_etherstatspkts512octetsto1023octets_hi;
2764        uint32_t     tx_stat_etherstatspkts512octetsto1023octets_lo;
2765        /* frames_transmitted_1024_1522_bytes */
2766        uint32_t     tx_stat_etherstatspkts1024octetsto1522octets_hi;
2767        uint32_t     tx_stat_etherstatspkts1024octetsto1522octets_lo;
2768        /* frames_transmitted_1523_9022_bytes */
2769        uint32_t     tx_stat_etherstatspktsover1522octets_hi;
2770        uint32_t     tx_stat_etherstatspktsover1522octets_lo;
2771        uint32_t     tx_stat_mac_2047_hi;
2772        uint32_t     tx_stat_mac_2047_lo;
2773        uint32_t     tx_stat_mac_4095_hi;
2774        uint32_t     tx_stat_mac_4095_lo;
2775        uint32_t     tx_stat_mac_9216_hi;
2776        uint32_t     tx_stat_mac_9216_lo;
2777        uint32_t     tx_stat_mac_16383_hi;
2778        uint32_t     tx_stat_mac_16383_lo;
2779
2780        /* internal_mac_transmit_errors */
2781        uint32_t     tx_stat_dot3statsinternalmactransmiterrors_hi;
2782        uint32_t     tx_stat_dot3statsinternalmactransmiterrors_lo;
2783
2784        /* if_out_discards */
2785        uint32_t     tx_stat_mac_ufl_hi;
2786        uint32_t     tx_stat_mac_ufl_lo;
2787};
2788
2789
2790#define MAC_STX_IDX_MAX                     2
2791
2792struct host_port_stats {
2793        uint32_t            host_port_stats_counter;
2794
2795        struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2796
2797        uint32_t            brb_drop_hi;
2798        uint32_t            brb_drop_lo;
2799
2800        uint32_t            not_used; /* obsolete */
2801        uint32_t            pfc_frames_tx_hi;
2802        uint32_t            pfc_frames_tx_lo;
2803        uint32_t            pfc_frames_rx_hi;
2804        uint32_t            pfc_frames_rx_lo;
2805
2806        uint32_t            eee_lpi_count_hi;
2807        uint32_t            eee_lpi_count_lo;
2808};
2809
2810
2811struct host_func_stats {
2812        uint32_t     host_func_stats_start;
2813
2814        uint32_t     total_bytes_received_hi;
2815        uint32_t     total_bytes_received_lo;
2816
2817        uint32_t     total_bytes_transmitted_hi;
2818        uint32_t     total_bytes_transmitted_lo;
2819
2820        uint32_t     total_unicast_packets_received_hi;
2821        uint32_t     total_unicast_packets_received_lo;
2822
2823        uint32_t     total_multicast_packets_received_hi;
2824        uint32_t     total_multicast_packets_received_lo;
2825
2826        uint32_t     total_broadcast_packets_received_hi;
2827        uint32_t     total_broadcast_packets_received_lo;
2828
2829        uint32_t     total_unicast_packets_transmitted_hi;
2830        uint32_t     total_unicast_packets_transmitted_lo;
2831
2832        uint32_t     total_multicast_packets_transmitted_hi;
2833        uint32_t     total_multicast_packets_transmitted_lo;
2834
2835        uint32_t     total_broadcast_packets_transmitted_hi;
2836        uint32_t     total_broadcast_packets_transmitted_lo;
2837
2838        uint32_t     valid_bytes_received_hi;
2839        uint32_t     valid_bytes_received_lo;
2840
2841        uint32_t     host_func_stats_end;
2842};
2843
2844/* VIC definitions */
2845#define VICSTATST_UIF_INDEX 2
2846
2847
2848/* stats collected for afex.
2849 * NOTE: structure is exactly as expected to be received by the switch.
2850 *       order must remain exactly as is unless protocol changes !
2851 */
2852struct afex_stats {
2853        uint32_t tx_unicast_frames_hi;
2854        uint32_t tx_unicast_frames_lo;
2855        uint32_t tx_unicast_bytes_hi;
2856        uint32_t tx_unicast_bytes_lo;
2857        uint32_t tx_multicast_frames_hi;
2858        uint32_t tx_multicast_frames_lo;
2859        uint32_t tx_multicast_bytes_hi;
2860        uint32_t tx_multicast_bytes_lo;
2861        uint32_t tx_broadcast_frames_hi;
2862        uint32_t tx_broadcast_frames_lo;
2863        uint32_t tx_broadcast_bytes_hi;
2864        uint32_t tx_broadcast_bytes_lo;
2865        uint32_t tx_frames_discarded_hi;
2866        uint32_t tx_frames_discarded_lo;
2867        uint32_t tx_frames_dropped_hi;
2868        uint32_t tx_frames_dropped_lo;
2869
2870        uint32_t rx_unicast_frames_hi;
2871        uint32_t rx_unicast_frames_lo;
2872        uint32_t rx_unicast_bytes_hi;
2873        uint32_t rx_unicast_bytes_lo;
2874        uint32_t rx_multicast_frames_hi;
2875        uint32_t rx_multicast_frames_lo;
2876        uint32_t rx_multicast_bytes_hi;
2877        uint32_t rx_multicast_bytes_lo;
2878        uint32_t rx_broadcast_frames_hi;
2879        uint32_t rx_broadcast_frames_lo;
2880        uint32_t rx_broadcast_bytes_hi;
2881        uint32_t rx_broadcast_bytes_lo;
2882        uint32_t rx_frames_discarded_hi;
2883        uint32_t rx_frames_discarded_lo;
2884        uint32_t rx_frames_dropped_hi;
2885        uint32_t rx_frames_dropped_lo;
2886};
2887
2888#define BCM_5710_FW_MAJOR_VERSION                       7
2889#define BCM_5710_FW_MINOR_VERSION                       10
2890#define BCM_5710_FW_REVISION_VERSION            51
2891#define BCM_5710_FW_ENGINEERING_VERSION         0
2892#define BCM_5710_FW_COMPILE_FLAGS                       1
2893
2894
2895/*
2896 * attention bits
2897 */
2898struct atten_sp_status_block {
2899        __le32 attn_bits;
2900        __le32 attn_bits_ack;
2901        uint8_t status_block_id;
2902        uint8_t reserved0;
2903        __le16 attn_bits_index;
2904        __le32 reserved1;
2905};
2906
2907
2908/*
2909 * The eth aggregative context of Cstorm
2910 */
2911struct cstorm_eth_ag_context {
2912        uint32_t __reserved0[10];
2913};
2914
2915
2916/*
2917 * dmae command structure
2918 */
2919struct dmae_command {
2920        uint32_t opcode;
2921#define DMAE_COMMAND_SRC (0x1<<0)
2922#define DMAE_COMMAND_SRC_SHIFT 0
2923#define DMAE_COMMAND_DST (0x3<<1)
2924#define DMAE_COMMAND_DST_SHIFT 1
2925#define DMAE_COMMAND_C_DST (0x1<<3)
2926#define DMAE_COMMAND_C_DST_SHIFT 3
2927#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2928#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2929#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2930#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2931#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2932#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2933#define DMAE_COMMAND_ENDIANITY (0x3<<9)
2934#define DMAE_COMMAND_ENDIANITY_SHIFT 9
2935#define DMAE_COMMAND_PORT (0x1<<11)
2936#define DMAE_COMMAND_PORT_SHIFT 11
2937#define DMAE_COMMAND_CRC_RESET (0x1<<12)
2938#define DMAE_COMMAND_CRC_RESET_SHIFT 12
2939#define DMAE_COMMAND_SRC_RESET (0x1<<13)
2940#define DMAE_COMMAND_SRC_RESET_SHIFT 13
2941#define DMAE_COMMAND_DST_RESET (0x1<<14)
2942#define DMAE_COMMAND_DST_RESET_SHIFT 14
2943#define DMAE_COMMAND_E1HVN (0x3<<15)
2944#define DMAE_COMMAND_E1HVN_SHIFT 15
2945#define DMAE_COMMAND_DST_VN (0x3<<17)
2946#define DMAE_COMMAND_DST_VN_SHIFT 17
2947#define DMAE_COMMAND_C_FUNC (0x1<<19)
2948#define DMAE_COMMAND_C_FUNC_SHIFT 19
2949#define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2950#define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2951#define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2952#define DMAE_COMMAND_RESERVED0_SHIFT 22
2953        uint32_t src_addr_lo;
2954        uint32_t src_addr_hi;
2955        uint32_t dst_addr_lo;
2956        uint32_t dst_addr_hi;
2957#if defined(__BIG_ENDIAN)
2958        uint16_t opcode_iov;
2959#define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2960#define DMAE_COMMAND_SRC_VFID_SHIFT 0
2961#define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2962#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2963#define DMAE_COMMAND_RESERVED1 (0x1<<7)
2964#define DMAE_COMMAND_RESERVED1_SHIFT 7
2965#define DMAE_COMMAND_DST_VFID (0x3F<<8)
2966#define DMAE_COMMAND_DST_VFID_SHIFT 8
2967#define DMAE_COMMAND_DST_VFPF (0x1<<14)
2968#define DMAE_COMMAND_DST_VFPF_SHIFT 14
2969#define DMAE_COMMAND_RESERVED2 (0x1<<15)
2970#define DMAE_COMMAND_RESERVED2_SHIFT 15
2971        uint16_t len;
2972#elif defined(__LITTLE_ENDIAN)
2973        uint16_t len;
2974        uint16_t opcode_iov;
2975#define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2976#define DMAE_COMMAND_SRC_VFID_SHIFT 0
2977#define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2978#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2979#define DMAE_COMMAND_RESERVED1 (0x1<<7)
2980#define DMAE_COMMAND_RESERVED1_SHIFT 7
2981#define DMAE_COMMAND_DST_VFID (0x3F<<8)
2982#define DMAE_COMMAND_DST_VFID_SHIFT 8
2983#define DMAE_COMMAND_DST_VFPF (0x1<<14)
2984#define DMAE_COMMAND_DST_VFPF_SHIFT 14
2985#define DMAE_COMMAND_RESERVED2 (0x1<<15)
2986#define DMAE_COMMAND_RESERVED2_SHIFT 15
2987#endif
2988        uint32_t comp_addr_lo;
2989        uint32_t comp_addr_hi;
2990        uint32_t comp_val;
2991        uint32_t crc32;
2992        uint32_t crc32_c;
2993#if defined(__BIG_ENDIAN)
2994        uint16_t crc16_c;
2995        uint16_t crc16;
2996#elif defined(__LITTLE_ENDIAN)
2997        uint16_t crc16;
2998        uint16_t crc16_c;
2999#endif
3000#if defined(__BIG_ENDIAN)
3001        uint16_t reserved3;
3002        uint16_t crc_t10;
3003#elif defined(__LITTLE_ENDIAN)
3004        uint16_t crc_t10;
3005        uint16_t reserved3;
3006#endif
3007#if defined(__BIG_ENDIAN)
3008        uint16_t xsum8;
3009        uint16_t xsum16;
3010#elif defined(__LITTLE_ENDIAN)
3011        uint16_t xsum16;
3012        uint16_t xsum8;
3013#endif
3014};
3015
3016
3017/*
3018 * common data for all protocols
3019 */
3020struct doorbell_hdr {
3021        uint8_t header;
3022#define DOORBELL_HDR_RX (0x1<<0)
3023#define DOORBELL_HDR_RX_SHIFT 0
3024#define DOORBELL_HDR_DB_TYPE (0x1<<1)
3025#define DOORBELL_HDR_DB_TYPE_SHIFT 1
3026#define DOORBELL_HDR_DPM_SIZE (0x3<<2)
3027#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
3028#define DOORBELL_HDR_CONN_TYPE (0xF<<4)
3029#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
3030};
3031
3032/*
3033 * Ethernet doorbell
3034 */
3035struct eth_tx_doorbell {
3036#if defined(__BIG_ENDIAN)
3037        uint16_t npackets;
3038        uint8_t params;
3039#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3040#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3041#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3042#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3043#define ETH_TX_DOORBELL_SPARE (0x1<<7)
3044#define ETH_TX_DOORBELL_SPARE_SHIFT 7
3045        struct doorbell_hdr hdr;
3046#elif defined(__LITTLE_ENDIAN)
3047        struct doorbell_hdr hdr;
3048        uint8_t params;
3049#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3050#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3051#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3052#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3053#define ETH_TX_DOORBELL_SPARE (0x1<<7)
3054#define ETH_TX_DOORBELL_SPARE_SHIFT 7
3055        uint16_t npackets;
3056#endif
3057};
3058
3059
3060/*
3061 * 3 lines. status block
3062 */
3063struct hc_status_block_e1x {
3064        __le16 index_values[HC_SB_MAX_INDICES_E1X];
3065        __le16 running_index[HC_SB_MAX_SM];
3066        __le32 rsrv[11];
3067};
3068
3069/*
3070 * host status block
3071 */
3072struct host_hc_status_block_e1x {
3073        struct hc_status_block_e1x sb;
3074};
3075
3076
3077/*
3078 * 3 lines. status block
3079 */
3080struct hc_status_block_e2 {
3081        __le16 index_values[HC_SB_MAX_INDICES_E2];
3082        __le16 running_index[HC_SB_MAX_SM];
3083        __le32 reserved[11];
3084};
3085
3086/*
3087 * host status block
3088 */
3089struct host_hc_status_block_e2 {
3090        struct hc_status_block_e2 sb;
3091};
3092
3093
3094/*
3095 * 5 lines. slow-path status block
3096 */
3097struct hc_sp_status_block {
3098        __le16 index_values[HC_SP_SB_MAX_INDICES];
3099        __le16 running_index;
3100        __le16 rsrv;
3101        uint32_t rsrv1;
3102};
3103
3104/*
3105 * host status block
3106 */
3107struct host_sp_status_block {
3108        struct atten_sp_status_block atten_status_block;
3109        struct hc_sp_status_block sp_sb;
3110};
3111
3112
3113/*
3114 * IGU driver acknowledgment register
3115 */
3116struct igu_ack_register {
3117#if defined(__BIG_ENDIAN)
3118        uint16_t sb_id_and_flags;
3119#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3120#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3121#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3122#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3123#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3124#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3125#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3126#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3127#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3128#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3129        uint16_t status_block_index;
3130#elif defined(__LITTLE_ENDIAN)
3131        uint16_t status_block_index;
3132        uint16_t sb_id_and_flags;
3133#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3134#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3135#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3136#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3137#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3138#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3139#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3140#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3141#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3142#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3143#endif
3144};
3145
3146
3147/*
3148 * IGU driver acknowledgement register
3149 */
3150struct igu_backward_compatible {
3151        uint32_t sb_id_and_flags;
3152#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
3153#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3154#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
3155#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3156#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
3157#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3158#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
3159#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3160#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
3161#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3162#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
3163#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3164        uint32_t reserved_2;
3165};
3166
3167
3168/*
3169 * IGU driver acknowledgement register
3170 */
3171struct igu_regular {
3172        uint32_t sb_id_and_flags;
3173#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
3174#define IGU_REGULAR_SB_INDEX_SHIFT 0
3175#define IGU_REGULAR_RESERVED0 (0x1<<20)
3176#define IGU_REGULAR_RESERVED0_SHIFT 20
3177#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
3178#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
3179#define IGU_REGULAR_BUPDATE (0x1<<24)
3180#define IGU_REGULAR_BUPDATE_SHIFT 24
3181#define IGU_REGULAR_ENABLE_INT (0x3<<25)
3182#define IGU_REGULAR_ENABLE_INT_SHIFT 25
3183#define IGU_REGULAR_RESERVED_1 (0x1<<27)
3184#define IGU_REGULAR_RESERVED_1_SHIFT 27
3185#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
3186#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
3187#define IGU_REGULAR_CLEANUP_SET (0x1<<30)
3188#define IGU_REGULAR_CLEANUP_SET_SHIFT 30
3189#define IGU_REGULAR_BCLEANUP (0x1<<31)
3190#define IGU_REGULAR_BCLEANUP_SHIFT 31
3191        uint32_t reserved_2;
3192};
3193
3194/*
3195 * IGU driver acknowledgement register
3196 */
3197union igu_consprod_reg {
3198        struct igu_regular regular;
3199        struct igu_backward_compatible backward_compatible;
3200};
3201
3202
3203/*
3204 * Igu control commands
3205 */
3206enum igu_ctrl_cmd {
3207        IGU_CTRL_CMD_TYPE_RD,
3208        IGU_CTRL_CMD_TYPE_WR,
3209        MAX_IGU_CTRL_CMD
3210};
3211
3212
3213/*
3214 * Control register for the IGU command register
3215 */
3216struct igu_ctrl_reg {
3217        uint32_t ctrl_data;
3218#define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3219#define IGU_CTRL_REG_ADDRESS_SHIFT 0
3220#define IGU_CTRL_REG_FID (0x7F<<12)
3221#define IGU_CTRL_REG_FID_SHIFT 12
3222#define IGU_CTRL_REG_RESERVED (0x1<<19)
3223#define IGU_CTRL_REG_RESERVED_SHIFT 19
3224#define IGU_CTRL_REG_TYPE (0x1<<20)
3225#define IGU_CTRL_REG_TYPE_SHIFT 20
3226#define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3227#define IGU_CTRL_REG_UNUSED_SHIFT 21
3228};
3229
3230
3231/*
3232 * Igu interrupt command
3233 */
3234enum igu_int_cmd {
3235        IGU_INT_ENABLE,
3236        IGU_INT_DISABLE,
3237        IGU_INT_NOP,
3238        IGU_INT_NOP2,
3239        MAX_IGU_INT_CMD
3240};
3241
3242
3243/*
3244 * Igu segments
3245 */
3246enum igu_seg_access {
3247        IGU_SEG_ACCESS_NORM,
3248        IGU_SEG_ACCESS_DEF,
3249        IGU_SEG_ACCESS_ATTN,
3250        MAX_IGU_SEG_ACCESS
3251};
3252
3253
3254/*
3255 * Parser parsing flags field
3256 */
3257struct parsing_flags {
3258        __le16 flags;
3259#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3260#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3261#define PARSING_FLAGS_VLAN (0x1<<1)
3262#define PARSING_FLAGS_VLAN_SHIFT 1
3263#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3264#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3265#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3266#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3267#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3268#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3269#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3270#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3271#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3272#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3273#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3274#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3275#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3276#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3277#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3278#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3279#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3280#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3281#define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3282#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3283#define PARSING_FLAGS_RESERVED0 (0x3<<14)
3284#define PARSING_FLAGS_RESERVED0_SHIFT 14
3285};
3286
3287
3288/*
3289 * Parsing flags for TCP ACK type
3290 */
3291enum prs_flags_ack_type {
3292        PRS_FLAG_PUREACK_PIGGY,
3293        PRS_FLAG_PUREACK_PURE,
3294        MAX_PRS_FLAGS_ACK_TYPE
3295};
3296
3297
3298/*
3299 * Parsing flags for Ethernet address type
3300 */
3301enum prs_flags_eth_addr_type {
3302        PRS_FLAG_ETHTYPE_NON_UNICAST,
3303        PRS_FLAG_ETHTYPE_UNICAST,
3304        MAX_PRS_FLAGS_ETH_ADDR_TYPE
3305};
3306
3307
3308/*
3309 * Parsing flags for over-ethernet protocol
3310 */
3311enum prs_flags_over_eth {
3312        PRS_FLAG_OVERETH_UNKNOWN,
3313        PRS_FLAG_OVERETH_IPV4,
3314        PRS_FLAG_OVERETH_IPV6,
3315        PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
3316        MAX_PRS_FLAGS_OVER_ETH
3317};
3318
3319
3320/*
3321 * Parsing flags for over-IP protocol
3322 */
3323enum prs_flags_over_ip {
3324        PRS_FLAG_OVERIP_UNKNOWN,
3325        PRS_FLAG_OVERIP_TCP,
3326        PRS_FLAG_OVERIP_UDP,
3327        MAX_PRS_FLAGS_OVER_IP
3328};
3329
3330
3331/*
3332 * SDM operation gen command (generate aggregative interrupt)
3333 */
3334struct sdm_op_gen {
3335        __le32 command;
3336#define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3337#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3338#define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3339#define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3340#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3341#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3342#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3343#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3344#define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3345#define SDM_OP_GEN_RESERVED_SHIFT 17
3346};
3347
3348
3349/*
3350 * Timers connection context
3351 */
3352struct timers_block_context {
3353        uint32_t __reserved_0;
3354        uint32_t __reserved_1;
3355        uint32_t __reserved_2;
3356        uint32_t flags;
3357#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3358#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3359#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3360#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3361#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3362#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3363};
3364
3365
3366/*
3367 * The eth aggregative context of Tstorm
3368 */
3369struct tstorm_eth_ag_context {
3370        uint32_t __reserved0[14];
3371};
3372
3373
3374/*
3375 * The eth aggregative context of Ustorm
3376 */
3377struct ustorm_eth_ag_context {
3378        uint32_t __reserved0;
3379#if defined(__BIG_ENDIAN)
3380        uint8_t cdu_usage;
3381        uint8_t __reserved2;
3382        uint16_t __reserved1;
3383#elif defined(__LITTLE_ENDIAN)
3384        uint16_t __reserved1;
3385        uint8_t __reserved2;
3386        uint8_t cdu_usage;
3387#endif
3388        uint32_t __reserved3[6];
3389};
3390
3391
3392/*
3393 * The eth aggregative context of Xstorm
3394 */
3395struct xstorm_eth_ag_context {
3396        uint32_t reserved0;
3397#if defined(__BIG_ENDIAN)
3398        uint8_t cdu_reserved;
3399        uint8_t reserved2;
3400        uint16_t reserved1;
3401#elif defined(__LITTLE_ENDIAN)
3402        uint16_t reserved1;
3403        uint8_t reserved2;
3404        uint8_t cdu_reserved;
3405#endif
3406        uint32_t reserved3[30];
3407};
3408
3409
3410/*
3411 * doorbell message sent to the chip
3412 */
3413struct doorbell {
3414#if defined(__BIG_ENDIAN)
3415        uint16_t zero_fill2;
3416        uint8_t zero_fill1;
3417        struct doorbell_hdr header;
3418#elif defined(__LITTLE_ENDIAN)
3419        struct doorbell_hdr header;
3420        uint8_t zero_fill1;
3421        uint16_t zero_fill2;
3422#endif
3423};
3424
3425
3426/*
3427 * doorbell message sent to the chip
3428 */
3429struct doorbell_set_prod {
3430#if defined(__BIG_ENDIAN)
3431        uint16_t prod;
3432        uint8_t zero_fill1;
3433        struct doorbell_hdr header;
3434#elif defined(__LITTLE_ENDIAN)
3435        struct doorbell_hdr header;
3436        uint8_t zero_fill1;
3437        uint16_t prod;
3438#endif
3439};
3440
3441
3442struct regpair {
3443        __le32 lo;
3444        __le32 hi;
3445};
3446
3447struct regpair_native {
3448        uint32_t lo;
3449        uint32_t hi;
3450};
3451
3452/*
3453 * Classify rule opcodes in E2/E3
3454 */
3455enum classify_rule {
3456        CLASSIFY_RULE_OPCODE_MAC,
3457        CLASSIFY_RULE_OPCODE_VLAN,
3458        CLASSIFY_RULE_OPCODE_PAIR,
3459        CLASSIFY_RULE_OPCODE_VXLAN,
3460        MAX_CLASSIFY_RULE
3461};
3462
3463
3464/*
3465 * Classify rule types in E2/E3
3466 */
3467enum classify_rule_action_type {
3468        CLASSIFY_RULE_REMOVE,
3469        CLASSIFY_RULE_ADD,
3470        MAX_CLASSIFY_RULE_ACTION_TYPE
3471};
3472
3473
3474/*
3475 * client init ramrod data
3476 */
3477struct client_init_general_data {
3478        uint8_t client_id;
3479        uint8_t statistics_counter_id;
3480        uint8_t statistics_en_flg;
3481        uint8_t is_fcoe_flg;
3482        uint8_t activate_flg;
3483        uint8_t sp_client_id;
3484        __le16 mtu;
3485        uint8_t statistics_zero_flg;
3486        uint8_t func_id;
3487        uint8_t cos;
3488        uint8_t traffic_type;
3489        uint8_t fp_hsi_ver;
3490        uint8_t reserved0[3];
3491};
3492
3493
3494/*
3495 * client init rx data
3496 */
3497struct client_init_rx_data {
3498        uint8_t tpa_en;
3499#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3500#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3501#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3502#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3503#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3504#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3505#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
3506#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
3507        uint8_t vmqueue_mode_en_flg;
3508        uint8_t extra_data_over_sgl_en_flg;
3509        uint8_t cache_line_alignment_log_size;
3510        uint8_t enable_dynamic_hc;
3511        uint8_t max_sges_for_packet;
3512        uint8_t client_qzone_id;
3513        uint8_t drop_ip_cs_err_flg;
3514        uint8_t drop_tcp_cs_err_flg;
3515        uint8_t drop_ttl0_flg;
3516        uint8_t drop_udp_cs_err_flg;
3517        uint8_t inner_vlan_removal_enable_flg;
3518        uint8_t outer_vlan_removal_enable_flg;
3519        uint8_t status_block_id;
3520        uint8_t rx_sb_index_number;
3521        uint8_t dont_verify_rings_pause_thr_flg;
3522        uint8_t max_tpa_queues;
3523        uint8_t silent_vlan_removal_flg;
3524        __le16 max_bytes_on_bd;
3525        __le16 sge_buff_size;
3526        uint8_t approx_mcast_engine_id;
3527        uint8_t rss_engine_id;
3528        struct regpair bd_page_base;
3529        struct regpair sge_page_base;
3530        struct regpair cqe_page_base;
3531        uint8_t is_leading_rss;
3532        uint8_t is_approx_mcast;
3533        __le16 max_agg_size;
3534        __le16 state;
3535#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3536#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3537#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3538#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3539#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3540#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3541#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3542#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3543#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3544#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3545#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3546#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3547#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3548#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3549#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3550#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3551        __le16 cqe_pause_thr_low;
3552        __le16 cqe_pause_thr_high;
3553        __le16 bd_pause_thr_low;
3554        __le16 bd_pause_thr_high;
3555        __le16 sge_pause_thr_low;
3556        __le16 sge_pause_thr_high;
3557        __le16 rx_cos_mask;
3558        __le16 silent_vlan_value;
3559        __le16 silent_vlan_mask;
3560        uint8_t handle_ptp_pkts_flg;
3561        uint8_t reserved6[3];
3562        __le32 reserved7;
3563};
3564
3565/*
3566 * client init tx data
3567 */
3568struct client_init_tx_data {
3569        uint8_t enforce_security_flg;
3570        uint8_t tx_status_block_id;
3571        uint8_t tx_sb_index_number;
3572        uint8_t tss_leading_client_id;
3573        uint8_t tx_switching_flg;
3574        uint8_t anti_spoofing_flg;
3575        __le16 default_vlan;
3576        struct regpair tx_bd_page_base;
3577        __le16 state;
3578#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3579#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3580#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3581#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3582#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3583#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3584#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3585#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3586#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4)
3587#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
3588        uint8_t default_vlan_flg;
3589        uint8_t force_default_pri_flg;
3590        uint8_t tunnel_lso_inc_ip_id;
3591        uint8_t refuse_outband_vlan_flg;
3592        uint8_t tunnel_non_lso_pcsum_location;
3593        uint8_t tunnel_non_lso_outer_ip_csum_location;
3594};
3595
3596/*
3597 * client init ramrod data
3598 */
3599struct client_init_ramrod_data {
3600        struct client_init_general_data general;
3601        struct client_init_rx_data rx;
3602        struct client_init_tx_data tx;
3603};
3604
3605
3606/*
3607 * client update ramrod data
3608 */
3609struct client_update_ramrod_data {
3610        uint8_t client_id;
3611        uint8_t func_id;
3612        uint8_t inner_vlan_removal_enable_flg;
3613        uint8_t inner_vlan_removal_change_flg;
3614        uint8_t outer_vlan_removal_enable_flg;
3615        uint8_t outer_vlan_removal_change_flg;
3616        uint8_t anti_spoofing_enable_flg;
3617        uint8_t anti_spoofing_change_flg;
3618        uint8_t activate_flg;
3619        uint8_t activate_change_flg;
3620        __le16 default_vlan;
3621        uint8_t default_vlan_enable_flg;
3622        uint8_t default_vlan_change_flg;
3623        __le16 silent_vlan_value;
3624        __le16 silent_vlan_mask;
3625        uint8_t silent_vlan_removal_flg;
3626        uint8_t silent_vlan_change_flg;
3627        uint8_t refuse_outband_vlan_flg;
3628        uint8_t refuse_outband_vlan_change_flg;
3629        uint8_t tx_switching_flg;
3630        uint8_t tx_switching_change_flg;
3631        uint8_t handle_ptp_pkts_flg;
3632        uint8_t handle_ptp_pkts_change_flg;
3633        __le16 reserved1;
3634        __le32 echo;
3635};
3636
3637
3638/*
3639 * The eth storm context of Cstorm
3640 */
3641struct cstorm_eth_st_context {
3642        uint32_t __reserved0[4];
3643};
3644
3645
3646struct double_regpair {
3647        uint32_t regpair0_lo;
3648        uint32_t regpair0_hi;
3649        uint32_t regpair1_lo;
3650        uint32_t regpair1_hi;
3651};
3652
3653/* 2nd parse bd type used in ethernet tx BDs */
3654enum eth_2nd_parse_bd_type {
3655        ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL,
3656        MAX_ETH_2ND_PARSE_BD_TYPE
3657};
3658
3659/*
3660 * Ethernet address typesm used in ethernet tx BDs
3661 */
3662enum eth_addr_type {
3663        UNKNOWN_ADDRESS,
3664        UNICAST_ADDRESS,
3665        MULTICAST_ADDRESS,
3666        BROADCAST_ADDRESS,
3667        MAX_ETH_ADDR_TYPE
3668};
3669
3670
3671/*
3672 *
3673 */
3674struct eth_classify_cmd_header {
3675        uint8_t cmd_general_data;
3676#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3677#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3678#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3679#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3680#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3681#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3682#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3683#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3684#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3685#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3686        uint8_t func_id;
3687        uint8_t client_id;
3688        uint8_t reserved1;
3689};
3690
3691
3692/*
3693 * header for eth classification config ramrod
3694 */
3695struct eth_classify_header {
3696        uint8_t rule_cnt;
3697        uint8_t reserved0;
3698        __le16 reserved1;
3699        __le32 echo;
3700};
3701
3702
3703/*
3704 * Command for adding/removing a MAC classification rule
3705 */
3706struct eth_classify_mac_cmd {
3707        struct eth_classify_cmd_header header;
3708        __le16 reserved0;
3709        __le16 inner_mac;
3710        __le16 mac_lsb;
3711        __le16 mac_mid;
3712        __le16 mac_msb;
3713        __le16 reserved1;
3714};
3715
3716
3717/*
3718 * Command for adding/removing a MAC-VLAN pair classification rule
3719 */
3720struct eth_classify_pair_cmd {
3721        struct eth_classify_cmd_header header;
3722        __le16 reserved0;
3723        __le16 inner_mac;
3724        __le16 mac_lsb;
3725        __le16 mac_mid;
3726        __le16 mac_msb;
3727        __le16 vlan;
3728};
3729
3730
3731/*
3732 * Command for adding/removing a VLAN classification rule
3733 */
3734struct eth_classify_vlan_cmd {
3735        struct eth_classify_cmd_header header;
3736        __le32 reserved0;
3737        __le32 reserved1;
3738        __le16 reserved2;
3739        __le16 vlan;
3740};
3741
3742/*
3743 * Command for adding/removing a VXLAN classification rule
3744 */
3745struct eth_classify_vxlan_cmd {
3746        struct eth_classify_cmd_header header;
3747        __le32 vni;
3748        __le16 inner_mac_lsb;
3749        __le16 inner_mac_mid;
3750        __le16 inner_mac_msb;
3751        __le16 reserved1;
3752};
3753
3754/*
3755 * union for eth classification rule
3756 */
3757union eth_classify_rule_cmd {
3758        struct eth_classify_mac_cmd mac;
3759        struct eth_classify_vlan_cmd vlan;
3760        struct eth_classify_pair_cmd pair;
3761        struct eth_classify_vxlan_cmd vxlan;
3762};
3763
3764/*
3765 * parameters for eth classification configuration ramrod
3766 */
3767struct eth_classify_rules_ramrod_data {
3768        struct eth_classify_header header;
3769        union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3770};
3771
3772
3773/*
3774 * The data contain client ID need to the ramrod
3775 */
3776struct eth_common_ramrod_data {
3777        __le32 client_id;
3778        __le32 reserved1;
3779};
3780
3781
3782/*
3783 * The eth storm context of Ustorm
3784 */
3785struct ustorm_eth_st_context {
3786        uint32_t reserved0[52];
3787};
3788
3789/*
3790 * The eth storm context of Tstorm
3791 */
3792struct tstorm_eth_st_context {
3793        uint32_t __reserved0[28];
3794};
3795
3796/*
3797 * The eth storm context of Xstorm
3798 */
3799struct xstorm_eth_st_context {
3800        uint32_t reserved0[60];
3801};
3802
3803/*
3804 * Ethernet connection context
3805 */
3806struct eth_context {
3807        struct ustorm_eth_st_context ustorm_st_context;
3808        struct tstorm_eth_st_context tstorm_st_context;
3809        struct xstorm_eth_ag_context xstorm_ag_context;
3810        struct tstorm_eth_ag_context tstorm_ag_context;
3811        struct cstorm_eth_ag_context cstorm_ag_context;
3812        struct ustorm_eth_ag_context ustorm_ag_context;
3813        struct timers_block_context timers_context;
3814        struct xstorm_eth_st_context xstorm_st_context;
3815        struct cstorm_eth_st_context cstorm_st_context;
3816};
3817
3818
3819/*
3820 * union for sgl and raw data.
3821 */
3822union eth_sgl_or_raw_data {
3823        __le16 sgl[8];
3824        uint32_t raw_data[4];
3825};
3826
3827/*
3828 * eth FP end aggregation CQE parameters struct
3829 */
3830struct eth_end_agg_rx_cqe {
3831        uint8_t type_error_flags;
3832#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3833#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3834#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3835#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3836#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3837#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3838        uint8_t reserved1;
3839        uint8_t queue_index;
3840        uint8_t reserved2;
3841        __le32 timestamp_delta;
3842        __le16 num_of_coalesced_segs;
3843        __le16 pkt_len;
3844        uint8_t pure_ack_count;
3845        uint8_t reserved3;
3846        __le16 reserved4;
3847        union eth_sgl_or_raw_data sgl_or_raw_data;
3848        __le32 reserved5[8];
3849};
3850
3851
3852/*
3853 * regular eth FP CQE parameters struct
3854 */
3855struct eth_fast_path_rx_cqe {
3856        uint8_t type_error_flags;
3857#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3858#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3859#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3860#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3861#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3862#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3863#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3864#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3865#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3866#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3867#define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6)
3868#define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6
3869#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7)
3870#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7
3871        uint8_t status_flags;
3872#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3873#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3874#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3875#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3876#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3877#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3878#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3879#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3880#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3881#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3882#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3883#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3884        uint8_t queue_index;
3885        uint8_t placement_offset;
3886        __le32 rss_hash_result;
3887        __le16 vlan_tag;
3888        __le16 pkt_len_or_gro_seg_len;
3889        __le16 len_on_bd;
3890        struct parsing_flags pars_flags;
3891        union eth_sgl_or_raw_data sgl_or_raw_data;
3892        __le32 reserved1[7];
3893        uint32_t marker;
3894};
3895
3896
3897/*
3898 * Command for setting classification flags for a client
3899 */
3900struct eth_filter_rules_cmd {
3901        uint8_t cmd_general_data;
3902#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3903#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3904#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3905#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3906#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3907#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3908        uint8_t func_id;
3909        uint8_t client_id;
3910        uint8_t reserved1;
3911        __le16 state;
3912#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3913#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3914#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3915#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3916#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3917#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3918#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3919#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3920#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3921#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3922#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3923#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3924#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3925#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3926#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3927#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3928        __le16 reserved3;
3929        struct regpair reserved4;
3930};
3931
3932
3933/*
3934 * parameters for eth classification filters ramrod
3935 */
3936struct eth_filter_rules_ramrod_data {
3937        struct eth_classify_header header;
3938        struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
3939};
3940
3941/* Hsi version */
3942enum eth_fp_hsi_ver {
3943        ETH_FP_HSI_VER_0,
3944        ETH_FP_HSI_VER_1,
3945        ETH_FP_HSI_VER_2,
3946        MAX_ETH_FP_HSI_VER
3947};
3948
3949/*
3950 * parameters for eth classification configuration ramrod
3951 */
3952struct eth_general_rules_ramrod_data {
3953        struct eth_classify_header header;
3954        union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3955};
3956
3957
3958/*
3959 * The data for Halt ramrod
3960 */
3961struct eth_halt_ramrod_data {
3962        __le32 client_id;
3963        __le32 reserved0;
3964};
3965
3966
3967/*
3968 * destination and source mac address.
3969 */
3970struct eth_mac_addresses {
3971#if defined(__BIG_ENDIAN)
3972        __le16 dst_mid;
3973        __le16 dst_lo;
3974#elif defined(__LITTLE_ENDIAN)
3975        __le16 dst_lo;
3976        __le16 dst_mid;
3977#endif
3978#if defined(__BIG_ENDIAN)
3979        __le16 src_lo;
3980        __le16 dst_hi;
3981#elif defined(__LITTLE_ENDIAN)
3982        __le16 dst_hi;
3983        __le16 src_lo;
3984#endif
3985#if defined(__BIG_ENDIAN)
3986        __le16 src_hi;
3987        __le16 src_mid;
3988#elif defined(__LITTLE_ENDIAN)
3989        __le16 src_mid;
3990        __le16 src_hi;
3991#endif
3992};
3993
3994/* tunneling related data */
3995struct eth_tunnel_data {
3996        __le16 dst_lo;
3997        __le16 dst_mid;
3998        __le16 dst_hi;
3999        __le16 fw_ip_hdr_csum;
4000        __le16 pseudo_csum;
4001        uint8_t ip_hdr_start_inner_w;
4002        uint8_t flags;
4003#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0)
4004#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
4005#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)
4006#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
4007};
4008
4009/* union for mac addresses and for tunneling data.
4010 * considered as tunneling data only if (tunnel_exist == 1).
4011 */
4012union eth_mac_addr_or_tunnel_data {
4013        struct eth_mac_addresses mac_addr;
4014        struct eth_tunnel_data tunnel_data;
4015};
4016
4017/*Command for setting multicast classification for a client */
4018struct eth_multicast_rules_cmd {
4019        uint8_t cmd_general_data;
4020#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
4021#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
4022#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
4023#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
4024#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
4025#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
4026#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
4027#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
4028        uint8_t func_id;
4029        uint8_t bin_id;
4030        uint8_t engine_id;
4031        __le32 reserved2;
4032        struct regpair reserved3;
4033};
4034
4035/*
4036 * parameters for multicast classification ramrod
4037 */
4038struct eth_multicast_rules_ramrod_data {
4039        struct eth_classify_header header;
4040        struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
4041};
4042
4043/*
4044 * Place holder for ramrods protocol specific data
4045 */
4046struct ramrod_data {
4047        __le32 data_lo;
4048        __le32 data_hi;
4049};
4050
4051/*
4052 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
4053 */
4054union eth_ramrod_data {
4055        struct ramrod_data general;
4056};
4057
4058
4059/*
4060 * RSS toeplitz hash type, as reported in CQE
4061 */
4062enum eth_rss_hash_type {
4063        DEFAULT_HASH_TYPE,
4064        IPV4_HASH_TYPE,
4065        TCP_IPV4_HASH_TYPE,
4066        IPV6_HASH_TYPE,
4067        TCP_IPV6_HASH_TYPE,
4068        VLAN_PRI_HASH_TYPE,
4069        E1HOV_PRI_HASH_TYPE,
4070        DSCP_HASH_TYPE,
4071        MAX_ETH_RSS_HASH_TYPE
4072};
4073
4074
4075/*
4076 * Ethernet RSS mode
4077 */
4078enum eth_rss_mode {
4079        ETH_RSS_MODE_DISABLED,
4080        ETH_RSS_MODE_REGULAR,
4081        ETH_RSS_MODE_VLAN_PRI,
4082        ETH_RSS_MODE_E1HOV_PRI,
4083        ETH_RSS_MODE_IP_DSCP,
4084        MAX_ETH_RSS_MODE
4085};
4086
4087
4088/*
4089 * parameters for RSS update ramrod (E2)
4090 */
4091struct eth_rss_update_ramrod_data {
4092        uint8_t rss_engine_id;
4093        uint8_t rss_mode;
4094        __le16 capabilities;
4095#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
4096#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
4097#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
4098#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
4099#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
4100#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
4101#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3)
4102#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3
4103#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4)
4104#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4
4105#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5)
4106#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5
4107#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6)
4108#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
4109#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)
4110#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
4111#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<8)
4112#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 8
4113#define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY (0x1<<9)
4114#define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY_SHIFT 9
4115#define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY (0x1<<10)
4116#define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY_SHIFT 10
4117#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<11)
4118#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 11
4119#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0xF<<12)
4120#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 12
4121        uint8_t rss_result_mask;
4122        uint8_t reserved3;
4123        __le16 reserved4;
4124        uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
4125        __le32 rss_key[T_ETH_RSS_KEY];
4126        __le32 echo;
4127        __le32 reserved5;
4128};
4129
4130
4131/*
4132 * The eth Rx Buffer Descriptor
4133 */
4134struct eth_rx_bd {
4135        __le32 addr_lo;
4136        __le32 addr_hi;
4137};
4138
4139
4140/*
4141 * Eth Rx Cqe structure- general structure for ramrods
4142 */
4143struct common_ramrod_eth_rx_cqe {
4144        uint8_t ramrod_type;
4145#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
4146#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
4147#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
4148#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
4149#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
4150#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
4151        uint8_t conn_type;
4152        __le16 reserved1;
4153        __le32 conn_and_cmd_data;
4154#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
4155#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
4156#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
4157#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
4158        struct ramrod_data protocol_data;
4159        __le32 echo;
4160        __le32 reserved2[11];
4161};
4162
4163/*
4164 * Rx Last CQE in page (in ETH)
4165 */
4166struct eth_rx_cqe_next_page {
4167        __le32 addr_lo;
4168        __le32 addr_hi;
4169        __le32 reserved[14];
4170};
4171
4172/*
4173 * union for all eth rx cqe types (fix their sizes)
4174 */
4175union eth_rx_cqe {
4176        struct eth_fast_path_rx_cqe fast_path_cqe;
4177        struct common_ramrod_eth_rx_cqe ramrod_cqe;
4178        struct eth_rx_cqe_next_page next_page_cqe;
4179        struct eth_end_agg_rx_cqe end_agg_cqe;
4180};
4181
4182
4183/*
4184 * Values for RX ETH CQE type field
4185 */
4186enum eth_rx_cqe_type {
4187        RX_ETH_CQE_TYPE_ETH_FASTPATH,
4188        RX_ETH_CQE_TYPE_ETH_RAMROD,
4189        RX_ETH_CQE_TYPE_ETH_START_AGG,
4190        RX_ETH_CQE_TYPE_ETH_STOP_AGG,
4191        MAX_ETH_RX_CQE_TYPE
4192};
4193
4194
4195/*
4196 * Type of SGL/Raw field in ETH RX fast path CQE
4197 */
4198enum eth_rx_fp_sel {
4199        ETH_FP_CQE_REGULAR,
4200        ETH_FP_CQE_RAW,
4201        MAX_ETH_RX_FP_SEL
4202};
4203
4204
4205/*
4206 * The eth Rx SGE Descriptor
4207 */
4208struct eth_rx_sge {
4209        __le32 addr_lo;
4210        __le32 addr_hi;
4211};
4212
4213
4214/*
4215 * common data for all protocols
4216 */
4217struct spe_hdr {
4218        __le32 conn_and_cmd_data;
4219#define SPE_HDR_CID (0xFFFFFF<<0)
4220#define SPE_HDR_CID_SHIFT 0
4221#define SPE_HDR_CMD_ID (0xFF<<24)
4222#define SPE_HDR_CMD_ID_SHIFT 24
4223        __le16 type;
4224#define SPE_HDR_CONN_TYPE (0xFF<<0)
4225#define SPE_HDR_CONN_TYPE_SHIFT 0
4226#define SPE_HDR_FUNCTION_ID (0xFF<<8)
4227#define SPE_HDR_FUNCTION_ID_SHIFT 8
4228        __le16 reserved1;
4229};
4230
4231/*
4232 * specific data for ethernet slow path element
4233 */
4234union eth_specific_data {
4235        uint8_t protocol_data[8];
4236        struct regpair client_update_ramrod_data;
4237        struct regpair client_init_ramrod_init_data;
4238        struct eth_halt_ramrod_data halt_ramrod_data;
4239        struct regpair update_data_addr;
4240        struct eth_common_ramrod_data common_ramrod_data;
4241        struct regpair classify_cfg_addr;
4242        struct regpair filter_cfg_addr;
4243        struct regpair mcast_cfg_addr;
4244};
4245
4246/*
4247 * Ethernet slow path element
4248 */
4249struct eth_spe {
4250        struct spe_hdr hdr;
4251        union eth_specific_data data;
4252};
4253
4254
4255/*
4256 * Ethernet command ID for slow path elements
4257 */
4258enum eth_spqe_cmd_id {
4259        RAMROD_CMD_ID_ETH_UNUSED,
4260        RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4261        RAMROD_CMD_ID_ETH_HALT,
4262        RAMROD_CMD_ID_ETH_FORWARD_SETUP,
4263        RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
4264        RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
4265        RAMROD_CMD_ID_ETH_EMPTY,
4266        RAMROD_CMD_ID_ETH_TERMINATE,
4267        RAMROD_CMD_ID_ETH_TPA_UPDATE,
4268        RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
4269        RAMROD_CMD_ID_ETH_FILTER_RULES,
4270        RAMROD_CMD_ID_ETH_MULTICAST_RULES,
4271        RAMROD_CMD_ID_ETH_RSS_UPDATE,
4272        RAMROD_CMD_ID_ETH_SET_MAC,
4273        MAX_ETH_SPQE_CMD_ID
4274};
4275
4276
4277/*
4278 * eth tpa update command
4279 */
4280enum eth_tpa_update_command {
4281        TPA_UPDATE_NONE_COMMAND,
4282        TPA_UPDATE_ENABLE_COMMAND,
4283        TPA_UPDATE_DISABLE_COMMAND,
4284        MAX_ETH_TPA_UPDATE_COMMAND
4285};
4286
4287/* In case of LSO over IPv4 tunnel, whether to increment
4288 * IP ID on external IP header or internal IP header
4289 */
4290enum eth_tunnel_lso_inc_ip_id {
4291        EXT_HEADER,
4292        INT_HEADER,
4293        MAX_ETH_TUNNEL_LSO_INC_IP_ID
4294};
4295
4296/* In case tunnel exist and L4 checksum offload,
4297 * the pseudo checksum location, on packet or on BD.
4298 */
4299enum eth_tunnel_non_lso_csum_location {
4300        CSUM_ON_PKT,
4301        CSUM_ON_BD,
4302        MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION
4303};
4304
4305/*
4306 * Tx regular BD structure
4307 */
4308struct eth_tx_bd {
4309        __le32 addr_lo;
4310        __le32 addr_hi;
4311        __le16 total_pkt_bytes;
4312        __le16 nbytes;
4313        uint8_t reserved[4];
4314};
4315
4316
4317/*
4318 * structure for easy accessibility to assembler
4319 */
4320struct eth_tx_bd_flags {
4321        uint8_t as_bitfield;
4322#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
4323#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4324#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
4325#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
4326#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
4327#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
4328#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
4329#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
4330#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
4331#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
4332#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
4333#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
4334#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
4335#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
4336};
4337
4338/*
4339 * The eth Tx Buffer Descriptor
4340 */
4341struct eth_tx_start_bd {
4342        __le32 addr_lo;
4343        __le32 addr_hi;
4344        __le16 nbd;
4345        __le16 nbytes;
4346        __le16 vlan_or_ethertype;
4347        struct eth_tx_bd_flags bd_flags;
4348        uint8_t general_data;
4349#define ETH_TX_START_BD_HDR_NBDS (0x7<<0)
4350#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4351#define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3)
4352#define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3
4353#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4354#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4355#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
4356#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
4357#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7)
4358#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
4359};
4360
4361/*
4362 * Tx parsing BD structure for ETH E1/E1h
4363 */
4364struct eth_tx_parse_bd_e1x {
4365        __le16 global_data;
4366#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4367#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4368#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
4369#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
4370#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
4371#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
4372#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
4373#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
4374#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
4375#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
4376#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
4377#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
4378        uint8_t tcp_flags;
4379#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4380#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4381#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
4382#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
4383#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
4384#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
4385#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
4386#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
4387#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
4388#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
4389#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
4390#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
4391#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
4392#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
4393#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4394#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4395        uint8_t ip_hlen_w;
4396        __le16 total_hlen_w;
4397        __le16 tcp_pseudo_csum;
4398        __le16 lso_mss;
4399        __le16 ip_id;
4400        __le32 tcp_send_seq;
4401};
4402
4403/*
4404 * Tx parsing BD structure for ETH E2
4405 */
4406struct eth_tx_parse_bd_e2 {
4407        union eth_mac_addr_or_tunnel_data data;
4408        __le32 parsing_data;
4409#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0)
4410#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
4411#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
4412#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
4413#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
4414#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
4415#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
4416#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
4417#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
4418#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
4419};
4420
4421/*
4422 * Tx 2nd parsing BD structure for ETH packet
4423 */
4424struct eth_tx_parse_2nd_bd {
4425        __le16 global_data;
4426#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0)
4427#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
4428#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4)
4429#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
4430#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5)
4431#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
4432#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6)
4433#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
4434#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7)
4435#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
4436#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8)
4437#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
4438#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13)
4439#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
4440        uint8_t bd_type;
4441#define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0)
4442#define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
4443#define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4)
4444#define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4
4445        uint8_t reserved3;
4446        uint8_t tcp_flags;
4447#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0)
4448#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
4449#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1)
4450#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
4451#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2)
4452#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
4453#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3)
4454#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
4455#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4)
4456#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
4457#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5)
4458#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
4459#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6)
4460#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
4461#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7)
4462#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
4463        uint8_t reserved4;
4464        uint8_t tunnel_udp_hdr_start_w;
4465        uint8_t fw_ip_hdr_to_payload_w;
4466        __le16 fw_ip_csum_wo_len_flags_frag;
4467        __le16 hw_ip_id;
4468        __le32 tcp_send_seq;
4469};
4470
4471/* The last BD in the BD memory will hold a pointer to the next BD memory */
4472struct eth_tx_next_bd {
4473        __le32 addr_lo;
4474        __le32 addr_hi;
4475        uint8_t reserved[8];
4476};
4477
4478/*
4479 * union for 4 Bd types
4480 */
4481union eth_tx_bd_types {
4482        struct eth_tx_start_bd start_bd;
4483        struct eth_tx_bd reg_bd;
4484        struct eth_tx_parse_bd_e1x parse_bd_e1x;
4485        struct eth_tx_parse_bd_e2 parse_bd_e2;
4486        struct eth_tx_parse_2nd_bd parse_2nd_bd;
4487        struct eth_tx_next_bd next_bd;
4488};
4489
4490/*
4491 * array of 13 bds as appears in the eth xstorm context
4492 */
4493struct eth_tx_bds_array {
4494        union eth_tx_bd_types bds[13];
4495};
4496
4497
4498/*
4499 * VLAN mode on TX BDs
4500 */
4501enum eth_tx_vlan_type {
4502        X_ETH_NO_VLAN,
4503        X_ETH_OUTBAND_VLAN,
4504        X_ETH_INBAND_VLAN,
4505        X_ETH_FW_ADDED_VLAN,
4506        MAX_ETH_TX_VLAN_TYPE
4507};
4508
4509
4510/*
4511 * Ethernet VLAN filtering mode in E1x
4512 */
4513enum eth_vlan_filter_mode {
4514        ETH_VLAN_FILTER_ANY_VLAN,
4515        ETH_VLAN_FILTER_SPECIFIC_VLAN,
4516        ETH_VLAN_FILTER_CLASSIFY,
4517        MAX_ETH_VLAN_FILTER_MODE
4518};
4519
4520
4521/*
4522 * MAC filtering configuration command header
4523 */
4524struct mac_configuration_hdr {
4525        uint8_t length;
4526        uint8_t offset;
4527        __le16 client_id;
4528        __le32 echo;
4529};
4530
4531/*
4532 * MAC address in list for ramrod
4533 */
4534struct mac_configuration_entry {
4535        __le16 lsb_mac_addr;
4536        __le16 middle_mac_addr;
4537        __le16 msb_mac_addr;
4538        __le16 vlan_id;
4539        uint8_t pf_id;
4540        uint8_t flags;
4541#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4542#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4543#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4544#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4545#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4546#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4547#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4548#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4549#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4550#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4551#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4552#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4553        __le16 reserved0;
4554        __le32 clients_bit_vector;
4555};
4556
4557/*
4558 * MAC filtering configuration command
4559 */
4560struct mac_configuration_cmd {
4561        struct mac_configuration_hdr hdr;
4562        struct mac_configuration_entry config_table[64];
4563};
4564
4565
4566/*
4567 * Set-MAC command type (in E1x)
4568 */
4569enum set_mac_action_type {
4570        T_ETH_MAC_COMMAND_INVALIDATE,
4571        T_ETH_MAC_COMMAND_SET,
4572        MAX_SET_MAC_ACTION_TYPE
4573};
4574
4575
4576/*
4577 * Ethernet TPA Modes
4578 */
4579enum tpa_mode {
4580        TPA_LRO,
4581        TPA_GRO,
4582        MAX_TPA_MODE};
4583
4584
4585/*
4586 * tpa update ramrod data
4587 */
4588struct tpa_update_ramrod_data {
4589        uint8_t update_ipv4;
4590        uint8_t update_ipv6;
4591        uint8_t client_id;
4592        uint8_t max_tpa_queues;
4593        uint8_t max_sges_for_packet;
4594        uint8_t complete_on_both_clients;
4595        uint8_t dont_verify_rings_pause_thr_flg;
4596        uint8_t tpa_mode;
4597        __le16 sge_buff_size;
4598        __le16 max_agg_size;
4599        __le32 sge_page_base_lo;
4600        __le32 sge_page_base_hi;
4601        __le16 sge_pause_thr_low;
4602        __le16 sge_pause_thr_high;
4603};
4604
4605
4606/*
4607 * approximate-match multicast filtering for E1H per function in Tstorm
4608 */
4609struct tstorm_eth_approximate_match_multicast_filtering {
4610        uint32_t mcast_add_hash_bit_array[8];
4611};
4612
4613
4614/*
4615 * Common configuration parameters per function in Tstorm
4616 */
4617struct tstorm_eth_function_common_config {
4618        __le16 config_flags;
4619#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4620#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4621#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4622#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4623#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4624#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4625#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4626#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4627#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4628#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4629#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4630#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4631#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4632#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4633        uint8_t rss_result_mask;
4634        uint8_t reserved1;
4635        __le16 vlan_id[2];
4636};
4637
4638
4639/*
4640 * MAC filtering configuration parameters per port in Tstorm
4641 */
4642struct tstorm_eth_mac_filter_config {
4643        uint32_t ucast_drop_all;
4644        uint32_t ucast_accept_all;
4645        uint32_t mcast_drop_all;
4646        uint32_t mcast_accept_all;
4647        uint32_t bcast_accept_all;
4648        uint32_t vlan_filter[2];
4649        uint32_t unmatched_unicast;
4650};
4651
4652
4653/*
4654 * tx only queue init ramrod data
4655 */
4656struct tx_queue_init_ramrod_data {
4657        struct client_init_general_data general;
4658        struct client_init_tx_data tx;
4659};
4660
4661
4662/*
4663 * Three RX producers for ETH
4664 */
4665struct ustorm_eth_rx_producers {
4666#if defined(__BIG_ENDIAN)
4667        uint16_t bd_prod;
4668        uint16_t cqe_prod;
4669#elif defined(__LITTLE_ENDIAN)
4670        uint16_t cqe_prod;
4671        uint16_t bd_prod;
4672#endif
4673#if defined(__BIG_ENDIAN)
4674        uint16_t reserved;
4675        uint16_t sge_prod;
4676#elif defined(__LITTLE_ENDIAN)
4677        uint16_t sge_prod;
4678        uint16_t reserved;
4679#endif
4680};
4681
4682
4683/*
4684 * FCoE RX statistics parameters section#0
4685 */
4686struct fcoe_rx_stat_params_section0 {
4687        __le32 fcoe_rx_pkt_cnt;
4688        __le32 fcoe_rx_byte_cnt;
4689};
4690
4691
4692/*
4693 * FCoE RX statistics parameters section#1
4694 */
4695struct fcoe_rx_stat_params_section1 {
4696        __le32 fcoe_ver_cnt;
4697        __le32 fcoe_rx_drop_pkt_cnt;
4698};
4699
4700
4701/*
4702 * FCoE RX statistics parameters section#2
4703 */
4704struct fcoe_rx_stat_params_section2 {
4705        __le32 fc_crc_cnt;
4706        __le32 eofa_del_cnt;
4707        __le32 miss_frame_cnt;
4708        __le32 seq_timeout_cnt;
4709        __le32 drop_seq_cnt;
4710        __le32 fcoe_rx_drop_pkt_cnt;
4711        __le32 fcp_rx_pkt_cnt;
4712        __le32 reserved0;
4713};
4714
4715
4716/*
4717 * FCoE TX statistics parameters
4718 */
4719struct fcoe_tx_stat_params {
4720        __le32 fcoe_tx_pkt_cnt;
4721        __le32 fcoe_tx_byte_cnt;
4722        __le32 fcp_tx_pkt_cnt;
4723        __le32 reserved0;
4724};
4725
4726/*
4727 * FCoE statistics parameters
4728 */
4729struct fcoe_statistics_params {
4730        struct fcoe_tx_stat_params tx_stat;
4731        struct fcoe_rx_stat_params_section0 rx_stat0;
4732        struct fcoe_rx_stat_params_section1 rx_stat1;
4733        struct fcoe_rx_stat_params_section2 rx_stat2;
4734};
4735
4736
4737/*
4738 * The data afex vif list ramrod need
4739 */
4740struct afex_vif_list_ramrod_data {
4741        uint8_t afex_vif_list_command;
4742        uint8_t func_bit_map;
4743        __le16 vif_list_index;
4744        uint8_t func_to_clear;
4745        uint8_t echo;
4746        __le16 reserved1;
4747};
4748
4749
4750/*
4751 * cfc delete event data
4752 */
4753struct cfc_del_event_data {
4754        uint32_t cid;
4755        uint32_t reserved0;
4756        uint32_t reserved1;
4757};
4758
4759
4760/*
4761 * per-port SAFC demo variables
4762 */
4763struct cmng_flags_per_port {
4764        uint32_t cmng_enables;
4765#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4766#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4767#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4768#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4769#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4770#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4771#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4772#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4773#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4774#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4775        uint32_t __reserved1;
4776};
4777
4778
4779/*
4780 * per-port rate shaping variables
4781 */
4782struct rate_shaping_vars_per_port {
4783        uint32_t rs_periodic_timeout;
4784        uint32_t rs_threshold;
4785};
4786
4787/*
4788 * per-port fairness variables
4789 */
4790struct fairness_vars_per_port {
4791        uint32_t upper_bound;
4792        uint32_t fair_threshold;
4793        uint32_t fairness_timeout;
4794        uint32_t reserved0;
4795};
4796
4797/*
4798 * per-port SAFC variables
4799 */
4800struct safc_struct_per_port {
4801#if defined(__BIG_ENDIAN)
4802        uint16_t __reserved1;
4803        uint8_t __reserved0;
4804        uint8_t safc_timeout_usec;
4805#elif defined(__LITTLE_ENDIAN)
4806        uint8_t safc_timeout_usec;
4807        uint8_t __reserved0;
4808        uint16_t __reserved1;
4809#endif
4810        uint8_t cos_to_traffic_types[MAX_COS_NUMBER];
4811        uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS];
4812};
4813
4814/*
4815 * Per-port congestion management variables
4816 */
4817struct cmng_struct_per_port {
4818        struct rate_shaping_vars_per_port rs_vars;
4819        struct fairness_vars_per_port fair_vars;
4820        struct safc_struct_per_port safc_vars;
4821        struct cmng_flags_per_port flags;
4822};
4823
4824/*
4825 * a single rate shaping counter. can be used as protocol or vnic counter
4826 */
4827struct rate_shaping_counter {
4828        uint32_t quota;
4829#if defined(__BIG_ENDIAN)
4830        uint16_t __reserved0;
4831        uint16_t rate;
4832#elif defined(__LITTLE_ENDIAN)
4833        uint16_t rate;
4834        uint16_t __reserved0;
4835#endif
4836};
4837
4838/*
4839 * per-vnic rate shaping variables
4840 */
4841struct rate_shaping_vars_per_vn {
4842        struct rate_shaping_counter vn_counter;
4843};
4844
4845/*
4846 * per-vnic fairness variables
4847 */
4848struct fairness_vars_per_vn {
4849        uint32_t cos_credit_delta[MAX_COS_NUMBER];
4850        uint32_t vn_credit_delta;
4851        uint32_t __reserved0;
4852};
4853
4854/*
4855 * cmng port init state
4856 */
4857struct cmng_vnic {
4858        struct rate_shaping_vars_per_vn vnic_max_rate[4];
4859        struct fairness_vars_per_vn vnic_min_rate[4];
4860};
4861
4862/*
4863 * cmng port init state
4864 */
4865struct cmng_init {
4866        struct cmng_struct_per_port port;
4867        struct cmng_vnic vnic;
4868};
4869
4870
4871/*
4872 * driver parameters for congestion management init, all rates are in Mbps
4873 */
4874struct cmng_init_input {
4875        uint32_t port_rate;
4876        uint16_t vnic_min_rate[4];
4877        uint16_t vnic_max_rate[4];
4878        uint16_t cos_min_rate[MAX_COS_NUMBER];
4879        uint16_t cos_to_pause_mask[MAX_COS_NUMBER];
4880        struct cmng_flags_per_port flags;
4881};
4882
4883
4884/*
4885 * Protocol-common command ID for slow path elements
4886 */
4887enum common_spqe_cmd_id {
4888        RAMROD_CMD_ID_COMMON_UNUSED,
4889        RAMROD_CMD_ID_COMMON_FUNCTION_START,
4890        RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
4891        RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
4892        RAMROD_CMD_ID_COMMON_CFC_DEL,
4893        RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
4894        RAMROD_CMD_ID_COMMON_STAT_QUERY,
4895        RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
4896        RAMROD_CMD_ID_COMMON_START_TRAFFIC,
4897        RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,
4898        RAMROD_CMD_ID_COMMON_SET_TIMESYNC,
4899        MAX_COMMON_SPQE_CMD_ID
4900};
4901
4902/*
4903 * Per-protocol connection types
4904 */
4905enum connection_type {
4906        ETH_CONNECTION_TYPE,
4907        TOE_CONNECTION_TYPE,
4908        RDMA_CONNECTION_TYPE,
4909        ISCSI_CONNECTION_TYPE,
4910        FCOE_CONNECTION_TYPE,
4911        RESERVED_CONNECTION_TYPE_0,
4912        RESERVED_CONNECTION_TYPE_1,
4913        RESERVED_CONNECTION_TYPE_2,
4914        NONE_CONNECTION_TYPE,
4915        MAX_CONNECTION_TYPE
4916};
4917
4918
4919/*
4920 * Cos modes
4921 */
4922enum cos_mode {
4923        OVERRIDE_COS,
4924        STATIC_COS,
4925        FW_WRR,
4926        MAX_COS_MODE
4927};
4928
4929
4930/*
4931 * Dynamic HC counters set by the driver
4932 */
4933struct hc_dynamic_drv_counter {
4934        uint32_t val[HC_SB_MAX_DYNAMIC_INDICES];
4935};
4936
4937/*
4938 * zone A per-queue data
4939 */
4940struct cstorm_queue_zone_data {
4941        struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
4942        struct regpair reserved[2];
4943};
4944
4945
4946/*
4947 * Vf-PF channel data in cstorm ram (non-triggered zone)
4948 */
4949struct vf_pf_channel_zone_data {
4950        uint32_t msg_addr_lo;
4951        uint32_t msg_addr_hi;
4952};
4953
4954/*
4955 * zone for VF non-triggered data
4956 */
4957struct non_trigger_vf_zone {
4958        struct vf_pf_channel_zone_data vf_pf_channel;
4959};
4960
4961/*
4962 * Vf-PF channel trigger zone in cstorm ram
4963 */
4964struct vf_pf_channel_zone_trigger {
4965        uint8_t addr_valid;
4966};
4967
4968/*
4969 * zone that triggers the in-bound interrupt
4970 */
4971struct trigger_vf_zone {
4972#if defined(__BIG_ENDIAN)
4973        uint16_t reserved1;
4974        uint8_t reserved0;
4975        struct vf_pf_channel_zone_trigger vf_pf_channel;
4976#elif defined(__LITTLE_ENDIAN)
4977        struct vf_pf_channel_zone_trigger vf_pf_channel;
4978        uint8_t reserved0;
4979        uint16_t reserved1;
4980#endif
4981        uint32_t reserved2;
4982};
4983
4984/*
4985 * zone B per-VF data
4986 */
4987struct cstorm_vf_zone_data {
4988        struct non_trigger_vf_zone non_trigger;
4989        struct trigger_vf_zone trigger;
4990};
4991
4992
4993/*
4994 * Dynamic host coalescing init parameters, per state machine
4995 */
4996struct dynamic_hc_sm_config {
4997        uint32_t threshold[3];
4998        uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
4999        uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
5000        uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
5001        uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
5002        uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
5003};
5004
5005/*
5006 * Dynamic host coalescing init parameters
5007 */
5008struct dynamic_hc_config {
5009        struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
5010};
5011
5012
5013struct e2_integ_data {
5014#if defined(__BIG_ENDIAN)
5015        uint8_t flags;
5016#define E2_INTEG_DATA_TESTING_EN (0x1<<0)
5017#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
5018#define E2_INTEG_DATA_LB_TX (0x1<<1)
5019#define E2_INTEG_DATA_LB_TX_SHIFT 1
5020#define E2_INTEG_DATA_COS_TX (0x1<<2)
5021#define E2_INTEG_DATA_COS_TX_SHIFT 2
5022#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
5023#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
5024#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
5025#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
5026#define E2_INTEG_DATA_RESERVED (0x7<<5)
5027#define E2_INTEG_DATA_RESERVED_SHIFT 5
5028        uint8_t cos;
5029        uint8_t voq;
5030        uint8_t pbf_queue;
5031#elif defined(__LITTLE_ENDIAN)
5032        uint8_t pbf_queue;
5033        uint8_t voq;
5034        uint8_t cos;
5035        uint8_t flags;
5036#define E2_INTEG_DATA_TESTING_EN (0x1<<0)
5037#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
5038#define E2_INTEG_DATA_LB_TX (0x1<<1)
5039#define E2_INTEG_DATA_LB_TX_SHIFT 1
5040#define E2_INTEG_DATA_COS_TX (0x1<<2)
5041#define E2_INTEG_DATA_COS_TX_SHIFT 2
5042#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
5043#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
5044#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
5045#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
5046#define E2_INTEG_DATA_RESERVED (0x7<<5)
5047#define E2_INTEG_DATA_RESERVED_SHIFT 5
5048#endif
5049#if defined(__BIG_ENDIAN)
5050        uint16_t reserved3;
5051        uint8_t reserved2;
5052        uint8_t ramEn;
5053#elif defined(__LITTLE_ENDIAN)
5054        uint8_t ramEn;
5055        uint8_t reserved2;
5056        uint16_t reserved3;
5057#endif
5058};
5059
5060
5061/*
5062 * set mac event data
5063 */
5064struct eth_event_data {
5065        uint32_t echo;
5066        uint32_t reserved0;
5067        uint32_t reserved1;
5068};
5069
5070
5071/*
5072 * pf-vf event data
5073 */
5074struct vf_pf_event_data {
5075        uint8_t vf_id;
5076        uint8_t reserved0;
5077        uint16_t reserved1;
5078        uint32_t msg_addr_lo;
5079        uint32_t msg_addr_hi;
5080};
5081
5082/*
5083 * VF FLR event data
5084 */
5085struct vf_flr_event_data {
5086        uint8_t vf_id;
5087        uint8_t reserved0;
5088        uint16_t reserved1;
5089        uint32_t reserved2;
5090        uint32_t reserved3;
5091};
5092
5093/*
5094 * malicious VF event data
5095 */
5096struct malicious_vf_event_data {
5097        uint8_t vf_id;
5098        uint8_t err_id;
5099        uint16_t reserved1;
5100        uint32_t reserved2;
5101        uint32_t reserved3;
5102};
5103
5104/*
5105 * vif list event data
5106 */
5107struct vif_list_event_data {
5108        uint8_t func_bit_map;
5109        uint8_t echo;
5110        __le16 reserved0;
5111        __le32 reserved1;
5112        __le32 reserved2;
5113};
5114
5115/* function update event data */
5116struct function_update_event_data {
5117        uint8_t echo;
5118        uint8_t reserved;
5119        __le16 reserved0;
5120        __le32 reserved1;
5121        __le32 reserved2;
5122};
5123
5124
5125/* union for all event ring message types */
5126union event_data {
5127        struct vf_pf_event_data vf_pf_event;
5128        struct eth_event_data eth_event;
5129        struct cfc_del_event_data cfc_del_event;
5130        struct vf_flr_event_data vf_flr_event;
5131        struct malicious_vf_event_data malicious_vf_event;
5132        struct vif_list_event_data vif_list_event;
5133        struct function_update_event_data function_update_event;
5134};
5135
5136
5137/*
5138 * per PF event ring data
5139 */
5140struct event_ring_data {
5141        struct regpair_native base_addr;
5142#if defined(__BIG_ENDIAN)
5143        uint8_t index_id;
5144        uint8_t sb_id;
5145        uint16_t producer;
5146#elif defined(__LITTLE_ENDIAN)
5147        uint16_t producer;
5148        uint8_t sb_id;
5149        uint8_t index_id;
5150#endif
5151        uint32_t reserved0;
5152};
5153
5154
5155/*
5156 * event ring message element (each element is 128 bits)
5157 */
5158struct event_ring_msg {
5159        uint8_t opcode;
5160        uint8_t error;
5161        uint16_t reserved1;
5162        union event_data data;
5163};
5164
5165/*
5166 * event ring next page element (128 bits)
5167 */
5168struct event_ring_next {
5169        struct regpair addr;
5170        uint32_t reserved[2];
5171};
5172
5173/*
5174 * union for event ring element types (each element is 128 bits)
5175 */
5176union event_ring_elem {
5177        struct event_ring_msg message;
5178        struct event_ring_next next_page;
5179};
5180
5181
5182/*
5183 * Common event ring opcodes
5184 */
5185enum event_ring_opcode {
5186        EVENT_RING_OPCODE_VF_PF_CHANNEL,
5187        EVENT_RING_OPCODE_FUNCTION_START,
5188        EVENT_RING_OPCODE_FUNCTION_STOP,
5189        EVENT_RING_OPCODE_CFC_DEL,
5190        EVENT_RING_OPCODE_CFC_DEL_WB,
5191        EVENT_RING_OPCODE_STAT_QUERY,
5192        EVENT_RING_OPCODE_STOP_TRAFFIC,
5193        EVENT_RING_OPCODE_START_TRAFFIC,
5194        EVENT_RING_OPCODE_VF_FLR,
5195        EVENT_RING_OPCODE_MALICIOUS_VF,
5196        EVENT_RING_OPCODE_FORWARD_SETUP,
5197        EVENT_RING_OPCODE_RSS_UPDATE_RULES,
5198        EVENT_RING_OPCODE_FUNCTION_UPDATE,
5199        EVENT_RING_OPCODE_AFEX_VIF_LISTS,
5200        EVENT_RING_OPCODE_SET_MAC,
5201        EVENT_RING_OPCODE_CLASSIFICATION_RULES,
5202        EVENT_RING_OPCODE_FILTERS_RULES,
5203        EVENT_RING_OPCODE_MULTICAST_RULES,
5204        EVENT_RING_OPCODE_SET_TIMESYNC,
5205        MAX_EVENT_RING_OPCODE
5206};
5207
5208/*
5209 * Modes for fairness algorithm
5210 */
5211enum fairness_mode {
5212        FAIRNESS_COS_WRR_MODE,
5213        FAIRNESS_COS_ETS_MODE,
5214        MAX_FAIRNESS_MODE
5215};
5216
5217
5218/*
5219 * Priority and cos
5220 */
5221struct priority_cos {
5222        uint8_t priority;
5223        uint8_t cos;
5224        __le16 reserved1;
5225};
5226
5227/*
5228 * The data for flow control configuration
5229 */
5230struct flow_control_configuration {
5231        struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
5232        uint8_t dcb_enabled;
5233        uint8_t dcb_version;
5234        uint8_t dont_add_pri_0_en;
5235        uint8_t reserved1;
5236        __le32 reserved2;
5237};
5238
5239
5240/*
5241 *
5242 */
5243struct function_start_data {
5244        uint8_t function_mode;
5245        uint8_t allow_npar_tx_switching;
5246        __le16 sd_vlan_tag;
5247        __le16 vif_id;
5248        uint8_t path_id;
5249        uint8_t network_cos_mode;
5250        uint8_t dmae_cmd_id;
5251        uint8_t tunnel_mode;
5252        uint8_t gre_tunnel_type;
5253        uint8_t tunn_clss_en;
5254        uint8_t inner_gre_rss_en;
5255        uint8_t sd_accept_mf_clss_fail;
5256        __le16 vxlan_dst_port;
5257        __le16 sd_accept_mf_clss_fail_ethtype;
5258        __le16 sd_vlan_eth_type;
5259        uint8_t sd_vlan_force_pri_flg;
5260        uint8_t sd_vlan_force_pri_val;
5261        uint8_t sd_accept_mf_clss_fail_match_ethtype;
5262        uint8_t no_added_tags;
5263};
5264
5265struct function_update_data {
5266        uint8_t vif_id_change_flg;
5267        uint8_t afex_default_vlan_change_flg;
5268        uint8_t allowed_priorities_change_flg;
5269        uint8_t network_cos_mode_change_flg;
5270        __le16 vif_id;
5271        __le16 afex_default_vlan;
5272        uint8_t allowed_priorities;
5273        uint8_t network_cos_mode;
5274        uint8_t lb_mode_en_change_flg;
5275        uint8_t lb_mode_en;
5276        uint8_t tx_switch_suspend_change_flg;
5277        uint8_t tx_switch_suspend;
5278        uint8_t echo;
5279        uint8_t update_tunn_cfg_flg;
5280        uint8_t tunnel_mode;
5281        uint8_t gre_tunnel_type;
5282        uint8_t tunn_clss_en;
5283        uint8_t inner_gre_rss_en;
5284        __le16 vxlan_dst_port;
5285        uint8_t sd_vlan_force_pri_change_flg;
5286        uint8_t sd_vlan_force_pri_flg;
5287        uint8_t sd_vlan_force_pri_val;
5288        uint8_t sd_vlan_tag_change_flg;
5289        uint8_t sd_vlan_eth_type_change_flg;
5290        uint8_t reserved1;
5291        __le16 sd_vlan_tag;
5292        __le16 sd_vlan_eth_type;
5293};
5294
5295/*
5296 * FW version stored in the Xstorm RAM
5297 */
5298struct fw_version {
5299#if defined(__BIG_ENDIAN)
5300        uint8_t engineering;
5301        uint8_t revision;
5302        uint8_t minor;
5303        uint8_t major;
5304#elif defined(__LITTLE_ENDIAN)
5305        uint8_t major;
5306        uint8_t minor;
5307        uint8_t revision;
5308        uint8_t engineering;
5309#endif
5310        uint32_t flags;
5311#define FW_VERSION_OPTIMIZED (0x1<<0)
5312#define FW_VERSION_OPTIMIZED_SHIFT 0
5313#define FW_VERSION_BIG_ENDIEN (0x1<<1)
5314#define FW_VERSION_BIG_ENDIEN_SHIFT 1
5315#define FW_VERSION_CHIP_VERSION (0x3<<2)
5316#define FW_VERSION_CHIP_VERSION_SHIFT 2
5317#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
5318#define __FW_VERSION_RESERVED_SHIFT 4
5319};
5320
5321
5322/* GRE Tunnel Mode */
5323enum gre_tunnel_type {
5324        NVGRE_TUNNEL,
5325        L2GRE_TUNNEL,
5326        IPGRE_TUNNEL,
5327        MAX_GRE_TUNNEL_TYPE
5328};
5329
5330/*
5331 * Dynamic Host-Coalescing - Driver(host) counters
5332 */
5333struct hc_dynamic_sb_drv_counters {
5334        uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
5335};
5336
5337
5338/*
5339 * 2 bytes. configuration/state parameters for a single protocol index
5340 */
5341struct hc_index_data {
5342#if defined(__BIG_ENDIAN)
5343        uint8_t flags;
5344#define HC_INDEX_DATA_SM_ID (0x1<<0)
5345#define HC_INDEX_DATA_SM_ID_SHIFT 0
5346#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5347#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5348#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5349#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5350#define HC_INDEX_DATA_RESERVE (0x1F<<3)
5351#define HC_INDEX_DATA_RESERVE_SHIFT 3
5352        uint8_t timeout;
5353#elif defined(__LITTLE_ENDIAN)
5354        uint8_t timeout;
5355        uint8_t flags;
5356#define HC_INDEX_DATA_SM_ID (0x1<<0)
5357#define HC_INDEX_DATA_SM_ID_SHIFT 0
5358#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5359#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5360#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5361#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5362#define HC_INDEX_DATA_RESERVE (0x1F<<3)
5363#define HC_INDEX_DATA_RESERVE_SHIFT 3
5364#endif
5365};
5366
5367
5368/*
5369 * HC state-machine
5370 */
5371struct hc_status_block_sm {
5372#if defined(__BIG_ENDIAN)
5373        uint8_t igu_seg_id;
5374        uint8_t igu_sb_id;
5375        uint8_t timer_value;
5376        uint8_t __flags;
5377#elif defined(__LITTLE_ENDIAN)
5378        uint8_t __flags;
5379        uint8_t timer_value;
5380        uint8_t igu_sb_id;
5381        uint8_t igu_seg_id;
5382#endif
5383        uint32_t time_to_expire;
5384};
5385
5386/*
5387 * hold PCI identification variables- used in various places in firmware
5388 */
5389struct pci_entity {
5390#if defined(__BIG_ENDIAN)
5391        uint8_t vf_valid;
5392        uint8_t vf_id;
5393        uint8_t vnic_id;
5394        uint8_t pf_id;
5395#elif defined(__LITTLE_ENDIAN)
5396        uint8_t pf_id;
5397        uint8_t vnic_id;
5398        uint8_t vf_id;
5399        uint8_t vf_valid;
5400#endif
5401};
5402
5403/*
5404 * The fast-path status block meta-data, common to all chips
5405 */
5406struct hc_sb_data {
5407        struct regpair_native host_sb_addr;
5408        struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
5409        struct pci_entity p_func;
5410#if defined(__BIG_ENDIAN)
5411        uint8_t rsrv0;
5412        uint8_t state;
5413        uint8_t dhc_qzone_id;
5414        uint8_t same_igu_sb_1b;
5415#elif defined(__LITTLE_ENDIAN)
5416        uint8_t same_igu_sb_1b;
5417        uint8_t dhc_qzone_id;
5418        uint8_t state;
5419        uint8_t rsrv0;
5420#endif
5421        struct regpair_native rsrv1[2];
5422};
5423
5424
5425/*
5426 * Segment types for host coaslescing
5427 */
5428enum hc_segment {
5429        HC_REGULAR_SEGMENT,
5430        HC_DEFAULT_SEGMENT,
5431        MAX_HC_SEGMENT
5432};
5433
5434
5435/*
5436 * The fast-path status block meta-data
5437 */
543