akaros/kern/drivers/net/bnx2x/bnx2x_cmn.h
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   1/* bnx2x_cmn.h: Broadcom Everest network driver.
   2 *
   3 * Copyright (c) 2007-2013 Broadcom Corporation
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation.
   8 *
   9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  10 * Written by: Eliezer Tamir
  11 * Based on code from Michael Chan's bnx2 driver
  12 * UDP CSUM errata workaround by Arik Gendelman
  13 * Slowpath and fastpath rework by Vladislav Zolotarov
  14 * Statistics and Link management by Yitchak Gertner
  15 *
  16 */
  17#pragma once
  18
  19#include <linux_compat.h>
  20
  21#include "bnx2x.h"
  22#include "bnx2x_sriov.h"
  23
  24/* This is used as a replacement for an MCP if it's not present */
  25extern int bnx2x_load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */
  26extern int bnx2x_num_queues;
  27
  28/************************ Macros ********************************/
  29#define BNX2X_PCI_FREE(x, y, size) \
  30        do { \
  31                if (x) { \
  32                        dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
  33                        x = NULL; \
  34                        y = 0; \
  35                } \
  36        } while (0)
  37
  38#define BNX2X_FREE(x) \
  39        do { \
  40                if (x) { \
  41                        kfree((void *)x); \
  42                        x = NULL; \
  43                } \
  44        } while (0)
  45
  46#define BNX2X_PCI_ALLOC(y, size)                                        \
  47({                                                                      \
  48        void *x = dma_zalloc_coherent(&bp->pdev->dev, size, y, MEM_WAIT); \
  49        if (x)                                                          \
  50                DP(NETIF_MSG_HW,                                        \
  51                   "BNX2X_PCI_ALLOC: Physical %p Virtual %p\n", \
  52                   (unsigned long long)(*y), x);                        \
  53        x;                                                              \
  54})
  55#define BNX2X_PCI_FALLOC(y, size)                                       \
  56({                                                                      \
  57        void *x = dma_alloc_coherent(&bp->pdev->dev, size, y, MEM_WAIT); \
  58        if (x) {                                                        \
  59                memset(x, 0xff, size);                                  \
  60                DP(NETIF_MSG_HW,                                        \
  61                   "BNX2X_PCI_FALLOC: Physical %p Virtual %p\n",        \
  62                   (unsigned long long)(*y), x);                        \
  63        }                                                               \
  64        x;                                                              \
  65})
  66
  67/*********************** Interfaces ****************************
  68 *  Functions that need to be implemented by each driver version
  69 */
  70/* Init */
  71
  72/**
  73 * bnx2x_send_unload_req - request unload mode from the MCP.
  74 *
  75 * @bp:                 driver handle
  76 * @unload_mode:        requested function's unload mode
  77 *
  78 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
  79 */
  80uint32_t bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
  81
  82/**
  83 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
  84 *
  85 * @bp:         driver handle
  86 * @keep_link:          true iff link should be kept up
  87 */
  88void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link);
  89
  90/**
  91 * bnx2x_config_rss_pf - configure RSS parameters in a PF.
  92 *
  93 * @bp:                 driver handle
  94 * @rss_obj:            RSS object to use
  95 * @ind_table:          indirection table to configure
  96 * @config_hash:        re-configure RSS hash keys configuration
  97 * @enable:             enabled or disabled configuration
  98 */
  99int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
 100              bool config_hash, bool enable);
 101
 102/**
 103 * bnx2x__init_func_obj - init function object
 104 *
 105 * @bp:                 driver handle
 106 *
 107 * Initializes the Function Object with the appropriate
 108 * parameters which include a function slow path driver
 109 * interface.
 110 */
 111void bnx2x__init_func_obj(struct bnx2x *bp);
 112
 113/**
 114 * bnx2x_setup_queue - setup eth queue.
 115 *
 116 * @bp:         driver handle
 117 * @fp:         pointer to the fastpath structure
 118 * @leading:    boolean
 119 *
 120 */
 121int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
 122                       bool leading);
 123
 124/**
 125 * bnx2x_setup_leading - bring up a leading eth queue.
 126 *
 127 * @bp:         driver handle
 128 */
 129int bnx2x_setup_leading(struct bnx2x *bp);
 130
 131/**
 132 * bnx2x_fw_command - send the MCP a request
 133 *
 134 * @bp:         driver handle
 135 * @command:    request
 136 * @param:      request's parameter
 137 *
 138 * block until there is a reply
 139 */
 140uint32_t bnx2x_fw_command(struct bnx2x *bp, uint32_t command, uint32_t param);
 141
 142/**
 143 * bnx2x_initial_phy_init - initialize link parameters structure variables.
 144 *
 145 * @bp:         driver handle
 146 * @load_mode:  current mode
 147 */
 148int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
 149
 150/**
 151 * bnx2x_link_set - configure hw according to link parameters structure.
 152 *
 153 * @bp:         driver handle
 154 */
 155void bnx2x_link_set(struct bnx2x *bp);
 156
 157/**
 158 * bnx2x_force_link_reset - Forces link reset, and put the PHY
 159 * in reset as well.
 160 *
 161 * @bp:         driver handle
 162 */
 163void bnx2x_force_link_reset(struct bnx2x *bp);
 164
 165/**
 166 * bnx2x_link_test - query link status.
 167 *
 168 * @bp:         driver handle
 169 * @is_serdes:  bool
 170 *
 171 * Returns 0 if link is UP.
 172 */
 173uint8_t bnx2x_link_test(struct bnx2x *bp, uint8_t is_serdes);
 174
 175/**
 176 * bnx2x_drv_pulse - write driver pulse to shmem
 177 *
 178 * @bp:         driver handle
 179 *
 180 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox
 181 * in the shmem.
 182 */
 183void bnx2x_drv_pulse(struct bnx2x *bp);
 184
 185/**
 186 * bnx2x_igu_ack_sb - update IGU with current SB value
 187 *
 188 * @bp:         driver handle
 189 * @igu_sb_id:  SB id
 190 * @segment:    SB segment
 191 * @index:      SB index
 192 * @op:         SB operation
 193 * @update:     is HW update required
 194 */
 195void bnx2x_igu_ack_sb(struct bnx2x *bp, uint8_t igu_sb_id, uint8_t segment,
 196                      uint16_t index, uint8_t op, uint8_t update);
 197
 198/* Disable transactions from chip to host */
 199void bnx2x_pf_disable(struct bnx2x *bp);
 200int bnx2x_pretend_func(struct bnx2x *bp, uint16_t pretend_func_val);
 201
 202/**
 203 * bnx2x__link_status_update - handles link status change.
 204 *
 205 * @bp:         driver handle
 206 */
 207void bnx2x__link_status_update(struct bnx2x *bp);
 208
 209/**
 210 * bnx2x_link_report - report link status to upper layer.
 211 *
 212 * @bp:         driver handle
 213 */
 214void bnx2x_link_report(struct bnx2x *bp);
 215
 216/* None-atomic version of bnx2x_link_report() */
 217void __bnx2x_link_report(struct bnx2x *bp);
 218
 219/**
 220 * bnx2x_get_mf_speed - calculate MF speed.
 221 *
 222 * @bp:         driver handle
 223 *
 224 * Takes into account current linespeed and MF configuration.
 225 */
 226uint16_t bnx2x_get_mf_speed(struct bnx2x *bp);
 227
 228/**
 229 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler
 230 *
 231 * @irq:                irq number
 232 * @dev_instance:       private instance
 233 */
 234void bnx2x_msix_sp_int(struct hw_trapframe *hw_tf, void *dev_instance);
 235
 236/**
 237 * bnx2x_interrupt - non MSI-X interrupt handler
 238 *
 239 * @irq:                irq number
 240 * @dev_instance:       private instance
 241 */
 242void bnx2x_interrupt(struct hw_trapframe *hw_tf, void *dev_instance);
 243
 244/**
 245 * bnx2x_cnic_notify - send command to cnic driver
 246 *
 247 * @bp:         driver handle
 248 * @cmd:        command
 249 */
 250int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
 251
 252/**
 253 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information
 254 *
 255 * @bp:         driver handle
 256 */
 257void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
 258
 259/**
 260 * bnx2x_setup_cnic_info - provides cnic with updated info
 261 *
 262 * @bp:         driver handle
 263 */
 264void bnx2x_setup_cnic_info(struct bnx2x *bp);
 265
 266/**
 267 * bnx2x_int_enable - enable HW interrupts.
 268 *
 269 * @bp:         driver handle
 270 */
 271void bnx2x_int_enable(struct bnx2x *bp);
 272
 273/**
 274 * bnx2x_int_disable_sync - disable interrupts.
 275 *
 276 * @bp:         driver handle
 277 * @disable_hw: true, disable HW interrupts.
 278 *
 279 * This function ensures that there are no
 280 * ISRs or SP DPCs (sp_task) are running after it returns.
 281 */
 282void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
 283
 284/**
 285 * bnx2x_nic_init_cnic - init driver internals for cnic.
 286 *
 287 * @bp:         driver handle
 288 * @load_code:  COMMON, PORT or FUNCTION
 289 *
 290 * Initializes:
 291 *  - rings
 292 *  - status blocks
 293 *  - etc.
 294 */
 295void bnx2x_nic_init_cnic(struct bnx2x *bp);
 296
 297/**
 298 * bnx2x_preirq_nic_init - init driver internals.
 299 *
 300 * @bp:         driver handle
 301 *
 302 * Initializes:
 303 *  - fastpath object
 304 *  - fastpath rings
 305 *  etc.
 306 */
 307void bnx2x_pre_irq_nic_init(struct bnx2x *bp);
 308
 309/**
 310 * bnx2x_postirq_nic_init - init driver internals.
 311 *
 312 * @bp:         driver handle
 313 * @load_code:  COMMON, PORT or FUNCTION
 314 *
 315 * Initializes:
 316 *  - status blocks
 317 *  - slowpath rings
 318 *  - etc.
 319 */
 320void bnx2x_post_irq_nic_init(struct bnx2x *bp, uint32_t load_code);
 321/**
 322 * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic.
 323 *
 324 * @bp:         driver handle
 325 */
 326int bnx2x_alloc_mem_cnic(struct bnx2x *bp);
 327/**
 328 * bnx2x_alloc_mem - allocate driver's memory.
 329 *
 330 * @bp:         driver handle
 331 */
 332int bnx2x_alloc_mem(struct bnx2x *bp);
 333
 334/**
 335 * bnx2x_free_mem_cnic - release driver's memory for cnic.
 336 *
 337 * @bp:         driver handle
 338 */
 339void bnx2x_free_mem_cnic(struct bnx2x *bp);
 340/**
 341 * bnx2x_free_mem - release driver's memory.
 342 *
 343 * @bp:         driver handle
 344 */
 345void bnx2x_free_mem(struct bnx2x *bp);
 346
 347/**
 348 * bnx2x_set_num_queues - set number of queues according to mode.
 349 *
 350 * @bp:         driver handle
 351 */
 352void bnx2x_set_num_queues(struct bnx2x *bp);
 353
 354/**
 355 * bnx2x_chip_cleanup - cleanup chip internals.
 356 *
 357 * @bp:                 driver handle
 358 * @unload_mode:        COMMON, PORT, FUNCTION
 359 * @keep_link:          true iff link should be kept up.
 360 *
 361 * - Cleanup MAC configuration.
 362 * - Closes clients.
 363 * - etc.
 364 */
 365void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link);
 366
 367/**
 368 * bnx2x_acquire_hw_lock - acquire HW lock.
 369 *
 370 * @bp:         driver handle
 371 * @resource:   resource bit which was locked
 372 */
 373int bnx2x_acquire_hw_lock(struct bnx2x *bp, uint32_t resource);
 374
 375/**
 376 * bnx2x_release_hw_lock - release HW lock.
 377 *
 378 * @bp:         driver handle
 379 * @resource:   resource bit which was locked
 380 */
 381int bnx2x_release_hw_lock(struct bnx2x *bp, uint32_t resource);
 382
 383/**
 384 * bnx2x_release_leader_lock - release recovery leader lock
 385 *
 386 * @bp:         driver handle
 387 */
 388int bnx2x_release_leader_lock(struct bnx2x *bp);
 389
 390/**
 391 * bnx2x_set_eth_mac - configure eth MAC address in the HW
 392 *
 393 * @bp:         driver handle
 394 * @set:        set or clear
 395 *
 396 * Configures according to the value in netdev->dev_addr.
 397 */
 398int bnx2x_set_eth_mac(struct bnx2x *bp, bool set);
 399
 400/**
 401 * bnx2x_set_rx_mode - set MAC filtering configurations.
 402 *
 403 * @dev:        netdevice
 404 *
 405 * called with netif_tx_lock from dev_mcast.c
 406 * If bp->state is OPEN, should be called with
 407 * netif_addr_lock_bh()
 408 */
 409void bnx2x_set_rx_mode_inner(struct bnx2x *bp);
 410
 411/* Parity errors related */
 412void bnx2x_set_pf_load(struct bnx2x *bp);
 413bool bnx2x_clear_pf_load(struct bnx2x *bp);
 414bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print);
 415bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
 416void bnx2x_set_reset_in_progress(struct bnx2x *bp);
 417void bnx2x_set_reset_global(struct bnx2x *bp);
 418void bnx2x_disable_close_the_gate(struct bnx2x *bp);
 419int bnx2x_init_hw_func_cnic(struct bnx2x *bp);
 420
 421/**
 422 * bnx2x_sp_event - handle ramrods completion.
 423 *
 424 * @fp:         fastpath handle for the event
 425 * @rr_cqe:     eth_rx_cqe
 426 */
 427void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
 428
 429/**
 430 * bnx2x_ilt_set_info - prepare ILT configurations.
 431 *
 432 * @bp:         driver handle
 433 */
 434void bnx2x_ilt_set_info(struct bnx2x *bp);
 435
 436/**
 437 * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC
 438 * and TM.
 439 *
 440 * @bp:         driver handle
 441 */
 442void bnx2x_ilt_set_info_cnic(struct bnx2x *bp);
 443
 444/**
 445 * bnx2x_dcbx_init - initialize dcbx protocol.
 446 *
 447 * @bp:         driver handle
 448 */
 449void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem);
 450
 451/**
 452 * bnx2x_set_power_state - set power state to the requested value.
 453 *
 454 * @bp:         driver handle
 455 * @state:      required state D0 or D3hot
 456 *
 457 * Currently only D0 and D3hot are supported.
 458 */
 459//int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
 460#define bnx2x_set_power_state(...)
 461
 462/**
 463 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW.
 464 *
 465 * @bp:         driver handle
 466 * @value:      new value
 467 */
 468void bnx2x_update_max_mf_config(struct bnx2x *bp, uint32_t value);
 469/* Error handling */
 470void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl);
 471
 472/* dev_close main block */
 473int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link);
 474
 475/* dev_open main block */
 476int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
 477
 478/* setup_tc callback */
 479int bnx2x_setup_tc(struct ether *dev, uint8_t num_tc);
 480
 481int bnx2x_get_vf_config(struct ether *dev, int vf,
 482                        struct ifla_vf_info *ivi);
 483int bnx2x_set_vf_mac(struct ether *dev, int queue, uint8_t *mac);
 484int bnx2x_set_vf_vlan(struct ether *netdev, int vf, uint16_t vlan,
 485                      uint8_t qos);
 486
 487/* select_queue callback */
 488uint16_t bnx2x_select_queue(struct ether *dev, struct sk_buff *skb,
 489                       void *accel_priv, select_queue_fallback_t fallback);
 490
 491static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
 492                                        struct bnx2x_fastpath *fp,
 493                                        uint16_t bd_prod,
 494                                        uint16_t rx_comp_prod,
 495                                        uint16_t rx_sge_prod)
 496{
 497        struct ustorm_eth_rx_producers rx_prods = {0};
 498        uint32_t i;
 499
 500        /* Update producers */
 501        rx_prods.bd_prod = bd_prod;
 502        rx_prods.cqe_prod = rx_comp_prod;
 503        rx_prods.sge_prod = rx_sge_prod;
 504
 505        /* Make sure that the BD and SGE data is updated before updating the
 506         * producers since FW might read the BD/SGE right after the producer
 507         * is updated.
 508         * This is only applicable for weak-ordered memory model archs such
 509         * as IA-64. The following barrier is also mandatory since FW will
 510         * assumes BDs must have buffers.
 511         */
 512        wmb();
 513
 514        for (i = 0; i < sizeof(rx_prods)/4; i++)
 515                REG_WR(bp, fp->ustorm_rx_prods_offset + i*4,
 516                       ((uint32_t *)&rx_prods)[i]);
 517
 518        bus_wmb(); /* keep prod updates ordered */
 519
 520        DP(NETIF_MSG_RX_STATUS,
 521           "queue[%d]:  wrote  bd_prod %u  cqe_prod %u  sge_prod %u\n",
 522           fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
 523}
 524
 525/* reload helper */
 526int bnx2x_reload_if_running(struct ether *dev);
 527
 528int bnx2x_change_mac_addr(struct ether *dev, void *p);
 529
 530/* NAPI poll Tx part */
 531int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata);
 532
 533/* suspend/resume callbacks */
 534int bnx2x_suspend(struct pci_device *pdev, pm_message_t state);
 535int bnx2x_resume(struct pci_device *pdev);
 536
 537/* Release IRQ vectors */
 538void bnx2x_free_irq(struct bnx2x *bp);
 539
 540void bnx2x_free_fp_mem(struct bnx2x *bp);
 541void bnx2x_init_rx_rings(struct bnx2x *bp);
 542void bnx2x_init_rx_rings_cnic(struct bnx2x *bp);
 543void bnx2x_free_skbs(struct bnx2x *bp);
 544void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
 545void bnx2x_netif_start(struct bnx2x *bp);
 546int bnx2x_load_cnic(struct bnx2x *bp);
 547
 548/**
 549 * bnx2x_enable_msix - set msix configuration.
 550 *
 551 * @bp:         driver handle
 552 *
 553 * fills msix_table, requests vectors, updates num_queues
 554 * according to number of available vectors.
 555 */
 556int bnx2x_enable_msix(struct bnx2x *bp);
 557
 558/**
 559 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly
 560 *
 561 * @bp:         driver handle
 562 */
 563int bnx2x_enable_msi(struct bnx2x *bp);
 564
 565/**
 566 * bnx2x_low_latency_recv - LL callback
 567 *
 568 * @napi:       napi structure
 569 */
 570int bnx2x_low_latency_recv(struct napi_struct *napi);
 571
 572/**
 573 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure
 574 *
 575 * @bp:         driver handle
 576 */
 577int bnx2x_alloc_mem_bp(struct bnx2x *bp);
 578
 579/**
 580 * bnx2x_free_mem_bp - release memories outsize main driver structure
 581 *
 582 * @bp:         driver handle
 583 */
 584void bnx2x_free_mem_bp(struct bnx2x *bp);
 585
 586/**
 587 * bnx2x_change_mtu - change mtu netdev callback
 588 *
 589 * @dev:        net device
 590 * @new_mtu:    requested mtu
 591 *
 592 */
 593int bnx2x_change_mtu(struct ether *dev, int new_mtu);
 594
 595#ifdef NETDEV_FCOE_WWNN
 596/**
 597 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port
 598 *
 599 * @dev:        net_device
 600 * @wwn:        output buffer
 601 * @type:       WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port)
 602 *
 603 */
 604int bnx2x_fcoe_get_wwn(struct ether *dev, uint64_t *wwn, int type);
 605#endif
 606
 607netdev_features_t bnx2x_fix_features(struct ether *dev,
 608                                     netdev_features_t features);
 609int bnx2x_set_features(struct ether *dev, netdev_features_t features);
 610
 611/**
 612 * bnx2x_tx_timeout - tx timeout netdev callback
 613 *
 614 * @dev:        net device
 615 */
 616void bnx2x_tx_timeout(struct ether *dev);
 617
 618/*********************** Inlines **********************************/
 619/*********************** Fast path ********************************/
 620static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
 621{
 622        cmb(); /* status block is written to by the chip */
 623        fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
 624}
 625
 626static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, uint8_t igu_sb_id,
 627                                        uint8_t segment, uint16_t index,
 628                                        uint8_t op,
 629                                        uint8_t update, uint32_t igu_addr)
 630{
 631        struct igu_regular cmd_data = {0};
 632
 633        cmd_data.sb_id_and_flags =
 634                        ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
 635                         (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
 636                         (update << IGU_REGULAR_BUPDATE_SHIFT) |
 637                         (op << IGU_REGULAR_ENABLE_INT_SHIFT));
 638
 639        DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
 640           cmd_data.sb_id_and_flags, igu_addr);
 641        REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
 642
 643        /* Make sure that ACK is written */
 644        bus_wmb();
 645        cmb();
 646}
 647
 648static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, uint8_t sb_id,
 649                                   uint8_t storm, uint16_t index, uint8_t op,
 650                                   uint8_t update)
 651{
 652        uint32_t hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
 653                       COMMAND_REG_INT_ACK);
 654        struct igu_ack_register igu_ack;
 655
 656        igu_ack.status_block_index = index;
 657        igu_ack.sb_id_and_flags =
 658                        ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
 659                         (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
 660                         (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
 661                         (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
 662
 663        REG_WR(bp, hc_addr, (*(uint32_t *)&igu_ack));
 664
 665        /* Make sure that ACK is written */
 666        bus_wmb();
 667        cmb();
 668}
 669
 670static inline void bnx2x_ack_sb(struct bnx2x *bp, uint8_t igu_sb_id,
 671                                uint8_t storm,
 672                                uint16_t index, uint8_t op, uint8_t update)
 673{
 674        if (bp->common.int_block == INT_BLOCK_HC)
 675                bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
 676        else {
 677                uint8_t segment;
 678
 679                if (CHIP_INT_MODE_IS_BC(bp))
 680                        segment = storm;
 681                else if (igu_sb_id != bp->igu_dsb_id)
 682                        segment = IGU_SEG_ACCESS_DEF;
 683                else if (storm == ATTENTION_ID)
 684                        segment = IGU_SEG_ACCESS_ATTN;
 685                else
 686                        segment = IGU_SEG_ACCESS_DEF;
 687                bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
 688        }
 689}
 690
 691static inline uint16_t bnx2x_hc_ack_int(struct bnx2x *bp)
 692{
 693        uint32_t hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
 694                       COMMAND_REG_SIMD_MASK);
 695        uint32_t result = REG_RD(bp, hc_addr);
 696
 697        cmb();
 698        return result;
 699}
 700
 701static inline uint16_t bnx2x_igu_ack_int(struct bnx2x *bp)
 702{
 703        uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
 704        uint32_t result = REG_RD(bp, igu_addr);
 705
 706        DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
 707           result, igu_addr);
 708
 709        cmb();
 710        return result;
 711}
 712
 713static inline uint16_t bnx2x_ack_int(struct bnx2x *bp)
 714{
 715        cmb();
 716        if (bp->common.int_block == INT_BLOCK_HC)
 717                return bnx2x_hc_ack_int(bp);
 718        else
 719                return bnx2x_igu_ack_int(bp);
 720}
 721
 722static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata)
 723{
 724        /* Tell compiler that consumer and producer can change */
 725        cmb();
 726        return txdata->tx_pkt_prod != txdata->tx_pkt_cons;
 727}
 728
 729static inline uint16_t bnx2x_tx_avail(struct bnx2x *bp,
 730                                 struct bnx2x_fp_txdata *txdata)
 731{
 732        int16_t used;
 733        uint16_t prod;
 734        uint16_t cons;
 735
 736        prod = txdata->tx_bd_prod;
 737        cons = txdata->tx_bd_cons;
 738
 739        used = SUB_S16(prod, cons);
 740
 741#ifdef BNX2X_STOP_ON_ERROR
 742        warn_on(used < 0);
 743        warn_on(used > txdata->tx_ring_size);
 744        warn_on((txdata->tx_ring_size - used) > MAX_TX_AVAIL);
 745#endif
 746
 747        return (int16_t)(txdata->tx_ring_size) - used;
 748}
 749
 750static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata)
 751{
 752        uint16_t hw_cons;
 753
 754        /* Tell compiler that status block fields can change */
 755        cmb();
 756        hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
 757        return hw_cons != txdata->tx_pkt_cons;
 758}
 759
 760static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
 761{
 762        uint8_t cos;
 763        for_each_cos_in_tx_queue(fp, cos)
 764                if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
 765                        return true;
 766        return false;
 767}
 768
 769#define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0)
 770#define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF)
 771static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
 772{
 773        uint16_t cons;
 774        union eth_rx_cqe *cqe;
 775        struct eth_fast_path_rx_cqe *cqe_fp;
 776
 777        cons = RCQ_BD(fp->rx_comp_cons);
 778        cqe = &fp->rx_comp_ring[cons];
 779        cqe_fp = &cqe->fast_path_cqe;
 780        return BNX2X_IS_CQE_COMPLETED(cqe_fp);
 781}
 782
 783/**
 784 * bnx2x_tx_disable - disables tx from stack point of view
 785 *
 786 * @bp:         driver handle
 787 */
 788static inline void bnx2x_tx_disable(struct bnx2x *bp)
 789{
 790panic("Not implemented");
 791#if 0 // AKAROS_PORT
 792        netif_tx_disable(bp->dev);
 793        netif_carrier_off(bp->dev);
 794#endif
 795}
 796
 797static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
 798                                     struct bnx2x_fastpath *fp,
 799                                     uint16_t index)
 800{
 801        struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
 802        struct page *page = sw_buf->page;
 803        struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
 804
 805        /* Skip "next page" elements */
 806        if (!page)
 807                return;
 808
 809        dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
 810                       SGE_PAGES, DMA_FROM_DEVICE);
 811        free_cont_pages(page2kva(page), PAGES_PER_SGE_SHIFT);
 812
 813        sw_buf->page = NULL;
 814        sge->addr_hi = 0;
 815        sge->addr_lo = 0;
 816}
 817
 818static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp)
 819{
 820panic("Not implemented");
 821#if 0 // AKAROS_PORT
 822        int i;
 823
 824        for_each_rx_queue_cnic(bp, i) {
 825                napi_hash_del(&bnx2x_fp(bp, i, napi));
 826                netif_napi_del(&bnx2x_fp(bp, i, napi));
 827        }
 828#endif
 829}
 830
 831static inline void bnx2x_del_all_napi(struct bnx2x *bp)
 832{
 833panic("Not implemented");
 834#if 0 // AKAROS_PORT
 835        int i;
 836
 837        for_each_eth_queue(bp, i) {
 838                napi_hash_del(&bnx2x_fp(bp, i, napi));
 839                netif_napi_del(&bnx2x_fp(bp, i, napi));
 840        }
 841#endif
 842}
 843
 844int bnx2x_set_int_mode(struct bnx2x *bp);
 845
 846static inline void bnx2x_disable_msi(struct bnx2x *bp)
 847{
 848panic("Not implemented");
 849#if 0 // AKAROS_PORT
 850        if (bp->flags & USING_MSIX_FLAG) {
 851                pci_disable_msix(bp->pdev);
 852                bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG);
 853        } else if (bp->flags & USING_MSI_FLAG) {
 854                pci_disable_msi(bp->pdev);
 855                bp->flags &= ~USING_MSI_FLAG;
 856        }
 857#endif
 858}
 859
 860static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
 861{
 862        int i, j;
 863
 864        for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
 865                int idx = RX_SGE_CNT * i - 1;
 866
 867                for (j = 0; j < 2; j++) {
 868                        BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
 869                        idx--;
 870                }
 871        }
 872}
 873
 874static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
 875{
 876        /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
 877        memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
 878
 879        /* Clear the two last indices in the page to 1:
 880           these are the indices that correspond to the "next" element,
 881           hence will never be indicated and should be removed from
 882           the calculations. */
 883        bnx2x_clear_sge_mask_next_elems(fp);
 884}
 885
 886/* note that we are not allocating a new buffer,
 887 * we are just moving one from cons to prod
 888 * we are not creating a new mapping,
 889 * so there is no need to check for dma_mapping_error().
 890 */
 891static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp,
 892                                      uint16_t cons, uint16_t prod)
 893{
 894        struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
 895        struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
 896        struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
 897        struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
 898
 899        dma_unmap_addr_set(prod_rx_buf, mapping,
 900                           dma_unmap_addr(cons_rx_buf, mapping));
 901        prod_rx_buf->data = cons_rx_buf->data;
 902        *prod_bd = *cons_bd;
 903}
 904
 905/************************* Init ******************************************/
 906
 907/* returns func by VN for current port */
 908static inline int func_by_vn(struct bnx2x *bp, int vn)
 909{
 910        return 2 * vn + BP_PORT(bp);
 911}
 912
 913static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash)
 914{
 915        return bnx2x_rss(bp, &bp->rss_conf_obj, config_hash, true);
 916}
 917
 918/**
 919 * bnx2x_func_start - init function
 920 *
 921 * @bp:         driver handle
 922 *
 923 * Must be called before sending CLIENT_SETUP for the first client.
 924 */
 925static inline int bnx2x_func_start(struct bnx2x *bp)
 926{
 927        struct bnx2x_func_state_params func_params = {NULL};
 928        struct bnx2x_func_start_params *start_params =
 929                &func_params.params.start;
 930
 931        /* Prepare parameters for function state transitions */
 932        __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
 933
 934        func_params.f_obj = &bp->func_obj;
 935        func_params.cmd = BNX2X_F_CMD_START;
 936
 937        /* Function parameters */
 938        start_params->mf_mode = bp->mf_mode;
 939        start_params->sd_vlan_tag = bp->mf_ov;
 940
 941        if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
 942                start_params->network_cos_mode = STATIC_COS;
 943        else /* CHIP_IS_E1X */
 944                start_params->network_cos_mode = FW_WRR;
 945
 946        start_params->tunnel_mode       = TUNN_MODE_GRE;
 947        start_params->gre_tunnel_type   = IPGRE_TUNNEL;
 948        start_params->inner_gre_rss_en  = 1;
 949
 950        if (IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
 951                start_params->class_fail_ethtype = ETH_P_FIP;
 952                start_params->class_fail = 1;
 953                start_params->no_added_tags = 1;
 954        }
 955
 956        return bnx2x_func_state_change(bp, &func_params);
 957}
 958
 959/**
 960 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format
 961 *
 962 * @fw_hi:      pointer to upper part
 963 * @fw_mid:     pointer to middle part
 964 * @fw_lo:      pointer to lower part
 965 * @mac:        pointer to MAC address
 966 */
 967static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid,
 968                                         __le16 *fw_lo, uint8_t *mac)
 969{
 970        ((uint8_t *)fw_hi)[0]  = mac[1];
 971        ((uint8_t *)fw_hi)[1]  = mac[0];
 972        ((uint8_t *)fw_mid)[0] = mac[3];
 973        ((uint8_t *)fw_mid)[1] = mac[2];
 974        ((uint8_t *)fw_lo)[0]  = mac[5];
 975        ((uint8_t *)fw_lo)[1]  = mac[4];
 976}
 977
 978static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
 979                                           struct bnx2x_fastpath *fp, int last)
 980{
 981        int i;
 982
 983        if (fp->disable_tpa)
 984                return;
 985
 986        for (i = 0; i < last; i++)
 987                bnx2x_free_rx_sge(bp, fp, i);
 988}
 989
 990static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
 991{
 992        int i;
 993
 994        for (i = 1; i <= NUM_RX_RINGS; i++) {
 995                struct eth_rx_bd *rx_bd;
 996
 997                rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
 998                rx_bd->addr_hi =
 999                        cpu_to_le32(U64_HI(fp->rx_desc_mapping +
1000                                    BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1001                rx_bd->addr_lo =
1002                        cpu_to_le32(U64_LO(fp->rx_desc_mapping +
1003                                    BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1004        }
1005}
1006
1007/* Statistics ID are global per chip/path, while Client IDs for E1x are per
1008 * port.
1009 */
1010static inline uint8_t bnx2x_stats_id(struct bnx2x_fastpath *fp)
1011{
1012        struct bnx2x *bp = fp->bp;
1013        if (!CHIP_IS_E1x(bp)) {
1014                /* there are special statistics counters for FCoE 136..140 */
1015                if (IS_FCOE_FP(fp))
1016                        return bp->cnic_base_cl_id + (bp->pf_num >> 1);
1017                return fp->cl_id;
1018        }
1019        return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x;
1020}
1021
1022static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp,
1023                                               bnx2x_obj_type obj_type)
1024{
1025        struct bnx2x *bp = fp->bp;
1026
1027        /* Configure classification DBs */
1028        bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id,
1029                           fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata),
1030                           bnx2x_sp_mapping(bp, mac_rdata),
1031                           BNX2X_FILTER_MAC_PENDING,
1032                           &bp->sp_state, obj_type,
1033                           &bp->macs_pool);
1034}
1035
1036/**
1037 * bnx2x_get_path_func_num - get number of active functions
1038 *
1039 * @bp:         driver handle
1040 *
1041 * Calculates the number of active (not hidden) functions on the
1042 * current path.
1043 */
1044static inline uint8_t bnx2x_get_path_func_num(struct bnx2x *bp)
1045{
1046        uint8_t func_num = 0, i;
1047
1048        /* 57710 has only one function per-port */
1049        if (CHIP_IS_E1(bp))
1050                return 1;
1051
1052        /* Calculate a number of functions enabled on the current
1053         * PATH/PORT.
1054         */
1055        if (CHIP_REV_IS_SLOW(bp)) {
1056                if (IS_MF(bp))
1057                        func_num = 4;
1058                else
1059                        func_num = 2;
1060        } else {
1061                for (i = 0; i < E1H_FUNC_MAX / 2; i++) {
1062                        uint32_t func_config =
1063                                MF_CFG_RD(bp,
1064                                          func_mf_config[BP_PORT(bp) + 2 * i].
1065                                          config);
1066                        func_num +=
1067                                ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1);
1068                }
1069        }
1070
1071        warn_on(!func_num);
1072
1073        return func_num;
1074}
1075
1076static inline void bnx2x_init_bp_objs(struct bnx2x *bp)
1077{
1078        /* RX_MODE controlling object */
1079        bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj);
1080
1081        /* multicast configuration controlling object */
1082        bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid,
1083                             BP_FUNC(bp), BP_FUNC(bp),
1084                             bnx2x_sp(bp, mcast_rdata),
1085                             bnx2x_sp_mapping(bp, mcast_rdata),
1086                             BNX2X_FILTER_MCAST_PENDING, &bp->sp_state,
1087                             BNX2X_OBJ_TYPE_RX);
1088
1089        /* Setup CAM credit pools */
1090        bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp),
1091                                   bnx2x_get_path_func_num(bp));
1092
1093        bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1,
1094                                    bnx2x_get_path_func_num(bp));
1095
1096        /* RSS configuration object */
1097        bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id,
1098                                  bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp),
1099                                  bnx2x_sp(bp, rss_rdata),
1100                                  bnx2x_sp_mapping(bp, rss_rdata),
1101                                  BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state,
1102                                  BNX2X_OBJ_TYPE_RX);
1103}
1104
1105static inline uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
1106{
1107        if (CHIP_IS_E1x(fp->bp))
1108                return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H;
1109        else
1110                return fp->cl_id;
1111}
1112
1113static inline void bnx2x_init_txdata(struct bnx2x *bp,
1114                                     struct bnx2x_fp_txdata *txdata,
1115                                     uint32_t cid,
1116                                     int txq_index, __le16 *tx_cons_sb,
1117                                     struct bnx2x_fastpath *fp)
1118{
1119        txdata->cid = cid;
1120        txdata->txq_index = txq_index;
1121        txdata->tx_cons_sb = tx_cons_sb;
1122        txdata->parent_fp = fp;
1123        txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size;
1124
1125        /* Poke function - ghetto extern from bnx2x_dev.c */
1126        extern void __bnx2x_tx_queue(void *txdata_arg);
1127        poke_init(&txdata->poker, __bnx2x_tx_queue);
1128        /* TODO: AKAROS_PORT multi queue: assign proper oq */
1129        txdata->oq = bp->edev->oq;
1130
1131        DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n",
1132           txdata->cid, txdata->txq_index);
1133}
1134
1135static inline uint8_t bnx2x_cnic_eth_cl_id(struct bnx2x *bp, uint8_t cl_idx)
1136{
1137        return bp->cnic_base_cl_id + cl_idx +
1138                (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX;
1139}
1140
1141static inline uint8_t bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
1142{
1143        /* the 'first' id is allocated for the cnic */
1144        return bp->base_fw_ndsb;
1145}
1146
1147static inline uint8_t bnx2x_cnic_igu_sb_id(struct bnx2x *bp)
1148{
1149        return bp->igu_base_sb;
1150}
1151
1152static inline int bnx2x_clean_tx_queue(struct bnx2x *bp,
1153                                       struct bnx2x_fp_txdata *txdata)
1154{
1155        int cnt = 1000;
1156
1157        while (bnx2x_has_tx_work_unload(txdata)) {
1158                if (!cnt) {
1159                        BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
1160                                  txdata->txq_index, txdata->tx_pkt_prod,
1161                                  txdata->tx_pkt_cons);
1162#ifdef BNX2X_STOP_ON_ERROR
1163                        bnx2x_panic();
1164                        return -EBUSY;
1165#else
1166                        break;
1167#endif
1168                }
1169                cnt--;
1170                kthread_usleep(1000);
1171        }
1172
1173        return 0;
1174}
1175
1176int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1177
1178static inline void __storm_memset_struct(struct bnx2x *bp,
1179                                         uint32_t addr, size_t size,
1180                                         uint32_t *data)
1181{
1182        int i;
1183        for (i = 0; i < size/4; i++)
1184                REG_WR(bp, addr + (i * 4), data[i]);
1185}
1186
1187/**
1188 * bnx2x_wait_sp_comp - wait for the outstanding SP commands.
1189 *
1190 * @bp:         driver handle
1191 * @mask:       bits that need to be cleared
1192 */
1193static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask)
1194{
1195        int tout = 5000; /* Wait for 5 secs tops */
1196
1197        while (tout--) {
1198                mb();
1199                qlock(&bp->dev->qlock);
1200                if (!(bp->sp_state & mask)) {
1201                        qunlock(&bp->dev->qlock);
1202                        return true;
1203                }
1204                qunlock(&bp->dev->qlock);
1205
1206                kthread_usleep(1000);
1207        }
1208
1209        mb();
1210
1211        qlock(&bp->dev->qlock);
1212        if (bp->sp_state & mask) {
1213                BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n",
1214                          bp->sp_state, mask);
1215                qunlock(&bp->dev->qlock);
1216                return false;
1217        }
1218        qunlock(&bp->dev->qlock);
1219
1220        return true;
1221}
1222
1223/**
1224 * bnx2x_set_ctx_validation - set CDU context validation values
1225 *
1226 * @bp:         driver handle
1227 * @cxt:        context of the connection on the host memory
1228 * @cid:        SW CID of the connection to be configured
1229 */
1230void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
1231                              uint32_t cid);
1232
1233void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, uint8_t fw_sb_id,
1234                                    uint8_t sb_index, uint8_t disable,
1235                                    uint16_t usec);
1236void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1237void bnx2x_release_phy_lock(struct bnx2x *bp);
1238
1239/**
1240 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration.
1241 *
1242 * @bp:         driver handle
1243 * @mf_cfg:     MF configuration
1244 *
1245 */
1246static inline uint16_t bnx2x_extract_max_cfg(struct bnx2x *bp,
1247                                             uint32_t mf_cfg)
1248{
1249        uint16_t max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1250                              FUNC_MF_CFG_MAX_BW_SHIFT;
1251        if (!max_cfg) {
1252                DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL,
1253                   "Max BW configured to 0 - using 100 instead\n");
1254                max_cfg = 100;
1255        }
1256        return max_cfg;
1257}
1258
1259/* checks if HW supports GRO for given MTU */
1260static inline bool bnx2x_mtu_allows_gro(int mtu)
1261{
1262panic("Not implemented");
1263#if 0 // AKAROS_PORT
1264        /* gro frags per page */
1265        int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE);
1266
1267        /*
1268         * 1. Number of frags should not grow above MAX_SKB_FRAGS
1269         * 2. Frag must fit the page
1270         */
1271        return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS;
1272#endif
1273}
1274
1275/**
1276 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info.
1277 *
1278 * @bp:         driver handle
1279 *
1280 */
1281void bnx2x_get_iscsi_info(struct bnx2x *bp);
1282
1283/**
1284 * bnx2x_link_sync_notify - send notification to other functions.
1285 *
1286 * @bp:         driver handle
1287 *
1288 */
1289static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
1290{
1291        int func;
1292        int vn;
1293
1294        /* Set the attention towards other drivers on the same port */
1295        for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
1296                if (vn == BP_VN(bp))
1297                        continue;
1298
1299                func = func_by_vn(bp, vn);
1300                REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
1301                       (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
1302        }
1303}
1304
1305/**
1306 * bnx2x_update_drv_flags - update flags in shmem
1307 *
1308 * @bp:         driver handle
1309 * @flags:      flags to update
1310 * @set:        set or clear
1311 *
1312 */
1313static inline void bnx2x_update_drv_flags(struct bnx2x *bp, uint32_t flags,
1314                                          uint32_t set)
1315{
1316        if (SHMEM2_HAS(bp, drv_flags)) {
1317                uint32_t drv_flags;
1318                bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1319                drv_flags = SHMEM2_RD(bp, drv_flags);
1320
1321                if (set)
1322                        SET_FLAGS(drv_flags, flags);
1323                else
1324                        RESET_FLAGS(drv_flags, flags);
1325
1326                SHMEM2_WR(bp, drv_flags, drv_flags);
1327                DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags);
1328                bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1329        }
1330}
1331
1332
1333
1334/**
1335 * bnx2x_fill_fw_str - Fill buffer with FW version string
1336 *
1337 * @bp:        driver handle
1338 * @buf:       character buffer to fill with the fw name
1339 * @buf_len:   length of the above buffer
1340 *
1341 */
1342void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len);
1343
1344int bnx2x_drain_tx_queues(struct bnx2x *bp);
1345void bnx2x_squeeze_objects(struct bnx2x *bp);
1346
1347void bnx2x_schedule_sp_rtnl(struct bnx2x*, enum sp_rtnl_flag,
1348                            uint32_t verbose);
1349