akaros/kern/drivers/net/bnx2x/bnx2x.h
<<
>>
Prefs
   1/* bnx2x.h: Broadcom Everest network driver.
   2 *
   3 * Copyright (c) 2007-2013 Broadcom Corporation
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation.
   8 *
   9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  10 * Written by: Eliezer Tamir
  11 * Based on code from Michael Chan's bnx2 driver
  12 */
  13
  14#pragma once
  15
  16/* compilation time flags */
  17
  18/* define this to make the driver freeze on error to allow getting debug info
  19 * (you will need to reboot afterwards) */
  20/* #define BNX2X_STOP_ON_ERROR */
  21
  22#define DRV_MODULE_VERSION      "1.710.51-0"
  23#define DRV_MODULE_RELDATE      "2014/02/10"
  24#define BNX2X_BC_VER            0x040200
  25
  26#if defined(CONFIG_DCB)
  27#define BCM_DCBNL
  28#endif
  29
  30#include <linux_compat.h>
  31
  32#include "bnx2x_hsi.h"
  33#include "cnic_if.h"
  34
  35#define BNX2X_MIN_MSIX_VEC_CNT(bp)              ((bp)->min_msix_vec_cnt)
  36
  37#include "bnx2x_reg.h"
  38#include "bnx2x_fw_defs.h"
  39#include "bnx2x_mfw_req.h"
  40#include "bnx2x_link.h"
  41#include "bnx2x_sp.h"
  42#include "bnx2x_dcb.h"
  43#include "bnx2x_stats.h"
  44#include "bnx2x_vfpf.h"
  45
  46enum bnx2x_int_mode {
  47        BNX2X_INT_MODE_MSIX,
  48        BNX2X_INT_MODE_INTX,
  49        BNX2X_INT_MODE_MSI
  50};
  51
  52/* error/debug prints */
  53
  54#define DRV_MODULE_NAME         "bnx2x"
  55
  56/* for messages that are currently off */
  57#define BNX2X_MSG_OFF                   0x0
  58#define BNX2X_MSG_MCP                   0x0010000 /* was: NETIF_MSG_HW */
  59#define BNX2X_MSG_STATS                 0x0020000 /* was: NETIF_MSG_TIMER */
  60#define BNX2X_MSG_NVM                   0x0040000 /* was: NETIF_MSG_HW */
  61#define BNX2X_MSG_DMAE                  0x0080000 /* was: NETIF_MSG_HW */
  62#define BNX2X_MSG_SP                    0x0100000 /* was: NETIF_MSG_INTR */
  63#define BNX2X_MSG_FP                    0x0200000 /* was: NETIF_MSG_INTR */
  64#define BNX2X_MSG_INFO                  0x0400000
  65#define BNX2X_MSG_IOV                   0x0800000
  66#define BNX2X_MSG_PTP                   0x1000000
  67#define BNX2X_MSG_IDLE                  0x2000000 /* used for idle check*/
  68#define BNX2X_MSG_ETHTOOL               0x4000000
  69#define BNX2X_MSG_DCB                   0x8000000
  70
  71/* regular debug print */
  72#define DP_INNER(fmt, ...)                                      \
  73        pr_notice("[%s:%d(%s)]" fmt,                            \
  74                  __func__, __LINE__,                           \
  75                  bp->dev ? (bp->dev->name) : "?",              \
  76                  ##__VA_ARGS__);
  77
  78#define DP(__mask, fmt, ...)                                    \
  79do {                                                            \
  80        if (unlikely(bp->msg_enable & (__mask)))                \
  81                DP_INNER(fmt, ##__VA_ARGS__);                   \
  82} while (0)
  83
  84#define DP_AND(__mask, fmt, ...)                                \
  85do {                                                            \
  86        if (unlikely((bp->msg_enable & (__mask)) == __mask))    \
  87                DP_INNER(fmt, ##__VA_ARGS__);                   \
  88} while (0)
  89
  90#define DP_CONT(__mask, fmt, ...)                               \
  91do {                                                            \
  92        if (unlikely(bp->msg_enable & (__mask)))                \
  93                pr_cont(fmt, ##__VA_ARGS__);                    \
  94} while (0)
  95
  96/* errors debug print */
  97#define BNX2X_DBG_ERR(fmt, ...)                                 \
  98do {                                                            \
  99        if (unlikely(netif_msg_probe(bp)))                      \
 100                pr_err("[%s:%d(%s)]" fmt,                       \
 101                       __func__, __LINE__,                      \
 102                       bp->dev ? (bp->dev->name) : "?",         \
 103                       ##__VA_ARGS__);                          \
 104} while (0)
 105
 106/* for errors (never masked) */
 107#define BNX2X_ERR(fmt, ...)                                     \
 108do {                                                            \
 109        pr_err("[%s:%d(%s)]" fmt,                               \
 110               __func__, __LINE__,                              \
 111               bp->dev ? (bp->dev->name) : "?",                 \
 112               ##__VA_ARGS__);                                  \
 113} while (0)
 114
 115#define BNX2X_ERROR(fmt, ...)                                   \
 116        pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
 117
 118/* before we have a dev->name use dev_info() */
 119#define BNX2X_DEV_INFO(fmt, ...) DP(BNX2X_MSG_INFO, fmt, ##__VA_ARGS__)
 120
 121/* Error handling */
 122void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
 123#ifdef BNX2X_STOP_ON_ERROR
 124#define bnx2x_panic()                           \
 125do {                                            \
 126        bp->panic = 1;                          \
 127        BNX2X_ERR("driver assert\n");           \
 128        bnx2x_panic_dump(bp, true);             \
 129} while (0)
 130#else
 131#define bnx2x_panic()                           \
 132do {                                            \
 133        bp->panic = 1;                          \
 134        BNX2X_ERR("driver assert\n");           \
 135        bnx2x_panic_dump(bp, false);            \
 136} while (0)
 137#endif
 138
 139#define bnx2x_mc_addr(ha)      ((ha)->addr)
 140#define bnx2x_uc_addr(ha)      ((ha)->addr)
 141
 142#define U64_LO(x)                       ((uint32_t)(((uint64_t)(x)) & 0xffffffff))
 143#define U64_HI(x)                       ((uint32_t)(((uint64_t)(x)) >> 32))
 144#define HILO_U64(hi, lo)                ((((uint64_t)(hi)) << 32) + (lo))
 145
 146#define REG_ADDR(bp, offset)            ((bp->regview) + (offset))
 147
 148#define REG_RD(bp, offset)              read32(REG_ADDR(bp, offset))
 149#define REG_RD8(bp, offset)             read8(REG_ADDR(bp, offset))
 150#define REG_RD16(bp, offset)            read16(REG_ADDR(bp, offset))
 151
 152#define REG_WR(bp, offset, val)         write32((uint32_t)val, REG_ADDR(bp, offset))
 153#define REG_WR8(bp, offset, val)        write8((uint8_t)val, REG_ADDR(bp, offset))
 154#define REG_WR16(bp, offset, val)       write16((uint16_t)val, REG_ADDR(bp, offset))
 155
 156#define REG_RD_IND(bp, offset)          bnx2x_reg_rd_ind(bp, offset)
 157#define REG_WR_IND(bp, offset, val)     bnx2x_reg_wr_ind(bp, offset, val)
 158
 159#define REG_RD_DMAE(bp, offset, valp, len32) \
 160        do { \
 161                bnx2x_read_dmae(bp, offset, len32);\
 162                memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
 163        } while (0)
 164
 165#define REG_WR_DMAE(bp, offset, valp, len32) \
 166        do { \
 167                memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
 168                bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
 169                                 offset, len32); \
 170        } while (0)
 171
 172#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
 173        REG_WR_DMAE(bp, offset, valp, len32)
 174
 175#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
 176        do { \
 177                memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
 178                bnx2x_write_big_buf_wb(bp, addr, len32); \
 179        } while (0)
 180
 181#define SHMEM_ADDR(bp, field)           (bp->common.shmem_base + \
 182                                         offsetof(struct shmem_region, field))
 183#define SHMEM_RD(bp, field)             REG_RD(bp, SHMEM_ADDR(bp, field))
 184#define SHMEM_WR(bp, field, val)        REG_WR(bp, SHMEM_ADDR(bp, field), val)
 185
 186#define SHMEM2_ADDR(bp, field)          (bp->common.shmem2_base + \
 187                                         offsetof(struct shmem2_region, field))
 188#define SHMEM2_RD(bp, field)            REG_RD(bp, SHMEM2_ADDR(bp, field))
 189#define SHMEM2_WR(bp, field, val)       REG_WR(bp, SHMEM2_ADDR(bp, field), val)
 190#define MF_CFG_ADDR(bp, field)          (bp->common.mf_cfg_base + \
 191                                         offsetof(struct mf_cfg, field))
 192#define MF2_CFG_ADDR(bp, field)         (bp->common.mf2_cfg_base + \
 193                                         offsetof(struct mf2_cfg, field))
 194
 195#define MF_CFG_RD(bp, field)            REG_RD(bp, MF_CFG_ADDR(bp, field))
 196#define MF_CFG_WR(bp, field, val)       REG_WR(bp,\
 197                                               MF_CFG_ADDR(bp, field), (val))
 198#define MF2_CFG_RD(bp, field)           REG_RD(bp, MF2_CFG_ADDR(bp, field))
 199
 200#define SHMEM2_HAS(bp, field)           ((bp)->common.shmem2_base &&    \
 201                                         (SHMEM2_RD((bp), size) >       \
 202                                         offsetof(struct shmem2_region, field)))
 203
 204#define EMAC_RD(bp, reg)                REG_RD(bp, emac_base + reg)
 205#define EMAC_WR(bp, reg, val)           REG_WR(bp, emac_base + reg, val)
 206
 207/* SP SB indices */
 208
 209/* General SP events - stats query, cfc delete, etc  */
 210#define HC_SP_INDEX_ETH_DEF_CONS                3
 211
 212/* EQ completions */
 213#define HC_SP_INDEX_EQ_CONS                     7
 214
 215/* FCoE L2 connection completions */
 216#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS         6
 217#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS         4
 218/* iSCSI L2 */
 219#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS           5
 220#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS        1
 221
 222/* Special clients parameters */
 223
 224/* SB indices */
 225/* FCoE L2 */
 226#define BNX2X_FCOE_L2_RX_INDEX \
 227        (&bp->def_status_blk->sp_sb.\
 228        index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
 229
 230#define BNX2X_FCOE_L2_TX_INDEX \
 231        (&bp->def_status_blk->sp_sb.\
 232        index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
 233
 234/**
 235 *  CIDs and CLIDs:
 236 *  CLIDs below is a CLID for func 0, then the CLID for other
 237 *  functions will be calculated by the formula:
 238 *
 239 *  FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
 240 *
 241 */
 242enum {
 243        BNX2X_ISCSI_ETH_CL_ID_IDX,
 244        BNX2X_FCOE_ETH_CL_ID_IDX,
 245        BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
 246};
 247
 248/* use a value high enough to be above all the PFs, which has least significant
 249 * nibble as 8, so when cnic needs to come up with a CID for UIO to use to
 250 * calculate doorbell address according to old doorbell configuration scheme
 251 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number
 252 * We must avoid coming up with cid 8 for iscsi since according to this method
 253 * the designated UIO cid will come out 0 and it has a special handling for that
 254 * case which doesn't suit us. Therefore will will cieling to closes cid which
 255 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18.
 256 */
 257
 258#define BNX2X_1st_NON_L2_ETH_CID(bp)    (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \
 259                                         (bp)->max_cos)
 260/* amount of cids traversed by UIO's DPM addition to doorbell */
 261#define UIO_DPM                         8
 262/* roundup to DPM offset */
 263#define UIO_ROUNDUP(bp)                 (ROUNDUP(BNX2X_1st_NON_L2_ETH_CID(bp), UIO_DPM))
 264/* offset to nearest value which has lsb nibble matching DPM */
 265#define UIO_CID_OFFSET(bp)              ((UIO_ROUNDUP(bp) + UIO_DPM) % \
 266                                         (UIO_DPM * 2))
 267/* add offset to rounded-up cid to get a value which could be used with UIO */
 268#define UIO_DPM_ALIGN(bp)               (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp))
 269/* but wait - avoid UIO special case for cid 0 */
 270#define UIO_DPM_CID0_OFFSET(bp)         ((UIO_DPM * 2) * \
 271                                         (UIO_DPM_ALIGN(bp) == UIO_DPM))
 272/* Properly DPM aligned CID dajusted to cid 0 secal case */
 273#define BNX2X_CNIC_START_ETH_CID(bp)    (UIO_DPM_ALIGN(bp) + \
 274                                         (UIO_DPM_CID0_OFFSET(bp)))
 275/* how many cids were wasted  - need this value for cid allocation */
 276#define UIO_CID_PAD(bp)                 (BNX2X_CNIC_START_ETH_CID(bp) - \
 277                                         BNX2X_1st_NON_L2_ETH_CID(bp))
 278        /* iSCSI L2 */
 279#define BNX2X_ISCSI_ETH_CID(bp)         (BNX2X_CNIC_START_ETH_CID(bp))
 280        /* FCoE L2 */
 281#define BNX2X_FCOE_ETH_CID(bp)          (BNX2X_CNIC_START_ETH_CID(bp) + 1)
 282
 283#define CNIC_SUPPORT(bp)                ((bp)->cnic_support)
 284#define CNIC_ENABLED(bp)                ((bp)->cnic_enabled)
 285#define CNIC_LOADED(bp)                 ((bp)->cnic_loaded)
 286#define FCOE_INIT(bp)                   ((bp)->fcoe_init)
 287
 288#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
 289        AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
 290
 291#define SM_RX_ID                        0
 292#define SM_TX_ID                        1
 293
 294/* defines for multiple tx priority indices */
 295#define FIRST_TX_ONLY_COS_INDEX         1
 296#define FIRST_TX_COS_INDEX              0
 297
 298/* rules for calculating the cids of tx-only connections */
 299#define CID_TO_FP(cid, bp)              ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
 300#define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
 301                                (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
 302
 303/* fp index inside class of service range */
 304#define FP_COS_TO_TXQ(fp, cos, bp) \
 305                        ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
 306
 307/* Indexes for transmission queues array:
 308 * txdata for RSS i CoS j is at location i + (j * num of RSS)
 309 * txdata for FCoE (if exist) is at location max cos * num of RSS
 310 * txdata for FWD (if exist) is one location after FCoE
 311 * txdata for OOO (if exist) is one location after FWD
 312 */
 313enum {
 314        FCOE_TXQ_IDX_OFFSET,
 315        FWD_TXQ_IDX_OFFSET,
 316        OOO_TXQ_IDX_OFFSET,
 317};
 318#define MAX_ETH_TXQ_IDX(bp)     (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
 319#define FCOE_TXQ_IDX(bp)        (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
 320
 321/* fast path */
 322/*
 323 * This driver uses new build_skb() API :
 324 * RX ring buffer contains pointer to kmalloc() data only,
 325 * skb are built only after Hardware filled the frame.
 326 */
 327struct sw_rx_bd {
 328        uint8_t         *data;
 329        DEFINE_DMA_UNMAP_ADDR(mapping);
 330};
 331
 332struct sw_tx_bd {
 333        struct block    *block;
 334        uint16_t                first_bd;
 335        uint8_t         flags;
 336/* Set on the first BD descriptor when there is a split BD */
 337#define BNX2X_TSO_SPLIT_BD              (1<<0)
 338#define BNX2X_HAS_SECOND_PBD            (1<<1)
 339};
 340
 341struct sw_rx_page {
 342        struct page     *page;
 343        DEFINE_DMA_UNMAP_ADDR(mapping);
 344};
 345
 346union db_prod {
 347        struct doorbell_set_prod data;
 348        uint32_t                raw;
 349};
 350
 351/* dropless fc FW/HW related params */
 352#define BRB_SIZE(bp)            (CHIP_IS_E3(bp) ? 1024 : 512)
 353#define MAX_AGG_QS(bp)          (CHIP_IS_E1(bp) ? \
 354                                        ETH_MAX_AGGREGATION_QUEUES_E1 :\
 355                                        ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
 356#define FW_DROP_LEVEL(bp)       (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
 357#define FW_PREFETCH_CNT         16
 358#define DROPLESS_FC_HEADROOM    100
 359
 360/* MC hsi */
 361#define BCM_PAGE_SHIFT          12
 362#define BCM_PAGE_SIZE           (1 << BCM_PAGE_SHIFT)
 363#define BCM_PAGE_MASK           (~(BCM_PAGE_SIZE - 1))
 364#define BCM_PAGE_ALIGN(addr)    (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
 365
 366#define PAGES_PER_SGE_SHIFT     0
 367#define PAGES_PER_SGE           (1 << PAGES_PER_SGE_SHIFT)
 368#define SGE_PAGE_SIZE           PAGE_SIZE
 369#define SGE_PAGE_SHIFT          PAGE_SHIFT
 370#define SGE_PAGE_ALIGN(addr)    PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
 371#define SGE_PAGES               (SGE_PAGE_SIZE * PAGES_PER_SGE)
 372#define TPA_AGG_SIZE            MIN_T(uint32_t, (MIN_T(uint32_t, 8, MAX_SKB_FRAGS) * \
 373                                            SGE_PAGES), 0xffff)
 374
 375/* SGE ring related macros */
 376#define NUM_RX_SGE_PAGES        2
 377#define RX_SGE_CNT              (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
 378#define NEXT_PAGE_SGE_DESC_CNT  2
 379#define MAX_RX_SGE_CNT          (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
 380/* RX_SGE_CNT is promised to be a power of 2 */
 381#define RX_SGE_MASK             (RX_SGE_CNT - 1)
 382#define NUM_RX_SGE              (RX_SGE_CNT * NUM_RX_SGE_PAGES)
 383#define MAX_RX_SGE              (NUM_RX_SGE - 1)
 384#define NEXT_SGE_IDX(x)         ((((x) & RX_SGE_MASK) == \
 385                                  (MAX_RX_SGE_CNT - 1)) ? \
 386                                        (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
 387                                        (x) + 1)
 388#define RX_SGE(x)               ((x) & MAX_RX_SGE)
 389
 390/*
 391 * Number of required  SGEs is the sum of two:
 392 * 1. Number of possible opened aggregations (next packet for
 393 *    these aggregations will probably consume SGE immediately)
 394 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
 395 *    after placement on BD for new TPA aggregation)
 396 *
 397 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
 398 */
 399#define NUM_SGE_REQ             (MAX_AGG_QS(bp) + \
 400                                        (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
 401#define NUM_SGE_PG_REQ          ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
 402                                                MAX_RX_SGE_CNT)
 403#define SGE_TH_LO(bp)           (NUM_SGE_REQ + \
 404                                 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
 405#define SGE_TH_HI(bp)           (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
 406
 407/* Manipulate a bit vector defined as an array of uint64_t */
 408
 409/* Number of bits in one sge_mask array element */
 410#define BIT_VEC64_ELEM_SZ               64
 411#define BIT_VEC64_ELEM_SHIFT            6
 412#define BIT_VEC64_ELEM_MASK             ((uint64_t)BIT_VEC64_ELEM_SZ - 1)
 413
 414#define __BIT_VEC64_SET_BIT(el, bit) \
 415        do { \
 416                el = ((el) | ((uint64_t)0x1 << (bit))); \
 417        } while (0)
 418
 419#define __BIT_VEC64_CLEAR_BIT(el, bit) \
 420        do { \
 421                el = ((el) & (~((uint64_t)0x1 << (bit)))); \
 422        } while (0)
 423
 424#define BIT_VEC64_SET_BIT(vec64, idx) \
 425        __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
 426                           (idx) & BIT_VEC64_ELEM_MASK)
 427
 428#define BIT_VEC64_CLEAR_BIT(vec64, idx) \
 429        __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
 430                             (idx) & BIT_VEC64_ELEM_MASK)
 431
 432#define BIT_VEC64_TEST_BIT(vec64, idx) \
 433        (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
 434        ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
 435
 436/* Creates a bitmask of all ones in less significant bits.
 437   idx - index of the most significant bit in the created mask */
 438#define BIT_VEC64_ONES_MASK(idx) \
 439                (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
 440#define BIT_VEC64_ELEM_ONE_MASK ((uint64_t)(~0))
 441
 442/*******************************************************/
 443
 444/* Number of uint64_t elements in SGE mask array */
 445#define RX_SGE_MASK_LEN                 (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
 446#define RX_SGE_MASK_LEN_MASK            (RX_SGE_MASK_LEN - 1)
 447#define NEXT_SGE_MASK_ELEM(el)          (((el) + 1) & RX_SGE_MASK_LEN_MASK)
 448
 449union host_hc_status_block {
 450        /* pointer to fp status block e1x */
 451        struct host_hc_status_block_e1x *e1x_sb;
 452        /* pointer to fp status block e2 */
 453        struct host_hc_status_block_e2  *e2_sb;
 454};
 455
 456struct bnx2x_agg_info {
 457        /*
 458         * First aggregation buffer is a data buffer, the following - are pages.
 459         * We will preallocate the data buffer for each aggregation when
 460         * we open the interface and will replace the BD at the consumer
 461         * with this one when we receive the TPA_START CQE in order to
 462         * keep the Rx BD ring consistent.
 463         */
 464        struct sw_rx_bd         first_buf;
 465        uint8_t                 tpa_state;
 466#define BNX2X_TPA_START                 1
 467#define BNX2X_TPA_STOP                  2
 468#define BNX2X_TPA_ERROR                 3
 469        uint8_t                 placement_offset;
 470        uint16_t                        parsing_flags;
 471        uint16_t                        vlan_tag;
 472        uint16_t                        len_on_bd;
 473        uint32_t                        rxhash;
 474        enum pkt_hash_types     rxhash_type;
 475        uint16_t                        gro_size;
 476        uint16_t                        full_page;
 477};
 478
 479#define Q_STATS_OFFSET32(stat_name) \
 480                        (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
 481
 482struct bnx2x_fp_txdata {
 483
 484        struct sw_tx_bd         *tx_buf_ring;
 485
 486        union eth_tx_bd_types   *tx_desc_ring;
 487        dma_addr_t              tx_desc_mapping;
 488
 489        uint32_t                        cid;
 490
 491        union db_prod           tx_db;
 492
 493        uint16_t                        tx_pkt_prod;
 494        uint16_t                        tx_pkt_cons;
 495        uint16_t                        tx_bd_prod;
 496        uint16_t                        tx_bd_cons;
 497
 498        unsigned long           tx_pkt;
 499
 500        __le16                  *tx_cons_sb;
 501
 502        int                     txq_index;
 503        struct bnx2x_fastpath   *parent_fp;
 504        int                     tx_ring_size;
 505
 506        struct poke_tracker                     poker;
 507        struct queue                            *oq;
 508};
 509
 510enum bnx2x_tpa_mode_t {
 511        TPA_MODE_LRO,
 512        TPA_MODE_GRO
 513};
 514
 515struct bnx2x_fastpath {
 516        struct bnx2x            *bp; /* parent */
 517
 518        struct napi_struct      napi;
 519
 520#ifdef CONFIG_NET_RX_BUSY_POLL
 521        unsigned int state;
 522#define BNX2X_FP_STATE_IDLE                   0
 523#define BNX2X_FP_STATE_NAPI             (1 << 0)    /* NAPI owns this FP */
 524#define BNX2X_FP_STATE_POLL             (1 << 1)    /* poll owns this FP */
 525#define BNX2X_FP_STATE_DISABLED         (1 << 2)
 526#define BNX2X_FP_STATE_NAPI_YIELD       (1 << 3)    /* NAPI yielded this FP */
 527#define BNX2X_FP_STATE_POLL_YIELD       (1 << 4)    /* poll yielded this FP */
 528#define BNX2X_FP_OWNED  (BNX2X_FP_STATE_NAPI | BNX2X_FP_STATE_POLL)
 529#define BNX2X_FP_YIELD  (BNX2X_FP_STATE_NAPI_YIELD | BNX2X_FP_STATE_POLL_YIELD)
 530#define BNX2X_FP_LOCKED (BNX2X_FP_OWNED | BNX2X_FP_STATE_DISABLED)
 531#define BNX2X_FP_USER_PEND (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_POLL_YIELD)
 532        /* protect state */
 533        spinlock_t lock;
 534#endif /* CONFIG_NET_RX_BUSY_POLL */
 535
 536        union host_hc_status_block      status_blk;
 537        /* chip independent shortcuts into sb structure */
 538        __le16                  *sb_index_values;
 539        __le16                  *sb_running_index;
 540        /* chip independent shortcut into rx_prods_offset memory */
 541        uint32_t                        ustorm_rx_prods_offset;
 542
 543        uint32_t                        rx_buf_size;
 544        uint32_t                        rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
 545        dma_addr_t              status_blk_mapping;
 546
 547        enum bnx2x_tpa_mode_t   mode;
 548
 549        uint8_t                 max_cos; /* actual number of active tx coses */
 550        struct bnx2x_fp_txdata  *txdata_ptr[BNX2X_MULTI_TX_COS];
 551
 552        struct sw_rx_bd         *rx_buf_ring;   /* BDs mappings ring */
 553        struct sw_rx_page       *rx_page_ring;  /* SGE pages mappings ring */
 554
 555        struct eth_rx_bd        *rx_desc_ring;
 556        dma_addr_t              rx_desc_mapping;
 557
 558        union eth_rx_cqe        *rx_comp_ring;
 559        dma_addr_t              rx_comp_mapping;
 560
 561        /* SGE ring */
 562        struct eth_rx_sge       *rx_sge_ring;
 563        dma_addr_t              rx_sge_mapping;
 564
 565        uint64_t                        sge_mask[RX_SGE_MASK_LEN];
 566
 567        uint32_t                        cid;
 568
 569        __le16                  fp_hc_idx;
 570
 571        uint8_t                 index;          /* number in fp array */
 572        uint8_t                 rx_queue;       /* index for skb_record */
 573        uint8_t                 cl_id;          /* eth client id */
 574        uint8_t                 cl_qzone_id;
 575        uint8_t                 fw_sb_id;       /* status block number in FW */
 576        uint8_t                 igu_sb_id;      /* status block number in HW */
 577
 578        uint16_t                        rx_bd_prod;
 579        uint16_t                        rx_bd_cons;
 580        uint16_t                        rx_comp_prod;
 581        uint16_t                        rx_comp_cons;
 582        uint16_t                        rx_sge_prod;
 583        /* The last maximal completed SGE */
 584        uint16_t                        last_max_sge;
 585        __le16                  *rx_cons_sb;
 586        unsigned long           rx_pkt,
 587                                rx_calls;
 588
 589        /* TPA related */
 590        struct bnx2x_agg_info   *tpa_info;
 591        uint8_t                 disable_tpa;
 592#ifdef BNX2X_STOP_ON_ERROR
 593        uint64_t                        tpa_queue_used;
 594#endif
 595        /* The size is calculated using the following:
 596             sizeof name field from netdev structure +
 597             4 ('-Xx-' string) +
 598             4 (for the digits and to make it DWORD aligned) */
 599#define FP_NAME_SIZE            (sizeof(((struct ether *)0)->name) + 8)
 600        char                    name[FP_NAME_SIZE];
 601};
 602
 603#define bnx2x_fp(bp, nr, var)   ((bp)->fp[(nr)].var)
 604#define bnx2x_sp_obj(bp, fp)    ((bp)->sp_objs[(fp)->index])
 605#define bnx2x_fp_stats(bp, fp)  (&((bp)->fp_stats[(fp)->index]))
 606#define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
 607
 608#ifdef CONFIG_NET_RX_BUSY_POLL
 609static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp)
 610{
 611        spinlock_init_irqsave(&fp->lock);
 612        fp->state = BNX2X_FP_STATE_IDLE;
 613}
 614
 615/* called from the device poll routine to get ownership of a FP */
 616static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
 617{
 618        bool rc = true;
 619
 620        spin_lock(&fp->lock);
 621        if (fp->state & BNX2X_FP_LOCKED) {
 622                warn_on(fp->state & BNX2X_FP_STATE_NAPI);
 623                fp->state |= BNX2X_FP_STATE_NAPI_YIELD;
 624                rc = false;
 625        } else {
 626                /* we don't care if someone yielded */
 627                fp->state = BNX2X_FP_STATE_NAPI;
 628        }
 629        spin_unlock(&fp->lock);
 630        return rc;
 631}
 632
 633/* returns true is someone tried to get the FP while napi had it */
 634static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
 635{
 636        bool rc = false;
 637
 638        spin_lock(&fp->lock);
 639        warn_on(fp->state &
 640                (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_NAPI_YIELD));
 641
 642        if (fp->state & BNX2X_FP_STATE_POLL_YIELD)
 643                rc = true;
 644
 645        /* state ==> idle, unless currently disabled */
 646        fp->state &= BNX2X_FP_STATE_DISABLED;
 647        spin_unlock(&fp->lock);
 648        return rc;
 649}
 650
 651/* called from bnx2x_low_latency_poll() */
 652static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
 653{
 654        bool rc = true;
 655
 656        spin_lock(&fp->lock);
 657        if ((fp->state & BNX2X_FP_LOCKED)) {
 658                fp->state |= BNX2X_FP_STATE_POLL_YIELD;
 659                rc = false;
 660        } else {
 661                /* preserve yield marks */
 662                fp->state |= BNX2X_FP_STATE_POLL;
 663        }
 664        spin_unlock(&fp->lock);
 665        return rc;
 666}
 667
 668/* returns true if someone tried to get the FP while it was locked */
 669static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
 670{
 671        bool rc = false;
 672
 673        spin_lock(&fp->lock);
 674        warn_on(fp->state & BNX2X_FP_STATE_NAPI);
 675
 676        if (fp->state & BNX2X_FP_STATE_POLL_YIELD)
 677                rc = true;
 678
 679        /* state ==> idle, unless currently disabled */
 680        fp->state &= BNX2X_FP_STATE_DISABLED;
 681        spin_unlock(&fp->lock);
 682        return rc;
 683}
 684
 685/* true if a socket is polling, even if it did not get the lock */
 686static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
 687{
 688        warn_on(!(fp->state & BNX2X_FP_OWNED));
 689        return fp->state & BNX2X_FP_USER_PEND;
 690}
 691
 692/* false if fp is currently owned */
 693static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp)
 694{
 695        int rc = true;
 696
 697        spin_lock(&fp->lock);
 698        if (fp->state & BNX2X_FP_OWNED)
 699                rc = false;
 700        fp->state |= BNX2X_FP_STATE_DISABLED;
 701        spin_unlock(&fp->lock);
 702
 703        return rc;
 704}
 705#else
 706static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp)
 707{
 708}
 709
 710static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
 711{
 712        return true;
 713}
 714
 715static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
 716{
 717        return false;
 718}
 719
 720static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
 721{
 722        return false;
 723}
 724
 725static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
 726{
 727        return false;
 728}
 729
 730static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
 731{
 732        return false;
 733}
 734static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp)
 735{
 736        return true;
 737}
 738#endif /* CONFIG_NET_RX_BUSY_POLL */
 739
 740/* Use 2500 as a mini-jumbo MTU for FCoE */
 741#define BNX2X_FCOE_MINI_JUMBO_MTU       2500
 742
 743#define FCOE_IDX_OFFSET         0
 744
 745#define FCOE_IDX(bp)            (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
 746                                 FCOE_IDX_OFFSET)
 747#define bnx2x_fcoe_fp(bp)       (&bp->fp[FCOE_IDX(bp)])
 748#define bnx2x_fcoe(bp, var)     (bnx2x_fcoe_fp(bp)->var)
 749#define bnx2x_fcoe_inner_sp_obj(bp)     (&bp->sp_objs[FCOE_IDX(bp)])
 750#define bnx2x_fcoe_sp_obj(bp, var)      (bnx2x_fcoe_inner_sp_obj(bp)->var)
 751#define bnx2x_fcoe_tx(bp, var)  (bnx2x_fcoe_fp(bp)-> \
 752                                                txdata_ptr[FIRST_TX_COS_INDEX] \
 753                                                ->var)
 754
 755#define IS_ETH_FP(fp)           ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
 756#define IS_FCOE_FP(fp)          ((fp)->index == FCOE_IDX((fp)->bp))
 757#define IS_FCOE_IDX(idx)        ((idx) == FCOE_IDX(bp))
 758
 759/* MC hsi */
 760#define MAX_FETCH_BD            13      /* HW max BDs per packet */
 761#define RX_COPY_THRESH          92
 762
 763#define NUM_TX_RINGS            16
 764#define TX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
 765#define NEXT_PAGE_TX_DESC_CNT   1
 766#define MAX_TX_DESC_CNT         (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
 767#define NUM_TX_BD               (TX_DESC_CNT * NUM_TX_RINGS)
 768#define MAX_TX_BD               (NUM_TX_BD - 1)
 769#define MAX_TX_AVAIL            (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
 770#define NEXT_TX_IDX(x)          ((((x) & MAX_TX_DESC_CNT) == \
 771                                  (MAX_TX_DESC_CNT - 1)) ? \
 772                                        (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
 773                                        (x) + 1)
 774#define TX_BD(x)                ((x) & MAX_TX_BD)
 775#define TX_BD_POFF(x)           ((x) & MAX_TX_DESC_CNT)
 776
 777/* number of NEXT_PAGE descriptors may be required during placement */
 778#define NEXT_CNT_PER_TX_PKT(bds)        \
 779                                (((bds) + MAX_TX_DESC_CNT - 1) / \
 780                                 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
 781/* max BDs per tx packet w/o next_pages:
 782 * START_BD             - describes packed
 783 * START_BD(splitted)   - includes unpaged data segment for GSO
 784 * PARSING_BD           - for TSO and CSUM data
 785 * PARSING_BD2          - for encapsulation data
 786 * Frag BDs             - describes pages for frags
 787 */
 788#define BDS_PER_TX_PKT          4
 789#define MAX_BDS_PER_TX_PKT      (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
 790/* max BDs per tx packet including next pages */
 791#define MAX_DESC_PER_TX_PKT     (MAX_BDS_PER_TX_PKT + \
 792                                 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
 793
 794/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
 795#define NUM_RX_RINGS            8
 796#define RX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
 797#define NEXT_PAGE_RX_DESC_CNT   2
 798#define MAX_RX_DESC_CNT         (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
 799#define RX_DESC_MASK            (RX_DESC_CNT - 1)
 800#define NUM_RX_BD               (RX_DESC_CNT * NUM_RX_RINGS)
 801#define MAX_RX_BD               (NUM_RX_BD - 1)
 802#define MAX_RX_AVAIL            (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
 803
 804/* dropless fc calculations for BDs
 805 *
 806 * Number of BDs should as number of buffers in BRB:
 807 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
 808 * "next" elements on each page
 809 */
 810#define NUM_BD_REQ              BRB_SIZE(bp)
 811#define NUM_BD_PG_REQ           ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
 812                                              MAX_RX_DESC_CNT)
 813#define BD_TH_LO(bp)            (NUM_BD_REQ + \
 814                                 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
 815                                 FW_DROP_LEVEL(bp))
 816#define BD_TH_HI(bp)            (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
 817
 818#define MIN_RX_AVAIL            ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
 819
 820#define MIN_RX_SIZE_TPA_HW      (CHIP_IS_E1(bp) ? \
 821                                        ETH_MIN_RX_CQES_WITH_TPA_E1 : \
 822                                        ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
 823#define MIN_RX_SIZE_NONTPA_HW   ETH_MIN_RX_CQES_WITHOUT_TPA
 824#define MIN_RX_SIZE_TPA         (MAX_T(uint32_t, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
 825#define MIN_RX_SIZE_NONTPA      (MAX_T(uint32_t, MIN_RX_SIZE_NONTPA_HW,\
 826                                                                MIN_RX_AVAIL))
 827
 828#define NEXT_RX_IDX(x)          ((((x) & RX_DESC_MASK) == \
 829                                  (MAX_RX_DESC_CNT - 1)) ? \
 830                                        (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
 831                                        (x) + 1)
 832#define RX_BD(x)                ((x) & MAX_RX_BD)
 833
 834/*
 835 * As long as CQE is X times bigger than BD entry we have to allocate X times
 836 * more pages for CQ ring in order to keep it balanced with BD ring
 837 */
 838#define CQE_BD_REL      (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
 839#define NUM_RCQ_RINGS           (NUM_RX_RINGS * CQE_BD_REL)
 840#define RCQ_DESC_CNT            (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
 841#define NEXT_PAGE_RCQ_DESC_CNT  1
 842#define MAX_RCQ_DESC_CNT        (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
 843#define NUM_RCQ_BD              (RCQ_DESC_CNT * NUM_RCQ_RINGS)
 844#define MAX_RCQ_BD              (NUM_RCQ_BD - 1)
 845#define MAX_RCQ_AVAIL           (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
 846#define NEXT_RCQ_IDX(x)         ((((x) & MAX_RCQ_DESC_CNT) == \
 847                                  (MAX_RCQ_DESC_CNT - 1)) ? \
 848                                        (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
 849                                        (x) + 1)
 850#define RCQ_BD(x)               ((x) & MAX_RCQ_BD)
 851
 852/* dropless fc calculations for RCQs
 853 *
 854 * Number of RCQs should be as number of buffers in BRB:
 855 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
 856 * "next" elements on each page
 857 */
 858#define NUM_RCQ_REQ             BRB_SIZE(bp)
 859#define NUM_RCQ_PG_REQ          ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
 860                                              MAX_RCQ_DESC_CNT)
 861#define RCQ_TH_LO(bp)           (NUM_RCQ_REQ + \
 862                                 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
 863                                 FW_DROP_LEVEL(bp))
 864#define RCQ_TH_HI(bp)           (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
 865
 866/* This is needed for determining of last_max */
 867#define SUB_S16(a, b)           (int16_t)((int16_t)(a) - (int16_t)(b))
 868#define SUB_S32(a, b)           (int32_t)((int32_t)(a) - (int32_t)(b))
 869
 870#define BNX2X_SWCID_SHIFT       17
 871#define BNX2X_SWCID_MASK        ((0x1 << BNX2X_SWCID_SHIFT) - 1)
 872
 873/* used on a CID received from the HW */
 874#define SW_CID(x)                       (le32_to_cpu(x) & BNX2X_SWCID_MASK)
 875#define CQE_CMD(x)                      (le32_to_cpu(x) >> \
 876                                        COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
 877
 878#define BD_UNMAP_ADDR(bd)               HILO_U64(le32_to_cpu((bd)->addr_hi), \
 879                                                 le32_to_cpu((bd)->addr_lo))
 880#define BD_UNMAP_LEN(bd)                (le16_to_cpu((bd)->nbytes))
 881
 882#define BNX2X_DB_MIN_SHIFT              3       /* 8 bytes */
 883#define BNX2X_DB_SHIFT                  3       /* 8 bytes*/
 884#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
 885#error "Min DB doorbell stride is 8"
 886#endif
 887#define DOORBELL(bp, cid, val) \
 888        do { \
 889                write32((uint32_t)(val), bp->doorbells + (bp->db_size * (cid))); \
 890        } while (0)
 891
 892/* TX CSUM helpers */
 893#define SKB_CS_OFF(skb)         (offsetof(struct tcphdr, check) - \
 894                                 skb->csum_offset)
 895#define SKB_CS(skb)             (*(uint16_t *)(skb_transport_header(skb) + \
 896                                          skb->csum_offset))
 897
 898#define pbd_tcp_flags(tcp_hdr)  (be32_to_cpu(tcp_flag_word(tcp_hdr))>>16 & 0xff)
 899
 900#define XMIT_PLAIN              0
 901#define XMIT_CSUM_V4            (1 << 0)
 902#define XMIT_CSUM_V6            (1 << 1)
 903#define XMIT_CSUM_TCP           (1 << 2)
 904#define XMIT_GSO_V4             (1 << 3)
 905#define XMIT_GSO_V6             (1 << 4)
 906#define XMIT_CSUM_ENC_V4        (1 << 5)
 907#define XMIT_CSUM_ENC_V6        (1 << 6)
 908#define XMIT_GSO_ENC_V4         (1 << 7)
 909#define XMIT_GSO_ENC_V6         (1 << 8)
 910
 911#define XMIT_CSUM_ENC           (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6)
 912#define XMIT_GSO_ENC            (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6)
 913
 914#define XMIT_CSUM               (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC)
 915#define XMIT_GSO                (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC)
 916
 917/* stuff added to make the code fit 80Col */
 918#define CQE_TYPE(cqe_fp_flags)   ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
 919#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
 920#define CQE_TYPE_STOP(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
 921#define CQE_TYPE_SLOW(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
 922#define CQE_TYPE_FAST(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
 923
 924#define ETH_RX_ERROR_FALGS              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
 925
 926#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
 927                                (((le16_to_cpu(flags) & \
 928                                   PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
 929                                  PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
 930                                 == PRS_FLAG_OVERETH_IPV4)
 931#define BNX2X_RX_SUM_FIX(cqe) \
 932        BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
 933
 934#define FP_USB_FUNC_OFF \
 935                        offsetof(struct cstorm_status_block_u, func)
 936#define FP_CSB_FUNC_OFF \
 937                        offsetof(struct cstorm_status_block_c, func)
 938
 939#define HC_INDEX_ETH_RX_CQ_CONS         1
 940
 941#define HC_INDEX_OOO_TX_CQ_CONS         4
 942
 943#define HC_INDEX_ETH_TX_CQ_CONS_COS0    5
 944
 945#define HC_INDEX_ETH_TX_CQ_CONS_COS1    6
 946
 947#define HC_INDEX_ETH_TX_CQ_CONS_COS2    7
 948
 949#define HC_INDEX_ETH_FIRST_TX_CQ_CONS   HC_INDEX_ETH_TX_CQ_CONS_COS0
 950
 951#define BNX2X_RX_SB_INDEX \
 952        (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
 953
 954#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
 955
 956#define BNX2X_TX_SB_INDEX_COS0 \
 957        (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
 958
 959/* end of fast path */
 960
 961/* common */
 962
 963struct bnx2x_common {
 964
 965        uint32_t                        chip_id;
 966/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
 967#define CHIP_ID(bp)                     (bp->common.chip_id & 0xfffffff0)
 968
 969#define CHIP_NUM(bp)                    (bp->common.chip_id >> 16)
 970#define CHIP_NUM_57710                  0x164e
 971#define CHIP_NUM_57711                  0x164f
 972#define CHIP_NUM_57711E                 0x1650
 973#define CHIP_NUM_57712                  0x1662
 974#define CHIP_NUM_57712_MF               0x1663
 975#define CHIP_NUM_57712_VF               0x166f
 976#define CHIP_NUM_57713                  0x1651
 977#define CHIP_NUM_57713E                 0x1652
 978#define CHIP_NUM_57800                  0x168a
 979#define CHIP_NUM_57800_MF               0x16a5
 980#define CHIP_NUM_57800_VF               0x16a9
 981#define CHIP_NUM_57810                  0x168e
 982#define CHIP_NUM_57810_MF               0x16ae
 983#define CHIP_NUM_57810_VF               0x16af
 984#define CHIP_NUM_57811                  0x163d
 985#define CHIP_NUM_57811_MF               0x163e
 986#define CHIP_NUM_57811_VF               0x163f
 987#define CHIP_NUM_57840_OBSOLETE         0x168d
 988#define CHIP_NUM_57840_MF_OBSOLETE      0x16ab
 989#define CHIP_NUM_57840_4_10             0x16a1
 990#define CHIP_NUM_57840_2_20             0x16a2
 991#define CHIP_NUM_57840_MF               0x16a4
 992#define CHIP_NUM_57840_VF               0x16ad
 993#define CHIP_IS_E1(bp)                  (CHIP_NUM(bp) == CHIP_NUM_57710)
 994#define CHIP_IS_57711(bp)               (CHIP_NUM(bp) == CHIP_NUM_57711)
 995#define CHIP_IS_57711E(bp)              (CHIP_NUM(bp) == CHIP_NUM_57711E)
 996#define CHIP_IS_57712(bp)               (CHIP_NUM(bp) == CHIP_NUM_57712)
 997#define CHIP_IS_57712_VF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57712_VF)
 998#define CHIP_IS_57712_MF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
 999#define CHIP_IS_57800(bp)               (CHIP_NUM(bp) == CHIP_NUM_57800)
1000#define CHIP_IS_57800_MF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
1001#define CHIP_IS_57800_VF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57800_VF)
1002#define CHIP_IS_57810(bp)               (CHIP_NUM(bp) == CHIP_NUM_57810)
1003#define CHIP_IS_57810_MF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
1004#define CHIP_IS_57810_VF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57810_VF)
1005#define CHIP_IS_57811(bp)               (CHIP_NUM(bp) == CHIP_NUM_57811)
1006#define CHIP_IS_57811_MF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
1007#define CHIP_IS_57811_VF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57811_VF)
1008#define CHIP_IS_57840(bp)               \
1009                ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
1010                 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
1011                 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
1012#define CHIP_IS_57840_MF(bp)    ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
1013                                 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
1014#define CHIP_IS_57840_VF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
1015#define CHIP_IS_E1H(bp)                 (CHIP_IS_57711(bp) || \
1016                                         CHIP_IS_57711E(bp))
1017#define CHIP_IS_57811xx(bp)             (CHIP_IS_57811(bp) || \
1018                                         CHIP_IS_57811_MF(bp) || \
1019                                         CHIP_IS_57811_VF(bp))
1020#define CHIP_IS_E2(bp)                  (CHIP_IS_57712(bp) || \
1021                                         CHIP_IS_57712_MF(bp) || \
1022                                         CHIP_IS_57712_VF(bp))
1023#define CHIP_IS_E3(bp)                  (CHIP_IS_57800(bp) || \
1024                                         CHIP_IS_57800_MF(bp) || \
1025                                         CHIP_IS_57800_VF(bp) || \
1026                                         CHIP_IS_57810(bp) || \
1027                                         CHIP_IS_57810_MF(bp) || \
1028                                         CHIP_IS_57810_VF(bp) || \
1029                                         CHIP_IS_57811xx(bp) || \
1030                                         CHIP_IS_57840(bp) || \
1031                                         CHIP_IS_57840_MF(bp) || \
1032                                         CHIP_IS_57840_VF(bp))
1033#define CHIP_IS_E1x(bp)                 (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
1034#define USES_WARPCORE(bp)               (CHIP_IS_E3(bp))
1035#define IS_E1H_OFFSET                   (!CHIP_IS_E1(bp))
1036
1037#define CHIP_REV_SHIFT                  12
1038#define CHIP_REV_MASK                   (0xF << CHIP_REV_SHIFT)
1039#define CHIP_REV_VAL(bp)                (bp->common.chip_id & CHIP_REV_MASK)
1040#define CHIP_REV_Ax                     (0x0 << CHIP_REV_SHIFT)
1041#define CHIP_REV_Bx                     (0x1 << CHIP_REV_SHIFT)
1042/* assume maximum 5 revisions */
1043#define CHIP_REV_IS_SLOW(bp)            (CHIP_REV_VAL(bp) > 0x00005000)
1044/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
1045#define CHIP_REV_IS_EMUL(bp)            ((CHIP_REV_IS_SLOW(bp)) && \
1046                                         !(CHIP_REV_VAL(bp) & 0x00001000))
1047/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
1048#define CHIP_REV_IS_FPGA(bp)            ((CHIP_REV_IS_SLOW(bp)) && \
1049                                         (CHIP_REV_VAL(bp) & 0x00001000))
1050
1051#define CHIP_TIME(bp)                   ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
1052                                        ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
1053
1054#define CHIP_METAL(bp)                  (bp->common.chip_id & 0x00000ff0)
1055#define CHIP_BOND_ID(bp)                (bp->common.chip_id & 0x0000000f)
1056#define CHIP_REV_SIM(bp)                (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
1057                                           (CHIP_REV_SHIFT + 1)) \
1058                                                << CHIP_REV_SHIFT)
1059#define CHIP_REV(bp)                    (CHIP_REV_IS_SLOW(bp) ? \
1060                                                CHIP_REV_SIM(bp) :\
1061                                                CHIP_REV_VAL(bp))
1062#define CHIP_IS_E3B0(bp)                (CHIP_IS_E3(bp) && \
1063                                         (CHIP_REV(bp) == CHIP_REV_Bx))
1064#define CHIP_IS_E3A0(bp)                (CHIP_IS_E3(bp) && \
1065                                         (CHIP_REV(bp) == CHIP_REV_Ax))
1066/* This define is used in two main places:
1067 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher
1068 * to nic-only mode or to offload mode. Offload mode is configured if either the
1069 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
1070 * registered for this port (which means that the user wants storage services).
1071 * 2. During cnic-related load, to know if offload mode is already configured in
1072 * the HW or needs to be configured.
1073 * Since the transition from nic-mode to offload-mode in HW causes traffic
1074 * corruption, nic-mode is configured only in ports on which storage services
1075 * where never requested.
1076 */
1077#define CONFIGURE_NIC_MODE(bp)          (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
1078
1079        int                     flash_size;
1080#define BNX2X_NVRAM_1MB_SIZE                    0x20000 /* 1M bit in bytes */
1081#define BNX2X_NVRAM_TIMEOUT_COUNT               30000
1082#define BNX2X_NVRAM_PAGE_SIZE                   256
1083
1084        uint32_t                        shmem_base;
1085        uint32_t                        shmem2_base;
1086        uint32_t                        mf_cfg_base;
1087        uint32_t                        mf2_cfg_base;
1088
1089        uint32_t                        hw_config;
1090
1091        uint32_t                        bc_ver;
1092
1093        uint8_t                 int_block;
1094#define INT_BLOCK_HC                    0
1095#define INT_BLOCK_IGU                   1
1096#define INT_BLOCK_MODE_NORMAL           0
1097#define INT_BLOCK_MODE_BW_COMP          2
1098#define CHIP_INT_MODE_IS_NBC(bp)                \
1099                        (!CHIP_IS_E1x(bp) &&    \
1100                        !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
1101#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
1102
1103        uint8_t                 chip_port_mode;
1104#define CHIP_4_PORT_MODE                        0x0
1105#define CHIP_2_PORT_MODE                        0x1
1106#define CHIP_PORT_MODE_NONE                     0x2
1107#define CHIP_MODE(bp)                   (bp->common.chip_port_mode)
1108#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
1109
1110        uint32_t                        boot_mode;
1111};
1112
1113/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
1114#define BNX2X_IGU_STAS_MSG_VF_CNT 64
1115#define BNX2X_IGU_STAS_MSG_PF_CNT 4
1116
1117#define MAX_IGU_ATTN_ACK_TO       100
1118/* end of common */
1119
1120/* port */
1121
1122struct bnx2x_port {
1123        uint32_t                        pmf;
1124
1125        uint32_t                        link_config[LINK_CONFIG_SIZE];
1126
1127        uint32_t                        supported[LINK_CONFIG_SIZE];
1128/* link settings - missing defines */
1129#define SUPPORTED_2500baseX_Full        (1 << 15)
1130
1131        uint32_t                        advertising[LINK_CONFIG_SIZE];
1132/* link settings - missing defines */
1133#define ADVERTISED_2500baseX_Full       (1 << 15)
1134
1135        uint32_t                        phy_addr;
1136
1137        /* used to synchronize phy accesses */
1138        qlock_t         phy_mutex;
1139
1140        uint32_t                        port_stx;
1141
1142        struct nig_stats        old_nig_stats;
1143};
1144
1145/* end of port */
1146
1147#define STATS_OFFSET32(stat_name) \
1148                        (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
1149
1150/* slow path */
1151#define BNX2X_MAX_NUM_OF_VFS    64
1152#define BNX2X_VF_CID_WND        4 /* log num of queues per VF. HW config. */
1153#define BNX2X_CIDS_PER_VF       (1 << BNX2X_VF_CID_WND)
1154
1155/* We need to reserve doorbell addresses for all VF and queue combinations */
1156#define BNX2X_VF_CIDS           (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
1157
1158/* The doorbell is configured to have the same number of CIDs for PFs and for
1159 * VFs. For this reason the PF CID zone is as large as the VF zone.
1160 */
1161#define BNX2X_FIRST_VF_CID      BNX2X_VF_CIDS
1162#define BNX2X_MAX_NUM_VF_QUEUES 64
1163#define BNX2X_VF_ID_INVALID     0xFF
1164
1165/* the number of VF CIDS multiplied by the amount of bytes reserved for each
1166 * cid must not exceed the size of the VF doorbell
1167 */
1168#define BNX2X_VF_BAR_SIZE       512
1169#if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT))
1170#error "VF doorbell bar size is 512"
1171#endif
1172
1173/*
1174 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
1175 * control by the number of fast-path status blocks supported by the
1176 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
1177 * status block represents an independent interrupts context that can
1178 * serve a regular L2 networking queue. However special L2 queues such
1179 * as the FCoE queue do not require a FP-SB and other components like
1180 * the CNIC may consume FP-SB reducing the number of possible L2 queues
1181 *
1182 * If the maximum number of FP-SB available is X then:
1183 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
1184 *    regular L2 queues is Y=X-1
1185 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
1186 * c. If the FCoE L2 queue is supported the actual number of L2 queues
1187 *    is Y+1
1188 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
1189 *    slow-path interrupts) or Y+2 if CNIC is supported (one additional
1190 *    FP interrupt context for the CNIC).
1191 * e. The number of HW context (CID count) is always X or X+1 if FCoE
1192 *    L2 queue is supported. The cid for the FCoE L2 queue is always X.
1193 */
1194
1195/* fast-path interrupt contexts E1x */
1196#define FP_SB_MAX_E1x           16
1197/* fast-path interrupt contexts E2 */
1198#define FP_SB_MAX_E2            HC_SB_MAX_SB_E2
1199
1200union cdu_context {
1201        struct eth_context eth;
1202        char pad[1024];
1203};
1204
1205/* CDU host DB constants */
1206#define CDU_ILT_PAGE_SZ_HW      2
1207#define CDU_ILT_PAGE_SZ         (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1208#define ILT_PAGE_CIDS           (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1209
1210#define CNIC_ISCSI_CID_MAX      256
1211#define CNIC_FCOE_CID_MAX       2048
1212#define CNIC_CID_MAX            (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1213#define CNIC_ILT_LINES          DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1214
1215#define QM_ILT_PAGE_SZ_HW       0
1216#define QM_ILT_PAGE_SZ          (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1217#define QM_CID_ROUND            1024
1218
1219/* TM (timers) host DB constants */
1220#define TM_ILT_PAGE_SZ_HW       0
1221#define TM_ILT_PAGE_SZ          (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1222#define TM_CONN_NUM             (BNX2X_FIRST_VF_CID + \
1223                                 BNX2X_VF_CIDS + \
1224                                 CNIC_ISCSI_CID_MAX)
1225#define TM_ILT_SZ               (8 * TM_CONN_NUM)
1226#define TM_ILT_LINES            DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1227
1228/* SRC (Searcher) host DB constants */
1229#define SRC_ILT_PAGE_SZ_HW      0
1230#define SRC_ILT_PAGE_SZ         (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1231#define SRC_HASH_BITS           10
1232#define SRC_CONN_NUM            (1 << SRC_HASH_BITS) /* 1024 */
1233#define SRC_ILT_SZ              (sizeof(struct src_ent) * SRC_CONN_NUM)
1234#define SRC_T2_SZ               SRC_ILT_SZ
1235#define SRC_ILT_LINES           DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1236
1237#define MAX_DMAE_C              8
1238
1239/* DMA memory not used in fastpath */
1240struct bnx2x_slowpath {
1241        union {
1242                struct mac_configuration_cmd            e1x;
1243                struct eth_classify_rules_ramrod_data   e2;
1244        } mac_rdata;
1245
1246        union {
1247                struct tstorm_eth_mac_filter_config     e1x;
1248                struct eth_filter_rules_ramrod_data     e2;
1249        } rx_mode_rdata;
1250
1251        union {
1252                struct mac_configuration_cmd            e1;
1253                struct eth_multicast_rules_ramrod_data  e2;
1254        } mcast_rdata;
1255
1256        struct eth_rss_update_ramrod_data       rss_rdata;
1257
1258        /* Queue State related ramrods are always sent under rtnl_lock */
1259        union {
1260                struct client_init_ramrod_data  init_data;
1261                struct client_update_ramrod_data update_data;
1262                struct tpa_update_ramrod_data tpa_data;
1263        } q_rdata;
1264
1265        union {
1266                struct function_start_data      func_start;
1267                /* pfc configuration for DCBX ramrod */
1268                struct flow_control_configuration pfc_config;
1269        } func_rdata;
1270
1271        /* afex ramrod can not be a part of func_rdata union because these
1272         * events might arrive in parallel to other events from func_rdata.
1273         * Therefore, if they would have been defined in the same union,
1274         * data can get corrupted.
1275         */
1276        union {
1277                struct afex_vif_list_ramrod_data        viflist_data;
1278                struct function_update_data             func_update;
1279        } func_afex_rdata;
1280
1281        /* used by dmae command executer */
1282        struct dmae_command             dmae[MAX_DMAE_C];
1283
1284        uint32_t                                stats_comp;
1285        union mac_stats                 mac_stats;
1286        struct nig_stats                nig_stats;
1287        struct host_port_stats          port_stats;
1288        struct host_func_stats          func_stats;
1289
1290        uint32_t                                wb_comp;
1291        uint32_t                                wb_data[4];
1292
1293        union drv_info_to_mcp           drv_info_to_mcp;
1294};
1295
1296#define bnx2x_sp(bp, var)               (&bp->slowpath->var)
1297#define bnx2x_sp_mapping(bp, var) \
1298                (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1299
1300/* attn group wiring */
1301#define MAX_DYNAMIC_ATTN_GRPS           8
1302
1303struct attn_route {
1304        uint32_t sig[5];
1305};
1306
1307struct iro {
1308        uint32_t base;
1309        uint16_t m1;
1310        uint16_t m2;
1311        uint16_t m3;
1312        uint16_t size;
1313};
1314
1315struct hw_context {
1316        union cdu_context *vcxt;
1317        dma_addr_t cxt_mapping;
1318        size_t size;
1319};
1320
1321/* forward */
1322struct bnx2x_ilt;
1323
1324struct bnx2x_vfdb;
1325
1326enum bnx2x_recovery_state {
1327        BNX2X_RECOVERY_DONE,
1328        BNX2X_RECOVERY_INIT,
1329        BNX2X_RECOVERY_WAIT,
1330        BNX2X_RECOVERY_FAILED,
1331        BNX2X_RECOVERY_NIC_LOADING
1332};
1333
1334/*
1335 * Event queue (EQ or event ring) MC hsi
1336 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1337 */
1338#define NUM_EQ_PAGES            1
1339#define EQ_DESC_CNT_PAGE        (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1340#define EQ_DESC_MAX_PAGE        (EQ_DESC_CNT_PAGE - 1)
1341#define NUM_EQ_DESC             (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1342#define EQ_DESC_MASK            (NUM_EQ_DESC - 1)
1343#define MAX_EQ_AVAIL            (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1344
1345/* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1346#define NEXT_EQ_IDX(x)          ((((x) & EQ_DESC_MAX_PAGE) == \
1347                                  (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1348
1349/* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1350#define EQ_DESC(x)              ((x) & EQ_DESC_MASK)
1351
1352#define BNX2X_EQ_INDEX \
1353        (&bp->def_status_blk->sp_sb.\
1354        index_values[HC_SP_INDEX_EQ_CONS])
1355
1356/* This is a data that will be used to create a link report message.
1357 * We will keep the data used for the last link report in order
1358 * to prevent reporting the same link parameters twice.
1359 */
1360struct bnx2x_link_report_data {
1361        uint16_t line_speed;                    /* Effective line speed */
1362        unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1363};
1364
1365enum {
1366        BNX2X_LINK_REPORT_FD,           /* Full DUPLEX */
1367        BNX2X_LINK_REPORT_LINK_DOWN,
1368        BNX2X_LINK_REPORT_RX_FC_ON,
1369        BNX2X_LINK_REPORT_TX_FC_ON,
1370};
1371
1372enum {
1373        BNX2X_PORT_QUERY_IDX,
1374        BNX2X_PF_QUERY_IDX,
1375        BNX2X_FCOE_QUERY_IDX,
1376        BNX2X_FIRST_QUEUE_QUERY_IDX,
1377};
1378
1379struct bnx2x_fw_stats_req {
1380        struct stats_query_header hdr;
1381        struct stats_query_entry query[FP_SB_MAX_E1x+
1382                BNX2X_FIRST_QUEUE_QUERY_IDX];
1383};
1384
1385struct bnx2x_fw_stats_data {
1386        struct stats_counter            storm_counters;
1387        struct per_port_stats           port;
1388        struct per_pf_stats             pf;
1389        struct fcoe_statistics_params   fcoe;
1390        struct per_queue_stats          queue_stats[1];
1391};
1392
1393/* Public slow path states */
1394enum sp_rtnl_flag {
1395        BNX2X_SP_RTNL_SETUP_TC,
1396        BNX2X_SP_RTNL_TX_TIMEOUT,
1397        BNX2X_SP_RTNL_FAN_FAILURE,
1398        BNX2X_SP_RTNL_AFEX_F_UPDATE,
1399        BNX2X_SP_RTNL_ENABLE_SRIOV,
1400        BNX2X_SP_RTNL_VFPF_MCAST,
1401        BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
1402        BNX2X_SP_RTNL_RX_MODE,
1403        BNX2X_SP_RTNL_HYPERVISOR_VLAN,
1404        BNX2X_SP_RTNL_TX_STOP,
1405        BNX2X_SP_RTNL_GET_DRV_VERSION,
1406};
1407
1408enum bnx2x_iov_flag {
1409        BNX2X_IOV_HANDLE_VF_MSG,
1410        BNX2X_IOV_HANDLE_FLR,
1411};
1412
1413struct bnx2x_prev_path_list {
1414        struct list_head list;
1415        uint8_t bus;
1416        uint8_t slot;
1417        uint8_t path;
1418        uint8_t aer;
1419        uint8_t undi;
1420};
1421
1422struct bnx2x_sp_objs {
1423        /* MACs object */
1424        struct bnx2x_vlan_mac_obj mac_obj;
1425
1426        /* Queue State object */
1427        struct bnx2x_queue_sp_obj q_obj;
1428};
1429
1430struct bnx2x_fp_stats {
1431        struct tstorm_per_queue_stats old_tclient;
1432        struct ustorm_per_queue_stats old_uclient;
1433        struct xstorm_per_queue_stats old_xclient;
1434        struct bnx2x_eth_q_stats eth_q_stats;
1435        struct bnx2x_eth_q_stats_old eth_q_stats_old;
1436};
1437
1438enum {
1439        SUB_MF_MODE_UNKNOWN = 0,
1440        SUB_MF_MODE_UFP,
1441        SUB_MF_MODE_NPAR1_DOT_5,
1442};
1443
1444struct bnx2x {
1445/* COMPAT GARBAGE */
1446        struct pci_device                       *pcidev;
1447        struct ether                            *edev;
1448        TAILQ_ENTRY(bnx2x)                      link9ns;
1449        const struct pci_device_id      *pci_id;                        /* for navigating pci/pnp */
1450        bool                                            attached;
1451
1452        /* These are in Linux's net_device */
1453        void                                            *mem_start;
1454        void                                            *mem_end;
1455        void                                            *base_addr;
1456
1457        /* e.g. */
1458        bool                                            active;
1459        void                                            *mmio;
1460        spinlock_t                                      imlock;                         /* interrupt mask lock */
1461        spinlock_t                                      tlock;                          /* transmit lock */
1462        qlock_t                                         slock;                          /* stats */
1463        qlock_t                                         alock;                          /* attach */
1464        struct rendez                           rrendez;                        /* rproc rendez */
1465#define Nstatistics 2
1466        unsigned int                            statistics[Nstatistics];
1467
1468        /* Fields used in the tx and intr/napi performance paths
1469         * are grouped together in the beginning of the structure
1470         */
1471        struct bnx2x_fastpath   *fp;
1472        struct bnx2x_sp_objs    *sp_objs;
1473        struct bnx2x_fp_stats   *fp_stats;
1474        struct bnx2x_fp_txdata  *bnx2x_txq;
1475        void __iomem            *regview;
1476        void __iomem            *doorbells;
1477        uint16_t                        db_size;
1478
1479        uint8_t                 pf_num; /* absolute PF number */
1480        uint8_t                 pfid;   /* per-path PF number */
1481        int                     base_fw_ndsb; /**/
1482#define BP_PATH(bp)                     (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1483#define BP_PORT(bp)                     (bp->pfid & 1)
1484#define BP_FUNC(bp)                     (bp->pfid)
1485#define BP_ABS_FUNC(bp)                 (bp->pf_num)
1486#define BP_VN(bp)                       ((bp)->pfid >> 1)
1487#define BP_MAX_VN_NUM(bp)               (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1488#define BP_L_ID(bp)                     (BP_VN(bp) << 2)
1489#define BP_FW_MB_IDX_VN(bp, vn)         (BP_PORT(bp) +\
1490          (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2  : 1))
1491#define BP_FW_MB_IDX(bp)                BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1492
1493#ifdef CONFIG_BNX2X_SRIOV
1494        /* protects vf2pf mailbox from simultaneous access */
1495        qlock_t         vf2pf_mutex;
1496        /* vf pf channel mailbox contains request and response buffers */
1497        struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1498        dma_addr_t              vf2pf_mbox_mapping;
1499
1500        /* we set aside a copy of the acquire response */
1501        struct pfvf_acquire_resp_tlv acquire_resp;
1502
1503        /* bulletin board for messages from pf to vf */
1504        union pf_vf_bulletin   *pf2vf_bulletin;
1505        dma_addr_t              pf2vf_bulletin_mapping;
1506
1507        union pf_vf_bulletin            shadow_bulletin;
1508        struct pf_vf_bulletin_content   old_bulletin;
1509
1510        uint16_t requested_nr_virtfn;
1511#endif /* CONFIG_BNX2X_SRIOV */
1512
1513        struct ether    *dev;
1514        struct pci_device               *pdev;
1515
1516        const struct iro        *iro_arr;
1517#define IRO (bp->iro_arr)
1518
1519        enum bnx2x_recovery_state recovery_state;
1520        int                     is_leader;
1521        struct msix_entry       *msix_table;
1522
1523        int                     tx_ring_size;
1524
1525/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1526#define ETH_OVREHEAD            (ETHERHDRSIZE + 8 + 8)
1527#define ETH_MIN_PACKET_SIZE             60
1528#define ETH_MAX_PACKET_SIZE             1500
1529#define ETH_MAX_JUMBO_PACKET_SIZE       9600
1530/* TCP with Timestamp Option (32) + IPv6 (40) */
1531#define ETH_MAX_TPA_HEADER_SIZE         72
1532
1533        /* Max supported alignment is 256 (8 shift)
1534         * minimal alignment shift 6 is optimal for 57xxx HW performance
1535         */
1536#define BNX2X_RX_ALIGN_SHIFT            MAX(6, MIN(8, L1_CACHE_SHIFT))
1537
1538        /* FW uses 2 Cache lines Alignment for start packet and size
1539         *
1540         * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1541         * at the end of skb->data, to avoid wasting a full cache line.
1542         * This reduces memory use (skb->truesize).
1543         */
1544#define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1545
1546#if 0 // AKAROS_PORT might have issues with block sizes
1547#define BNX2X_FW_RX_ALIGN_END                                   \
1548        MAX_T(uint64_t, 1UL << BNX2X_RX_ALIGN_SHIFT,                    \
1549            SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1550#else
1551#define BNX2X_FW_RX_ALIGN_END                                   \
1552        MAX_T(uint64_t, 1UL << BNX2X_RX_ALIGN_SHIFT, 0)
1553#endif
1554
1555#define BNX2X_PXP_DRAM_ALIGN            (BNX2X_RX_ALIGN_SHIFT - 5)
1556
1557        struct host_sp_status_block *def_status_blk;
1558#define DEF_SB_IGU_ID                   16
1559#define DEF_SB_ID                       HC_SP_SB_ID
1560        __le16                  def_idx;
1561        __le16                  def_att_idx;
1562        uint32_t                        attn_state;
1563        struct attn_route       attn_group[MAX_DYNAMIC_ATTN_GRPS];
1564
1565        /* slow path ring */
1566        struct eth_spe          *spq;
1567        dma_addr_t              spq_mapping;
1568        uint16_t                        spq_prod_idx;
1569        struct eth_spe          *spq_prod_bd;
1570        struct eth_spe          *spq_last_bd;
1571        __le16                  *dsb_sp_prod;
1572        atomic_t                cq_spq_left; /* ETH_XXX ramrods credit */
1573        /* used to synchronize spq accesses */
1574        spinlock_t              spq_lock;
1575
1576        /* event queue */
1577        union event_ring_elem   *eq_ring;
1578        dma_addr_t              eq_mapping;
1579        uint16_t                        eq_prod;
1580        uint16_t                        eq_cons;
1581        __le16                  *eq_cons_sb;
1582        atomic_t                eq_spq_left; /* COMMON_XXX ramrods credit */
1583
1584        /* Counter for marking that there is a STAT_QUERY ramrod pending */
1585        uint16_t                        stats_pending;
1586        /*  Counter for completed statistics ramrods */
1587        uint16_t                        stats_comp;
1588
1589        /* End of fields used in the performance code paths */
1590
1591        int                     panic;
1592        int                     msg_enable;
1593
1594        uint32_t                        flags;
1595#define PCIX_FLAG                       (1 << 0)
1596#define PCI_32BIT_FLAG                  (1 << 1)
1597#define ONE_PORT_FLAG                   (1 << 2)
1598#define NO_WOL_FLAG                     (1 << 3)
1599#define USING_MSIX_FLAG                 (1 << 5)
1600#define USING_MSI_FLAG                  (1 << 6)
1601#define DISABLE_MSI_FLAG                (1 << 7)
1602#define TPA_ENABLE_FLAG                 (1 << 8)
1603#define NO_MCP_FLAG                     (1 << 9)
1604#define GRO_ENABLE_FLAG                 (1 << 10)
1605#define MF_FUNC_DIS                     (1 << 11)
1606#define OWN_CNIC_IRQ                    (1 << 12)
1607#define NO_ISCSI_OOO_FLAG               (1 << 13)
1608#define NO_ISCSI_FLAG                   (1 << 14)
1609#define NO_FCOE_FLAG                    (1 << 15)
1610#define BC_SUPPORTS_PFC_STATS           (1 << 17)
1611#define TX_SWITCHING                    (1 << 18)
1612#define BC_SUPPORTS_FCOE_FEATURES       (1 << 19)
1613#define USING_SINGLE_MSIX_FLAG          (1 << 20)
1614#define BC_SUPPORTS_DCBX_MSG_NON_PMF    (1 << 21)
1615#define IS_VF_FLAG                      (1 << 22)
1616#define BC_SUPPORTS_RMMOD_CMD           (1 << 23)
1617#define HAS_PHYS_PORT_ID                (1 << 24)
1618#define AER_ENABLED                     (1 << 25)
1619#define PTP_SUPPORTED                   (1 << 26)
1620#define TX_TIMESTAMPING_EN              (1 << 27)
1621
1622#define BP_NOMCP(bp)                    ((bp)->flags & NO_MCP_FLAG)
1623
1624#ifdef CONFIG_BNX2X_SRIOV
1625#define IS_VF(bp)                       ((bp)->flags & IS_VF_FLAG)
1626#define IS_PF(bp)                       (!((bp)->flags & IS_VF_FLAG))
1627#else
1628#define IS_VF(bp)                       false
1629#define IS_PF(bp)                       true
1630#endif
1631
1632#define NO_ISCSI(bp)            ((bp)->flags & NO_ISCSI_FLAG)
1633#define NO_ISCSI_OOO(bp)        ((bp)->flags & NO_ISCSI_OOO_FLAG)
1634#define NO_FCOE(bp)             ((bp)->flags & NO_FCOE_FLAG)
1635
1636        uint8_t                 cnic_support;
1637        bool                    cnic_enabled;
1638        bool                    cnic_loaded;
1639        struct cnic_eth_dev     *(*cnic_probe)(struct ether *);
1640
1641        /* Flag that indicates that we can start looking for FCoE L2 queue
1642         * completions in the default status block.
1643         */
1644        bool                    fcoe_init;
1645
1646        int                     mrrs;
1647
1648        struct delayed_work     sp_task;
1649        struct delayed_work     iov_task;
1650
1651        atomic_t                interrupt_occurred;
1652        struct delayed_work     sp_rtnl_task;
1653
1654        struct delayed_work     period_task;
1655        struct alarm_waiter timer;
1656        int                     current_interval;
1657
1658        uint16_t                        fw_seq;
1659        uint16_t                        fw_drv_pulse_wr_seq;
1660        uint32_t                        func_stx;
1661
1662        struct link_params      link_params;
1663        struct link_vars        link_vars;
1664        uint32_t                        link_cnt;
1665        struct bnx2x_link_report_data last_reported_link;
1666
1667        //struct mdio_if_info   mdio;
1668
1669        struct bnx2x_common     common;
1670        struct bnx2x_port       port;
1671
1672        struct cmng_init        cmng;
1673
1674        uint32_t                        mf_config[E1HVN_MAX];
1675        uint32_t                        mf_ext_config;
1676        uint32_t                        path_has_ovlan; /* E3 */
1677        uint16_t                        mf_ov;
1678        uint8_t                 mf_mode;
1679#define IS_MF(bp)               (bp->mf_mode != 0)
1680#define IS_MF_SI(bp)            (bp->mf_mode == MULTI_FUNCTION_SI)
1681#define IS_MF_SD(bp)            (bp->mf_mode == MULTI_FUNCTION_SD)
1682#define IS_MF_AFEX(bp)          (bp->mf_mode == MULTI_FUNCTION_AFEX)
1683        uint8_t                 mf_sub_mode;
1684#define IS_MF_UFP(bp)           (IS_MF_SD(bp) && \
1685                                 bp->mf_sub_mode == SUB_MF_MODE_UFP)
1686
1687        uint8_t                 wol;
1688
1689        int                     rx_ring_size;
1690
1691        uint16_t                        tx_quick_cons_trip_int;
1692        uint16_t                        tx_quick_cons_trip;
1693        uint16_t                        tx_ticks_int;
1694        uint16_t                        tx_ticks;
1695
1696        uint16_t                        rx_quick_cons_trip_int;
1697        uint16_t                        rx_quick_cons_trip;
1698        uint16_t                        rx_ticks_int;
1699        uint16_t                        rx_ticks;
1700/* Maximal coalescing timeout in us */
1701#define BNX2X_MAX_COALESCE_TOUT         (0xff*BNX2X_BTR)
1702
1703        uint32_t                        lin_cnt;
1704
1705        uint16_t                        state;
1706#define BNX2X_STATE_CLOSED              0
1707#define BNX2X_STATE_OPENING_WAIT4_LOAD  0x1000
1708#define BNX2X_STATE_OPENING_WAIT4_PORT  0x2000
1709#define BNX2X_STATE_OPEN                0x3000
1710#define BNX2X_STATE_CLOSING_WAIT4_HALT  0x4000
1711#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1712
1713#define BNX2X_STATE_DIAG                0xe000
1714#define BNX2X_STATE_ERROR               0xf000
1715
1716#define BNX2X_MAX_PRIORITY              8
1717        int                     num_queues;
1718        unsigned int                    num_ethernet_queues;
1719        unsigned int                    num_cnic_queues;
1720        int                     disable_tpa;
1721
1722        uint32_t                        rx_mode;
1723#define BNX2X_RX_MODE_NONE              0
1724#define BNX2X_RX_MODE_NORMAL            1
1725#define BNX2X_RX_MODE_ALLMULTI          2
1726#define BNX2X_RX_MODE_PROMISC           3
1727#define BNX2X_MAX_MULTICAST             64
1728
1729        uint8_t                 igu_dsb_id;
1730        uint8_t                 igu_base_sb;
1731        uint8_t                 igu_sb_cnt;
1732        uint8_t                 min_msix_vec_cnt;
1733
1734        uint32_t                        igu_base_addr;
1735        dma_addr_t              def_status_blk_mapping;
1736
1737        struct bnx2x_slowpath   *slowpath;
1738        dma_addr_t              slowpath_mapping;
1739
1740        /* Mechanism protecting the drv_info_to_mcp */
1741        qlock_t         drv_info_mutex;
1742        bool                    drv_info_mng_owner;
1743
1744        /* Total number of FW statistics requests */
1745        uint8_t                 fw_stats_num;
1746
1747        /*
1748         * This is a memory buffer that will contain both statistics
1749         * ramrod request and data.
1750         */
1751        void                    *fw_stats;
1752        dma_addr_t              fw_stats_mapping;
1753
1754        /*
1755         * FW statistics request shortcut (points at the
1756         * beginning of fw_stats buffer).
1757         */
1758        struct bnx2x_fw_stats_req       *fw_stats_req;
1759        dma_addr_t                      fw_stats_req_mapping;
1760        int                             fw_stats_req_sz;
1761
1762        /*
1763         * FW statistics data shortcut (points at the beginning of
1764         * fw_stats buffer + fw_stats_req_sz).
1765         */
1766        struct bnx2x_fw_stats_data      *fw_stats_data;
1767        dma_addr_t                      fw_stats_data_mapping;
1768        int                             fw_stats_data_sz;
1769
1770        /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB
1771         * context size we need 8 ILT entries.
1772         */
1773#define ILT_MAX_L2_LINES        32
1774        struct hw_context       context[ILT_MAX_L2_LINES];
1775
1776        struct bnx2x_ilt        *ilt;
1777#define BP_ILT(bp)              ((bp)->ilt)
1778#define ILT_MAX_LINES           256
1779/*
1780 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1781 * to CNIC.
1782 */
1783#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1784
1785/*
1786 * Maximum CID count that might be required by the bnx2x:
1787 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1788 */
1789
1790#define BNX2X_L2_CID_COUNT(bp)  (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1791                                + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1792#define BNX2X_L2_MAX_CID(bp)    (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1793                                + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1794#define L2_ILT_LINES(bp)        (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1795                                        ILT_PAGE_CIDS))
1796
1797        int                     qm_cid_count;
1798
1799        bool                    dropless_fc;
1800
1801        void                    *t2;
1802        dma_addr_t              t2_mapping;
1803        struct cnic_ops __rcu   *cnic_ops;
1804        void                    *cnic_data;
1805        uint32_t                        cnic_tag;
1806        struct cnic_eth_dev     cnic_eth_dev;
1807        union host_hc_status_block cnic_sb;
1808        dma_addr_t              cnic_sb_mapping;
1809        struct eth_spe          *cnic_kwq;
1810        struct eth_spe          *cnic_kwq_prod;
1811        struct eth_spe          *cnic_kwq_cons;
1812        struct eth_spe          *cnic_kwq_last;
1813        uint16_t                        cnic_kwq_pending;
1814        uint16_t                        cnic_spq_pending;
1815        uint8_t                 fip_mac[Eaddrlen];
1816        qlock_t         cnic_mutex;
1817        struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1818
1819        /* Start index of the "special" (CNIC related) L2 clients */
1820        uint8_t                         cnic_base_cl_id;
1821
1822        int                     dmae_ready;
1823        /* used to synchronize dmae accesses */
1824        spinlock_t              dmae_lock;
1825
1826        /* used to protect the FW mail box */
1827        qlock_t         fw_mb_mutex;
1828
1829        /* used to synchronize stats collecting */
1830        int                     stats_state;
1831
1832        /* used for synchronization of concurrent threads statistics handling */
1833        spinlock_t              stats_lock;
1834
1835        /* used by dmae command loader */
1836        struct dmae_command     stats_dmae;
1837        int                     executer_idx;
1838
1839        uint16_t                        stats_counter;
1840        struct bnx2x_eth_stats  eth_stats;
1841        struct host_func_stats          func_stats;
1842        struct bnx2x_eth_stats_old      eth_stats_old;
1843        struct bnx2x_net_stats_old      net_stats_old;
1844        struct bnx2x_fw_port_stats_old  fw_stats_old;
1845        bool                    stats_init;
1846
1847        struct z_stream_s       *strm;
1848        void                    *gunzip_buf;
1849        dma_addr_t              gunzip_mapping;
1850        int                     gunzip_outlen;
1851#define FW_BUF_SIZE                     0x8000
1852#define GUNZIP_BUF(bp)                  (bp->gunzip_buf)
1853#define GUNZIP_PHYS(bp)                 (bp->gunzip_mapping)
1854#define GUNZIP_OUTLEN(bp)               (bp->gunzip_outlen)
1855
1856        struct raw_op           *init_ops;
1857        /* Init blocks offsets inside init_ops */
1858        uint16_t                        *init_ops_offsets;
1859        /* Data blob - has 32 bit granularity */
1860        uint32_t                        *init_data;
1861        uint32_t                        init_mode_flags;
1862#define INIT_MODE_FLAGS(bp)     (bp->init_mode_flags)
1863        /* Zipped PRAM blobs - raw data */
1864        const uint8_t           *tsem_int_table_data;
1865        const uint8_t           *tsem_pram_data;
1866        const uint8_t           *usem_int_table_data;
1867        const uint8_t           *usem_pram_data;
1868        const uint8_t           *xsem_int_table_data;
1869        const uint8_t           *xsem_pram_data;
1870        const uint8_t           *csem_int_table_data;
1871        const uint8_t           *csem_pram_data;
1872#define INIT_OPS(bp)                    (bp->init_ops)
1873#define INIT_OPS_OFFSETS(bp)            (bp->init_ops_offsets)
1874#define INIT_DATA(bp)                   (bp->init_data)
1875#define INIT_TSEM_INT_TABLE_DATA(bp)    (bp->tsem_int_table_data)
1876#define INIT_TSEM_PRAM_DATA(bp)         (bp->tsem_pram_data)
1877#define INIT_USEM_INT_TABLE_DATA(bp)    (bp->usem_int_table_data)
1878#define INIT_USEM_PRAM_DATA(bp)         (bp->usem_pram_data)
1879#define INIT_XSEM_INT_TABLE_DATA(bp)    (bp->xsem_int_table_data)
1880#define INIT_XSEM_PRAM_DATA(bp)         (bp->xsem_pram_data)
1881#define INIT_CSEM_INT_TABLE_DATA(bp)    (bp->csem_int_table_data)
1882#define INIT_CSEM_PRAM_DATA(bp)         (bp->csem_pram_data)
1883
1884#define PHY_FW_VER_LEN                  20
1885        char                    fw_ver[32];
1886        const struct firmware   *firmware;
1887
1888        struct bnx2x_vfdb       *vfdb;
1889#define IS_SRIOV(bp)            ((bp)->vfdb)
1890
1891        /* DCB support on/off */
1892        uint16_t dcb_state;
1893#define BNX2X_DCB_STATE_OFF                     0
1894#define BNX2X_DCB_STATE_ON                      1
1895
1896        /* DCBX engine mode */
1897        int dcbx_enabled;
1898#define BNX2X_DCBX_ENABLED_OFF                  0
1899#define BNX2X_DCBX_ENABLED_ON_NEG_OFF           1
1900#define BNX2X_DCBX_ENABLED_ON_NEG_ON            2
1901#define BNX2X_DCBX_ENABLED_INVALID              (-1)
1902
1903        bool dcbx_mode_uset;
1904
1905        struct bnx2x_config_dcbx_params         dcbx_config_params;
1906        struct bnx2x_dcbx_port_params           dcbx_port_params;
1907        int                                     dcb_version;
1908
1909        /* CAM credit pools */
1910
1911        /* used only in sriov */
1912        struct bnx2x_credit_pool_obj            vlans_pool;
1913
1914        struct bnx2x_credit_pool_obj            macs_pool;
1915
1916        /* RX_MODE object */
1917        struct bnx2x_rx_mode_obj                rx_mode_obj;
1918
1919        /* MCAST object */
1920        struct bnx2x_mcast_obj                  mcast_obj;
1921
1922        /* RSS configuration object */
1923        struct bnx2x_rss_config_obj             rss_conf_obj;
1924
1925        /* Function State controlling object */
1926        struct bnx2x_func_sp_obj                func_obj;
1927
1928        unsigned long                           sp_state;
1929
1930        /* operation indication for the sp_rtnl task */
1931        unsigned long                           sp_rtnl_state;
1932
1933        /* Indication of the IOV tasks */
1934        unsigned long                           iov_task_state;
1935
1936        /* DCBX Negotiation results */
1937        struct dcbx_features                    dcbx_local_feat;
1938        uint32_t                                        dcbx_error;
1939
1940#ifdef BCM_DCBNL
1941        struct dcbx_features                    dcbx_remote_feat;
1942        uint32_t                                        dcbx_remote_flags;
1943#endif
1944        /* AFEX: store default vlan used */
1945        int                                     afex_def_vlan_tag;
1946        enum mf_cfg_afex_vlan_mode              afex_vlan_mode;
1947        uint32_t                                        pending_max;
1948
1949        /* multiple tx classes of service */
1950        uint8_t                                 max_cos;
1951
1952        /* priority to cos mapping */
1953        uint8_t                                 prio_to_cos[8];
1954
1955        int fp_array_size;
1956        uint32_t dump_preset_idx;
1957        bool                                    stats_started;
1958        struct semaphore                        stats_sema;
1959
1960        uint8_t                                 phys_port_id[Eaddrlen];
1961
1962        struct bnx2x_link_report_data           vf_link_vars;
1963};
1964
1965/* Tx queues may be less or equal to Rx queues */
1966extern int num_queues;
1967#define BNX2X_NUM_QUEUES(bp)    (bp->num_queues)
1968#define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1969#define BNX2X_NUM_NON_CNIC_QUEUES(bp)   (BNX2X_NUM_QUEUES(bp) - \
1970                                         (bp)->num_cnic_queues)
1971#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1972
1973#define is_multi(bp)            (BNX2X_NUM_QUEUES(bp) > 1)
1974
1975#define BNX2X_MAX_QUEUES(bp)    BNX2X_MAX_RSS_COUNT(bp)
1976/* #define is_eth_multi(bp)     (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1977
1978#define RSS_IPV4_CAP_MASK                                               \
1979        TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1980
1981#define RSS_IPV4_TCP_CAP_MASK                                           \
1982        TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1983
1984#define RSS_IPV6_CAP_MASK                                               \
1985        TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1986
1987#define RSS_IPV6_TCP_CAP_MASK                                           \
1988        TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1989
1990/* func init flags */
1991#define FUNC_FLG_RSS            0x0001
1992#define FUNC_FLG_STATS          0x0002
1993/* removed  FUNC_FLG_UNMATCHED  0x0004 */
1994#define FUNC_FLG_TPA            0x0008
1995#define FUNC_FLG_SPQ            0x0010
1996#define FUNC_FLG_LEADING        0x0020  /* PF only */
1997#define FUNC_FLG_LEADING_STATS  0x0040
1998struct bnx2x_func_init_params {
1999        /* dma */
2000        dma_addr_t      fw_stat_map;    /* valid iff FUNC_FLG_STATS */
2001        dma_addr_t      spq_map;        /* valid iff FUNC_FLG_SPQ */
2002
2003        uint16_t                func_flgs;
2004        uint16_t                func_id;        /* abs fid */
2005        uint16_t                pf_id;
2006        uint16_t                spq_prod;       /* valid iff FUNC_FLG_SPQ */
2007};
2008
2009#define for_each_cnic_queue(bp, var) \
2010        for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
2011             (var)++) \
2012                if (skip_queue(bp, var))        \
2013                        continue;               \
2014                else
2015
2016#define for_each_eth_queue(bp, var) \
2017        for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
2018
2019#define for_each_nondefault_eth_queue(bp, var) \
2020        for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
2021
2022#define for_each_queue(bp, var) \
2023        for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2024                if (skip_queue(bp, var))        \
2025                        continue;               \
2026                else
2027
2028/* Skip forwarding FP */
2029#define for_each_valid_rx_queue(bp, var)                        \
2030        for ((var) = 0;                                         \
2031             (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) :  \
2032                      BNX2X_NUM_ETH_QUEUES(bp));                \
2033             (var)++)                                           \
2034                if (skip_rx_queue(bp, var))                     \
2035                        continue;                               \
2036                else
2037
2038#define for_each_rx_queue_cnic(bp, var) \
2039        for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
2040             (var)++) \
2041                if (skip_rx_queue(bp, var))     \
2042                        continue;               \
2043                else
2044
2045#define for_each_rx_queue(bp, var) \
2046        for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2047                if (skip_rx_queue(bp, var))     \
2048                        continue;               \
2049                else
2050
2051/* Skip OOO FP */
2052#define for_each_valid_tx_queue(bp, var)                        \
2053        for ((var) = 0;                                         \
2054             (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) :  \
2055                      BNX2X_NUM_ETH_QUEUES(bp));                \
2056             (var)++)                                           \
2057                if (skip_tx_queue(bp, var))                     \
2058                        continue;                               \
2059                else
2060
2061#define for_each_tx_queue_cnic(bp, var) \
2062        for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
2063             (var)++) \
2064                if (skip_tx_queue(bp, var))     \
2065                        continue;               \
2066                else
2067
2068#define for_each_tx_queue(bp, var) \
2069        for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2070                if (skip_tx_queue(bp, var))     \
2071                        continue;               \
2072                else
2073
2074#define for_each_nondefault_queue(bp, var) \
2075        for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2076                if (skip_queue(bp, var))        \
2077                        continue;               \
2078                else
2079
2080#define for_each_cos_in_tx_queue(fp, var) \
2081        for ((var) = 0; (var) < (fp)->max_cos; (var)++)
2082
2083/* skip rx queue
2084 * if FCOE l2 support is disabled and this is the fcoe L2 queue
2085 */
2086#define skip_rx_queue(bp, idx)  (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2087
2088/* skip tx queue
2089 * if FCOE l2 support is disabled and this is the fcoe L2 queue
2090 */
2091#define skip_tx_queue(bp, idx)  (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2092
2093#define skip_queue(bp, idx)     (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2094
2095/**
2096 * bnx2x_set_mac_one - configure a single MAC address
2097 *
2098 * @bp:                 driver handle
2099 * @mac:                MAC to configure
2100 * @obj:                MAC object handle
2101 * @set:                if 'true' add a new MAC, otherwise - delete
2102 * @mac_type:           the type of the MAC to configure (e.g. ETH, UC list)
2103 * @ramrod_flags:       RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
2104 *
2105 * Configures one MAC according to provided parameters or continues the
2106 * execution of previously scheduled commands if RAMROD_CONT is set in
2107 * ramrod_flags.
2108 *
2109 * Returns zero if operation has successfully completed, a positive value if the
2110 * operation has been successfully scheduled and a negative - if a requested
2111 * operations has failed.
2112 */
2113int bnx2x_set_mac_one(struct bnx2x *bp, uint8_t *mac,
2114                      struct bnx2x_vlan_mac_obj *obj, bool set,
2115                      int mac_type, unsigned long *ramrod_flags);
2116/**
2117 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
2118 *
2119 * @bp:                 driver handle
2120 * @mac_obj:            MAC object handle
2121 * @mac_type:           type of the MACs to clear (BNX2X_XXX_MAC)
2122 * @wait_for_comp:      if 'true' block until completion
2123 *
2124 * Deletes all MACs of the specific type (e.g. ETH, UC list).
2125 *
2126 * Returns zero if operation has successfully completed, a positive value if the
2127 * operation has been successfully scheduled and a negative - if a requested
2128 * operations has failed.
2129 */
2130int bnx2x_del_all_macs(struct bnx2x *bp,
2131                       struct bnx2x_vlan_mac_obj *mac_obj,
2132                       int mac_type, bool wait_for_comp);
2133
2134/* Init Function API  */
2135void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
2136void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
2137                    uint8_t vf_valid, int fw_sb_id, int igu_sb_id);
2138int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, uint8_t port);
2139int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, uint32_t mode,
2140                   uint8_t port);
2141int bnx2x_set_mult_gpio(struct bnx2x *bp, uint8_t pins, uint32_t mode);
2142int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, uint32_t mode,
2143                       uint8_t port);
2144void bnx2x_read_mf_cfg(struct bnx2x *bp);
2145
2146int bnx2x_pretend_func(struct bnx2x *bp, uint16_t pretend_func_val);
2147
2148/* dmae */
2149void bnx2x_read_dmae(struct bnx2x *bp, uint32_t src_addr, uint32_t len32);
2150void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
2151                      uint32_t dst_addr,
2152                      uint32_t len32);
2153void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
2154uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
2155uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode);
2156uint32_t bnx2x_dmae_opcode(struct bnx2x *bp, uint8_t src_type, uint8_t dst_type,
2157                      bool with_comp, uint8_t comp_type);
2158
2159void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2160                               uint8_t src_type, uint8_t dst_type);
2161int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2162                               uint32_t *comp);
2163
2164/* FLR related routines */
2165uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
2166void bnx2x_tx_hw_flushed(struct bnx2x *bp, uint32_t poll_count);
2167int bnx2x_send_final_clnup(struct bnx2x *bp, uint8_t clnup_func,
2168                           uint32_t poll_cnt);
2169uint8_t bnx2x_is_pcie_pending(struct pci_device *dev);
2170int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, uint32_t reg,
2171                                    char *msg, uint32_t poll_cnt);
2172
2173void bnx2x_calc_fc_adv(struct bnx2x *bp);
2174int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2175                  uint32_t data_hi, uint32_t data_lo, int cmd_type);
2176void bnx2x_update_coalesce(struct bnx2x *bp);
2177int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
2178
2179bool bnx2x_port_after_undi(struct bnx2x *bp);
2180
2181static inline uint32_t reg_poll(struct bnx2x *bp, uint32_t reg,
2182                                uint32_t expected, int ms,
2183                           int wait)
2184{
2185        uint32_t val;
2186
2187        do {
2188                val = REG_RD(bp, reg);
2189                if (val == expected)
2190                        break;
2191                ms -= wait;
2192                kthread_usleep(1000 * wait);
2193
2194        } while (ms > 0);
2195
2196        return val;
2197}
2198
2199void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, uint8_t func,
2200                            uint8_t idu_sb_id,
2201                            bool is_pf);
2202
2203#define BNX2X_ILT_ZALLOC(x, y, size)                                    \
2204        x = dma_zalloc_coherent(&bp->pdev->dev, size, y, MEM_WAIT)
2205
2206#define BNX2X_ILT_FREE(x, y, size) \
2207        do { \
2208                if (x) { \
2209                        dma_free_coherent(&bp->pdev->dev, size, x, y); \
2210                        x = NULL; \
2211                        y = 0; \
2212                } \
2213        } while (0)
2214
2215#define ILOG2(x)        (LOG2_UP((x)))
2216
2217#define ILT_NUM_PAGE_ENTRIES    (3072)
2218/* In 57710/11 we use whole table since we have 8 func
2219 * In 57712 we have only 4 func, but use same size per func, then only half of
2220 * the table in use
2221 */
2222#define ILT_PER_FUNC            (ILT_NUM_PAGE_ENTRIES/8)
2223
2224#define FUNC_ILT_BASE(func)     (func * ILT_PER_FUNC)
2225/*
2226 * the phys address is shifted right 12 bits and has an added
2227 * 1=valid bit added to the 53rd bit
2228 * then since this is a wide register(TM)
2229 * we split it into two 32 bit writes
2230 */
2231#define ONCHIP_ADDR1(x)         ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
2232#define ONCHIP_ADDR2(x)         ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
2233
2234/* load/unload mode */
2235#define LOAD_NORMAL                     0
2236#define LOAD_OPEN                       1
2237#define LOAD_DIAG                       2
2238#define LOAD_LOOPBACK_EXT               3
2239#define UNLOAD_NORMAL                   0
2240#define UNLOAD_CLOSE                    1
2241#define UNLOAD_RECOVERY                 2
2242
2243/* DMAE command defines */
2244#define DMAE_TIMEOUT                    -1
2245#define DMAE_PCI_ERROR                  -2      /* E2 and onward */
2246#define DMAE_NOT_RDY                    -3
2247#define DMAE_PCI_ERR_FLAG               0x80000000
2248
2249#define DMAE_SRC_PCI                    0
2250#define DMAE_SRC_GRC                    1
2251
2252#define DMAE_DST_NONE                   0
2253#define DMAE_DST_PCI                    1
2254#define DMAE_DST_GRC                    2
2255
2256#define DMAE_COMP_PCI                   0
2257#define DMAE_COMP_GRC                   1
2258
2259/* E2 and onward - PCI error handling in the completion */
2260
2261#define DMAE_COMP_REGULAR               0
2262#define DMAE_COM_SET_ERR                1
2263
2264#define DMAE_CMD_SRC_PCI                (DMAE_SRC_PCI << \
2265                                                DMAE_COMMAND_SRC_SHIFT)
2266#define DMAE_CMD_SRC_GRC                (DMAE_SRC_GRC << \
2267                                                DMAE_COMMAND_SRC_SHIFT)
2268
2269#define DMAE_CMD_DST_PCI                (DMAE_DST_PCI << \
2270                                                DMAE_COMMAND_DST_SHIFT)
2271#define DMAE_CMD_DST_GRC                (DMAE_DST_GRC << \
2272                                                DMAE_COMMAND_DST_SHIFT)
2273
2274#define DMAE_CMD_C_DST_PCI              (DMAE_COMP_PCI << \
2275                                                DMAE_COMMAND_C_DST_SHIFT)
2276#define DMAE_CMD_C_DST_GRC              (DMAE_COMP_GRC << \
2277                                                DMAE_COMMAND_C_DST_SHIFT)
2278
2279#define DMAE_CMD_C_ENABLE               DMAE_COMMAND_C_TYPE_ENABLE
2280
2281#define DMAE_CMD_ENDIANITY_NO_SWAP      (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2282#define DMAE_CMD_ENDIANITY_B_SWAP       (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2283#define DMAE_CMD_ENDIANITY_DW_SWAP      (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2284#define DMAE_CMD_ENDIANITY_B_DW_SWAP    (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2285
2286#define DMAE_CMD_PORT_0                 0
2287#define DMAE_CMD_PORT_1                 DMAE_COMMAND_PORT
2288
2289#define DMAE_CMD_SRC_RESET              DMAE_COMMAND_SRC_RESET
2290#define DMAE_CMD_DST_RESET              DMAE_COMMAND_DST_RESET
2291#define DMAE_CMD_E1HVN_SHIFT            DMAE_COMMAND_E1HVN_SHIFT
2292
2293#define DMAE_SRC_PF                     0
2294#define DMAE_SRC_VF                     1
2295
2296#define DMAE_DST_PF                     0
2297#define DMAE_DST_VF                     1
2298
2299#define DMAE_C_SRC                      0
2300#define DMAE_C_DST                      1
2301
2302#define DMAE_LEN32_RD_MAX               0x80
2303#define DMAE_LEN32_WR_MAX(bp)           (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2304
2305#define DMAE_COMP_VAL                   0x60d0d0ae /* E2 and on - upper bit
2306                                                    * indicates error
2307                                                    */
2308
2309#define MAX_DMAE_C_PER_PORT             8
2310#define INIT_DMAE_C(bp)                 (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2311                                         BP_VN(bp))
2312#define PMF_DMAE_C(bp)                  (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2313                                         E1HVN_MAX)
2314
2315/* PCIE link and speed */
2316#define PCICFG_LINK_WIDTH               0x1f00000
2317#define PCICFG_LINK_WIDTH_SHIFT         20
2318#define PCICFG_LINK_SPEED               0xf0000
2319#define PCICFG_LINK_SPEED_SHIFT         16
2320
2321#define BNX2X_NUM_TESTS_SF              7
2322#define BNX2X_NUM_TESTS_MF              3
2323#define BNX2X_NUM_TESTS(bp)             (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2324                                             IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF)
2325
2326#define BNX2X_PHY_LOOPBACK              0
2327#define BNX2X_MAC_LOOPBACK              1
2328#define BNX2X_EXT_LOOPBACK              2
2329#define BNX2X_PHY_LOOPBACK_FAILED       1
2330#define BNX2X_MAC_LOOPBACK_FAILED       2
2331#define BNX2X_EXT_LOOPBACK_FAILED       3
2332#define BNX2X_LOOPBACK_FAILED           (BNX2X_MAC_LOOPBACK_FAILED | \
2333                                         BNX2X_PHY_LOOPBACK_FAILED)
2334
2335#define STROM_ASSERT_ARRAY_SIZE         50
2336
2337/* must be used on a CID before placing it on a HW ring */
2338#define HW_CID(bp, x)                   ((BP_PORT(bp) << 23) | \
2339                                         (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2340                                         (x))
2341
2342#define SP_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2343#define MAX_SP_DESC_CNT                 (SP_DESC_CNT - 1)
2344
2345#define BNX2X_BTR                       4
2346#define MAX_SPQ_PENDING                 8
2347
2348/* CMNG constants, as derived from system spec calculations */
2349/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2350#define DEF_MIN_RATE                                    100
2351/* resolution of the rate shaping timer - 400 usec */
2352#define RS_PERIODIC_TIMEOUT_USEC                        400
2353/* number of bytes in single QM arbitration cycle -
2354 * coefficient for calculating the fairness timer */
2355#define QM_ARB_BYTES                                    160000
2356/* resolution of Min algorithm 1:100 */
2357#define MIN_RES                                         100
2358/* how many bytes above threshold for the minimal credit of Min algorithm*/
2359#define MIN_ABOVE_THRESH                                32768
2360/* Fairness algorithm integration time coefficient -
2361 * for calculating the actual Tfair */
2362#define T_FAIR_COEF     ((MIN_ABOVE_THRESH +  QM_ARB_BYTES) * 8 * MIN_RES)
2363/* Memory of fairness algorithm . 2 cycles */
2364#define FAIR_MEM                                        2
2365
2366#define ATTN_NIG_FOR_FUNC               (1L << 8)
2367#define ATTN_SW_TIMER_4_FUNC            (1L << 9)
2368#define GPIO_2_FUNC                     (1L << 10)
2369#define GPIO_3_FUNC                     (1L << 11)
2370#define GPIO_4_FUNC                     (1L << 12)
2371#define ATTN_GENERAL_ATTN_1             (1L << 13)
2372#define ATTN_GENERAL_ATTN_2             (1L << 14)
2373#define ATTN_GENERAL_ATTN_3             (1L << 15)
2374#define ATTN_GENERAL_ATTN_4             (1L << 13)
2375#define ATTN_GENERAL_ATTN_5             (1L << 14)
2376#define ATTN_GENERAL_ATTN_6             (1L << 15)
2377
2378#define ATTN_HARD_WIRED_MASK            0xff00
2379#define ATTENTION_ID                    4
2380
2381#define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \
2382                                 IS_MF_FCOE_AFEX(bp))
2383
2384/* stuff added to make the code fit 80Col */
2385
2386#define BNX2X_PMF_LINK_ASSERT \
2387        GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2388
2389#define BNX2X_MC_ASSERT_BITS \
2390        (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2391         GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2392         GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2393         GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2394
2395#define BNX2X_MCP_ASSERT \
2396        GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2397
2398#define BNX2X_GRC_TIMEOUT       GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2399#define BNX2X_GRC_RSV           (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2400                                 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2401                                 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2402                                 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2403                                 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2404                                 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2405
2406#define HW_INTERRUT_ASSERT_SET_0 \
2407                                (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2408                                 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2409                                 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2410                                 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
2411                                 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2412#define HW_PRTY_ASSERT_SET_0    (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2413                                 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2414                                 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2415                                 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2416                                 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2417                                 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2418                                 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2419#define HW_INTERRUT_ASSERT_SET_1 \
2420                                (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2421                                 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2422                                 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2423                                 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2424                                 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2425                                 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2426                                 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2427                                 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2428                                 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2429                                 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2430                                 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2431#define HW_PRTY_ASSERT_SET_1    (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2432                                 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2433                                 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2434                                 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2435                                 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2436                                 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2437                                 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2438                                 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2439                             AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2440                                 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2441                                 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2442                                 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2443                                 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2444                                 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2445                                 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2446                                 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2447#define HW_INTERRUT_ASSERT_SET_2 \
2448                                (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2449                                 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2450                                 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2451                        AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2452                                 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2453#define HW_PRTY_ASSERT_SET_2    (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2454                                 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2455                        AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2456                                 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2457                                 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2458                                 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2459                                 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2460                                 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2461
2462#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2463                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2464                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2465                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2466
2467#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2468                              AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2469
2470#define MULTI_MASK                      0x7f
2471
2472#define DEF_USB_FUNC_OFF        offsetof(struct cstorm_def_status_block_u, func)
2473#define DEF_CSB_FUNC_OFF        offsetof(struct cstorm_def_status_block_c, func)
2474#define DEF_XSB_FUNC_OFF        offsetof(struct xstorm_def_status_block, func)
2475#define DEF_TSB_FUNC_OFF        offsetof(struct tstorm_def_status_block, func)
2476
2477#define DEF_USB_IGU_INDEX_OFF \
2478                        offsetof(struct cstorm_def_status_block_u, igu_index)
2479#define DEF_CSB_IGU_INDEX_OFF \
2480                        offsetof(struct cstorm_def_status_block_c, igu_index)
2481#define DEF_XSB_IGU_INDEX_OFF \
2482                        offsetof(struct xstorm_def_status_block, igu_index)
2483#define DEF_TSB_IGU_INDEX_OFF \
2484                        offsetof(struct tstorm_def_status_block, igu_index)
2485
2486#define DEF_USB_SEGMENT_OFF \
2487                        offsetof(struct cstorm_def_status_block_u, segment)
2488#define DEF_CSB_SEGMENT_OFF \
2489                        offsetof(struct cstorm_def_status_block_c, segment)
2490#define DEF_XSB_SEGMENT_OFF \
2491                        offsetof(struct xstorm_def_status_block, segment)
2492#define DEF_TSB_SEGMENT_OFF \
2493                        offsetof(struct tstorm_def_status_block, segment)
2494
2495#define BNX2X_SP_DSB_INDEX \
2496                (&bp->def_status_blk->sp_sb.\
2497                                        index_values[HC_SP_INDEX_ETH_DEF_CONS])
2498
2499#define CAM_IS_INVALID(x) \
2500        (GET_FLAG(x.flags, \
2501        MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2502        (T_ETH_MAC_COMMAND_INVALIDATE))
2503
2504/* Number of uint32_t elements in MC hash array */
2505#define MC_HASH_SIZE                    8
2506#define MC_HASH_OFFSET(bp, i)           (BAR_TSTRORM_INTMEM + \
2507        TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2508
2509#ifndef PXP2_REG_PXP2_INT_STS
2510#define PXP2_REG_PXP2_INT_STS           PXP2_REG_PXP2_INT_STS_0
2511#endif
2512
2513#ifndef ETH_MAX_RX_CLIENTS_E2
2514#define ETH_MAX_RX_CLIENTS_E2           ETH_MAX_RX_CLIENTS_E1H
2515#endif
2516
2517#define BNX2X_VPD_LEN                   128
2518#define VENDOR_ID_LEN                   4
2519
2520#define VF_ACQUIRE_THRESH               3
2521#define VF_ACQUIRE_MAC_FILTERS          1
2522#define VF_ACQUIRE_MC_FILTERS           10
2523
2524#define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2525                            (!((me_reg) & ME_REG_VF_ERR)))
2526int bnx2x_compare_fw_ver(struct bnx2x *bp, uint32_t load_code,
2527                         bool print_err);
2528
2529/* Congestion management fairness mode */
2530#define CMNG_FNS_NONE                   0
2531#define CMNG_FNS_MINMAX                 1
2532
2533#define HC_SEG_ACCESS_DEF               0   /*Driver decision 0-3*/
2534#define HC_SEG_ACCESS_ATTN              4
2535#define HC_SEG_ACCESS_NORM              0   /*Driver decision 0-1*/
2536
2537static const uint32_t dmae_reg_go_c[] = {
2538        DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2539        DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2540        DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2541        DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2542};
2543
2544void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct ether *netdev);
2545void bnx2x_notify_link_changed(struct bnx2x *bp);
2546
2547#define BNX2X_MF_SD_PROTOCOL(bp) \
2548        ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2549
2550#define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2551        (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2552
2553#define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2554        (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2555
2556#define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2557#define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2558#define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp))
2559
2560#define IS_MF_ISCSI_ONLY(bp)    (IS_MF_ISCSI_SD(bp) ||  IS_MF_ISCSI_SI(bp))
2561
2562#define BNX2X_MF_EXT_PROTOCOL_MASK                                      \
2563                                (MACP_FUNC_CFG_FLAGS_ETHERNET |         \
2564                                 MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD |    \
2565                                 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2566
2567#define BNX2X_MF_EXT_PROT(bp)   ((bp)->mf_ext_config &                  \
2568                                 BNX2X_MF_EXT_PROTOCOL_MASK)
2569
2570#define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp)                              \
2571                (BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2572
2573#define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)                               \
2574                (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2575
2576#define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp)                              \
2577                (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD)
2578
2579#define IS_MF_FCOE_AFEX(bp)                                             \
2580                (IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))
2581
2582#define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)                           \
2583                                (IS_MF_SD(bp) &&                        \
2584                                 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) ||  \
2585                                  BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2586
2587#define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp)                           \
2588                                (IS_MF_SI(bp) &&                        \
2589                                 (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) || \
2590                                  BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)))
2591
2592#define IS_MF_STORAGE_PERSONALITY_ONLY(bp)                              \
2593                        (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) ||       \
2594                         IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp))
2595
2596
2597#define SET_FLAG(value, mask, flag) \
2598        do {\
2599                (value) &= ~(mask);\
2600                (value) |= ((flag) << (mask##_SHIFT));\
2601        } while (0)
2602
2603#define GET_FLAG(value, mask) \
2604        (((value) & (mask)) >> (mask##_SHIFT))
2605
2606#define GET_FIELD(value, fname) \
2607        (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2608
2609enum {
2610        SWITCH_UPDATE,
2611        AFEX_UPDATE,
2612};
2613
2614#define NUM_MACS        8
2615
2616void bnx2x_set_local_cmng(struct bnx2x *bp);
2617
2618void bnx2x_update_mng_version(struct bnx2x *bp);
2619
2620#define MCPR_SCRATCH_BASE(bp) \
2621        (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
2622
2623#define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX))
2624
2625#define BNX2X_MAX_PHC_DRIFT 31000000
2626#define BNX2X_PTP_TX_TIMEOUT
2627