akaros/kern/arch/x86/ros/trapframe.h
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   1#pragma once
   2
   3#define ROS_INC_ARCH_TRAPFRAME_H
   4
   5#ifndef ROS_INC_TRAPFRAME_H
   6#error "Do not include include ros/arch/trapframe.h directly"
   7#endif
   8
   9#include <ros/common.h>
  10
  11#define ROS_ARCH_REFL_ID 0x1234
  12
  13/* Page faults return the nature of the fault in the bits of the error code: */
  14#define PF_ERROR_PRESENT                0x01
  15#define PF_ERROR_WRITE                  0x02
  16#define PF_ERROR_USER                   0x04
  17#define PF_VMR_BACKED                   (1 << 31)
  18
  19#include <ros/arch/trapframe64.h>
  20
  21static inline uintptr_t get_hwtf_pc(struct hw_trapframe *hw_tf)
  22{
  23        return hw_tf->tf_rip;
  24}
  25
  26static inline uintptr_t get_hwtf_fp(struct hw_trapframe *hw_tf)
  27{
  28        return hw_tf->tf_rbp;
  29}
  30
  31static inline uintptr_t get_hwtf_sp(struct hw_trapframe *hw_tf)
  32{
  33        return hw_tf->tf_rsp;
  34}
  35
  36static inline uintptr_t get_swtf_pc(struct sw_trapframe *sw_tf)
  37{
  38        return sw_tf->tf_rip;
  39}
  40
  41static inline uintptr_t get_swtf_fp(struct sw_trapframe *sw_tf)
  42{
  43        return sw_tf->tf_rbp;
  44}
  45
  46static inline uintptr_t get_swtf_sp(struct sw_trapframe *sw_tf)
  47{
  48        return sw_tf->tf_rsp;
  49}
  50
  51static inline uintptr_t get_vmtf_pc(struct vm_trapframe *vm_tf)
  52{
  53        return vm_tf->tf_rip;
  54}
  55
  56static inline uintptr_t get_vmtf_fp(struct vm_trapframe *vm_tf)
  57{
  58        return vm_tf->tf_rbp;
  59}
  60
  61static inline uintptr_t get_vmtf_sp(struct vm_trapframe *vm_tf)
  62{
  63        return vm_tf->tf_rsp;
  64}
  65
  66/* FP state and whatever else the kernel won't muck with automatically.  For
  67 * now, it's the Non-64-bit-mode layout of FP and XMM registers, as used by
  68 * FXSAVE and FXRSTOR.  Other modes will require a union on a couple entries.
  69 * See SDM 2a 3-451. */
  70/* Header for the non-64-bit mode FXSAVE map */
  71struct fp_header_non_64bit {
  72        uint16_t                        fcw;
  73        uint16_t                        fsw;
  74        uint8_t                         ftw;
  75        uint8_t                         padding0;
  76        uint16_t                        fop;
  77        uint32_t                        fpu_ip;
  78        uint16_t                        cs;
  79        uint16_t                        padding1;
  80        uint32_t                        fpu_dp;
  81        uint16_t                        ds;
  82        uint16_t                        padding2;
  83        uint32_t                        mxcsr;
  84        uint32_t                        mxcsr_mask;
  85};
  86
  87/* Header for the 64-bit mode FXSAVE map with promoted operand size */
  88struct fp_header_64bit_promoted {
  89        uint16_t                        fcw;
  90        uint16_t                        fsw;
  91        uint8_t                         ftw;
  92        uint8_t                         padding0;
  93        uint16_t                        fop;
  94        uint64_t                        fpu_ip;
  95        uint64_t                        fpu_dp;
  96        uint32_t                        mxcsr;
  97        uint32_t                        mxcsr_mask;
  98};
  99
 100/* Header for the 64-bit mode FXSAVE map with default operand size */
 101struct fp_header_64bit_default {
 102        uint16_t                        fcw;
 103        uint16_t                        fsw;
 104        uint8_t                         ftw;
 105        uint8_t                         padding0;
 106        uint16_t                        fop;
 107        uint32_t                        fpu_ip;
 108        uint16_t                        cs;
 109        uint16_t                        padding1;
 110        uint32_t                        fpu_dp;
 111        uint16_t                        ds;
 112        uint16_t                        padding2;
 113        uint32_t                        mxcsr;
 114        uint32_t                        mxcsr_mask;
 115};
 116
 117/* Just for storage space, not for real use     */
 118typedef struct {
 119        unsigned int stor[4];
 120} __128bits;
 121
 122/*
 123 *  X86_MAX_XCR0 specifies the maximum set of processor extended state
 124 *  feature components that Akaros supports saving through the
 125 *  XSAVE instructions.
 126 *  This may be a superset of available state components on a given
 127 *  processor. We CPUID at boot and determine the intersection
 128 *  of Akaros-supported and processor-supported features, and we
 129 *  save this value to __proc_global_info.x86_default_xcr0 in arch/x86/init.c.
 130 *  We guarantee that the set of feature components specified by
 131 *  X86_MAX_XCR0 will fit in the ancillary_state struct.
 132 *  If you add to the mask, make sure you also extend ancillary_state!
 133 */
 134
 135#define X86_MAX_XCR0 0x2ff
 136
 137typedef struct ancillary_state {
 138        /* Legacy region of the XSAVE area */
 139        union { /* whichever header used depends on the mode */
 140                struct fp_header_non_64bit              fp_head_n64;
 141                struct fp_header_64bit_promoted         fp_head_64p;
 142                struct fp_header_64bit_default          fp_head_64d;
 143        };
 144        /* offset 32 bytes */
 145        /* 128 bits: 80 for the st0, 48 reserved */
 146        __128bits                       st0_mm0;
 147        __128bits                       st1_mm1;
 148        __128bits                       st2_mm2;
 149        __128bits                       st3_mm3;
 150        __128bits                       st4_mm4;
 151        __128bits                       st5_mm5;
 152        __128bits                       st6_mm6;
 153        __128bits                       st7_mm7;
 154        /* offset 160 bytes */
 155        __128bits                       xmm0;
 156        __128bits                       xmm1;
 157        __128bits                       xmm2;
 158        __128bits                       xmm3;
 159        __128bits                       xmm4;
 160        __128bits                       xmm5;
 161        __128bits                       xmm6;
 162        __128bits                       xmm7;
 163        /* xmm8-xmm15 are only available in 64-bit-mode */
 164        __128bits                       xmm8;
 165        __128bits                       xmm9;
 166        __128bits                       xmm10;
 167        __128bits                       xmm11;
 168        __128bits                       xmm12;
 169        __128bits                       xmm13;
 170        __128bits                       xmm14;
 171        __128bits                       xmm15;
 172        /* offset 416 bytes */
 173        __128bits                       reserv0;
 174        __128bits                       reserv1;
 175        __128bits                       reserv2;
 176        __128bits                       reserv3;
 177        __128bits                       reserv4;
 178        __128bits                       reserv5;
 179        /* offset 512 bytes */
 180
 181        /*
 182         * XSAVE header (64 bytes, starting at offset 512 from
 183         * the XSAVE area's base address)
 184         */
 185
 186        // xstate_bv identifies the state components in the XSAVE area
 187        uint64_t                        xstate_bv;
 188        /*
 189         *      xcomp_bv[bit 63] is 1 if the compacted format is used, else 0.
 190         *      All bits in xcomp_bv should be 0 if the processor does not
 191         *      support the compaction extensions to the XSAVE feature set.
 192         */
 193        uint64_t                        xcomp_bv;
 194        __128bits                       reserv6;
 195
 196        /* offset 576 bytes */
 197        /*
 198         *      Extended region of the XSAVE area
 199         *      We currently support an extended region of up to 2112 bytes,
 200         *      for a total ancillary_state size of 2688 bytes.
 201         *      This supports x86 state components up through the zmm31
 202         *      register.  If you need more, please ask!
 203         *      See the Intel Architecture Instruction Set Extensions
 204         *      Programming Reference page 3-3 for detailed offsets in this
 205         *      region.
 206         */
 207        uint8_t                         extended_region[2120];
 208
 209        /* ancillary state  */
 210} __attribute__((aligned(64))) ancillary_state_t;
 211