akaros/kern/arch/x86/ros/msr-index.h
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   1#pragma once
   2
   3/* CPU model specific register (MSR) numbers */
   4
   5/* x86-64 specific MSRs */
   6#define MSR_EFER                0xc0000080      /* extended feature register */
   7#define MSR_STAR                0xc0000081      /* legacy mode SYSCALL target */
   8#define MSR_LSTAR               0xc0000082      /* long mode SYSCALL target */
   9#define MSR_CSTAR               0xc0000083      /* compat mode SYSCALL target */
  10#define MSR_SYSCALL_MASK        0xc0000084      /* EFLAGS mask for syscall */
  11#define MSR_FS_BASE             0xc0000100      /* 64bit FS base */
  12#define MSR_GS_BASE             0xc0000101      /* 64bit GS base */
  13#define MSR_KERNEL_GS_BASE      0xc0000102      /* SwapGS GS shadow */
  14#define MSR_TSC_AUX             0xc0000103      /* Auxiliary TSC */
  15
  16/* EFER bits: */
  17#define _EFER_SCE               0       /* SYSCALL/SYSRET */
  18#define _EFER_LME               8       /* Long mode enable */
  19#define _EFER_LMA               10      /* Long mode active (read-only) */
  20#define _EFER_NX                11      /* No execute enable */
  21#define _EFER_SVME              12      /* Enable virtualization */
  22#define _EFER_LMSLE             13      /* Long Mode Segment Limit Enable */
  23#define _EFER_FFXSR             14      /* Enable Fast FXSAVE/FXRSTOR */
  24
  25#define EFER_SCE                (1<<_EFER_SCE)
  26#define EFER_LME                (1<<_EFER_LME)
  27#define EFER_LMA                (1<<_EFER_LMA)
  28#define EFER_NX                 (1<<_EFER_NX)
  29#define EFER_SVME               (1<<_EFER_SVME)
  30#define EFER_LMSLE              (1<<_EFER_LMSLE)
  31#define EFER_FFXSR              (1<<_EFER_FFXSR)
  32
  33/* Intel MSRs. Some also available on other CPUs */
  34#define MSR_IA32_PERFCTR0               0x000000c1
  35#define MSR_IA32_PERFCTR1               0x000000c2
  36#define MSR_ARCH_PERFMON_EVENTSEL0           0x186
  37#define MSR_ARCH_PERFMON_EVENTSEL1           0x187
  38
  39#define ARCH_PERFMON_EVENTSEL_EVENT             0x000000FFULL
  40#define ARCH_PERFMON_EVENTSEL_UMASK             0x0000FF00ULL
  41#define ARCH_PERFMON_EVENTSEL_USR               (1ULL << 16)
  42#define ARCH_PERFMON_EVENTSEL_OS                (1ULL << 17)
  43#define ARCH_PERFMON_EVENTSEL_EDGE              (1ULL << 18)
  44#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL       (1ULL << 19)
  45#define ARCH_PERFMON_EVENTSEL_INT               (1ULL << 20)
  46#define ARCH_PERFMON_EVENTSEL_ANY               (1ULL << 21)
  47#define ARCH_PERFMON_EVENTSEL_ENABLE            (1ULL << 22)
  48#define ARCH_PERFMON_EVENTSEL_INV               (1ULL << 23)
  49#define ARCH_PERFMON_EVENTSEL_CMASK             0xFF000000ULL
  50
  51#define MSR_FSB_FREQ                    0x000000cd
  52#define MSR_PLATFORM_INFO               0x000000ce
  53
  54#define MSR_NHM_SNB_PKG_CST_CFG_CTL     0x000000e2
  55#define NHM_C3_AUTO_DEMOTE              (1UL << 25)
  56#define NHM_C1_AUTO_DEMOTE              (1UL << 26)
  57#define ATM_LNC_C6_AUTO_DEMOTE          (1UL << 25)
  58#define SNB_C1_AUTO_UNDEMOTE            (1UL << 27)
  59#define SNB_C3_AUTO_UNDEMOTE            (1UL << 28)
  60
  61#define MSR_MTRRcap                     0x000000fe
  62#define MSR_IA32_BBL_CR_CTL             0x00000119
  63#define MSR_IA32_BBL_CR_CTL3            0x0000011e
  64
  65#define MSR_IA32_SYSENTER_CS            0x00000174
  66#define MSR_IA32_SYSENTER_ESP           0x00000175
  67#define MSR_IA32_SYSENTER_EIP           0x00000176
  68
  69#define MSR_IA32_MCG_CAP                0x00000179
  70#define MSR_IA32_MCG_STATUS             0x0000017a
  71#define MSR_IA32_MCG_CTL                0x0000017b
  72
  73#define MSR_OFFCORE_RSP_0               0x000001a6
  74#define MSR_OFFCORE_RSP_1               0x000001a7
  75#define MSR_NHM_TURBO_RATIO_LIMIT       0x000001ad
  76#define MSR_TURBO_RATIO_LIMIT           0x000001ad
  77#define MSR_IVT_TURBO_RATIO_LIMIT       0x000001ae
  78
  79#define MSR_LBR_SELECT                  0x000001c8
  80#define MSR_LBR_TOS                     0x000001c9
  81#define MSR_LBR_NHM_FROM                0x00000680
  82#define MSR_LBR_NHM_TO                  0x000006c0
  83#define MSR_LBR_CORE_FROM               0x00000040
  84#define MSR_LBR_CORE_TO                 0x00000060
  85
  86#define MSR_IA32_PEBS_ENABLE            0x000003f1
  87#define MSR_P4_PEBS_MATRIX_VERT         0x000003f2
  88#define MSR_PEBS_LD_LAT_THRESHOLD       0x000003f6
  89#define MSR_IA32_DS_AREA                0x00000600
  90#define MSR_IA32_PERF_CAPABILITIES      0x00000345
  91
  92#define MSR_MTRRfix64K_00000            0x00000250
  93#define MSR_MTRRfix16K_80000            0x00000258
  94#define MSR_MTRRfix16K_A0000            0x00000259
  95#define MSR_MTRRfix4K_C0000             0x00000268
  96#define MSR_MTRRfix4K_C8000             0x00000269
  97#define MSR_MTRRfix4K_D0000             0x0000026a
  98#define MSR_MTRRfix4K_D8000             0x0000026b
  99#define MSR_MTRRfix4K_E0000             0x0000026c
 100#define MSR_MTRRfix4K_E8000             0x0000026d
 101#define MSR_MTRRfix4K_F0000             0x0000026e
 102#define MSR_MTRRfix4K_F8000             0x0000026f
 103#define MSR_MTRRdefType                 0x000002ff
 104
 105#define MSR_IA32_CR_PAT                 0x00000277
 106
 107#define MSR_IA32_DEBUGCTLMSR            0x000001d9
 108#define MSR_IA32_LASTBRANCHFROMIP       0x000001db
 109#define MSR_IA32_LASTBRANCHTOIP         0x000001dc
 110#define MSR_IA32_LASTINTFROMIP          0x000001dd
 111#define MSR_IA32_LASTINTTOIP            0x000001de
 112
 113/* X86 X2APIC registers */
 114#define MSR_LAPIC_ID                    0x00000802
 115#define MSR_LAPIC_VERSION               0x00000803
 116#define MSR_LAPIC_TPR                   0x00000808
 117#define MSR_LAPIC_PPR                   0x0000080a
 118#define MSR_LAPIC_EOI                   0x0000080b
 119#define MSR_LAPIC_LDR                   0x0000080d
 120#define MSR_LAPIC_SPURIOUS              0x0000080f
 121
 122#define MSR_LAPIC_ISR_31_0              0x00000810
 123#define MSR_LAPIC_ISR_63_32             0x00000811
 124#define MSR_LAPIC_ISR_95_64             0x00000812
 125#define MSR_LAPIC_ISR_127_96            0x00000813
 126#define MSR_LAPIC_ISR_159_128           0x00000814
 127#define MSR_LAPIC_ISR_191_160           0x00000815
 128#define MSR_LAPIC_ISR_223_192           0x00000816
 129#define MSR_LAPIC_ISR_255_224           0x00000817
 130// For easier looping
 131#define MSR_LAPIC_ISR_START             MSR_LAPIC_ISR_31_0
 132#define MSR_LAPIC_ISR_END               (MSR_LAPIC_ISR_255_224 + 1)
 133
 134#define MSR_LAPIC_TMR_31_0              0x00000818
 135#define MSR_LAPIC_TMR_63_32             0x00000819
 136#define MSR_LAPIC_TMR_95_64             0x0000081a
 137#define MSR_LAPIC_TMR_127_96            0x0000081b
 138#define MSR_LAPIC_TMR_159_128           0x0000081c
 139#define MSR_LAPIC_TMR_191_160           0x0000081d
 140#define MSR_LAPIC_TMR_223_192           0x0000081e
 141#define MSR_LAPIC_TMR_255_224           0x0000081f
 142// For easier looping
 143#define MSR_LAPIC_TMR_START             MSR_LAPIC_TMR_31_0
 144#define MSR_LAPIC_TMR_END               (MSR_LAPIC_TMR_255_224 + 1)
 145
 146#define MSR_LAPIC_IRR_31_0              0x00000820
 147#define MSR_LAPIC_IRR_63_32             0x00000821
 148#define MSR_LAPIC_IRR_95_64             0x00000822
 149#define MSR_LAPIC_IRR_127_96            0x00000823
 150#define MSR_LAPIC_IRR_159_128           0x00000824
 151#define MSR_LAPIC_IRR_191_160           0x00000825
 152#define MSR_LAPIC_IRR_223_192           0x00000826
 153#define MSR_LAPIC_IRR_255_224           0x00000827
 154// For easier looping
 155#define MSR_LAPIC_IRR_START             MSR_LAPIC_IRR_31_0
 156#define MSR_LAPIC_IRR_END               (MSR_LAPIC_IRR_255_224 + 1)
 157
 158#define MSR_LAPIC_ESR                   0x00000828
 159#define MSR_LAPIC_LVT_CMCI              0x0000082f
 160#define MSR_LAPIC_ICR                   0x00000830
 161#define MSR_LAPIC_LVT_TIMER             0x00000832
 162#define MSR_LAPIC_LVT_THERMAL           0x00000833
 163#define MSR_LAPIC_LVT_PERFMON           0x00000834
 164#define MSR_LAPIC_LVT_LINT0             0x00000835
 165#define MSR_LAPIC_LVT_LINT1             0x00000836
 166#define MSR_LAPIC_LVT_ERROR_REG         0x00000837
 167#define MSR_LAPIC_INITIAL_COUNT         0x00000838
 168#define MSR_LAPIC_CURRENT_COUNT         0x00000839
 169#define MSR_LAPIC_DIVIDE_CONFIG_REG     0x0000083e
 170#define MSR_LAPIC_SELF_IPI              0x0000083f
 171
 172#define MSR_LAPIC_END                   (MSR_LAPIC_SELF_IPI + 1)
 173
 174/* DEBUGCTLMSR bits (others vary by model): */
 175#define DEBUGCTLMSR_LBR                 (1UL <<  0)/* last branch recording */
 176#define DEBUGCTLMSR_BTF                 (1UL <<  1)/* single-step on branches */
 177#define DEBUGCTLMSR_TR                  (1UL <<  6)
 178#define DEBUGCTLMSR_BTS                 (1UL <<  7)
 179#define DEBUGCTLMSR_BTINT               (1UL <<  8)
 180#define DEBUGCTLMSR_BTS_OFF_OS          (1UL <<  9)
 181#define DEBUGCTLMSR_BTS_OFF_USR         (1UL << 10)
 182#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI  (1UL << 11)
 183
 184#define MSR_IA32_MC0_CTL                0x00000400
 185#define MSR_IA32_MC0_STATUS             0x00000401
 186#define MSR_IA32_MC0_ADDR               0x00000402
 187#define MSR_IA32_MC0_MISC               0x00000403
 188
 189/* C-state Residency Counters */
 190#define MSR_PKG_C3_RESIDENCY            0x000003f8
 191#define MSR_PKG_C6_RESIDENCY            0x000003f9
 192#define MSR_PKG_C7_RESIDENCY            0x000003fa
 193#define MSR_CORE_C3_RESIDENCY           0x000003fc
 194#define MSR_CORE_C6_RESIDENCY           0x000003fd
 195#define MSR_CORE_C7_RESIDENCY           0x000003fe
 196#define MSR_PKG_C2_RESIDENCY            0x0000060d
 197#define MSR_PKG_C8_RESIDENCY            0x00000630      /* HSW-ULT only */
 198#define MSR_PKG_C9_RESIDENCY            0x00000631      /* HSW-ULT only */
 199#define MSR_PKG_C10_RESIDENCY           0x00000632      /* HSW-ULT only */
 200
 201/* Run Time Average Power Limiting (RAPL) Interface */
 202
 203#define MSR_RAPL_POWER_UNIT             0x00000606
 204
 205#define MSR_PKG_POWER_LIMIT             0x00000610
 206#define MSR_PKG_ENERGY_STATUS           0x00000611
 207#define MSR_PKG_PERF_STATUS             0x00000613
 208#define MSR_PKG_POWER_INFO              0x00000614
 209
 210#define MSR_DRAM_POWER_LIMIT            0x00000618
 211#define MSR_DRAM_ENERGY_STATUS          0x00000619
 212#define MSR_DRAM_PERF_STATUS            0x0000061b
 213#define MSR_DRAM_POWER_INFO             0x0000061c
 214
 215#define MSR_PP0_POWER_LIMIT             0x00000638
 216#define MSR_PP0_ENERGY_STATUS           0x00000639
 217#define MSR_PP0_POLICY                  0x0000063a
 218#define MSR_PP0_PERF_STATUS             0x0000063b
 219
 220#define MSR_PP1_POWER_LIMIT             0x00000640
 221#define MSR_PP1_ENERGY_STATUS           0x00000641
 222#define MSR_PP1_POLICY                  0x00000642
 223
 224#define MSR_AMD64_MC0_MASK              0xc0010044
 225
 226#define MSR_IA32_MCx_CTL(x)             (MSR_IA32_MC0_CTL + 4*(x))
 227#define MSR_IA32_MCx_STATUS(x)          (MSR_IA32_MC0_STATUS + 4*(x))
 228#define MSR_IA32_MCx_ADDR(x)            (MSR_IA32_MC0_ADDR + 4*(x))
 229#define MSR_IA32_MCx_MISC(x)            (MSR_IA32_MC0_MISC + 4*(x))
 230
 231#define MSR_AMD64_MCx_MASK(x)           (MSR_AMD64_MC0_MASK + (x))
 232
 233/* These are consecutive and not in the normal 4er MCE bank block */
 234#define MSR_IA32_MC0_CTL2               0x00000280
 235#define MSR_IA32_MCx_CTL2(x)            (MSR_IA32_MC0_CTL2 + (x))
 236
 237#define MSR_P6_PERFCTR0                 0x000000c1
 238#define MSR_P6_PERFCTR1                 0x000000c2
 239#define MSR_P6_EVNTSEL0                 0x00000186
 240#define MSR_P6_EVNTSEL1                 0x00000187
 241
 242#define MSR_KNC_PERFCTR0               0x00000020
 243#define MSR_KNC_PERFCTR1               0x00000021
 244#define MSR_KNC_EVNTSEL0               0x00000028
 245#define MSR_KNC_EVNTSEL1               0x00000029
 246
 247/* AMD64 MSRs. Not complete. See the architecture manual for a more
 248   complete list. */
 249
 250#define MSR_AMD64_PATCH_LEVEL           0x0000008b
 251#define MSR_AMD64_TSC_RATIO             0xc0000104
 252#define MSR_AMD64_NB_CFG                0xc001001f
 253#define MSR_AMD64_PATCH_LOADER          0xc0010020
 254#define MSR_AMD64_OSVW_ID_LENGTH        0xc0010140
 255#define MSR_AMD64_OSVW_STATUS           0xc0010141
 256#define MSR_AMD64_DC_CFG                0xc0011022
 257#define MSR_AMD64_IBSFETCHCTL           0xc0011030
 258#define MSR_AMD64_IBSFETCHLINAD         0xc0011031
 259#define MSR_AMD64_IBSFETCHPHYSAD        0xc0011032
 260#define MSR_AMD64_IBSFETCH_REG_COUNT    3
 261#define MSR_AMD64_IBSFETCH_REG_MASK     ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
 262#define MSR_AMD64_IBSOPCTL              0xc0011033
 263#define MSR_AMD64_IBSOPRIP              0xc0011034
 264#define MSR_AMD64_IBSOPDATA             0xc0011035
 265#define MSR_AMD64_IBSOPDATA2            0xc0011036
 266#define MSR_AMD64_IBSOPDATA3            0xc0011037
 267#define MSR_AMD64_IBSDCLINAD            0xc0011038
 268#define MSR_AMD64_IBSDCPHYSAD           0xc0011039
 269#define MSR_AMD64_IBSOP_REG_COUNT       7
 270#define MSR_AMD64_IBSOP_REG_MASK        ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
 271#define MSR_AMD64_IBSCTL                0xc001103a
 272#define MSR_AMD64_IBSBRTARGET           0xc001103b
 273#define MSR_AMD64_IBS_REG_COUNT_MAX     8       /* includes MSR_AMD64_IBSBRTARGET */
 274
 275/* Fam 15h MSRs */
 276#define MSR_F15H_PERF_CTL               0xc0010200
 277#define MSR_F15H_PERF_CTR               0xc0010201
 278
 279/* Fam 10h MSRs */
 280#define MSR_FAM10H_MMIO_CONF_BASE       0xc0010058
 281#define FAM10H_MMIO_CONF_ENABLE         (1<<0)
 282#define FAM10H_MMIO_CONF_BUSRANGE_MASK  0xf
 283#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
 284#define FAM10H_MMIO_CONF_BASE_MASK      0xfffffffULL
 285#define FAM10H_MMIO_CONF_BASE_SHIFT     20
 286#define MSR_FAM10H_NODE_ID              0xc001100c
 287
 288/* K8 MSRs */
 289#define MSR_K8_TOP_MEM1                 0xc001001a
 290#define MSR_K8_TOP_MEM2                 0xc001001d
 291#define MSR_K8_SYSCFG                   0xc0010010
 292#define MSR_K8_INT_PENDING_MSG          0xc0010055
 293/* C1E active bits in int pending message */
 294#define K8_INTP_C1E_ACTIVE_MASK         0x18000000
 295#define MSR_K8_TSEG_ADDR                0xc0010112
 296#define K8_MTRRFIXRANGE_DRAM_ENABLE     0x00040000      /* MtrrFixDramEn bit    */
 297#define K8_MTRRFIXRANGE_DRAM_MODIFY     0x00080000      /* MtrrFixDramModEn bit */
 298#define K8_MTRR_RDMEM_WRMEM_MASK        0x18181818      /* Mask: RdMem|WrMem    */
 299
 300/* K7 MSRs */
 301#define MSR_K7_EVNTSEL0                 0xc0010000
 302#define MSR_K7_PERFCTR0                 0xc0010004
 303#define MSR_K7_EVNTSEL1                 0xc0010001
 304#define MSR_K7_PERFCTR1                 0xc0010005
 305#define MSR_K7_EVNTSEL2                 0xc0010002
 306#define MSR_K7_PERFCTR2                 0xc0010006
 307#define MSR_K7_EVNTSEL3                 0xc0010003
 308#define MSR_K7_PERFCTR3                 0xc0010007
 309#define MSR_K7_CLK_CTL                  0xc001001b
 310#define MSR_K7_HWCR                     0xc0010015
 311#define MSR_K7_FID_VID_CTL              0xc0010041
 312#define MSR_K7_FID_VID_STATUS           0xc0010042
 313
 314/* K6 MSRs */
 315#define MSR_K6_WHCR                     0xc0000082
 316#define MSR_K6_UWCCR                    0xc0000085
 317#define MSR_K6_EPMR                     0xc0000086
 318#define MSR_K6_PSOR                     0xc0000087
 319#define MSR_K6_PFIR                     0xc0000088
 320
 321/* Centaur-Hauls/IDT defined MSRs. */
 322#define MSR_IDT_FCR1                    0x00000107
 323#define MSR_IDT_FCR2                    0x00000108
 324#define MSR_IDT_FCR3                    0x00000109
 325#define MSR_IDT_FCR4                    0x0000010a
 326
 327#define MSR_IDT_MCR0                    0x00000110
 328#define MSR_IDT_MCR1                    0x00000111
 329#define MSR_IDT_MCR2                    0x00000112
 330#define MSR_IDT_MCR3                    0x00000113
 331#define MSR_IDT_MCR4                    0x00000114
 332#define MSR_IDT_MCR5                    0x00000115
 333#define MSR_IDT_MCR6                    0x00000116
 334#define MSR_IDT_MCR7                    0x00000117
 335#define MSR_IDT_MCR_CTRL                0x00000120
 336
 337/* VIA Cyrix defined MSRs*/
 338#define MSR_VIA_FCR                     0x00001107
 339#define MSR_VIA_LONGHAUL                0x0000110a
 340#define MSR_VIA_RNG                     0x0000110b
 341#define MSR_VIA_BCR2                    0x00001147
 342
 343/* Transmeta defined MSRs */
 344#define MSR_TMTA_LONGRUN_CTRL           0x80868010
 345#define MSR_TMTA_LONGRUN_FLAGS          0x80868011
 346#define MSR_TMTA_LRTI_READOUT           0x80868018
 347#define MSR_TMTA_LRTI_VOLT_MHZ          0x8086801a
 348
 349/* Intel defined MSRs. */
 350#define MSR_IA32_P5_MC_ADDR             0x00000000
 351#define MSR_IA32_P5_MC_TYPE             0x00000001
 352#define MSR_IA32_TSC                    0x00000010
 353#define MSR_IA32_PLATFORM_ID            0x00000017
 354#define MSR_IA32_EBL_CR_POWERON         0x0000002a
 355#define MSR_EBC_FREQUENCY_ID            0x0000002c
 356#define MSR_IA32_FEATURE_CONTROL        0x0000003a
 357#define MSR_IA32_TSC_ADJUST             0x0000003b
 358
 359#define FEATURE_CONTROL_LOCKED                          (1<<0)
 360#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX        (1<<1)
 361#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX       (1<<2)
 362
 363#define MSR_IA32_APICBASE               0x0000001b
 364#define MSR_IA32_APICBASE_BSP           (1<<8)
 365#define MSR_IA32_APICBASE_ENABLE        (1<<11)
 366#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 367
 368#define MSR_IA32_TSCDEADLINE            0x000006e0
 369
 370#define MSR_IA32_UCODE_WRITE            0x00000079
 371#define MSR_IA32_UCODE_REV              0x0000008b
 372
 373#define MSR_IA32_PERF_STATUS            0x00000198
 374#define MSR_IA32_PERF_CTL               0x00000199
 375#define MSR_AMD_PSTATE_DEF_BASE         0xc0010064
 376#define MSR_AMD_PERF_STATUS             0xc0010063
 377#define MSR_AMD_PERF_CTL                0xc0010062
 378
 379#define MSR_IA32_MPERF                  0x000000e7
 380#define MSR_IA32_APERF                  0x000000e8
 381
 382#define MSR_IA32_THERM_CONTROL          0x0000019a
 383#define MSR_IA32_THERM_INTERRUPT        0x0000019b
 384
 385#define THERM_INT_HIGH_ENABLE           (1 << 0)
 386#define THERM_INT_LOW_ENABLE            (1 << 1)
 387#define THERM_INT_PLN_ENABLE            (1 << 24)
 388
 389#define MSR_IA32_THERM_STATUS           0x0000019c
 390
 391#define THERM_STATUS_PROCHOT            (1 << 0)
 392#define THERM_STATUS_POWER_LIMIT        (1 << 10)
 393
 394#define MSR_THERM2_CTL                  0x0000019d
 395
 396#define MSR_THERM2_CTL_TM_SELECT        (1ULL << 16)
 397
 398#define MSR_IA32_MISC_ENABLE            0x000001a0
 399
 400#define MSR_IA32_TEMPERATURE_TARGET     0x000001a2
 401
 402#define MSR_IA32_ENERGY_PERF_BIAS       0x000001b0
 403#define ENERGY_PERF_BIAS_PERFORMANCE    0
 404#define ENERGY_PERF_BIAS_NORMAL         6
 405#define ENERGY_PERF_BIAS_POWERSAVE      15
 406
 407#define MSR_IA32_PACKAGE_THERM_STATUS           0x000001b1
 408
 409#define PACKAGE_THERM_STATUS_PROCHOT            (1 << 0)
 410#define PACKAGE_THERM_STATUS_POWER_LIMIT        (1 << 10)
 411
 412#define MSR_IA32_PACKAGE_THERM_INTERRUPT        0x000001b2
 413
 414#define PACKAGE_THERM_INT_HIGH_ENABLE           (1 << 0)
 415#define PACKAGE_THERM_INT_LOW_ENABLE            (1 << 1)
 416#define PACKAGE_THERM_INT_PLN_ENABLE            (1 << 24)
 417
 418/* Thermal Thresholds Support */
 419#define THERM_INT_THRESHOLD0_ENABLE    (1 << 15)
 420#define THERM_SHIFT_THRESHOLD0        8
 421#define THERM_MASK_THRESHOLD0          (0x7f << THERM_SHIFT_THRESHOLD0)
 422#define THERM_INT_THRESHOLD1_ENABLE    (1 << 23)
 423#define THERM_SHIFT_THRESHOLD1        16
 424#define THERM_MASK_THRESHOLD1          (0x7f << THERM_SHIFT_THRESHOLD1)
 425#define THERM_STATUS_THRESHOLD0        (1 << 6)
 426#define THERM_LOG_THRESHOLD0           (1 << 7)
 427#define THERM_STATUS_THRESHOLD1        (1 << 8)
 428#define THERM_LOG_THRESHOLD1           (1 << 9)
 429
 430/* MISC_ENABLE bits: architectural */
 431#define MSR_IA32_MISC_ENABLE_FAST_STRING        (1ULL << 0)
 432#define MSR_IA32_MISC_ENABLE_TCC                (1ULL << 1)
 433#define MSR_IA32_MISC_ENABLE_EMON               (1ULL << 7)
 434#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL        (1ULL << 11)
 435#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL       (1ULL << 12)
 436#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
 437#define MSR_IA32_MISC_ENABLE_MWAIT              (1ULL << 18)
 438#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID        (1ULL << 22)
 439#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE       (1ULL << 23)
 440#define MSR_IA32_MISC_ENABLE_XD_DISABLE         (1ULL << 34)
 441
 442/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
 443#define MSR_IA32_MISC_ENABLE_X87_COMPAT         (1ULL << 2)
 444#define MSR_IA32_MISC_ENABLE_TM1                (1ULL << 3)
 445#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
 446#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE    (1ULL << 6)
 447#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK      (1ULL << 8)
 448#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE   (1ULL << 9)
 449#define MSR_IA32_MISC_ENABLE_FERR               (1ULL << 10)
 450#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX     (1ULL << 10)
 451#define MSR_IA32_MISC_ENABLE_TM2                (1ULL << 13)
 452#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE   (1ULL << 19)
 453#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK     (1ULL << 20)
 454#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT        (1ULL << 24)
 455#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE   (1ULL << 37)
 456#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE      (1ULL << 38)
 457#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE    (1ULL << 39)
 458
 459#define MSR_IA32_TSC_DEADLINE           0x000006E0
 460#define MSR_IA32_SPEC_CTRL              0x48
 461#define MSR_IA32_PRED_CMD               0x49
 462
 463/* P4/Xeon+ specific */
 464#define MSR_IA32_MCG_EAX                0x00000180
 465#define MSR_IA32_MCG_EBX                0x00000181
 466#define MSR_IA32_MCG_ECX                0x00000182
 467#define MSR_IA32_MCG_EDX                0x00000183
 468#define MSR_IA32_MCG_ESI                0x00000184
 469#define MSR_IA32_MCG_EDI                0x00000185
 470#define MSR_IA32_MCG_EBP                0x00000186
 471#define MSR_IA32_MCG_ESP                0x00000187
 472#define MSR_IA32_MCG_EFLAGS             0x00000188
 473#define MSR_IA32_MCG_EIP                0x00000189
 474#define MSR_IA32_MCG_RESERVED           0x0000018a
 475
 476/* Pentium IV performance counter MSRs */
 477#define MSR_P4_BPU_PERFCTR0             0x00000300
 478#define MSR_P4_BPU_PERFCTR1             0x00000301
 479#define MSR_P4_BPU_PERFCTR2             0x00000302
 480#define MSR_P4_BPU_PERFCTR3             0x00000303
 481#define MSR_P4_MS_PERFCTR0              0x00000304
 482#define MSR_P4_MS_PERFCTR1              0x00000305
 483#define MSR_P4_MS_PERFCTR2              0x00000306
 484#define MSR_P4_MS_PERFCTR3              0x00000307
 485#define MSR_P4_FLAME_PERFCTR0           0x00000308
 486#define MSR_P4_FLAME_PERFCTR1           0x00000309
 487#define MSR_P4_FLAME_PERFCTR2           0x0000030a
 488#define MSR_P4_FLAME_PERFCTR3           0x0000030b
 489#define MSR_P4_IQ_PERFCTR0              0x0000030c
 490#define MSR_P4_IQ_PERFCTR1              0x0000030d
 491#define MSR_P4_IQ_PERFCTR2              0x0000030e
 492#define MSR_P4_IQ_PERFCTR3              0x0000030f
 493#define MSR_P4_IQ_PERFCTR4              0x00000310
 494#define MSR_P4_IQ_PERFCTR5              0x00000311
 495#define MSR_P4_BPU_CCCR0                0x00000360
 496#define MSR_P4_BPU_CCCR1                0x00000361
 497#define MSR_P4_BPU_CCCR2                0x00000362
 498#define MSR_P4_BPU_CCCR3                0x00000363
 499#define MSR_P4_MS_CCCR0                 0x00000364
 500#define MSR_P4_MS_CCCR1                 0x00000365
 501#define MSR_P4_MS_CCCR2                 0x00000366
 502#define MSR_P4_MS_CCCR3                 0x00000367
 503#define MSR_P4_FLAME_CCCR0              0x00000368
 504#define MSR_P4_FLAME_CCCR1              0x00000369
 505#define MSR_P4_FLAME_CCCR2              0x0000036a
 506#define MSR_P4_FLAME_CCCR3              0x0000036b
 507#define MSR_P4_IQ_CCCR0                 0x0000036c
 508#define MSR_P4_IQ_CCCR1                 0x0000036d
 509#define MSR_P4_IQ_CCCR2                 0x0000036e
 510#define MSR_P4_IQ_CCCR3                 0x0000036f
 511#define MSR_P4_IQ_CCCR4                 0x00000370
 512#define MSR_P4_IQ_CCCR5                 0x00000371
 513#define MSR_P4_ALF_ESCR0                0x000003ca
 514#define MSR_P4_ALF_ESCR1                0x000003cb
 515#define MSR_P4_BPU_ESCR0                0x000003b2
 516#define MSR_P4_BPU_ESCR1                0x000003b3
 517#define MSR_P4_BSU_ESCR0                0x000003a0
 518#define MSR_P4_BSU_ESCR1                0x000003a1
 519#define MSR_P4_CRU_ESCR0                0x000003b8
 520#define MSR_P4_CRU_ESCR1                0x000003b9
 521#define MSR_P4_CRU_ESCR2                0x000003cc
 522#define MSR_P4_CRU_ESCR3                0x000003cd
 523#define MSR_P4_CRU_ESCR4                0x000003e0
 524#define MSR_P4_CRU_ESCR5                0x000003e1
 525#define MSR_P4_DAC_ESCR0                0x000003a8
 526#define MSR_P4_DAC_ESCR1                0x000003a9
 527#define MSR_P4_FIRM_ESCR0               0x000003a4
 528#define MSR_P4_FIRM_ESCR1               0x000003a5
 529#define MSR_P4_FLAME_ESCR0              0x000003a6
 530#define MSR_P4_FLAME_ESCR1              0x000003a7
 531#define MSR_P4_FSB_ESCR0                0x000003a2
 532#define MSR_P4_FSB_ESCR1                0x000003a3
 533#define MSR_P4_IQ_ESCR0                 0x000003ba
 534#define MSR_P4_IQ_ESCR1                 0x000003bb
 535#define MSR_P4_IS_ESCR0                 0x000003b4
 536#define MSR_P4_IS_ESCR1                 0x000003b5
 537#define MSR_P4_ITLB_ESCR0               0x000003b6
 538#define MSR_P4_ITLB_ESCR1               0x000003b7
 539#define MSR_P4_IX_ESCR0                 0x000003c8
 540#define MSR_P4_IX_ESCR1                 0x000003c9
 541#define MSR_P4_MOB_ESCR0                0x000003aa
 542#define MSR_P4_MOB_ESCR1                0x000003ab
 543#define MSR_P4_MS_ESCR0                 0x000003c0
 544#define MSR_P4_MS_ESCR1                 0x000003c1
 545#define MSR_P4_PMH_ESCR0                0x000003ac
 546#define MSR_P4_PMH_ESCR1                0x000003ad
 547#define MSR_P4_RAT_ESCR0                0x000003bc
 548#define MSR_P4_RAT_ESCR1                0x000003bd
 549#define MSR_P4_SAAT_ESCR0               0x000003ae
 550#define MSR_P4_SAAT_ESCR1               0x000003af
 551#define MSR_P4_SSU_ESCR0                0x000003be
 552#define MSR_P4_SSU_ESCR1                0x000003bf      /* guess: not in manual */
 553
 554#define MSR_P4_TBPU_ESCR0               0x000003c2
 555#define MSR_P4_TBPU_ESCR1               0x000003c3
 556#define MSR_P4_TC_ESCR0                 0x000003c4
 557#define MSR_P4_TC_ESCR1                 0x000003c5
 558#define MSR_P4_U2L_ESCR0                0x000003b0
 559#define MSR_P4_U2L_ESCR1                0x000003b1
 560
 561#define MSR_P4_PEBS_MATRIX_VERT         0x000003f2
 562
 563/* Intel Core-based CPU performance counters */
 564#define MSR_CORE_PERF_FIXED_CTR0        0x00000309
 565#define MSR_CORE_PERF_FIXED_CTR1        0x0000030a
 566#define MSR_CORE_PERF_FIXED_CTR2        0x0000030b
 567#define MSR_CORE_PERF_FIXED_CTR_CTRL    0x0000038d
 568#define MSR_CORE_PERF_GLOBAL_STATUS     0x0000038e
 569#define MSR_CORE_PERF_GLOBAL_CTRL       0x0000038f
 570#define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x00000390
 571
 572/* Geode defined MSRs */
 573#define MSR_GEODE_BUSCONT_CONF0         0x00001900
 574
 575/* Intel VT MSRs */
 576#define MSR_IA32_VMX_BASIC              0x00000480
 577#define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
 578#define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
 579#define MSR_IA32_VMX_EXIT_CTLS          0x00000483
 580#define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
 581#define MSR_IA32_VMX_MISC               0x00000485
 582#define MSR_IA32_VMX_CR0_FIXED0         0x00000486
 583#define MSR_IA32_VMX_CR0_FIXED1         0x00000487
 584#define MSR_IA32_VMX_CR4_FIXED0         0x00000488
 585#define MSR_IA32_VMX_CR4_FIXED1         0x00000489
 586#define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
 587#define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
 588#define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
 589#define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048d
 590#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
 591#define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
 592#define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490
 593
 594/* VMX_BASIC bits and bitmasks */
 595#define VMX_BASIC_VMCS_SIZE_SHIFT       32
 596#define VMX_BASIC_64                    (1ULL << 48)
 597#define VMX_BASIC_MEM_TYPE_SHIFT        50
 598#define VMX_BASIC_MEM_TYPE_MASK         (0xfULL << VMX_BASIC_MEM_TYPE_SHIFT)
 599#define VMX_BASIC_MEM_TYPE_WB           6LLU
 600#define VMX_BASIC_INOUT                 (1ULL << 54)
 601#define VMX_BASIC_TRUE_CTLS             (1ULL << 55)
 602
 603/* AMD-V MSRs */
 604
 605#define MSR_VM_CR                       0xc0010114
 606#define MSR_VM_IGNNE                    0xc0010115
 607#define MSR_VM_HSAVE_PA                 0xc0010117
 608