akaros/kern/arch/x86/ros/membar.h
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   1#pragma once
   2
   3/* Full CPU memory barrier */
   4#define mb() ({ asm volatile("mfence" ::: "memory"); })
   5/* Compiler memory barrier (optimization barrier) */
   6#define cmb() ({ asm volatile("" ::: "memory"); })
   7/* Partial CPU memory barriers */
   8#define rmb() cmb()
   9#define wmb() cmb()
  10#define wrmb() mb()
  11#define rwmb() cmb()
  12
  13/* Forced barriers, used for string ops, SSE ops, dealing with hardware, or
  14 * other places where you avoid 'normal' x86 read/writes (like having an IPI
  15 * beat a write) */
  16#define mb_f() ({ asm volatile("mfence" ::: "memory"); })
  17#define rmb_f() ({ asm volatile("lfence" ::: "memory"); })
  18#define wmb_f() ({ asm volatile("sfence" ::: "memory"); })
  19#define wrmb_f() mb_f()
  20#define rwmb_f() mb_f()
  21
  22/* Bus memory barriers */
  23#define bus_wmb() cmb()
  24#define bus_rmb() asm volatile("lock; addl $0,0(%%rsp)" : : : "memory")
  25