1/* Copyright (c) 2009, 2014 The Regents of the University of California
   2 * Barret Rhoden <brho@cs.berkeley.edu>
   3 * See LICENSE for details.
   4 *
   5 * PIC: 8259 interrupt controller */
   7#pragma once
   9#include <ros/common.h>
  11/* PIC (8259A)
  12 * When looking at the specs, A0 is our CMD line, and A1 is the DATA line.  This
  13 * means that blindly writing to PIC1_DATA is an OCW1 (interrupt masks).  When
  14 * writing to CMD (A0), the chip can determine betweeb OCW2 and OCW3 by the
  15 * setting of a few specific bits (OCW2 has bit 3 unset, OCW3 has it set). */
  16#define PIC1_CMD                0x20
  17#define PIC1_DATA               0x21
  18#define PIC2_CMD                0xA0
  19#define PIC2_DATA               0xA1
  20// These are also hardcoded into the IRQ_HANDLERs of kern/trapentry.S
  21#define PIC1_OFFSET             0x20
  22#define PIC2_OFFSET             0x28
  23#define PIC1_SPURIOUS           (7 + PIC1_OFFSET)
  24#define PIC2_SPURIOUS           (7 + PIC2_OFFSET)
  25#define PIC_EOI                 0x20    /* OCW2 EOI */
  26/* These set the next CMD read to return specific values.  Note that the chip
  27 * remembers what setting we had before (IRR or ISR), if you do other reads of
  28 * CMD. (not tested, written in the spec sheet) */
  29#define PIC_READ_IRR            0x0a    /* OCW3 irq ready next CMD read */
  30#define PIC_READ_ISR            0x0b    /* OCW3 irq service next CMD read */
  32struct irq_handler;     /* include loops */
  34void pic_remap(void);
  35void pic_mask_irq(struct irq_handler *unused, int trap_nr);
  36void pic_unmask_irq(struct irq_handler *unused, int trap_nr);
  37void pic_mask_all(void);
  38uint16_t pic_get_mask(void);
  39uint16_t pic_get_irr(void);
  40uint16_t pic_get_isr(void);
  41bool pic_check_spurious(int trap_nr);
  42void pic_send_eoi(int trap_nr);