akaros/kern/arch/x86/pci_regs.h
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   1/*
   2 *      pci_regs.h
   3 *
   4 *      PCI standard defines
   5 *      Copyright 1994, Drew Eckhardt
   6 *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
   7 *
   8 *      For more information, please consult the following manuals (look at
   9 *      http://www.pcisig.com/ for how to get them):
  10 *
  11 *      PCI BIOS Specification
  12 *      PCI Local Bus Specification
  13 *      PCI to PCI Bridge Specification
  14 *      PCI System Design Guide
  15 *
  16 *      For HyperTransport information, please consult the following manuals
  17 *      from http://www.hypertransport.org
  18 *
  19 *      The HyperTransport I/O Link Specification
  20 */
  21
  22#pragma once
  23
  24/*
  25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
  26 * configuration space.  PCI-X Mode 2 and PCIe devices have 4096 bytes of
  27 * configuration space.
  28 */
  29#define PCI_CFG_SPACE_SIZE      256
  30#define PCI_CFG_SPACE_EXP_SIZE  4096
  31
  32/*
  33 * Under PCI, each device has 256 bytes of configuration address space,
  34 * of which the first 64 bytes are standardized as follows:
  35 */
  36#define PCI_STD_HEADER_SIZEOF   64
  37#define PCI_VENDOR_ID           0x00    /* 16 bits */
  38#define PCI_DEVICE_ID           0x02    /* 16 bits */
  39#define PCI_COMMAND             0x04    /* 16 bits */
  40#define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
  41#define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
  42#define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
  43#define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
  44#define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
  45#define  PCI_COMMAND_VGA_PALETTE 0x20   /* Enable palette snooping */
  46#define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
  47#define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
  48#define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
  49#define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
  50#define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
  51
  52#define PCI_STATUS              0x06    /* 16 bits */
  53#define  PCI_STATUS_INTERRUPT   0x08    /* Interrupt status */
  54#define  PCI_STATUS_CAP_LIST    0x10    /* Support Capability List */
  55#define  PCI_STATUS_66MHZ       0x20    /* Support 66 MHz PCI 2.1 bus */
  56#define  PCI_STATUS_UDF         0x40    /* Support User Definable Features [obsolete] */
  57#define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
  58#define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
  59#define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
  60#define  PCI_STATUS_DEVSEL_FAST         0x000
  61#define  PCI_STATUS_DEVSEL_MEDIUM       0x200
  62#define  PCI_STATUS_DEVSEL_SLOW         0x400
  63#define  PCI_STATUS_SIG_TARGET_ABORT    0x800 /* Set on target abort */
  64#define  PCI_STATUS_REC_TARGET_ABORT    0x1000 /* Master ack of " */
  65#define  PCI_STATUS_REC_MASTER_ABORT    0x2000 /* Set on master abort */
  66#define  PCI_STATUS_SIG_SYSTEM_ERROR    0x4000 /* Set when we drive SERR */
  67#define  PCI_STATUS_DETECTED_PARITY     0x8000 /* Set on parity error */
  68
  69#define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8 revision */
  70#define PCI_REVISION_ID         0x08    /* Revision ID */
  71#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
  72#define PCI_CLASS_DEVICE        0x0a    /* Device class */
  73
  74#define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
  75#define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
  76#define PCI_HEADER_TYPE         0x0e    /* 8 bits */
  77#define  PCI_HEADER_TYPE_NORMAL         0
  78#define  PCI_HEADER_TYPE_BRIDGE         1
  79#define  PCI_HEADER_TYPE_CARDBUS        2
  80
  81#define PCI_BIST                0x0f    /* 8 bits */
  82#define  PCI_BIST_CODE_MASK     0x0f    /* Return result */
  83#define  PCI_BIST_START         0x40    /* 1 to start BIST, 2 secs or less */
  84#define  PCI_BIST_CAPABLE       0x80    /* 1 if BIST capable */
  85
  86/*
  87 * Base addresses specify locations in memory or I/O space.
  88 * Decoded size can be determined by writing a value of
  89 * 0xffffffff to the register, and reading it back.  Only
  90 * 1 bits are decoded.
  91 */
  92#define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
  93#define PCI_BASE_ADDRESS_1      0x14    /* 32 bits [htype 0,1 only] */
  94#define PCI_BASE_ADDRESS_2      0x18    /* 32 bits [htype 0 only] */
  95#define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
  96#define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
  97#define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
  98#define  PCI_BASE_ADDRESS_SPACE         0x01    /* 0 = memory, 1 = I/O */
  99#define  PCI_BASE_ADDRESS_SPACE_IO      0x01
 100#define  PCI_BASE_ADDRESS_SPACE_MEMORY  0x00
 101#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
 102#define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
 103#define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M [obsolete] */
 104#define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
 105#define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
 106#define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0fUL)
 107#define  PCI_BASE_ADDRESS_IO_MASK       (~0x03UL)
 108/* bit 1 is reserved if address_space = 1 */
 109
 110/* Header type 0 (normal devices) */
 111#define PCI_CARDBUS_CIS         0x28
 112#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
 113#define PCI_SUBSYSTEM_ID        0x2e
 114#define PCI_ROM_ADDRESS         0x30    /* Bits 31..11 are address, 10..1 reserved */
 115#define  PCI_ROM_ADDRESS_ENABLE 0x01
 116#define PCI_ROM_ADDRESS_MASK    (~0x7ffU)
 117
 118#define PCI_CAPABILITY_LIST     0x34    /* Offset of first capability list entry */
 119
 120/* 0x35-0x3b are reserved */
 121#define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 122#define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 123#define PCI_MIN_GNT             0x3e    /* 8 bits */
 124#define PCI_MAX_LAT             0x3f    /* 8 bits */
 125
 126/* Header type 1 (PCI-to-PCI bridges) */
 127#define PCI_PRIMARY_BUS         0x18    /* Primary bus number */
 128#define PCI_SECONDARY_BUS       0x19    /* Secondary bus number */
 129#define PCI_SUBORDINATE_BUS     0x1a    /* Highest bus number behind the bridge */
 130#define PCI_SEC_LATENCY_TIMER   0x1b    /* Latency timer for secondary interface */
 131#define PCI_IO_BASE             0x1c    /* I/O range behind the bridge */
 132#define PCI_IO_LIMIT            0x1d
 133#define  PCI_IO_RANGE_TYPE_MASK 0x0fUL  /* I/O bridging type */
 134#define  PCI_IO_RANGE_TYPE_16   0x00
 135#define  PCI_IO_RANGE_TYPE_32   0x01
 136#define  PCI_IO_RANGE_MASK      (~0x0fUL) /* Standard 4K I/O windows */
 137#define  PCI_IO_1K_RANGE_MASK   (~0x03UL) /* Intel 1K I/O windows */
 138#define PCI_SEC_STATUS          0x1e    /* Secondary status register, only bit 14 used */
 139#define PCI_MEMORY_BASE         0x20    /* Memory range behind */
 140#define PCI_MEMORY_LIMIT        0x22
 141#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
 142#define  PCI_MEMORY_RANGE_MASK  (~0x0fUL)
 143#define PCI_PREF_MEMORY_BASE    0x24    /* Prefetchable memory range behind */
 144#define PCI_PREF_MEMORY_LIMIT   0x26
 145#define  PCI_PREF_RANGE_TYPE_MASK 0x0fUL
 146#define  PCI_PREF_RANGE_TYPE_32 0x00
 147#define  PCI_PREF_RANGE_TYPE_64 0x01
 148#define  PCI_PREF_RANGE_MASK    (~0x0fUL)
 149#define PCI_PREF_BASE_UPPER32   0x28    /* Upper half of prefetchable memory range */
 150#define PCI_PREF_LIMIT_UPPER32  0x2c
 151#define PCI_IO_BASE_UPPER16     0x30    /* Upper half of I/O addresses */
 152#define PCI_IO_LIMIT_UPPER16    0x32
 153/* 0x34 same as for htype 0 */
 154/* 0x35-0x3b is reserved */
 155#define PCI_ROM_ADDRESS1        0x38    /* Same as PCI_ROM_ADDRESS, but for htype 1 */
 156/* 0x3c-0x3d are same as for htype 0 */
 157#define PCI_BRIDGE_CONTROL      0x3e
 158#define  PCI_BRIDGE_CTL_PARITY  0x01    /* Enable parity detection on secondary interface */
 159#define  PCI_BRIDGE_CTL_SERR    0x02    /* The same for SERR forwarding */
 160#define  PCI_BRIDGE_CTL_ISA     0x04    /* Enable ISA mode */
 161#define  PCI_BRIDGE_CTL_VGA     0x08    /* Forward VGA addresses */
 162#define  PCI_BRIDGE_CTL_MASTER_ABORT    0x20  /* Report master aborts */
 163#define  PCI_BRIDGE_CTL_BUS_RESET       0x40    /* Secondary bus reset */
 164#define  PCI_BRIDGE_CTL_FAST_BACK       0x80    /* Fast Back2Back enabled on secondary interface */
 165
 166/* Header type 2 (CardBus bridges) */
 167#define PCI_CB_CAPABILITY_LIST  0x14
 168/* 0x15 reserved */
 169#define PCI_CB_SEC_STATUS       0x16    /* Secondary status */
 170#define PCI_CB_PRIMARY_BUS      0x18    /* PCI bus number */
 171#define PCI_CB_CARD_BUS         0x19    /* CardBus bus number */
 172#define PCI_CB_SUBORDINATE_BUS  0x1a    /* Subordinate bus number */
 173#define PCI_CB_LATENCY_TIMER    0x1b    /* CardBus latency timer */
 174#define PCI_CB_MEMORY_BASE_0    0x1c
 175#define PCI_CB_MEMORY_LIMIT_0   0x20
 176#define PCI_CB_MEMORY_BASE_1    0x24
 177#define PCI_CB_MEMORY_LIMIT_1   0x28
 178#define PCI_CB_IO_BASE_0        0x2c
 179#define PCI_CB_IO_BASE_0_HI     0x2e
 180#define PCI_CB_IO_LIMIT_0       0x30
 181#define PCI_CB_IO_LIMIT_0_HI    0x32
 182#define PCI_CB_IO_BASE_1        0x34
 183#define PCI_CB_IO_BASE_1_HI     0x36
 184#define PCI_CB_IO_LIMIT_1       0x38
 185#define PCI_CB_IO_LIMIT_1_HI    0x3a
 186#define  PCI_CB_IO_RANGE_MASK   (~0x03UL)
 187/* 0x3c-0x3d are same as for htype 0 */
 188#define PCI_CB_BRIDGE_CONTROL   0x3e
 189#define  PCI_CB_BRIDGE_CTL_PARITY       0x01    /* Similar to standard bridge control register */
 190#define  PCI_CB_BRIDGE_CTL_SERR         0x02
 191#define  PCI_CB_BRIDGE_CTL_ISA          0x04
 192#define  PCI_CB_BRIDGE_CTL_VGA          0x08
 193#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
 194#define  PCI_CB_BRIDGE_CTL_CB_RESET     0x40    /* CardBus reset */
 195#define  PCI_CB_BRIDGE_CTL_16BIT_INT    0x80    /* Enable interrupt for 16-bit cards */
 196#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100  /* Prefetch enable for both memory regions */
 197#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
 198#define  PCI_CB_BRIDGE_CTL_POST_WRITES  0x400
 199#define PCI_CB_SUBSYSTEM_VENDOR_ID      0x40
 200#define PCI_CB_SUBSYSTEM_ID             0x42
 201#define PCI_CB_LEGACY_MODE_BASE         0x44    /* 16-bit PC Card legacy mode base address (ExCa) */
 202/* 0x48-0x7f reserved */
 203
 204/* Capability lists */
 205
 206#define PCI_CAP_LIST_ID         0       /* Capability ID */
 207#define  PCI_CAP_ID_PM          0x01    /* Power Management */
 208#define  PCI_CAP_ID_AGP         0x02    /* Accelerated Graphics Port */
 209#define  PCI_CAP_ID_VPD         0x03    /* Vital Product Data */
 210#define  PCI_CAP_ID_SLOTID      0x04    /* Slot Identification */
 211#define  PCI_CAP_ID_MSI         0x05    /* Message Signalled Interrupts */
 212#define  PCI_CAP_ID_CHSWP       0x06    /* CompactPCI HotSwap */
 213#define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
 214#define  PCI_CAP_ID_HT          0x08    /* HyperTransport */
 215#define  PCI_CAP_ID_VNDR        0x09    /* Vendor-Specific */
 216#define  PCI_CAP_ID_DBG         0x0A    /* Debug port */
 217#define  PCI_CAP_ID_CCRC        0x0B    /* CompactPCI Central Resource Control */
 218#define  PCI_CAP_ID_SHPC        0x0C    /* PCI Standard Hot-Plug Controller */
 219#define  PCI_CAP_ID_SSVID       0x0D    /* Bridge subsystem vendor/device ID */
 220#define  PCI_CAP_ID_AGP3        0x0E    /* AGP Target PCI-PCI bridge */
 221#define  PCI_CAP_ID_SECDEV      0x0F    /* Secure Device */
 222#define  PCI_CAP_ID_EXP         0x10    /* PCI Express */
 223#define  PCI_CAP_ID_MSIX        0x11    /* MSI-X */
 224#define  PCI_CAP_ID_SATA        0x12    /* SATA Data/Index Conf. */
 225#define  PCI_CAP_ID_AF          0x13    /* PCI Advanced Features */
 226#define  PCI_CAP_ID_EA          0x14    /* PCI Enhanced Allocation */
 227#define  PCI_CAP_ID_MAX         PCI_CAP_ID_EA
 228#define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
 229#define PCI_CAP_FLAGS           2       /* Capability defined flags (16 bits) */
 230#define PCI_CAP_SIZEOF          4
 231
 232/* Power Management Registers */
 233
 234#define PCI_PM_PMC              2       /* PM Capabilities Register */
 235#define  PCI_PM_CAP_VER_MASK    0x0007  /* Version */
 236#define  PCI_PM_CAP_PME_CLOCK   0x0008  /* PME clock required */
 237#define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
 238#define  PCI_PM_CAP_DSI         0x0020  /* Device specific initialization */
 239#define  PCI_PM_CAP_AUX_POWER   0x01C0  /* Auxiliary power support mask */
 240#define  PCI_PM_CAP_D1          0x0200  /* D1 power state support */
 241#define  PCI_PM_CAP_D2          0x0400  /* D2 power state support */
 242#define  PCI_PM_CAP_PME         0x0800  /* PME pin supported */
 243#define  PCI_PM_CAP_PME_MASK    0xF800  /* PME Mask of all supported states */
 244#define  PCI_PM_CAP_PME_D0      0x0800  /* PME# from D0 */
 245#define  PCI_PM_CAP_PME_D1      0x1000  /* PME# from D1 */
 246#define  PCI_PM_CAP_PME_D2      0x2000  /* PME# from D2 */
 247#define  PCI_PM_CAP_PME_D3      0x4000  /* PME# from D3 (hot) */
 248#define  PCI_PM_CAP_PME_D3cold  0x8000  /* PME# from D3 (cold) */
 249#define  PCI_PM_CAP_PME_SHIFT   11      /* Start of the PME Mask in PMC */
 250#define PCI_PM_CTRL             4       /* PM control and status register */
 251#define  PCI_PM_CTRL_STATE_MASK 0x0003  /* Current power state (D0 to D3) */
 252#define  PCI_PM_CTRL_NO_SOFT_RESET      0x0008  /* No reset for D3hot->D0 */
 253#define  PCI_PM_CTRL_PME_ENABLE 0x0100  /* PME pin enable */
 254#define  PCI_PM_CTRL_DATA_SEL_MASK      0x1e00  /* Data select (??) */
 255#define  PCI_PM_CTRL_DATA_SCALE_MASK    0x6000  /* Data scale (??) */
 256#define  PCI_PM_CTRL_PME_STATUS 0x8000  /* PME pin status */
 257#define PCI_PM_PPB_EXTENSIONS   6       /* PPB support extensions (??) */
 258#define  PCI_PM_PPB_B2_B3       0x40    /* Stop clock when in D3hot (??) */
 259#define  PCI_PM_BPCC_ENABLE     0x80    /* Bus power/clock control enable (??) */
 260#define PCI_PM_DATA_REGISTER    7       /* (??) */
 261#define PCI_PM_SIZEOF           8
 262
 263/* AGP registers */
 264
 265#define PCI_AGP_VERSION         2       /* BCD version number */
 266#define PCI_AGP_RFU             3       /* Rest of capability flags */
 267#define PCI_AGP_STATUS          4       /* Status register */
 268#define  PCI_AGP_STATUS_RQ_MASK 0xff000000      /* Maximum number of requests - 1 */
 269#define  PCI_AGP_STATUS_SBA     0x0200  /* Sideband addressing supported */
 270#define  PCI_AGP_STATUS_64BIT   0x0020  /* 64-bit addressing supported */
 271#define  PCI_AGP_STATUS_FW      0x0010  /* FW transfers supported */
 272#define  PCI_AGP_STATUS_RATE4   0x0004  /* 4x transfer rate supported */
 273#define  PCI_AGP_STATUS_RATE2   0x0002  /* 2x transfer rate supported */
 274#define  PCI_AGP_STATUS_RATE1   0x0001  /* 1x transfer rate supported */
 275#define PCI_AGP_COMMAND         8       /* Control register */
 276#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
 277#define  PCI_AGP_COMMAND_SBA    0x0200  /* Sideband addressing enabled */
 278#define  PCI_AGP_COMMAND_AGP    0x0100  /* Allow processing of AGP transactions */
 279#define  PCI_AGP_COMMAND_64BIT  0x0020  /* Allow processing of 64-bit addresses */
 280#define  PCI_AGP_COMMAND_FW     0x0010  /* Force FW transfers */
 281#define  PCI_AGP_COMMAND_RATE4  0x0004  /* Use 4x rate */
 282#define  PCI_AGP_COMMAND_RATE2  0x0002  /* Use 2x rate */
 283#define  PCI_AGP_COMMAND_RATE1  0x0001  /* Use 1x rate */
 284#define PCI_AGP_SIZEOF          12
 285
 286/* Vital Product Data */
 287
 288#define PCI_VPD_ADDR            2       /* Address to access (15 bits!) */
 289#define  PCI_VPD_ADDR_MASK      0x7fff  /* Address mask */
 290#define  PCI_VPD_ADDR_F         0x8000  /* Write 0, 1 indicates completion */
 291#define PCI_VPD_DATA            4       /* 32-bits of data returned here */
 292#define PCI_CAP_VPD_SIZEOF      8
 293
 294/* Slot Identification */
 295
 296#define PCI_SID_ESR             2       /* Expansion Slot Register */
 297#define  PCI_SID_ESR_NSLOTS     0x1f    /* Number of expansion slots available */
 298#define  PCI_SID_ESR_FIC        0x20    /* First In Chassis Flag */
 299#define PCI_SID_CHASSIS_NR      3       /* Chassis Number */
 300
 301/* Message Signalled Interrupts registers */
 302
 303#define PCI_MSI_FLAGS           2       /* Message Control */
 304#define  PCI_MSI_FLAGS_ENABLE   0x0001  /* MSI feature enabled */
 305#define  PCI_MSI_FLAGS_QMASK    0x000e  /* Maximum queue size available */
 306#define  PCI_MSI_FLAGS_QSIZE    0x0070  /* Message queue size configured */
 307#define  PCI_MSI_FLAGS_64BIT    0x0080  /* 64-bit addresses allowed */
 308#define  PCI_MSI_FLAGS_MASKBIT  0x0100  /* Per-vector masking capable */
 309#define PCI_MSI_RFU             3       /* Rest of capability flags */
 310#define PCI_MSI_ADDRESS_LO      4       /* Lower 32 bits */
 311#define PCI_MSI_ADDRESS_HI      8       /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
 312#define PCI_MSI_DATA_32         8       /* 16 bits of data for 32-bit devices */
 313#define PCI_MSI_MASK_32         12      /* Mask bits register for 32-bit devices */
 314#define PCI_MSI_PENDING_32      16      /* Pending intrs for 32-bit devices */
 315#define PCI_MSI_DATA_64         12      /* 16 bits of data for 64-bit devices */
 316#define PCI_MSI_MASK_64         16      /* Mask bits register for 64-bit devices */
 317#define PCI_MSI_PENDING_64      20      /* Pending intrs for 64-bit devices */
 318
 319/* MSI-X registers */
 320#define PCI_MSIX_FLAGS          2       /* Message Control */
 321#define  PCI_MSIX_FLAGS_QSIZE   0x07FF  /* Table size */
 322#define  PCI_MSIX_FLAGS_MASKALL 0x4000  /* Mask all vectors for this function */
 323#define  PCI_MSIX_FLAGS_ENABLE  0x8000  /* MSI-X enable */
 324#define PCI_MSIX_TABLE          4       /* Table offset */
 325#define  PCI_MSIX_TABLE_BIR     0x00000007 /* BAR index */
 326#define  PCI_MSIX_TABLE_OFFSET  0xfffffff8 /* Offset into specified BAR */
 327#define PCI_MSIX_PBA            8       /* Pending Bit Array offset */
 328#define  PCI_MSIX_PBA_BIR       0x00000007 /* BAR index */
 329#define  PCI_MSIX_PBA_OFFSET    0xfffffff8 /* Offset into specified BAR */
 330#define PCI_MSIX_FLAGS_BIRMASK  PCI_MSIX_PBA_BIR /* deprecated */
 331#define PCI_CAP_MSIX_SIZEOF     12      /* size of MSIX registers */
 332
 333/* MSI-X Table entry format */
 334#define PCI_MSIX_ENTRY_SIZE             16
 335#define  PCI_MSIX_ENTRY_LOWER_ADDR      0
 336#define  PCI_MSIX_ENTRY_UPPER_ADDR      4
 337#define  PCI_MSIX_ENTRY_DATA            8
 338#define  PCI_MSIX_ENTRY_VECTOR_CTRL     12
 339#define   PCI_MSIX_ENTRY_CTRL_MASKBIT   1
 340
 341/* CompactPCI Hotswap Register */
 342
 343#define PCI_CHSWP_CSR           2       /* Control and Status Register */
 344#define  PCI_CHSWP_DHA          0x01    /* Device Hiding Arm */
 345#define  PCI_CHSWP_EIM          0x02    /* ENUM# Signal Mask */
 346#define  PCI_CHSWP_PIE          0x04    /* Pending Insert or Extract */
 347#define  PCI_CHSWP_LOO          0x08    /* LED On / Off */
 348#define  PCI_CHSWP_PI           0x30    /* Programming Interface */
 349#define  PCI_CHSWP_EXT          0x40    /* ENUM# status - extraction */
 350#define  PCI_CHSWP_INS          0x80    /* ENUM# status - insertion */
 351
 352/* PCI Advanced Feature registers */
 353
 354#define PCI_AF_LENGTH           2
 355#define PCI_AF_CAP              3
 356#define  PCI_AF_CAP_TP          0x01
 357#define  PCI_AF_CAP_FLR         0x02
 358#define PCI_AF_CTRL             4
 359#define  PCI_AF_CTRL_FLR        0x01
 360#define PCI_AF_STATUS           5
 361#define  PCI_AF_STATUS_TP       0x01
 362#define PCI_CAP_AF_SIZEOF       6       /* size of AF registers */
 363
 364/* PCI Enhanced Allocation registers */
 365
 366#define PCI_EA_NUM_ENT          2       /* Number of Capability Entries */
 367#define  PCI_EA_NUM_ENT_MASK    0x3f    /* Num Entries Mask */
 368#define PCI_EA_FIRST_ENT        4       /* First EA Entry in List */
 369#define PCI_EA_FIRST_ENT_BRIDGE 8       /* First EA Entry for Bridges */
 370#define  PCI_EA_ES              0x00000007 /* Entry Size */
 371#define  PCI_EA_BEI             0x000000f0 /* BAR Equivalent Indicator */
 372/* 0-5 map to BARs 0-5 respectively */
 373#define   PCI_EA_BEI_BAR0               0
 374#define   PCI_EA_BEI_BAR5               5
 375#define   PCI_EA_BEI_BRIDGE             6       /* Resource behind bridge */
 376#define   PCI_EA_BEI_ENI                7       /* Equivalent Not Indicated */
 377#define   PCI_EA_BEI_ROM                8       /* Expansion ROM */
 378/* 9-14 map to VF BARs 0-5 respectively */
 379#define   PCI_EA_BEI_VF_BAR0            9
 380#define   PCI_EA_BEI_VF_BAR5            14
 381#define   PCI_EA_BEI_RESERVED           15      /* Reserved - Treat like ENI */
 382#define  PCI_EA_PP              0x0000ff00      /* Primary Properties */
 383#define  PCI_EA_SP              0x00ff0000      /* Secondary Properties */
 384#define   PCI_EA_P_MEM                  0x00    /* Non-Prefetch Memory */
 385#define   PCI_EA_P_MEM_PREFETCH         0x01    /* Prefetchable Memory */
 386#define   PCI_EA_P_IO                   0x02    /* I/O Space */
 387#define   PCI_EA_P_VF_MEM_PREFETCH      0x03    /* VF Prefetchable Memory */
 388#define   PCI_EA_P_VF_MEM               0x04    /* VF Non-Prefetch Memory */
 389#define   PCI_EA_P_BRIDGE_MEM           0x05    /* Bridge Non-Prefetch Memory */
 390#define   PCI_EA_P_BRIDGE_MEM_PREFETCH  0x06    /* Bridge Prefetchable Memory */
 391#define   PCI_EA_P_BRIDGE_IO            0x07    /* Bridge I/O Space */
 392/* 0x08-0xfc reserved */
 393#define   PCI_EA_P_MEM_RESERVED         0xfd    /* Reserved Memory */
 394#define   PCI_EA_P_IO_RESERVED          0xfe    /* Reserved I/O Space */
 395#define   PCI_EA_P_UNAVAILABLE          0xff    /* Entry Unavailable */
 396#define  PCI_EA_WRITABLE        0x40000000      /* Writable: 1 = RW, 0 = HwInit */
 397#define  PCI_EA_ENABLE          0x80000000      /* Enable for this entry */
 398#define PCI_EA_BASE             4               /* Base Address Offset */
 399#define PCI_EA_MAX_OFFSET       8               /* MaxOffset (resource length) */
 400/* bit 0 is reserved */
 401#define  PCI_EA_IS_64           0x00000002      /* 64-bit field flag */
 402#define  PCI_EA_FIELD_MASK      0xfffffffc      /* For Base & Max Offset */
 403
 404/* PCI-X registers (Type 0 (non-bridge) devices) */
 405
 406#define PCI_X_CMD               2       /* Modes & Features */
 407#define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */
 408#define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
 409#define  PCI_X_CMD_READ_512     0x0000  /* 512 byte maximum read byte count */
 410#define  PCI_X_CMD_READ_1K      0x0004  /* 1Kbyte maximum read byte count */
 411#define  PCI_X_CMD_READ_2K      0x0008  /* 2Kbyte maximum read byte count */
 412#define  PCI_X_CMD_READ_4K      0x000c  /* 4Kbyte maximum read byte count */
 413#define  PCI_X_CMD_MAX_READ     0x000c  /* Max Memory Read Byte Count */
 414                                /* Max # of outstanding split transactions */
 415#define  PCI_X_CMD_SPLIT_1      0x0000  /* Max 1 */
 416#define  PCI_X_CMD_SPLIT_2      0x0010  /* Max 2 */
 417#define  PCI_X_CMD_SPLIT_3      0x0020  /* Max 3 */
 418#define  PCI_X_CMD_SPLIT_4      0x0030  /* Max 4 */
 419#define  PCI_X_CMD_SPLIT_8      0x0040  /* Max 8 */
 420#define  PCI_X_CMD_SPLIT_12     0x0050  /* Max 12 */
 421#define  PCI_X_CMD_SPLIT_16     0x0060  /* Max 16 */
 422#define  PCI_X_CMD_SPLIT_32     0x0070  /* Max 32 */
 423#define  PCI_X_CMD_MAX_SPLIT    0x0070  /* Max Outstanding Split Transactions */
 424#define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
 425#define PCI_X_STATUS            4       /* PCI-X capabilities */
 426#define  PCI_X_STATUS_DEVFN     0x000000ff      /* A copy of devfn */
 427#define  PCI_X_STATUS_BUS       0x0000ff00      /* A copy of bus nr */
 428#define  PCI_X_STATUS_64BIT     0x00010000      /* 64-bit device */
 429#define  PCI_X_STATUS_133MHZ    0x00020000      /* 133 MHz capable */
 430#define  PCI_X_STATUS_SPL_DISC  0x00040000      /* Split Completion Discarded */
 431#define  PCI_X_STATUS_UNX_SPL   0x00080000      /* Unexpected Split Completion */
 432#define  PCI_X_STATUS_COMPLEX   0x00100000      /* Device Complexity */
 433#define  PCI_X_STATUS_MAX_READ  0x00600000      /* Designed Max Memory Read Count */
 434#define  PCI_X_STATUS_MAX_SPLIT 0x03800000      /* Designed Max Outstanding Split Transactions */
 435#define  PCI_X_STATUS_MAX_CUM   0x1c000000      /* Designed Max Cumulative Read Size */
 436#define  PCI_X_STATUS_SPL_ERR   0x20000000      /* Rcvd Split Completion Error Msg */
 437#define  PCI_X_STATUS_266MHZ    0x40000000      /* 266 MHz capable */
 438#define  PCI_X_STATUS_533MHZ    0x80000000      /* 533 MHz capable */
 439#define PCI_X_ECC_CSR           8       /* ECC control and status */
 440#define PCI_CAP_PCIX_SIZEOF_V0  8       /* size of registers for Version 0 */
 441#define PCI_CAP_PCIX_SIZEOF_V1  24      /* size for Version 1 */
 442#define PCI_CAP_PCIX_SIZEOF_V2  PCI_CAP_PCIX_SIZEOF_V1  /* Same for v2 */
 443
 444/* PCI-X registers (Type 1 (bridge) devices) */
 445
 446#define PCI_X_BRIDGE_SSTATUS    2       /* Secondary Status */
 447#define  PCI_X_SSTATUS_64BIT    0x0001  /* Secondary AD interface is 64 bits */
 448#define  PCI_X_SSTATUS_133MHZ   0x0002  /* 133 MHz capable */
 449#define  PCI_X_SSTATUS_FREQ     0x03c0  /* Secondary Bus Mode and Frequency */
 450#define  PCI_X_SSTATUS_VERS     0x3000  /* PCI-X Capability Version */
 451#define  PCI_X_SSTATUS_V1       0x1000  /* Mode 2, not Mode 1 */
 452#define  PCI_X_SSTATUS_V2       0x2000  /* Mode 1 or Modes 1 and 2 */
 453#define  PCI_X_SSTATUS_266MHZ   0x4000  /* 266 MHz capable */
 454#define  PCI_X_SSTATUS_533MHZ   0x8000  /* 533 MHz capable */
 455#define PCI_X_BRIDGE_STATUS     4       /* Bridge Status */
 456
 457/* PCI Bridge Subsystem ID registers */
 458
 459#define PCI_SSVID_VENDOR_ID     4       /* PCI Bridge subsystem vendor ID */
 460#define PCI_SSVID_DEVICE_ID     6       /* PCI Bridge subsystem device ID */
 461
 462/* PCI Express capability registers */
 463
 464#define PCI_EXP_FLAGS           2       /* Capabilities register */
 465#define PCI_EXP_FLAGS_VERS      0x000f  /* Capability version */
 466#define PCI_EXP_FLAGS_TYPE      0x00f0  /* Device/Port type */
 467#define  PCI_EXP_TYPE_ENDPOINT  0x0     /* Express Endpoint */
 468#define  PCI_EXP_TYPE_LEG_END   0x1     /* Legacy Endpoint */
 469#define  PCI_EXP_TYPE_ROOT_PORT 0x4     /* Root Port */
 470#define  PCI_EXP_TYPE_UPSTREAM  0x5     /* Upstream Port */
 471#define  PCI_EXP_TYPE_DOWNSTREAM 0x6    /* Downstream Port */
 472#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7    /* PCIe to PCI/PCI-X Bridge */
 473#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8   /* PCI/PCI-X to PCIe Bridge */
 474#define  PCI_EXP_TYPE_RC_END    0x9     /* Root Complex Integrated Endpoint */
 475#define  PCI_EXP_TYPE_RC_EC     0xa     /* Root Complex Event Collector */
 476#define PCI_EXP_FLAGS_SLOT      0x0100  /* Slot implemented */
 477#define PCI_EXP_FLAGS_IRQ       0x3e00  /* Interrupt message number */
 478#define PCI_EXP_DEVCAP          4       /* Device capabilities */
 479#define  PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */
 480#define  PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */
 481#define  PCI_EXP_DEVCAP_EXT_TAG 0x00000020 /* Extended tags */
 482#define  PCI_EXP_DEVCAP_L0S     0x000001c0 /* L0s Acceptable Latency */
 483#define  PCI_EXP_DEVCAP_L1      0x00000e00 /* L1 Acceptable Latency */
 484#define  PCI_EXP_DEVCAP_ATN_BUT 0x00001000 /* Attention Button Present */
 485#define  PCI_EXP_DEVCAP_ATN_IND 0x00002000 /* Attention Indicator Present */
 486#define  PCI_EXP_DEVCAP_PWR_IND 0x00004000 /* Power Indicator Present */
 487#define  PCI_EXP_DEVCAP_RBER    0x00008000 /* Role-Based Error Reporting */
 488#define  PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 /* Slot Power Limit Value */
 489#define  PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 /* Slot Power Limit Scale */
 490#define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
 491#define PCI_EXP_DEVCTL          8       /* Device Control */
 492#define  PCI_EXP_DEVCTL_CERE    0x0001  /* Correctable Error Reporting En. */
 493#define  PCI_EXP_DEVCTL_NFERE   0x0002  /* Non-Fatal Error Reporting Enable */
 494#define  PCI_EXP_DEVCTL_FERE    0x0004  /* Fatal Error Reporting Enable */
 495#define  PCI_EXP_DEVCTL_URRE    0x0008  /* Unsupported Request Reporting En. */
 496#define  PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
 497#define  PCI_EXP_DEVCTL_PAYLOAD 0x00e0  /* Max_Payload_Size */
 498#define  PCI_EXP_DEVCTL_EXT_TAG 0x0100  /* Extended Tag Field Enable */
 499#define  PCI_EXP_DEVCTL_PHANTOM 0x0200  /* Phantom Functions Enable */
 500#define  PCI_EXP_DEVCTL_AUX_PME 0x0400  /* Auxiliary Power PM Enable */
 501#define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
 502#define  PCI_EXP_DEVCTL_READRQ  0x7000  /* Max_Read_Request_Size */
 503#define  PCI_EXP_DEVCTL_READRQ_128B  0x0000 /* 128 Bytes */
 504#define  PCI_EXP_DEVCTL_READRQ_256B  0x1000 /* 256 Bytes */
 505#define  PCI_EXP_DEVCTL_READRQ_512B  0x2000 /* 512 Bytes */
 506#define  PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */
 507#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
 508#define PCI_EXP_DEVSTA          10      /* Device Status */
 509#define  PCI_EXP_DEVSTA_CED     0x0001  /* Correctable Error Detected */
 510#define  PCI_EXP_DEVSTA_NFED    0x0002  /* Non-Fatal Error Detected */
 511#define  PCI_EXP_DEVSTA_FED     0x0004  /* Fatal Error Detected */
 512#define  PCI_EXP_DEVSTA_URD     0x0008  /* Unsupported Request Detected */
 513#define  PCI_EXP_DEVSTA_AUXPD   0x0010  /* AUX Power Detected */
 514#define  PCI_EXP_DEVSTA_TRPND   0x0020  /* Transactions Pending */
 515#define PCI_EXP_LNKCAP          12      /* Link Capabilities */
 516#define  PCI_EXP_LNKCAP_SLS     0x0000000f /* Supported Link Speeds */
 517#define  PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
 518#define  PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
 519#define  PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
 520#define  PCI_EXP_LNKCAP_MLW     0x000003f0 /* Maximum Link Width */
 521#define  PCI_EXP_LNKCAP_ASPMS   0x00000c00 /* ASPM Support */
 522#define  PCI_EXP_LNKCAP_L0SEL   0x00007000 /* L0s Exit Latency */
 523#define  PCI_EXP_LNKCAP_L1EL    0x00038000 /* L1 Exit Latency */
 524#define  PCI_EXP_LNKCAP_CLKPM   0x00040000 /* Clock Power Management */
 525#define  PCI_EXP_LNKCAP_SDERC   0x00080000 /* Surprise Down Error Reporting Capable */
 526#define  PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
 527#define  PCI_EXP_LNKCAP_LBNC    0x00200000 /* Link Bandwidth Notification Capability */
 528#define  PCI_EXP_LNKCAP_PN      0xff000000 /* Port Number */
 529#define PCI_EXP_LNKCTL          16      /* Link Control */
 530#define  PCI_EXP_LNKCTL_ASPMC   0x0003  /* ASPM Control */
 531#define  PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */
 532#define  PCI_EXP_LNKCTL_ASPM_L1  0x0002 /* L1 Enable */
 533#define  PCI_EXP_LNKCTL_RCB     0x0008  /* Read Completion Boundary */
 534#define  PCI_EXP_LNKCTL_LD      0x0010  /* Link Disable */
 535#define  PCI_EXP_LNKCTL_RL      0x0020  /* Retrain Link */
 536#define  PCI_EXP_LNKCTL_CCC     0x0040  /* Common Clock Configuration */
 537#define  PCI_EXP_LNKCTL_ES      0x0080  /* Extended Synch */
 538#define  PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */
 539#define  PCI_EXP_LNKCTL_HAWD    0x0200  /* Hardware Autonomous Width Disable */
 540#define  PCI_EXP_LNKCTL_LBMIE   0x0400  /* Link Bandwidth Management Interrupt Enable */
 541#define  PCI_EXP_LNKCTL_LABIE   0x0800  /* Link Autonomous Bandwidth Interrupt Enable */
 542#define PCI_EXP_LNKSTA          18      /* Link Status */
 543#define  PCI_EXP_LNKSTA_CLS     0x000f  /* Current Link Speed */
 544#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
 545#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
 546#define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
 547#define  PCI_EXP_LNKSTA_NLW     0x03f0  /* Negotiated Link Width */
 548#define  PCI_EXP_LNKSTA_NLW_X1  0x0010  /* Current Link Width x1 */
 549#define  PCI_EXP_LNKSTA_NLW_X2  0x0020  /* Current Link Width x2 */
 550#define  PCI_EXP_LNKSTA_NLW_X4  0x0040  /* Current Link Width x4 */
 551#define  PCI_EXP_LNKSTA_NLW_X8  0x0080  /* Current Link Width x8 */
 552#define  PCI_EXP_LNKSTA_NLW_SHIFT 4     /* start of NLW mask in link status */
 553#define  PCI_EXP_LNKSTA_LT      0x0800  /* Link Training */
 554#define  PCI_EXP_LNKSTA_SLC     0x1000  /* Slot Clock Configuration */
 555#define  PCI_EXP_LNKSTA_DLLLA   0x2000  /* Data Link Layer Link Active */
 556#define  PCI_EXP_LNKSTA_LBMS    0x4000  /* Link Bandwidth Management Status */
 557#define  PCI_EXP_LNKSTA_LABS    0x8000  /* Link Autonomous Bandwidth Status */
 558#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1  20      /* v1 endpoints end here */
 559#define PCI_EXP_SLTCAP          20      /* Slot Capabilities */
 560#define  PCI_EXP_SLTCAP_ABP     0x00000001 /* Attention Button Present */
 561#define  PCI_EXP_SLTCAP_PCP     0x00000002 /* Power Controller Present */
 562#define  PCI_EXP_SLTCAP_MRLSP   0x00000004 /* MRL Sensor Present */
 563#define  PCI_EXP_SLTCAP_AIP     0x00000008 /* Attention Indicator Present */
 564#define  PCI_EXP_SLTCAP_PIP     0x00000010 /* Power Indicator Present */
 565#define  PCI_EXP_SLTCAP_HPS     0x00000020 /* Hot-Plug Surprise */
 566#define  PCI_EXP_SLTCAP_HPC     0x00000040 /* Hot-Plug Capable */
 567#define  PCI_EXP_SLTCAP_SPLV    0x00007f80 /* Slot Power Limit Value */
 568#define  PCI_EXP_SLTCAP_SPLS    0x00018000 /* Slot Power Limit Scale */
 569#define  PCI_EXP_SLTCAP_EIP     0x00020000 /* Electromechanical Interlock Present */
 570#define  PCI_EXP_SLTCAP_NCCS    0x00040000 /* No Command Completed Support */
 571#define  PCI_EXP_SLTCAP_PSN     0xfff80000 /* Physical Slot Number */
 572#define PCI_EXP_SLTCTL          24      /* Slot Control */
 573#define  PCI_EXP_SLTCTL_ABPE    0x0001  /* Attention Button Pressed Enable */
 574#define  PCI_EXP_SLTCTL_PFDE    0x0002  /* Power Fault Detected Enable */
 575#define  PCI_EXP_SLTCTL_MRLSCE  0x0004  /* MRL Sensor Changed Enable */
 576#define  PCI_EXP_SLTCTL_PDCE    0x0008  /* Presence Detect Changed Enable */
 577#define  PCI_EXP_SLTCTL_CCIE    0x0010  /* Command Completed Interrupt Enable */
 578#define  PCI_EXP_SLTCTL_HPIE    0x0020  /* Hot-Plug Interrupt Enable */
 579#define  PCI_EXP_SLTCTL_AIC     0x00c0  /* Attention Indicator Control */
 580#define  PCI_EXP_SLTCTL_ATTN_IND_ON    0x0040 /* Attention Indicator on */
 581#define  PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */
 582#define  PCI_EXP_SLTCTL_ATTN_IND_OFF   0x00c0 /* Attention Indicator off */
 583#define  PCI_EXP_SLTCTL_PIC     0x0300  /* Power Indicator Control */
 584#define  PCI_EXP_SLTCTL_PWR_IND_ON     0x0100 /* Power Indicator on */
 585#define  PCI_EXP_SLTCTL_PWR_IND_BLINK  0x0200 /* Power Indicator blinking */
 586#define  PCI_EXP_SLTCTL_PWR_IND_OFF    0x0300 /* Power Indicator off */
 587#define  PCI_EXP_SLTCTL_PCC     0x0400  /* Power Controller Control */
 588#define  PCI_EXP_SLTCTL_PWR_ON         0x0000 /* Power On */
 589#define  PCI_EXP_SLTCTL_PWR_OFF        0x0400 /* Power Off */
 590#define  PCI_EXP_SLTCTL_EIC     0x0800  /* Electromechanical Interlock Control */
 591#define  PCI_EXP_SLTCTL_DLLSCE  0x1000  /* Data Link Layer State Changed Enable */
 592#define PCI_EXP_SLTSTA          26      /* Slot Status */
 593#define  PCI_EXP_SLTSTA_ABP     0x0001  /* Attention Button Pressed */
 594#define  PCI_EXP_SLTSTA_PFD     0x0002  /* Power Fault Detected */
 595#define  PCI_EXP_SLTSTA_MRLSC   0x0004  /* MRL Sensor Changed */
 596#define  PCI_EXP_SLTSTA_PDC     0x0008  /* Presence Detect Changed */
 597#define  PCI_EXP_SLTSTA_CC      0x0010  /* Command Completed */
 598#define  PCI_EXP_SLTSTA_MRLSS   0x0020  /* MRL Sensor State */
 599#define  PCI_EXP_SLTSTA_PDS     0x0040  /* Presence Detect State */
 600#define  PCI_EXP_SLTSTA_EIS     0x0080  /* Electromechanical Interlock Status */
 601#define  PCI_EXP_SLTSTA_DLLSC   0x0100  /* Data Link Layer State Changed */
 602#define PCI_EXP_RTCTL           28      /* Root Control */
 603#define  PCI_EXP_RTCTL_SECEE    0x0001  /* System Error on Correctable Error */
 604#define  PCI_EXP_RTCTL_SENFEE   0x0002  /* System Error on Non-Fatal Error */
 605#define  PCI_EXP_RTCTL_SEFEE    0x0004  /* System Error on Fatal Error */
 606#define  PCI_EXP_RTCTL_PMEIE    0x0008  /* PME Interrupt Enable */
 607#define  PCI_EXP_RTCTL_CRSSVE   0x0010  /* CRS Software Visibility Enable */
 608#define PCI_EXP_RTCAP           30      /* Root Capabilities */
 609#define  PCI_EXP_RTCAP_CRSVIS   0x0001  /* CRS Software Visibility capability */
 610#define PCI_EXP_RTSTA           32      /* Root Status */
 611#define PCI_EXP_RTSTA_PME       0x00010000 /* PME status */
 612#define PCI_EXP_RTSTA_PENDING   0x00020000 /* PME pending */
 613/*
 614 * The Device Capabilities 2, Device Status 2, Device Control 2,
 615 * Link Capabilities 2, Link Status 2, Link Control 2,
 616 * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers
 617 * are only present on devices with PCIe Capability version 2.
 618 * Use pcie_capability_read_word() and similar interfaces to use them
 619 * safely.
 620 */
 621#define PCI_EXP_DEVCAP2         36      /* Device Capabilities 2 */
 622#define  PCI_EXP_DEVCAP2_ARI            0x00000020 /* Alternative Routing-ID */
 623#define  PCI_EXP_DEVCAP2_ATOMIC_ROUTE   0x00000040 /* Atomic Op routing */
 624#define PCI_EXP_DEVCAP2_ATOMIC_COMP64   0x00000100 /* Atomic 64-bit compare */
 625#define  PCI_EXP_DEVCAP2_LTR            0x00000800 /* Latency tolerance reporting */
 626#define  PCI_EXP_DEVCAP2_OBFF_MASK      0x000c0000 /* OBFF support mechanism */
 627#define  PCI_EXP_DEVCAP2_OBFF_MSG       0x00040000 /* New message signaling */
 628#define  PCI_EXP_DEVCAP2_OBFF_WAKE      0x00080000 /* Re-use WAKE# for OBFF */
 629#define PCI_EXP_DEVCTL2         40      /* Device Control 2 */
 630#define  PCI_EXP_DEVCTL2_COMP_TIMEOUT   0x000f  /* Completion Timeout Value */
 631#define  PCI_EXP_DEVCTL2_ARI            0x0020  /* Alternative Routing-ID */
 632#define PCI_EXP_DEVCTL2_ATOMIC_REQ      0x0040  /* Set Atomic requests */
 633#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
 634#define  PCI_EXP_DEVCTL2_IDO_REQ_EN     0x0100  /* Allow IDO for requests */
 635#define  PCI_EXP_DEVCTL2_IDO_CMP_EN     0x0200  /* Allow IDO for completions */
 636#define  PCI_EXP_DEVCTL2_LTR_EN         0x0400  /* Enable LTR mechanism */
 637#define  PCI_EXP_DEVCTL2_OBFF_MSGA_EN   0x2000  /* Enable OBFF Message type A */
 638#define  PCI_EXP_DEVCTL2_OBFF_MSGB_EN   0x4000  /* Enable OBFF Message type B */
 639#define  PCI_EXP_DEVCTL2_OBFF_WAKE_EN   0x6000  /* OBFF using WAKE# signaling */
 640#define PCI_EXP_DEVSTA2         42      /* Device Status 2 */
 641#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2  44      /* v2 endpoints end here */
 642#define PCI_EXP_LNKCAP2         44      /* Link Capabilities 2 */
 643#define  PCI_EXP_LNKCAP2_SLS_2_5GB      0x00000002 /* Supported Speed 2.5GT/s */
 644#define  PCI_EXP_LNKCAP2_SLS_5_0GB      0x00000004 /* Supported Speed 5.0GT/s */
 645#define  PCI_EXP_LNKCAP2_SLS_8_0GB      0x00000008 /* Supported Speed 8.0GT/s */
 646#define  PCI_EXP_LNKCAP2_CROSSLINK      0x00000100 /* Crosslink supported */
 647#define PCI_EXP_LNKCTL2         48      /* Link Control 2 */
 648#define PCI_EXP_LNKSTA2         50      /* Link Status 2 */
 649#define PCI_EXP_SLTCAP2         52      /* Slot Capabilities 2 */
 650#define PCI_EXP_SLTCTL2         56      /* Slot Control 2 */
 651#define PCI_EXP_SLTSTA2         58      /* Slot Status 2 */
 652
 653/* Extended Capabilities (PCI-X 2.0 and Express) */
 654#define PCI_EXT_CAP_ID(header)          (header & 0x0000ffff)
 655#define PCI_EXT_CAP_VER(header)         ((header >> 16) & 0xf)
 656#define PCI_EXT_CAP_NEXT(header)        ((header >> 20) & 0xffc)
 657
 658#define PCI_EXT_CAP_ID_ERR      0x01    /* Advanced Error Reporting */
 659#define PCI_EXT_CAP_ID_VC       0x02    /* Virtual Channel Capability */
 660#define PCI_EXT_CAP_ID_DSN      0x03    /* Device Serial Number */
 661#define PCI_EXT_CAP_ID_PWR      0x04    /* Power Budgeting */
 662#define PCI_EXT_CAP_ID_RCLD     0x05    /* Root Complex Link Declaration */
 663#define PCI_EXT_CAP_ID_RCILC    0x06    /* Root Complex Internal Link Control */
 664#define PCI_EXT_CAP_ID_RCEC     0x07    /* Root Complex Event Collector */
 665#define PCI_EXT_CAP_ID_MFVC     0x08    /* Multi-Function VC Capability */
 666#define PCI_EXT_CAP_ID_VC9      0x09    /* same as _VC */
 667#define PCI_EXT_CAP_ID_RCRB     0x0A    /* Root Complex RB? */
 668#define PCI_EXT_CAP_ID_VNDR     0x0B    /* Vendor-Specific */
 669#define PCI_EXT_CAP_ID_CAC      0x0C    /* Config Access - obsolete */
 670#define PCI_EXT_CAP_ID_ACS      0x0D    /* Access Control Services */
 671#define PCI_EXT_CAP_ID_ARI      0x0E    /* Alternate Routing ID */
 672#define PCI_EXT_CAP_ID_ATS      0x0F    /* Address Translation Services */
 673#define PCI_EXT_CAP_ID_SRIOV    0x10    /* Single Root I/O Virtualization */
 674#define PCI_EXT_CAP_ID_MRIOV    0x11    /* Multi Root I/O Virtualization */
 675#define PCI_EXT_CAP_ID_MCAST    0x12    /* Multicast */
 676#define PCI_EXT_CAP_ID_PRI      0x13    /* Page Request Interface */
 677#define PCI_EXT_CAP_ID_AMD_XXX  0x14    /* Reserved for AMD */
 678#define PCI_EXT_CAP_ID_REBAR    0x15    /* Resizable BAR */
 679#define PCI_EXT_CAP_ID_DPA      0x16    /* Dynamic Power Allocation */
 680#define PCI_EXT_CAP_ID_TPH      0x17    /* TPH Requester */
 681#define PCI_EXT_CAP_ID_LTR      0x18    /* Latency Tolerance Reporting */
 682#define PCI_EXT_CAP_ID_SECPCI   0x19    /* Secondary PCIe Capability */
 683#define PCI_EXT_CAP_ID_PMUX     0x1A    /* Protocol Multiplexing */
 684#define PCI_EXT_CAP_ID_PASID    0x1B    /* Process Address Space ID */
 685#define PCI_EXT_CAP_ID_DPC      0x1D    /* Downstream Port Containment */
 686#define PCI_EXT_CAP_ID_L1SS     0x1E    /* L1 PM Substates */
 687#define PCI_EXT_CAP_ID_PTM      0x1F    /* Precision Time Measurement */
 688#define PCI_EXT_CAP_ID_MAX      PCI_EXT_CAP_ID_PTM
 689
 690#define PCI_EXT_CAP_DSN_SIZEOF  12
 691#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
 692
 693/* Advanced Error Reporting */
 694#define PCI_ERR_UNCOR_STATUS    4       /* Uncorrectable Error Status */
 695#define  PCI_ERR_UNC_UND        0x00000001      /* Undefined */
 696#define  PCI_ERR_UNC_DLP        0x00000010      /* Data Link Protocol */
 697#define  PCI_ERR_UNC_SURPDN     0x00000020      /* Surprise Down */
 698#define  PCI_ERR_UNC_POISON_TLP 0x00001000      /* Poisoned TLP */
 699#define  PCI_ERR_UNC_FCP        0x00002000      /* Flow Control Protocol */
 700#define  PCI_ERR_UNC_COMP_TIME  0x00004000      /* Completion Timeout */
 701#define  PCI_ERR_UNC_COMP_ABORT 0x00008000      /* Completer Abort */
 702#define  PCI_ERR_UNC_UNX_COMP   0x00010000      /* Unexpected Completion */
 703#define  PCI_ERR_UNC_RX_OVER    0x00020000      /* Receiver Overflow */
 704#define  PCI_ERR_UNC_MALF_TLP   0x00040000      /* Malformed TLP */
 705#define  PCI_ERR_UNC_ECRC       0x00080000      /* ECRC Error Status */
 706#define  PCI_ERR_UNC_UNSUP      0x00100000      /* Unsupported Request */
 707#define  PCI_ERR_UNC_ACSV       0x00200000      /* ACS Violation */
 708#define  PCI_ERR_UNC_INTN       0x00400000      /* internal error */
 709#define  PCI_ERR_UNC_MCBTLP     0x00800000      /* MC blocked TLP */
 710#define  PCI_ERR_UNC_ATOMEG     0x01000000      /* Atomic egress blocked */
 711#define  PCI_ERR_UNC_TLPPRE     0x02000000      /* TLP prefix blocked */
 712#define PCI_ERR_UNCOR_MASK      8       /* Uncorrectable Error Mask */
 713        /* Same bits as above */
 714#define PCI_ERR_UNCOR_SEVER     12      /* Uncorrectable Error Severity */
 715        /* Same bits as above */
 716#define PCI_ERR_COR_STATUS      16      /* Correctable Error Status */
 717#define  PCI_ERR_COR_RCVR       0x00000001      /* Receiver Error Status */
 718#define  PCI_ERR_COR_BAD_TLP    0x00000040      /* Bad TLP Status */
 719#define  PCI_ERR_COR_BAD_DLLP   0x00000080      /* Bad DLLP Status */
 720#define  PCI_ERR_COR_REP_ROLL   0x00000100      /* REPLAY_NUM Rollover */
 721#define  PCI_ERR_COR_REP_TIMER  0x00001000      /* Replay Timer Timeout */
 722#define  PCI_ERR_COR_ADV_NFAT   0x00002000      /* Advisory Non-Fatal */
 723#define  PCI_ERR_COR_INTERNAL   0x00004000      /* Corrected Internal */
 724#define  PCI_ERR_COR_LOG_OVER   0x00008000      /* Header Log Overflow */
 725#define PCI_ERR_COR_MASK        20      /* Correctable Error Mask */
 726        /* Same bits as above */
 727#define PCI_ERR_CAP             24      /* Advanced Error Capabilities */
 728#define  PCI_ERR_CAP_FEP(x)     ((x) & 31)      /* First Error Pointer */
 729#define  PCI_ERR_CAP_ECRC_GENC  0x00000020      /* ECRC Generation Capable */
 730#define  PCI_ERR_CAP_ECRC_GENE  0x00000040      /* ECRC Generation Enable */
 731#define  PCI_ERR_CAP_ECRC_CHKC  0x00000080      /* ECRC Check Capable */
 732#define  PCI_ERR_CAP_ECRC_CHKE  0x00000100      /* ECRC Check Enable */
 733#define PCI_ERR_HEADER_LOG      28      /* Header Log Register (16 bytes) */
 734#define PCI_ERR_ROOT_COMMAND    44      /* Root Error Command */
 735/* Correctable Err Reporting Enable */
 736#define PCI_ERR_ROOT_CMD_COR_EN         0x00000001
 737/* Non-fatal Err Reporting Enable */
 738#define PCI_ERR_ROOT_CMD_NONFATAL_EN    0x00000002
 739/* Fatal Err Reporting Enable */
 740#define PCI_ERR_ROOT_CMD_FATAL_EN       0x00000004
 741#define PCI_ERR_ROOT_STATUS     48
 742#define PCI_ERR_ROOT_COR_RCV            0x00000001      /* ERR_COR Received */
 743/* Multi ERR_COR Received */
 744#define PCI_ERR_ROOT_MULTI_COR_RCV      0x00000002
 745/* ERR_FATAL/NONFATAL Received */
 746#define PCI_ERR_ROOT_UNCOR_RCV          0x00000004
 747/* Multi ERR_FATAL/NONFATAL Received */
 748#define PCI_ERR_ROOT_MULTI_UNCOR_RCV    0x00000008
 749#define PCI_ERR_ROOT_FIRST_FATAL        0x00000010      /* First Fatal */
 750#define PCI_ERR_ROOT_NONFATAL_RCV       0x00000020      /* Non-Fatal Received */
 751#define PCI_ERR_ROOT_FATAL_RCV          0x00000040      /* Fatal Received */
 752#define PCI_ERR_ROOT_ERR_SRC    52      /* Error Source Identification */
 753
 754/* Virtual Channel */
 755#define PCI_VC_PORT_CAP1        4
 756#define  PCI_VC_CAP1_EVCC       0x00000007      /* extended VC count */
 757#define  PCI_VC_CAP1_LPEVCC     0x00000070      /* low prio extended VC count */
 758#define  PCI_VC_CAP1_ARB_SIZE   0x00000c00
 759#define PCI_VC_PORT_CAP2        8
 760#define  PCI_VC_CAP2_32_PHASE           0x00000002
 761#define  PCI_VC_CAP2_64_PHASE           0x00000004
 762#define  PCI_VC_CAP2_128_PHASE          0x00000008
 763#define  PCI_VC_CAP2_ARB_OFF            0xff000000
 764#define PCI_VC_PORT_CTRL        12
 765#define  PCI_VC_PORT_CTRL_LOAD_TABLE    0x00000001
 766#define PCI_VC_PORT_STATUS      14
 767#define  PCI_VC_PORT_STATUS_TABLE       0x00000001
 768#define PCI_VC_RES_CAP          16
 769#define  PCI_VC_RES_CAP_32_PHASE        0x00000002
 770#define  PCI_VC_RES_CAP_64_PHASE        0x00000004
 771#define  PCI_VC_RES_CAP_128_PHASE       0x00000008
 772#define  PCI_VC_RES_CAP_128_PHASE_TB    0x00000010
 773#define  PCI_VC_RES_CAP_256_PHASE       0x00000020
 774#define  PCI_VC_RES_CAP_ARB_OFF         0xff000000
 775#define PCI_VC_RES_CTRL         20
 776#define  PCI_VC_RES_CTRL_LOAD_TABLE     0x00010000
 777#define  PCI_VC_RES_CTRL_ARB_SELECT     0x000e0000
 778#define  PCI_VC_RES_CTRL_ID             0x07000000
 779#define  PCI_VC_RES_CTRL_ENABLE         0x80000000
 780#define PCI_VC_RES_STATUS       26
 781#define  PCI_VC_RES_STATUS_TABLE        0x00000001
 782#define  PCI_VC_RES_STATUS_NEGO         0x00000002
 783#define PCI_CAP_VC_BASE_SIZEOF          0x10
 784#define PCI_CAP_VC_PER_VC_SIZEOF        0x0C
 785
 786/* Power Budgeting */
 787#define PCI_PWR_DSR             4       /* Data Select Register */
 788#define PCI_PWR_DATA            8       /* Data Register */
 789#define  PCI_PWR_DATA_BASE(x)   ((x) & 0xff)        /* Base Power */
 790#define  PCI_PWR_DATA_SCALE(x)  (((x) >> 8) & 3)    /* Data Scale */
 791#define  PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7)   /* PM Sub State */
 792#define  PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
 793#define  PCI_PWR_DATA_TYPE(x)   (((x) >> 15) & 7)   /* Type */
 794#define  PCI_PWR_DATA_RAIL(x)   (((x) >> 18) & 7)   /* Power Rail */
 795#define PCI_PWR_CAP             12      /* Capability */
 796#define  PCI_PWR_CAP_BUDGET(x)  ((x) & 1)       /* Included in system budget */
 797#define PCI_EXT_CAP_PWR_SIZEOF  16
 798
 799/* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */
 800#define PCI_VNDR_HEADER         4       /* Vendor-Specific Header */
 801#define  PCI_VNDR_HEADER_ID(x)  ((x) & 0xffff)
 802#define  PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf)
 803#define  PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff)
 804
 805/*
 806 * HyperTransport sub capability types
 807 *
 808 * Unfortunately there are both 3 bit and 5 bit capability types defined
 809 * in the HT spec, catering for that is a little messy. You probably don't
 810 * want to use these directly, just use pci_find_ht_capability() and it
 811 * will do the right thing for you.
 812 */
 813#define HT_3BIT_CAP_MASK        0xE0
 814#define HT_CAPTYPE_SLAVE        0x00    /* Slave/Primary link configuration */
 815#define HT_CAPTYPE_HOST         0x20    /* Host/Secondary link configuration */
 816
 817#define HT_5BIT_CAP_MASK        0xF8
 818#define HT_CAPTYPE_IRQ          0x80    /* IRQ Configuration */
 819#define HT_CAPTYPE_REMAPPING_40 0xA0    /* 40 bit address remapping */
 820#define HT_CAPTYPE_REMAPPING_64 0xA2    /* 64 bit address remapping */
 821#define HT_CAPTYPE_UNITID_CLUMP 0x90    /* Unit ID clumping */
 822#define HT_CAPTYPE_EXTCONF      0x98    /* Extended Configuration Space Access */
 823#define HT_CAPTYPE_MSI_MAPPING  0xA8    /* MSI Mapping Capability */
 824#define  HT_MSI_FLAGS           0x02            /* Offset to flags */
 825#define  HT_MSI_FLAGS_ENABLE    0x1             /* Mapping enable */
 826#define  HT_MSI_FLAGS_FIXED     0x2             /* Fixed mapping only */
 827#define  HT_MSI_FIXED_ADDR      0x00000000FEE00000ULL   /* Fixed addr */
 828#define  HT_MSI_ADDR_LO         0x04            /* Offset to low addr bits */
 829#define  HT_MSI_ADDR_LO_MASK    0xFFF00000      /* Low address bit mask */
 830#define  HT_MSI_ADDR_HI         0x08            /* Offset to high addr bits */
 831#define HT_CAPTYPE_DIRECT_ROUTE 0xB0    /* Direct routing configuration */
 832#define HT_CAPTYPE_VCSET        0xB8    /* Virtual Channel configuration */
 833#define HT_CAPTYPE_ERROR_RETRY  0xC0    /* Retry on error configuration */
 834#define HT_CAPTYPE_GEN3         0xD0    /* Generation 3 HyperTransport configuration */
 835#define HT_CAPTYPE_PM           0xE0    /* HyperTransport power management configuration */
 836#define HT_CAP_SIZEOF_LONG      28      /* slave & primary */
 837#define HT_CAP_SIZEOF_SHORT     24      /* host & secondary */
 838
 839/* Alternative Routing-ID Interpretation */
 840#define PCI_ARI_CAP             0x04    /* ARI Capability Register */
 841#define  PCI_ARI_CAP_MFVC       0x0001  /* MFVC Function Groups Capability */
 842#define  PCI_ARI_CAP_ACS        0x0002  /* ACS Function Groups Capability */
 843#define  PCI_ARI_CAP_NFN(x)     (((x) >> 8) & 0xff) /* Next Function Number */
 844#define PCI_ARI_CTRL            0x06    /* ARI Control Register */
 845#define  PCI_ARI_CTRL_MFVC      0x0001  /* MFVC Function Groups Enable */
 846#define  PCI_ARI_CTRL_ACS       0x0002  /* ACS Function Groups Enable */
 847#define  PCI_ARI_CTRL_FG(x)     (((x) >> 4) & 7) /* Function Group */
 848#define PCI_EXT_CAP_ARI_SIZEOF  8
 849
 850/* Address Translation Service */
 851#define PCI_ATS_CAP             0x04    /* ATS Capability Register */
 852#define  PCI_ATS_CAP_QDEP(x)    ((x) & 0x1f)    /* Invalidate Queue Depth */
 853#define  PCI_ATS_MAX_QDEP       32      /* Max Invalidate Queue Depth */
 854#define PCI_ATS_CTRL            0x06    /* ATS Control Register */
 855#define  PCI_ATS_CTRL_ENABLE    0x8000  /* ATS Enable */
 856#define  PCI_ATS_CTRL_STU(x)    ((x) & 0x1f)    /* Smallest Translation Unit */
 857#define  PCI_ATS_MIN_STU        12      /* shift of minimum STU block */
 858#define PCI_EXT_CAP_ATS_SIZEOF  8
 859
 860/* Page Request Interface */
 861#define PCI_PRI_CTRL            0x04    /* PRI control register */
 862#define  PCI_PRI_CTRL_ENABLE    0x01    /* Enable */
 863#define  PCI_PRI_CTRL_RESET     0x02    /* Reset */
 864#define PCI_PRI_STATUS          0x06    /* PRI status register */
 865#define  PCI_PRI_STATUS_RF      0x001   /* Response Failure */
 866#define  PCI_PRI_STATUS_UPRGI   0x002   /* Unexpected PRG index */
 867#define  PCI_PRI_STATUS_STOPPED 0x100   /* PRI Stopped */
 868#define PCI_PRI_MAX_REQ         0x08    /* PRI max reqs supported */
 869#define PCI_PRI_ALLOC_REQ       0x0c    /* PRI max reqs allowed */
 870#define PCI_EXT_CAP_PRI_SIZEOF  16
 871
 872/* Process Address Space ID */
 873#define PCI_PASID_CAP           0x04    /* PASID feature register */
 874#define  PCI_PASID_CAP_EXEC     0x02    /* Exec permissions Supported */
 875#define  PCI_PASID_CAP_PRIV     0x04    /* Privilege Mode Supported */
 876#define PCI_PASID_CTRL          0x06    /* PASID control register */
 877#define  PCI_PASID_CTRL_ENABLE  0x01    /* Enable bit */
 878#define  PCI_PASID_CTRL_EXEC    0x02    /* Exec permissions Enable */
 879#define  PCI_PASID_CTRL_PRIV    0x04    /* Privilege Mode Enable */
 880#define PCI_EXT_CAP_PASID_SIZEOF        8
 881
 882/* Single Root I/O Virtualization */
 883#define PCI_SRIOV_CAP           0x04    /* SR-IOV Capabilities */
 884#define  PCI_SRIOV_CAP_VFM      0x01    /* VF Migration Capable */
 885#define  PCI_SRIOV_CAP_INTR(x)  ((x) >> 21) /* Interrupt Message Number */
 886#define PCI_SRIOV_CTRL          0x08    /* SR-IOV Control */
 887#define  PCI_SRIOV_CTRL_VFE     0x01    /* VF Enable */
 888#define  PCI_SRIOV_CTRL_VFM     0x02    /* VF Migration Enable */
 889#define  PCI_SRIOV_CTRL_INTR    0x04    /* VF Migration Interrupt Enable */
 890#define  PCI_SRIOV_CTRL_MSE     0x08    /* VF Memory Space Enable */
 891#define  PCI_SRIOV_CTRL_ARI     0x10    /* ARI Capable Hierarchy */
 892#define PCI_SRIOV_STATUS        0x0a    /* SR-IOV Status */
 893#define  PCI_SRIOV_STATUS_VFM   0x01    /* VF Migration Status */
 894#define PCI_SRIOV_INITIAL_VF    0x0c    /* Initial VFs */
 895#define PCI_SRIOV_TOTAL_VF      0x0e    /* Total VFs */
 896#define PCI_SRIOV_NUM_VF        0x10    /* Number of VFs */
 897#define PCI_SRIOV_FUNC_LINK     0x12    /* Function Dependency Link */
 898#define PCI_SRIOV_VF_OFFSET     0x14    /* First VF Offset */
 899#define PCI_SRIOV_VF_STRIDE     0x16    /* Following VF Stride */
 900#define PCI_SRIOV_VF_DID        0x1a    /* VF Device ID */
 901#define PCI_SRIOV_SUP_PGSIZE    0x1c    /* Supported Page Sizes */
 902#define PCI_SRIOV_SYS_PGSIZE    0x20    /* System Page Size */
 903#define PCI_SRIOV_BAR           0x24    /* VF BAR0 */
 904#define  PCI_SRIOV_NUM_BARS     6       /* Number of VF BARs */
 905#define PCI_SRIOV_VFM           0x3c    /* VF Migration State Array Offset*/
 906#define  PCI_SRIOV_VFM_BIR(x)   ((x) & 7)       /* State BIR */
 907#define  PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7)     /* State Offset */
 908#define  PCI_SRIOV_VFM_UA       0x0     /* Inactive.Unavailable */
 909#define  PCI_SRIOV_VFM_MI       0x1     /* Dormant.MigrateIn */
 910#define  PCI_SRIOV_VFM_MO       0x2     /* Active.MigrateOut */
 911#define  PCI_SRIOV_VFM_AV       0x3     /* Active.Available */
 912#define PCI_EXT_CAP_SRIOV_SIZEOF 64
 913
 914#define PCI_LTR_MAX_SNOOP_LAT   0x4
 915#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
 916#define  PCI_LTR_VALUE_MASK     0x000003ff
 917#define  PCI_LTR_SCALE_MASK     0x00001c00
 918#define  PCI_LTR_SCALE_SHIFT    10
 919#define PCI_EXT_CAP_LTR_SIZEOF  8
 920
 921/* Access Control Service */
 922#define PCI_ACS_CAP             0x04    /* ACS Capability Register */
 923#define  PCI_ACS_SV             0x01    /* Source Validation */
 924#define  PCI_ACS_TB             0x02    /* Translation Blocking */
 925#define  PCI_ACS_RR             0x04    /* P2P Request Redirect */
 926#define  PCI_ACS_CR             0x08    /* P2P Completion Redirect */
 927#define  PCI_ACS_UF             0x10    /* Upstream Forwarding */
 928#define  PCI_ACS_EC             0x20    /* P2P Egress Control */
 929#define  PCI_ACS_DT             0x40    /* Direct Translated P2P */
 930#define PCI_ACS_EGRESS_BITS     0x05    /* ACS Egress Control Vector Size */
 931#define PCI_ACS_CTRL            0x06    /* ACS Control Register */
 932#define PCI_ACS_EGRESS_CTL_V    0x08    /* ACS Egress Control Vector */
 933
 934#define PCI_VSEC_HDR            4       /* extended cap - vendor-specific */
 935#define  PCI_VSEC_HDR_LEN_SHIFT 20      /* shift for length field */
 936
 937/* SATA capability */
 938#define PCI_SATA_REGS           4       /* SATA REGs specifier */
 939#define  PCI_SATA_REGS_MASK     0xF     /* location - BAR#/inline */
 940#define  PCI_SATA_REGS_INLINE   0xF     /* REGS in config space */
 941#define PCI_SATA_SIZEOF_SHORT   8
 942#define PCI_SATA_SIZEOF_LONG    16
 943
 944/* Resizable BARs */
 945#define PCI_REBAR_CTRL          8       /* control register */
 946#define  PCI_REBAR_CTRL_NBAR_MASK       (7 << 5)        /* mask for # bars */
 947#define  PCI_REBAR_CTRL_NBAR_SHIFT      5       /* shift for # bars */
 948
 949/* Dynamic Power Allocation */
 950#define PCI_DPA_CAP             4       /* capability register */
 951#define  PCI_DPA_CAP_SUBSTATE_MASK      0x1F    /* # substates - 1 */
 952#define PCI_DPA_BASE_SIZEOF     16      /* size with 0 substates */
 953
 954/* TPH Requester */
 955#define PCI_TPH_CAP             4       /* capability register */
 956#define  PCI_TPH_CAP_LOC_MASK   0x600   /* location mask */
 957#define   PCI_TPH_LOC_NONE      0x000   /* no location */
 958#define   PCI_TPH_LOC_CAP       0x200   /* in capability */
 959#define   PCI_TPH_LOC_MSIX      0x400   /* in MSI-X */
 960#define PCI_TPH_CAP_ST_MASK     0x07FF0000      /* st table mask */
 961#define PCI_TPH_CAP_ST_SHIFT    16      /* st table shift */
 962#define PCI_TPH_BASE_SIZEOF     12      /* size with no st table */
 963
 964/* Downstream Port Containment */
 965#define PCI_EXP_DPC_CAP                 4       /* DPC Capability */
 966#define  PCI_EXP_DPC_CAP_RP_EXT         0x20    /* Root Port Extensions for DPC */
 967#define  PCI_EXP_DPC_CAP_POISONED_TLP   0x40    /* Poisoned TLP Egress Blocking Supported */
 968#define  PCI_EXP_DPC_CAP_SW_TRIGGER     0x80    /* Software Triggering Supported */
 969#define  PCI_EXP_DPC_CAP_DL_ACTIVE      0x1000  /* ERR_COR signal on DL_Active supported */
 970
 971#define PCI_EXP_DPC_CTL                 6       /* DPC control */
 972#define  PCI_EXP_DPC_CTL_EN_NONFATAL    0x02    /* Enable trigger on ERR_NONFATAL message */
 973#define  PCI_EXP_DPC_CTL_INT_EN         0x08    /* DPC Interrupt Enable */
 974
 975#define PCI_EXP_DPC_STATUS              8       /* DPC Status */
 976#define  PCI_EXP_DPC_STATUS_TRIGGER     0x01    /* Trigger Status */
 977#define  PCI_EXP_DPC_STATUS_INTERRUPT   0x08    /* Interrupt Status */
 978#define  PCI_EXP_DPC_RP_BUSY            0x10    /* Root Port Busy */
 979
 980#define PCI_EXP_DPC_SOURCE_ID           10      /* DPC Source Identifier */
 981
 982/* Precision Time Measurement */
 983#define PCI_PTM_CAP                     0x04        /* PTM Capability */
 984#define  PCI_PTM_CAP_REQ                0x00000001  /* Requester capable */
 985#define  PCI_PTM_CAP_ROOT               0x00000004  /* Root capable */
 986#define  PCI_PTM_GRANULARITY_MASK       0x0000FF00  /* Clock granularity */
 987#define PCI_PTM_CTRL                    0x08        /* PTM Control */
 988#define  PCI_PTM_CTRL_ENABLE            0x00000001  /* PTM enable */
 989#define  PCI_PTM_CTRL_ROOT              0x00000002  /* Root select */
 990
 991/* L1 PM Substates */
 992#define PCI_L1SS_CAP                4   /* capability register */
 993#define  PCI_L1SS_CAP_PCIPM_L1_2         1      /* PCI PM L1.2 Support */
 994#define  PCI_L1SS_CAP_PCIPM_L1_1         2      /* PCI PM L1.1 Support */
 995#define  PCI_L1SS_CAP_ASPM_L1_2          4      /* ASPM L1.2 Support */
 996#define  PCI_L1SS_CAP_ASPM_L1_1          8      /* ASPM L1.1 Support */
 997#define  PCI_L1SS_CAP_L1_PM_SS          16      /* L1 PM Substates Support */
 998#define PCI_L1SS_CTL1               8   /* Control Register 1 */
 999#define  PCI_L1SS_CTL1_PCIPM_L1_2       1       /* PCI PM L1.2 Enable */
1000#define  PCI_L1SS_CTL1_PCIPM_L1_1       2       /* PCI PM L1.1 Support */
1001#define  PCI_L1SS_CTL1_ASPM_L1_2        4       /* ASPM L1.2 Support */
1002#define  PCI_L1SS_CTL1_ASPM_L1_1        8       /* ASPM L1.1 Support */
1003#define  PCI_L1SS_CTL1_L1SS_MASK        0x0000000F
1004#define PCI_L1SS_CTL2               0xC /* Control Register 2 */
1005