akaros/kern/arch/x86/ioapic.h
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   1/*
   2 * This file is part of the UCB release of Plan 9. It is subject to the license
   3 * terms in the LICENSE file found in the top-level directory of this
   4 * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
   5 * part of the UCB release of Plan 9, including this file, may be copied,
   6 * modified, propagated, or distributed except according to the terms contained
   7 * in the LICENSE file.
   8 */
   9
  10#pragma once
  11
  12#include <atomic.h>
  13#include <arch/apic.h>
  14
  15enum {
  16        MaxAPICNO       = 254,          /* 255 is physical broadcast */
  17};
  18
  19enum {                                  /* I/O APIC registers */
  20        IoapicID        = 0x00,         /* ID */
  21        IoapicVER       = 0x01,         /* version */
  22        IoapicARB       = 0x02,         /* arbitration ID */
  23        IoapicRDT       = 0x10,         /* redirection table */
  24};
  25
  26/*
  27 * Common bits for
  28 *      I/O APIC Redirection Table Entry;
  29 *      Local APIC Local Interrupt Vector Table;
  30 *      Local APIC Inter-Processor Interrupt;
  31 *      Local APIC Timer Vector Table.
  32 */
  33enum {
  34        ApicFIXED       = 0x00000000,   /* [10:8] Delivery Mode */
  35        ApicLOWEST      = 0x00000100,   /* Lowest priority */
  36        ApicSMI         = 0x00000200,   /* System Management Interrupt */
  37        ApicRR          = 0x00000300,   /* Remote Read */
  38        ApicNMI         = 0x00000400,
  39        ApicINIT        = 0x00000500,   /* INIT/RESET */
  40        ApicSTARTUP     = 0x00000600,   /* Startup IPI */
  41        ApicExtINT      = 0x00000700,
  42
  43        ApicPHYSICAL    = 0x00000000,   /* [11] Destination Mode (RW) */
  44        ApicLOGICAL     = 0x00000800,
  45
  46        ApicDELIVS      = 0x00001000,   /* [12] Delivery Status (RO) */
  47        ApicHIGH        = 0x00000000,   /* [13] IRQ Input Pin Polarity (RW) */
  48        ApicLOW         = 0x00002000,
  49        ApicRemoteIRR   = 0x00004000,   /* [14] Remote IRR (RO) */
  50        ApicEDGE        = 0x00000000,   /* [15] Trigger Mode (RW) */
  51        ApicLEVEL       = 0x00008000,
  52        ApicIMASK       = 0x00010000,   /* [16] Interrupt Mask */
  53        IOAPIC_PBASE    = 0xfec00000,   /* default *physical* address */
  54};
  55
  56extern int mpisabusno;
  57
  58void ioapicintrinit(int busno, int apicno, int intin, int devno, int lo);
  59void ioapiconline(void);
  60void ioapicinit(int id, int ibase, uintptr_t pa);
  61void ioapicrdtr(struct apic*, int unused_int, int*, int*);
  62void ioapicrdtw(struct apic*, int unused_int, int, int);
  63char *ioapicdump(char *start, char *end);
  64