akaros/kern/arch/x86/io.h
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   1/*
   2 * This file is part of the UCB release of Plan 9. It is subject to the license
   3 * terms in the LICENSE file found in the top-level directory of this
   4 * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
   5 * part of the UCB release of Plan 9, including this file, may be copied,
   6 * modified, propagated, or distributed except according to the terms contained
   7 * in the LICENSE file.
   8 */
   9
  10#pragma once
  11
  12enum {
  13        BusCBUS = 0,                            /* Corollary CBUS */
  14        BusCBUSII,      /* Corollary CBUS II */
  15        BusEISA,        /* Extended ISA */
  16        BusFUTURE,      /* IEEE Futurebus */
  17        BusINTERN,      /* Internal bus */
  18        BusISA, /* Industry Standard Architecture */
  19        BusMBI, /* Multibus I */
  20        BusMBII,        /* Multibus II */
  21        BusMCA, /* Micro Channel Architecture */
  22        BusMPI, /* MPI */
  23        BusMPSA,        /* MPSA */
  24        BusNUBUS,       /* Apple Macintosh NuBus */
  25        BusPCI, /* Peripheral Component Interconnect */
  26        BusPCMCIA,      /* PC Memory Card International Association */
  27        BusTC,  /* DEC TurboChannel */
  28        BusVL,  /* VESA Local bus */
  29        BusVME, /* VMEbus */
  30        BusXPRESS,      /* Express System Bus */
  31        BusLAPIC,       /* Local APIC, fake type */
  32        BusIPI, /* IPIs, fake type like the LAPIC */
  33};
  34
  35#define MKBUS(t,b,d,f)  (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
  36#define BUSFNO(tbdf)    (((tbdf)>>8)&0x07)
  37#define BUSDNO(tbdf)    (((tbdf)>>11)&0x1F)
  38#define BUSBNO(tbdf)    (((tbdf)>>16)&0xFF)
  39#define BUSTYPE(tbdf)   ((tbdf)>>24)
  40#define BUSBDF(tbdf)    ((tbdf)&0x00FFFF00)
  41#define BUSUNKNOWN      (-1)
  42
  43enum {
  44        MaxEISA = 16,
  45        CfgEISA = 0xC80,
  46};
  47
  48/* IO Ports */
  49
  50#define CMOS_RAM_IDX                    0x70
  51#define CMOS_RAM_DATA                   0x71
  52
  53/*
  54 * PCI support code.
  55 */
  56enum {                  /* type 0 and type 1 pre-defined header */
  57        PciVID = 0x00,  /* vendor ID */
  58        PciDID = 0x02,  /* device ID */
  59        PciPCR = 0x04,  /* command */
  60        PciPSR = 0x06,  /* status */
  61        PciRID = 0x08,  /* revision ID */
  62        PciCCRp = 0x09, /* programming interface class code */
  63        PciCCRu = 0x0A, /* sub-class code */
  64        PciCCRb = 0x0B, /* base class code */
  65        PciCLS = 0x0C,  /* cache line size */
  66        PciLTR = 0x0D,  /* latency timer */
  67        PciHDT = 0x0E,  /* header type */
  68        PciBST = 0x0F,  /* BIST */
  69
  70        PciBAR0 = 0x10, /* base address */
  71        PciBAR1 = 0x14,
  72
  73        PciCP = 0x34,   /* capabilities pointer */
  74
  75        PciINTL = 0x3C, /* interrupt line */
  76        PciINTP = 0x3D, /* interrupt pin */
  77};
  78
  79/* ccrb (base class code) values; controller types */
  80enum {
  81        Pcibcpci1 = 0,          /* pci 1.0; no class codes defined */
  82        Pcibcstore = 1,         /* mass storage */
  83        Pcibcnet = 2,           /* network */
  84        Pcibcdisp = 3,          /* display */
  85        Pcibcmmedia = 4,        /* multimedia */
  86        Pcibcmem = 5,           /* memory */
  87        Pcibcbridge = 6,        /* bridge */
  88        Pcibccomm = 7,          /* simple comms (e.g., serial) */
  89        Pcibcbasesys = 8,       /* base system */
  90        Pcibcinput = 9,         /* input */
  91        Pcibcdock = 0xa,        /* docking stations */
  92        Pcibcproc = 0xb,        /* processors */
  93        Pcibcserial = 0xc,      /* serial bus (e.g., USB) */
  94        Pcibcwireless = 0xd,    /* wireless */
  95        Pcibcintell = 0xe,      /* intelligent i/o */
  96        Pcibcsatcom = 0xf,      /* satellite comms */
  97        Pcibccrypto = 0x10,     /* encryption/decryption */
  98        Pcibcdacq = 0x11,       /* data acquisition & signal proc. */
  99};
 100
 101/* ccru (sub-class code) values; common cases only */
 102enum {
 103        /* mass storage */
 104        Pciscscsi = 0,          /* SCSI */
 105        Pciscide = 1,           /* IDE (ATA) */
 106        Pciscsata = 6,          /* SATA */
 107
 108        /* network */
 109        Pciscether = 0,         /* Ethernet */
 110
 111        /* display */
 112        Pciscvga = 0,           /* VGA */
 113        Pciscxga = 1,           /* XGA */
 114        Pcisc3d = 2,            /* 3D */
 115
 116        /* bridges */
 117        Pcischostpci = 0,       /* host/pci */
 118        Pciscpcicpci = 1,       /* pci/pci */
 119
 120        /* simple comms */
 121        Pciscserial = 0,        /* 16450, etc. */
 122        Pciscmultiser = 1,      /* multiport serial */
 123
 124        /* serial bus */
 125        Pciscusb = 3,   /* USB */
 126};
 127
 128enum {                  /* type 0 pre-defined header */
 129        PciCIS = 0x28,  /* cardbus CIS pointer */
 130        PciSVID = 0x2C, /* subsystem vendor ID */
 131        PciSID = 0x2E,  /* cardbus CIS pointer */
 132        PciEBAR0 = 0x30,/* expansion ROM base address */
 133        PciMGNT = 0x3E, /* burst period length */
 134        PciMLT = 0x3F,  /* maximum latency between bursts */
 135};
 136
 137enum {                  /* type 1 pre-defined header */
 138        PciPBN = 0x18,  /* primary bus number */
 139        PciSBN = 0x19,  /* secondary bus number */
 140        PciUBN = 0x1A,  /* subordinate bus number */
 141        PciSLTR = 0x1B, /* secondary latency timer */
 142        PciIBR = 0x1C,  /* I/O base */
 143        PciILR = 0x1D,  /* I/O limit */
 144        PciSPSR = 0x1E, /* secondary status */
 145        PciMBR = 0x20,  /* memory base */
 146        PciMLR = 0x22,  /* memory limit */
 147        PciPMBR = 0x24, /* prefetchable memory base */
 148        PciPMLR = 0x26, /* prefetchable memory limit */
 149        PciPUBR = 0x28, /* prefetchable base upper 32 bits */
 150        PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
 151        PciIUBR = 0x30, /* I/O base upper 16 bits */
 152        PciIULR = 0x32, /* I/O limit upper 16 bits */
 153        PciEBAR1 = 0x28,/* expansion ROM base address */
 154        PciBCR = 0x3E,  /* bridge control register */
 155};
 156
 157enum {                          /* type 2 pre-defined header */
 158        PciCBExCA = 0x10,
 159        PciCBSPSR = 0x16,
 160        PciCBPBN = 0x18,        /* primary bus number */
 161        PciCBSBN = 0x19,        /* secondary bus number */
 162        PciCBUBN = 0x1A,        /* subordinate bus number */
 163        PciCBSLTR = 0x1B,       /* secondary latency timer */
 164        PciCBMBR0 = 0x1C,
 165        PciCBMLR0 = 0x20,
 166        PciCBMBR1 = 0x24,
 167        PciCBMLR1 = 0x28,
 168        PciCBIBR0 = 0x2C,       /* I/O base */
 169        PciCBILR0 = 0x30,       /* I/O limit */
 170        PciCBIBR1 = 0x34,       /* I/O base */
 171        PciCBILR1 = 0x38,       /* I/O limit */
 172        PciCBSVID = 0x40,       /* subsystem vendor ID */
 173        PciCBSID = 0x42,        /* subsystem ID */
 174        PciCBLMBAR = 0x44,      /* legacy mode base address */
 175};
 176
 177/* capabilities */
 178enum {
 179        PciCapPMG = 0x01,       /* power management */
 180        PciCapAGP = 0x02,
 181        PciCapVPD = 0x03,       /* vital product data */
 182        PciCapSID = 0x04,       /* slot id */
 183        PciCapMSI = 0x05,
 184        PciCapCHS = 0x06,       /* compact pci hot swap */
 185        PciCapPCIX = 0x07,
 186        PciCapHTC = 0x08,       /* hypertransport irq conf */
 187        PciCapVND = 0x09,       /* vendor specific information */
 188        PciCapPCIe = 0x10,
 189        PciCapMSIX = 0x11,
 190        PciCapSATA = 0x12,
 191        PciCapHSW = 0x0c,       /* hot swap */
 192};
 193#if 0
 194struct Pcisiz {
 195//  Pcidev* dev;
 196        int siz;
 197        int bar;
 198};
 199
 200struct Pcidev {
 201        int tbdf;                                       /* type+bus+device+function */
 202        ushort vid;                                     /* vendor ID */
 203        ushort did;                                     /* device ID */
 204
 205        ushort pcr;
 206
 207        uchar rid;
 208        uchar ccrp;
 209        uchar ccru;
 210        uchar ccrb;
 211        uchar cls;
 212        uchar ltr;
 213
 214        struct {
 215                ulong bar;                              /* base address */
 216                int size;
 217        } mem[6];
 218
 219        struct {
 220                ulong bar;
 221                int size;
 222        } rom;
 223        uchar intl;                                     /* interrupt line */
 224
 225        Pcidev *list;
 226        Pcidev *link;                           /* next device on this bno */
 227
 228        Pcidev *bridge;                         /* down a bus */
 229        struct {
 230                ulong bar;
 231                int size;
 232        } ioa, mema;
 233};
 234#endif
 235#define PCIWINDOW       0
 236#define PCIWADDR(va)    (PADDR(va)+PCIWINDOW)
 237#define ISAWINDOW       0
 238#define ISAWADDR(va)    (PADDR(va)+ISAWINDOW)
 239