Treat tabs as having eight spaces instead of four
authorBarret Rhoden <brho@cs.berkeley.edu>
Tue, 12 Mar 2019 23:41:50 +0000 (19:41 -0400)
committerBarret Rhoden <brho@cs.berkeley.edu>
Sun, 24 Mar 2019 02:43:40 +0000 (22:43 -0400)
For whatever bad reason, we chose to treat tabs as four spaces instead
of eight.  e.g. in vim, tabstop=4.

That's a huge pain - both when dealing with other tools and when
switching between projects.  I don't particularly like having
per-project vim settings and whatnot.  Plus, that's a bit harder for
other people who look at our code and have their vim/emacs set to 8
space tabs.

I had regretted that for a long time, but I didn't want to make the
change for two reasons:

1) With other people working on the project, changes of this sort can
lead to merge conflicts.  Since I'm the only one working on it, for the
most part, this isn't a concern.

2) The bigger reason is that major reformatting changes break git blame.
However, there are tools that can ignore commits when running git blame.
Chromium has git hyper-blame.  I thought that feature ought to be baked
into git, so I have a patchset out for git to do so.  Either way, I'll
either have my own patched git or the feature will get merged.  In a
future commit, I'll have instructions for how to use that feature.

A lot of our files didn't need too much attention, due to our old
"spaces for formatting" policy.  I didn't change those to use tabs
instead of spaces for the formatting either.  I expect newer code will
just do whatever people's editors do.  I didn't want to change more
lines than were needed, and the code looks the same either way.

The biggest offenders were indented comments.  Structs with
column-aligned members needed some work too.  I did most of that stuff
manually, since the tools do a mediocre job.

Since I was making changes, I also fixed up the switch-case indenting:
don't do an extra level of indentation for the case keywords.  Doing
this now actually helped with the 8-space tab change, since switch
statements got a few spaces to work with.

A few of the kernel's C files were so badly messed up that I just used
clang-format on them.  Same for Plan 9 files that had been
clang-formatted before and hadn't been heavily modified by us.
Clang-format caused a few problems with its "alphabetized headers"
policy.  That was fun.

Higher-quality (subjectively) code didn't need as much work as older,
poorer code.  Specifically, code with way too many levels of indentation
looks even worse than before - that's actually a benefit of 8-space
tabs: it tells you when your code is bad.  A lot of that older code
needs a more serious refactoring, which this commit does not do.

Signed-off-by: Barret Rhoden <brho@cs.berkeley.edu>
528 files changed:
.clang-format
Documentation/Contributing.md
kern/arch/riscv/arch.h
kern/arch/riscv/cboot.c
kern/arch/riscv/console.c
kern/arch/riscv/cpuinfo.c
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tests/mount.c
tests/netstat.c
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tests/peek.c
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tests/pipetest.c
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tests/prov.c
tests/pthread_barrier_test.c
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tests/pthread_switch.c
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tests/signal_futex.c
tests/stat.c
tests/strace.c
tests/testclone.c
tests/timerfd.c
tests/trandom.c
tests/ttcp.c
tests/turbo.c
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tests/vmm/vmrunkernel.c
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tools/apps/ipconfig/dhcp.h
tools/apps/ipconfig/ipconfig.h
tools/apps/ipconfig/ipv6.c
tools/apps/ipconfig/main.c
tools/compilers/gcc-glibc/glibc-2.19-akaros/sysdeps/akaros/accept4.c
tools/compilers/gcc-glibc/glibc-2.19-akaros/sysdeps/akaros/bind.c
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user/pthread/pthread.h
user/pthread/semaphore.h
user/utest/alarm.c
user/utest/atexit.c
user/utest/cv.c
user/utest/dtls.c
user/utest/efence.c
user/utest/example.c
user/utest/file-posix.c
user/utest/include/utest.h
user/utest/mmap_pf.c
user/utest/pthread.c
user/utest/pvcalarm.c
user/utest/qio.c
user/utest/signal.c
user/vmm/apic.c
user/vmm/biostables.c
user/vmm/decode.c
user/vmm/include/vmm/net.h
user/vmm/include/vmm/sched.h
user/vmm/include/vmm/virtio_balloon.h
user/vmm/include/vmm/virtio_config.h
user/vmm/include/vmm/virtio_lguest_helpers.h
user/vmm/include/vmm/virtio_mmio.h
user/vmm/include/vmm/virtio_pci.h
user/vmm/include/vmm/virtio_ring.h
user/vmm/include/vmm/virtio_scsi.h
user/vmm/include/vmm/vmm.h
user/vmm/include/vmm/vthread.h
user/vmm/io.c
user/vmm/ioapic.c
user/vmm/linuxemu.c
user/vmm/load_elf.c
user/vmm/memory.c
user/vmm/nat.c
user/vmm/pagetables.c
user/vmm/sched.c
user/vmm/util.c
user/vmm/virtio.c
user/vmm/virtio_blk.c
user/vmm/virtio_lguest_console.c
user/vmm/virtio_lguest_helpers.c
user/vmm/virtio_mmio.c
user/vmm/virtio_net.c
user/vmm/vmexit.c
user/vmm/vmm.c
user/vmm/vmx.c
user/vmm/vmxmsr.c
user/vmm/vthread.c

index 65fc911..7080dce 100644 (file)
@@ -1,6 +1,6 @@
 BasedOnStyle: LLVM
-IndentWidth: 4
-TabWidth: 4
+IndentWidth: 8
+TabWidth: 8
 UseTab: ForIndentation
 BreakBeforeBraces: Linux
 AllowShortIfStatementsOnASingleLine: false
index d7d672a..991c73c 100644 (file)
@@ -1,6 +1,6 @@
 Akaros Contribution Policies
 ===========================
-**2016-03-14** Barret Rhoden (`brho`)
+**2019-03-14** Barret Rhoden (`brho`)
 
 Interested in contributing to Akaros?  This document covers coding standards,
 version control usage, and other contribution policies.
@@ -148,20 +148,25 @@ commits.
 
 Coding Standard
 ---------------------------
-Our coding standard is similar to the Linux kernel style (but with a tabstop of
-4), so when in doubt, do what they do.
+We use the Linux kernel coding style.  When in doubt, do what they do.
 
 + If you are bringing in code from another project other than Linux, such as
-Plan 9, run clang-format on it.  We have a format file in the root of the Akaros
-repo.  clang-format isn't perfect, but it's close enough.  Linux code is usually
-fine (even with 8 space tabs), and formatters sometimes do more harm than good
-on that code.  You can try clang-format for Linux code and see how it works.
+  Plan 9, consider running clang-format on it.  We have a format file in the
+  root of the Akaros repo.  clang-format isn't perfect, but it's close enough.
+  We do this for Plan 9 code, which we heavily internalize, but if the code is
+  a library (random, crypto, zlib) that we won't touch, then just leave it as
+  is.  That makes it easier to update the library.
 
 + You'll note that old code may lack the correct style, especially due to the
   large bodies of code from other systems involved.  Typically, we fix it when
   fixing the code for other reasons, so that git blame points at the most
   recent relevant change.
 
++ We can do major reformatting commits and have git blame ignore them.  Talk
+  with brho before doing major reformatting.
+
++ Indentation is done with tabs, 8-spaces wide.
+
 + No spaces after the name of a function in a call.  For example,
   `printk("hello")` not `printk ("hello")`.
 
@@ -181,8 +186,11 @@ on that code.  You can try clang-format for Linux code and see how it works.
   and one of them has braces, put braces on both.  An `else` line should start
   with a brace.
 
-+ Beginning-of-line indentation via tabs, not spaces.  Use spaces for
-  additional formatting (such as lining up text when word wrapping).
++ You can use tabs or spaces for indentation, so long as the spaces follow the
+  tabs and they are not intermixed.  Older code used tabs for indentation, and
+  spaces for formatting/aligning.  Using spaces for alignment  was easier when
+  we changed from four-space tabs to eight-space tabs.  That style is also
+  eaiser for some scenarios and editors.  Don't worry too much about it.
 
 + Preprocessor macros are usually upper-case.  Try to avoid using macros
   unless necessary (I prefer static inlines).
@@ -213,6 +221,8 @@ on that code.  You can try clang-format for Linux code and see how it works.
   hierarchies.  Keep in mind that people will need to work with and find these
   files (even via tab completion, it can be a pain).
 
++ Consider aligning the members of structs with multiple values.  I often align
+  the members (not the types) at 40 chars.  This is a stylistic choice.
 
 Git Workflow
 ------------------------------------
index 76e8c9a..53b09ca 100644 (file)
@@ -86,9 +86,10 @@ static __inline void enable_irqsave(int8_t* state)
        // < 0 means more disabled calls have been made
        // Mostly doing this so we can call disable_irqsave first if we want
 
-       // one side or another "gets a point" if interrupts were already the
-       // way it wanted to go.  o/w, state stays at 0.  if the state was not 0
-       // then, enabling/disabling isn't even an option.  just increment/decrement
+       // one side or another "gets a point" if interrupts were already the way
+       // it wanted to go.  o/w, state stays at 0.  if the state was not 0
+       // then, enabling/disabling isn't even an option.  just
+       // increment/decrement
 
        // if enabling is winning or tied, make sure it's enabled
        if ((*state == 0) && !irq_is_enabled())
index cd6717b..3b031a3 100644 (file)
@@ -1,37 +1,37 @@
-#include <multiboot.h>
-#include <ros/memlayout.h>
 #include <arch/arch.h>
 #include <arch/mmu.h>
-#include <string.h>
 #include <assert.h>
-#include <stdio.h>
+#include <multiboot.h>
 #include <pmap.h>
+#include <ros/memlayout.h>
+#include <stdio.h>
+#include <string.h>
 
 #define MAX_KERNBASE_SIZE (KERN_VMAP_TOP - KERNBASE)
 
-uint32_t num_cores = 1;   // this must not be in BSS
+uint32_t num_cores = 1; // this must not be in BSS
 
-static uint64_t
-mem_size(uint64_t sz_mb)
+static uint64_t mem_size(uint64_t sz_mb)
 {
        uint64_t sz = (uint64_t)sz_mb * 1024 * 1024;
-       return MIN(sz,  MIN(MAX_KERNBASE_SIZE, (uint64_t)L1PGSIZE * NPTENTRIES));
+
+       return MIN(sz, MIN(MAX_KERNBASE_SIZE, (uint64_t)L1PGSIZE * NPTENTRIES));
 }
 
-void pagetable_init(uint32_t memsize_mb, pte_t* l1pt, pte_t* l1pt_boot,
-                    pte_tl2pt)
+void pagetable_init(uint32_t memsize_mb, pte_t *l1pt, pte_t *l1pt_boot,
+                    pte_t *l2pt)
 {
        static_assert(KERNBASE % L1PGSIZE == 0);
        // The boot L1 PT retains the identity mapping [0,memsize-1],
        // whereas the post-boot L1 PT does not.
        uint64_t memsize = mem_size(memsize_mb);
-       for(uint64_t pa = 0; pa < memsize+L1PGSIZE-1; pa += L1PGSIZE)
-       {
+
+       for (uint64_t pa = 0; pa < memsize + L1PGSIZE - 1; pa += L1PGSIZE) {
                pte_t pte = build_pte(pa, PTE_KERN_RW | PTE_E);
 
-               l1pt_boot[L1X(pa)] = pte; // identity mapping
-               l1pt_boot[L1X(KERNBASE+pa)] = pte; // KERNBASE mapping
-               l1pt[L1X(KERNBASE+pa)] = pte; // KERNBASE mapping
+               l1pt_boot[L1X(pa)] = pte;            // identity mapping
+               l1pt_boot[L1X(KERNBASE + pa)] = pte; // KERNBASE mapping
+               l1pt[L1X(KERNBASE + pa)] = pte;      // KERNBASE mapping
        }
 
 #ifdef __riscv64
@@ -47,15 +47,16 @@ void pagetable_init(uint32_t memsize_mb, pte_t* l1pt, pte_t* l1pt_boot,
        l1pt[L1X(KERN_LOAD_ADDR)] = PTD(l2pt);
        l1pt_boot[L1X(KERN_LOAD_ADDR)] = PTD(l2pt);
 
-       for (uintptr_t pa = 0; pa < (uintptr_t)(-KERN_LOAD_ADDR); pa += L2PGSIZE)
-               l2pt[L2X(KERN_LOAD_ADDR+pa)] = build_pte(pa, PTE_KERN_RW | PTE_E);
+       for (uintptr_t pa = 0; pa < (uintptr_t)(-KERN_LOAD_ADDR);
+            pa += L2PGSIZE)
+               l2pt[L2X(KERN_LOAD_ADDR + pa)] =
+                   build_pte(pa, PTE_KERN_RW | PTE_E);
 #else
-       (void) l2pt; // don't need this for rv32
+       (void)l2pt; // don't need this for rv32
 #endif
 }
 
-void
-cmain(uint32_t memsize_mb, uint32_t nc)
+void cmain(uint32_t memsize_mb, uint32_t nc)
 {
        multiboot_info_t mbi;
        memset(&mbi, 0, sizeof(mbi));
@@ -64,7 +65,8 @@ cmain(uint32_t memsize_mb, uint32_t nc)
 
        num_cores = nc;
 
-       extern void kernel_init(multiboot_info_t *mboot_info);
+       extern void kernel_init(multiboot_info_t * mboot_info);
+
        // kernel_init expects a pre-relocation mbi address
-       kernel_init((multiboot_info_t*)PADDR(&mbi));
+       kernel_init((multiboot_info_t *)PADDR(&mbi));
 }
index 1f92e1a..34881d4 100644 (file)
@@ -1,10 +1,10 @@
 #include <arch/console.h>
-#include <pmap.h>
 #include <atomic.h>
-#include <smp.h>
 #include <kmalloc.h>
 #include <monitor.h>
+#include <pmap.h>
 #include <process.h>
+#include <smp.h>
 
 int cons_get_any_char(void)
 {
@@ -13,14 +13,14 @@ int cons_get_any_char(void)
 
 void cons_init()
 {
-       mtpcr(PCR_SR, mfpcr(PCR_SR) | (1 << (IRQ_HOST+SR_IM_SHIFT)));
-       while (mtpcr(PCR_TOHOST, 0x01L << 56));
+       mtpcr(PCR_SR, mfpcr(PCR_SR) | (1 << (IRQ_HOST + SR_IM_SHIFT)));
+       while (mtpcr(PCR_TOHOST, 0x01L << 56))
+               ;
 }
 
 // `High'-level console I/O.  Used by readline and cprintf.
 
-void
-cputbuf(const char* str, int len)
+void cputbuf(const char *str, int len)
 {
        for (int i = 0; i < len; i++)
                cputchar(str[i]);
@@ -32,25 +32,23 @@ void poll_keyboard()
 
 // Low-level console I/O
 
-void
-cputchar(int c)
+void cputchar(int c)
 {
-       while (mtpcr(PCR_TOHOST, 0x0101000000000000 | (unsigned char)c));
+       while (mtpcr(PCR_TOHOST, 0x0101000000000000 | (unsigned char)c))
+               ;
 }
 
-int
-getchar(void)
+int getchar(void)
 {
        char c = 'x';
 
-       #warning "implement me"
+#warning "implement me"
        /* maybe do a qio read */
 
        return c;
 }
 
-int
-iscons(int fdnum)
+int iscons(int fdnum)
 {
        // used by readline
        return 1;
index ba71bc1..ecf086b 100644 (file)
@@ -1,51 +1,49 @@
 #include <arch/arch.h>
 #include <arch/mmu.h>
-#include <stdio.h>
 #include <assert.h>
+#include <pmap.h>
 #include <smp.h>
+#include <stdio.h>
 #include <umem.h>
-#include <pmap.h>
 
-static void
-static_asserts_can_go_here()
+static void static_asserts_can_go_here(void)
 {
        static_assert(SIZEOF_HW_TRAPFRAME == sizeof(struct hw_trapframe));
 }
 
-void
-print_cpuinfo(void)
+void print_cpuinfo(void)
 {
        int id = mfpcr(PCR_IMPL);
-       const charname = "(unknown implementation)";
+       const char *name = "(unknown implementation)";
        if (id == 1)
-         name = "ISA Simulator";
+               name = "ISA Simulator";
        else if (id == 2)
-         name = "Rocket64";
+               name = "Rocket64";
        cprintf("CPU Info: RISC-V %s\n", name);
 }
 
 #warning "convert pgdir* to pgdir_t"
 void show_mapping(pgdir_t *pt, uintptr_t start, size_t size)
 {
-       pte_tpte;
+       pte_t *pte;
        uintptr_t i;
-       page_tpage;
+       page_t *page;
 
-       cprintf("      Virtual            Physical      SR SW SX UR UW UX D R\n");
-       cprintf("------------------------------------------------------------\n");
-       for(i = 0; i < size; i += PGSIZE, start += PGSIZE)
-       {
-               page = page_lookup(pt, (void*)start, &pte);
-               cprintf("%016p  ",start);
-               if(page)
-               {
+       cprintf(
+           "      Virtual            Physical      SR SW SX UR UW UX D R\n");
+       cprintf(
+           "------------------------------------------------------------\n");
+       for (i = 0; i < size; i += PGSIZE, start += PGSIZE) {
+               page = page_lookup(pt, (void *)start, &pte);
+               cprintf("%016p  ", start);
+               if (page) {
                        cprintf("%016p  %1d  %1d  %1d  %1d  %1d  %1d %1d %1d\n",
-                               page2pa(page),
-                               !!(*pte & PTE_SR), !!(*pte & PTE_SW), !!(*pte & PTE_SX),
-                               !!(*pte & PTE_UR), !!(*pte & PTE_UW), !!(*pte & PTE_UX),
-                               !!(*pte & PTE_D), !!(*pte & PTE_R));
-               }
-               else
-                       cprintf("%016p\n",0);
+                               page2pa(page), !!(*pte & PTE_SR),
+                               !!(*pte & PTE_SW), !!(*pte & PTE_SX),
+                               !!(*pte & PTE_UR), !!(*pte & PTE_UW),
+                               !!(*pte & PTE_UX), !!(*pte & PTE_D),
+                               !!(*pte & PTE_R));
+               else
+                       cprintf("%016p\n", 0);
        }
 }
index 2b7d32d..0adcdd0 100644 (file)
@@ -1,10 +1,10 @@
-#include <trap.h>
-#include <env.h>
-#include <assert.h>
 #include <arch/arch.h>
+#include <assert.h>
+#include <env.h>
 #include <pmap.h>
+#include <trap.h>
 
-void save_fp_state(ancillary_state_tsilly)
+void save_fp_state(ancillary_state_t *silly)
 {
        uintptr_t sr = enable_fp();
        uint32_t fsr = read_fsr();
@@ -46,7 +46,7 @@ void save_fp_state(ancillary_state_t* silly)
        mtpcr(PCR_SR, sr);
 }
 
-void restore_fp_state(ancillary_state_tsilly)
+void restore_fp_state(ancillary_state_t *silly)
 {
        uintptr_t sr = enable_fp();
        uint32_t fsr = silly->fsr;
@@ -92,70 +92,74 @@ void init_fp_state(void)
 {
        uintptr_t sr = enable_fp();
 
-       asm("fcvt.d.w f0, x0; fcvt.d.w f1 ,x0; fcvt.d.w f2, x0; fcvt.d.w f3, x0;");
-       asm("fcvt.d.w f4, x0; fcvt.d.w f5, x0; fcvt.d.w f6, x0; fcvt.d.w f7, x0;");
-       asm("fcvt.d.w f8, x0; fcvt.d.w f9, x0; fcvt.d.w f10,x0; fcvt.d.w f11,x0;");
-       asm("fcvt.d.w f12,x0; fcvt.d.w f13,x0; fcvt.d.w f14,x0; fcvt.d.w f15,x0;");
-       asm("fcvt.d.w f16,x0; fcvt.d.w f17,x0; fcvt.d.w f18,x0; fcvt.d.w f19,x0;");
-       asm("fcvt.d.w f20,x0; fcvt.d.w f21,x0; fcvt.d.w f22,x0; fcvt.d.w f23,x0;");
-       asm("fcvt.d.w f24,x0; fcvt.d.w f25,x0; fcvt.d.w f26,x0; fcvt.d.w f27,x0;");
-       asm("fcvt.d.w f28,x0; fcvt.d.w f29,x0; fcvt.d.w f30,x0; fcvt.d.w f31,x0;");
+       asm("fcvt.d.w f0, x0; fcvt.d.w f1 ,x0; fcvt.d.w f2, x0; fcvt.d.w f3, "
+           "x0;");
+       asm("fcvt.d.w f4, x0; fcvt.d.w f5, x0; fcvt.d.w f6, x0; fcvt.d.w f7, "
+           "x0;");
+       asm("fcvt.d.w f8, x0; fcvt.d.w f9, x0; fcvt.d.w f10,x0; fcvt.d.w "
+           "f11,x0;");
+       asm("fcvt.d.w f12,x0; fcvt.d.w f13,x0; fcvt.d.w f14,x0; fcvt.d.w "
+           "f15,x0;");
+       asm("fcvt.d.w f16,x0; fcvt.d.w f17,x0; fcvt.d.w f18,x0; fcvt.d.w "
+           "f19,x0;");
+       asm("fcvt.d.w f20,x0; fcvt.d.w f21,x0; fcvt.d.w f22,x0; fcvt.d.w "
+           "f23,x0;");
+       asm("fcvt.d.w f24,x0; fcvt.d.w f25,x0; fcvt.d.w f26,x0; fcvt.d.w "
+           "f27,x0;");
+       asm("fcvt.d.w f28,x0; fcvt.d.w f29,x0; fcvt.d.w f30,x0; fcvt.d.w "
+           "f31,x0;");
        asm("mtfsr x0");
 
        mtpcr(PCR_SR, sr);
 }
 
-static int
-user_mem_walk_recursive(env_t* e, uintptr_t start, size_t len,
-                        mem_walk_callback_t callback, void* arg,
-                        mem_walk_callback_t pt_callback, void* pt_arg,
-                        pte_t* pt, int level)
+static int user_mem_walk_recursive(env_t *e, uintptr_t start, size_t len,
+                                   mem_walk_callback_t callback, void *arg,
+                                   mem_walk_callback_t pt_callback,
+                                   void *pt_arg, pte_t *pt, int level)
 {
        int ret = 0;
-       int pgshift = L1PGSHIFT - level*(L1PGSHIFT-L2PGSHIFT);
+       int pgshift = L1PGSHIFT - level * (L1PGSHIFT - L2PGSHIFT);
        uintptr_t pgsize = 1UL << pgshift;
 
-       uintptr_t start_idx = (start >> pgshift) & (NPTENTRIES-1);
-       uintptr_t end_idx = ((start+len-1) >> pgshift) & (NPTENTRIES-1);
+       uintptr_t start_idx = (start >> pgshift) & (NPTENTRIES - 1);
+       uintptr_t end_idx = ((start + len - 1) >> pgshift) & (NPTENTRIES - 1);
 
-       for(uintptr_t idx = start_idx; idx <= end_idx; idx++)
-       {
-               uintptr_t pgaddr = ROUNDDOWN(start, pgsize) + (idx-start_idx)*pgsize;
-               pte_tpte = &pt[idx];
+       for (uintptr_t idx = start_idx; idx <= end_idx; idx++) {
+               uintptr_t pgaddr =
+                   ROUNDDOWN(start, pgsize) + (idx - start_idx) * pgsize;
+               pte_t *pte = &pt[idx];
 
-               if(*pte & PTE_T)
-               {
-                       assert(level < NPTLEVELS-1);
+               if (*pte & PTE_T) {
+                       assert(level < NPTLEVELS - 1);
                        uintptr_t st = MAX(pgaddr, start);
                        size_t ln = MIN(start + len, pgaddr + pgsize) - st;
-                       if((ret = user_mem_walk_recursive(e, st, ln, callback, arg,
-                                                         pt_callback, pt_arg,
-                                                         KADDR(PTD_ADDR(*pte)), level+1)))
+                       if ((ret = user_mem_walk_recursive(
+                                e, st, ln, callback, arg, pt_callback, pt_arg,
+                                KADDR(PTD_ADDR(*pte)), level + 1)))
                                goto out;
-                       if(pt_callback != NULL && (ret = pt_callback(e, pte, (void*)pgaddr, arg)))
+                       if (pt_callback != NULL &&
+                           (ret = pt_callback(e, pte, (void *)pgaddr, arg)))
                                goto out;
-               }
-               else if(callback != NULL)
-                       if((ret = callback(e, pte, (void*)pgaddr, arg)))
+               } else if (callback != NULL)
+                       if ((ret = callback(e, pte, (void *)pgaddr, arg)))
                                goto out;
        }
 out:
        return ret;
 }
 
-int
-env_user_mem_walk(env_t* e, void* start, size_t len,
-                  mem_walk_callback_t callback, void* arg)
+int env_user_mem_walk(env_t *e, void *start, size_t len,
+                      mem_walk_callback_t callback, void *arg)
 {
        assert(PGOFF(start) == 0 && PGOFF(len) == 0);
        return user_mem_walk_recursive(e, (uintptr_t)start, len, callback, arg,
                                       NULL, NULL, e->env_pgdir, 0);
 }
 
-void
-env_pagetable_free(env_t* e)
+void env_pagetable_free(env_t *e)
 {
-       int pt_free(env_t* e, pte_t* pte, void* va, void* arg)
+       int pt_free(env_t * e, pte_t * pte, void *va, void *arg)
        {
                if (!PAGE_PRESENT(pte))
                        return 0;
@@ -163,6 +167,6 @@ env_pagetable_free(env_t* e)
                return 0;
        }
 
-       assert(user_mem_walk_recursive(e, 0, KERNBASE, NULL, NULL,
-                                      pt_free, NULL, e->env_pgdir, 0) == 0);
+       assert(user_mem_walk_recursive(e, 0, KERNBASE, NULL, NULL, pt_free,
+                                      NULL, e->env_pgdir, 0) == 0);
 }
index e2b0c2e..6c89015 100644 (file)
@@ -1,35 +1,34 @@
-#include <trap.h>
+#include <arch/softfloat.h>
 #include <smp.h>
+#include <trap.h>
 #include <umem.h>
-#include <arch/softfloat.h>
 
-static uint32_t ls(uint64_taddr)
+static uint32_t ls(uint64_t *addr)
 {
        uint32_t r;
-       asm ("fld f0, %1; mftx.s %0, f0" : "=r"(r) : "m"(*addr));
+       asm("fld f0, %1; mftx.s %0, f0" : "=r"(r) : "m"(*addr));
        return r;
 }
 
-static void ss(uint64_taddr, uint32_t val)
+static void ss(uint64_t *addr, uint32_t val)
 {
-       asm ("mxtf.s f0, %0; fsd f0, %1" : : "r"(val), "m"(*addr));
+       asm("mxtf.s f0, %0; fsd f0, %1" : : "r"(val), "m"(*addr));
 }
 
 static int emulate_fpu_silly(struct hw_trapframe *state,
                              ancillary_state_t *silly)
 {
        int insn;
-       if (memcpy_from_user(current, &insn, (void*)state->epc, 4))
-       {
+       if (memcpy_from_user(current, &insn, (void *)state->epc, 4)) {
                state->cause = CAUSE_FAULT_FETCH;
                handle_trap(state);
        }
 
-       #define DECLARE_INSN(name, match, mask) bool is_##name = (insn & mask) == match;
-       #include <arch/opcodes.h>
-       #undef DECLARE_INSN
+#define DECLARE_INSN(name, match, mask) bool is_##name = (insn & mask) == match;
+#include <arch/opcodes.h>
+#undef DECLARE_INSN
 
-       int rd  = (insn >> 27) & 0x1f;
+       int rd = (insn >> 27) & 0x1f;
        int rs1 = (insn >> 22) & 0x1f;
        int rs2 = (insn >> 17) & 0x1f;
        int rs3 = (insn >> 12) & 0x1f;
@@ -37,8 +36,8 @@ static int emulate_fpu_silly(struct hw_trapframe *state,
        int imm = (insn << 10) >> 20;
        int bimm = ((insn >> 10) & 0x7f) | ((insn & 0xf8000000) >> 20);
 
-       void* load_address = (void*)(state->gpr[rs1] + imm);
-       void* store_address = (void*)(state->gpr[rs1] + bimm);
+       void *load_address = (void *)(state->gpr[rs1] + imm);
+       void *store_address = (void *)(state->gpr[rs1] + bimm);
 
        softfloat_t sf;
        sf.float_rounding_mode = silly->fsr >> 5;
@@ -49,65 +48,71 @@ static int emulate_fpu_silly(struct hw_trapframe *state,
        else if (is_fsqrt_d)
                silly->fpr[rd] = float64_sqrt(&sf, silly->fpr[rs1]);
        else if (is_fdiv_s)
-               ss(&silly->fpr[rd], float32_div(&sf, ls(&silly->fpr[rs1]), ls(&silly->fpr[rs2])));
+               ss(&silly->fpr[rd], float32_div(&sf, ls(&silly->fpr[rs1]),
+                                               ls(&silly->fpr[rs2])));
        else if (is_fdiv_d)
-               silly->fpr[rd] = float64_div(&sf, silly->fpr[rs1], silly->fpr[rs2]);
+               silly->fpr[rd] =
+                   float64_div(&sf, silly->fpr[rs1], silly->fpr[rs2]);
        /* Eventually, we will emulate the full FPU, including the below insns
        else if (is_mffsr)
        {
-               // use sf instead of silly->fsr
-               state->gpr[rd] = silly->fsr;
+               // use sf instead of silly->fsr
+               state->gpr[rd] = silly->fsr;
        }
        else if (is_mtfsr)
        {
-               // use sf instead of silly->fsr
-               int temp = silly->fsr;
-               silly->fsr = state->gpr[rs1] & 0xFF;
-               state->gpr[rd] = silly->fsr;
+               // use sf instead of silly->fsr
+               int temp = silly->fsr;
+               silly->fsr = state->gpr[rs1] & 0xFF;
+               state->gpr[rd] = silly->fsr;
        }
        else if (is_fld)
        {
-               uint64_t dest;
-               if (!memcpy_from_user(current, &dest, load_address, sizeof(dest)))
-               {
-                       state->cause = CAUSE_FAULT_LOAD;
-                       state->badvaddr = (long)load_address;
-                       handle_trap(state);
-               }
-               silly->fpr[rd] = dest;
+               uint64_t dest;
+               if (!memcpy_from_user(current, &dest, load_address,
+       sizeof(dest)))
+               {
+                       state->cause = CAUSE_FAULT_LOAD;
+                       state->badvaddr = (long)load_address;
+                       handle_trap(state);
+               }
+               silly->fpr[rd] = dest;
        }
        else if (is_flw)
        {
-               uint32_t dest;
-               if (!memcpy_from_user(current, &dest, load_address, sizeof(dest)))
-               {
-                       state->cause = CAUSE_FAULT_LOAD;
-                       state->badvaddr = (long)load_address;
-                       handle_trap(state);
-               }
-               silly->fpr[rd] = dest;
+               uint32_t dest;
+               if (!memcpy_from_user(current, &dest, load_address,
+       sizeof(dest)))
+               {
+                       state->cause = CAUSE_FAULT_LOAD;
+                       state->badvaddr = (long)load_address;
+                       handle_trap(state);
+               }
+               silly->fpr[rd] = dest;
        }
        else if (is_fsd)
        {
-               if (!memcpy_to_user(current, store_address, &silly->fpr[rs2], sizeof(uint64_t)))
-               {
-                       state->cause = CAUSE_FAULT_STORE;
-                       state->badvaddr = (long)store_address;
-                       handle_trap(state);
-               }
+               if (!memcpy_to_user(current, store_address, &silly->fpr[rs2],
+       sizeof(uint64_t)))
+               {
+                       state->cause = CAUSE_FAULT_STORE;
+                       state->badvaddr = (long)store_address;
+                       handle_trap(state);
+               }
        }
        else if (is_flw)
        {
-               if (!memcpy_to_user(current, store_address, &silly->fpr[rs2], sizeof(uint32_t)))
-               {
-                       state->cause = CAUSE_FAULT_STORE;
-                       state->badvaddr = (long)store_address;
-                       handle_trap(state);
-               }
+               if (!memcpy_to_user(current, store_address, &silly->fpr[rs2],
+       sizeof(uint32_t)))
+               {
+                       state->cause = CAUSE_FAULT_STORE;
+                       state->badvaddr = (long)store_address;
+                       handle_trap(state);
+               }
        }
        */
        else
-         return 1;
+               return 1;
 
        silly->fsr = sf.float_rounding_mode << 5 | sf.float_exception_flags;
        return 0;
@@ -116,8 +121,7 @@ static int emulate_fpu_silly(struct hw_trapframe *state,
 /* For now we can only emulate missing compute insns, not the whole FPU */
 int emulate_fpu(struct hw_trapframe *state)
 {
-       if (!(state->sr & SR_EF))
-       {
+       if (!(state->sr & SR_EF)) {
                state->cause = CAUSE_FP_DISABLED;
                handle_trap(state);
        }
@@ -125,6 +129,7 @@ int emulate_fpu(struct hw_trapframe *state)
        ancillary_state_t fp_state;
        save_fp_state(&fp_state);
        int code = emulate_fpu_silly(state, &fp_state);
+
        restore_fp_state(&fp_state);
        return code;
 }
index 1c53b15..6aab49b 100644 (file)
@@ -1,10 +1,10 @@
 /* See COPYRIGHT for copyright information. */
 
-#include <smp.h>
-#include <arch/init.h>
 #include <arch/console.h>
+#include <arch/init.h>
+#include <smp.h>
 
-void arch_init()
+void arch_init(void)
 {
        smp_boot();
        proc_init();
index fb196cb..2b30155 100644 (file)
@@ -1,8 +1,8 @@
-#include <string.h>
 #include <assert.h>
 #include <kdebug.h>
 #include <pmap.h>
 #include <process.h>
+#include <string.h>
 
 /* Here's the old backtrace, remove it once gen_backtrace is done: */
 #if 0
@@ -36,7 +36,7 @@ size_t backtrace_list(uintptr_t pc, uintptr_t fp, uintptr_t *pcs,
 }
 
 size_t backtrace_user_list(uintptr_t pc, uintptr_t fp, uintptr_t *pcs,
-                                                  size_t nr_slots)
+                           size_t nr_slots)
 {
        printk("\n\tTODO: %s on riscv\n\n", __func__);
        return 0;
index dac28d2..97a0cc2 100644 (file)
@@ -7,11 +7,11 @@
  * Kevin Klues <klueska@cs.berkeley.edu>
  */
 
-#include <sys/queue.h>
-#include <page_alloc.h>
-#include <pmap.h>
 #include <kmalloc.h>
 #include <multiboot.h>
+#include <page_alloc.h>
+#include <pmap.h>
+#include <sys/queue.h>
 
 void base_arena_init(struct multiboot_info *mbi)
 {
@@ -26,8 +26,8 @@ void base_arena_init(struct multiboot_info *mbi)
        first_invalid_page = ROUNDUP(boot_freelimit, PGSIZE);
        assert(first_invalid_page == max_nr_pages * PGSIZE);
 
-       base_arena = arena_builder(base_pg, "base", PGSIZE, NULL, NULL, NULL,
-                                  0);
+       base_arena =
+           arena_builder(base_pg, "base", PGSIZE, NULL, NULL, NULL, 0);
        arena_add(base_arena, KADDR(first_free_page),
                  first_invalid_page - first_free_page, MEM_WAIT);
 }
index 031d12e..5709109 100644 (file)
@@ -5,25 +5,24 @@
 #include <error.h>
 #include <sys/queue.h>
 
-#include <atomic.h>
-#include <string.h>
 #include <assert.h>
-#include <pmap.h>
+#include <atomic.h>
 #include <env.h>
-#include <stdio.h>
 #include <kmalloc.h>
 #include <page_alloc.h>
+#include <pmap.h>
+#include <stdio.h>
+#include <string.h>
 
 #warning "convert pgdir* to pgdir_t"
-pgdir_t* boot_pgdir;           // Virtual address of boot time page directory
-physaddr_t boot_cr3;           // Physical address of boot time page directory
+pgdir_t *boot_pgdir; // Virtual address of boot time page directory
+physaddr_t boot_cr3; // Physical address of boot time page directory
 
 // --------------------------------------------------------------
 // Set up initial memory mappings and turn on MMU.
 // --------------------------------------------------------------
 
-void
-vm_init(void)
+void vm_init(void)
 {
        // we already set up our page tables before jumping
        // into the kernel, so there's not much going on here
@@ -45,55 +44,54 @@ vm_init(void)
 //
 // This is boot_pgdir_walk, but using page_alloc() instead of boot_alloc().
 // Unlike boot_pgdir_walk, pgdir_walk can fail.
-pte_t*
-pgdir_walk(pgdir_t *pgdir, const void *va, int create)
+pte_t *pgdir_walk(pgdir_t *pgdir, const void *va, int create)
 {
-       pte_tppte;
-       pte_tpt;
+       pte_t *ppte;
+       pte_t *pt;
 
        pt = pgdir;
-       for(int i = 0; i < NPTLEVELS-1; i++)
-       {
-               // this code relies upon the fact that all page tables are the same size
-               uintptr_t idx = (uintptr_t)va >> (L1PGSHIFT - i*(L1PGSHIFT-L2PGSHIFT));
-               idx = idx & (NPTENTRIES-1);
+       for (int i = 0; i < NPTLEVELS - 1; i++) {
+               // this code relies upon the fact that all page tables are the
+               // same size
+               uintptr_t idx = (uintptr_t)va >>
+                       (L1PGSHIFT - i * (L1PGSHIFT - L2PGSHIFT));
+               idx = idx & (NPTENTRIES - 1);
 
                ppte = &pt[idx];
 
-               if(*ppte & PTE_E)
+               if (*ppte & PTE_E)
                        return ppte;
 
-               if(!(*ppte & PTE_T))
-               {
-                       if(!create)
+               if (!(*ppte & PTE_T)) {
+                       if (!create)
                                return NULL;
 
                        page_t *new_table;
-                       if(kpage_alloc(&new_table))
+                       if (kpage_alloc(&new_table))
                                return NULL;
                        memset(page2kva(new_table), 0, PGSIZE);
 
                        *ppte = PTD(page2pa(new_table));
                }
 
-               pt = (pte_t*)KADDR(PTD_ADDR(*ppte));
+               pt = (pte_t *)KADDR(PTD_ADDR(*ppte));
        }
 
-       uintptr_t idx = (uintptr_t)va >> (L1PGSHIFT - (NPTLEVELS-1)*(L1PGSHIFT-L2PGSHIFT));
-       idx = idx & (NPTENTRIES-1);
-  return &pt[idx];
+       uintptr_t idx = (uintptr_t)va >>
+                       (L1PGSHIFT - (NPTLEVELS - 1) * (L1PGSHIFT - L2PGSHIFT));
+       idx = idx & (NPTENTRIES - 1);
+       return &pt[idx];
 }
 
 /* Returns the effective permissions for PTE_U, PTE_W, and PTE_P on a given
  * virtual address. */
 int get_va_perms(pgdir_t *pgdir, const void *va)
 {
-       pte_tpte = pgdir_walk(pgdir, va, 0);
+       pte_t *pte = pgdir_walk(pgdir, va, 0);
        return pte == NULL ? 0 : (*pte & (PTE_PERM | PTE_E));
 }
 
-void
-page_check(void)
+void page_check(void)
 {
 }
 
@@ -108,7 +106,7 @@ int arch_pgdir_setup(pgdir_t boot_copy, pgdir_t *new_pd)
        pte_t *kpt = kpage_alloc_addr();
        if (!kpt)
                return -ENOMEM;
-       memcpy(kpt, (pte_t*)boot_copy, PGSIZE);
+       memcpy(kpt, (pte_t *)boot_copy, PGSIZE);
 
        /* TODO: VPT/UVPT mappings */
 
@@ -118,7 +116,7 @@ int arch_pgdir_setup(pgdir_t boot_copy, pgdir_t *new_pd)
 
 physaddr_t arch_pgdir_get_cr3(pgdir_t pd)
 {
-       return PADDR((pte_t*)pd);
+       return PADDR((pte_t *)pd);
 }
 
 void arch_pgdir_clear(pgdir_t *pd)
@@ -129,24 +127,25 @@ void arch_pgdir_clear(pgdir_t *pd)
 /* Returns the page shift of the largest jumbo supported */
 int arch_max_jumbo_page_shift(void)
 {
-       #warning "What jumbo page sizes does RISC support?"
+#warning "What jumbo page sizes does RISC support?"
        return PGSHIFT;
 }
 
-#warning "Not sure where you do your PT destruction.  Be sure to not unmap any intermediate page tables for kernel mappings.  At least not the PML(n-1) maps"
+#warning                                                                       \
+    "Not sure where you do your PT destruction.  Be sure to not unmap any intermediate page tables for kernel mappings.  At least not the PML(n-1) maps"
 
 void arch_add_intermediate_pts(pgdir_t pgdir, uintptr_t va, size_t len)
 {
-       #error "Implement me"
+#error "Implement me"
 }
 
 void map_segment(pgdir_t pgdir, uintptr_t va, size_t size, physaddr_t pa,
                  int perm, int pml_shift)
 {
-       #error "Implement me"
+#error "Implement me"
 }
 
 int unmap_segment(pgdir_t pgdir, uintptr_t va, size_t size)
 {
-       #error "Implement me"
+#error "Implement me"
 }
index 0cc2963..4761ce9 100644 (file)
@@ -14,15 +14,15 @@ static inline bool pte_walk_okay(pte_t pte)
 }
 
 /* PTE states:
- *  - present: the PTE is involved in a valid page table walk, with the physaddr
- *  part pointing to a physical page.
+ * - present: the PTE is involved in a valid page table walk, with the physaddr
+ *   part pointing to a physical page.
  *
- *     - mapped: the PTE is involved in some sort of mapping, e.g. a VMR.  We're
- *     storing something in the PTE, but it is isn't necessarily present and
- *     pointing to an actual physical page.  All present are mapped, but not vice
- *     versa.  Mapped could also include paged-out, if we support that later.
+ * - mapped: the PTE is involved in some sort of mapping, e.g. a VMR.  We're
+ *   storing something in the PTE, but it is isn't necessarily present and
+ *   pointing to an actual physical page.  All present are mapped, but not vice
+ *   versa.  Mapped could also include paged-out, if we support that later.
  *
- *     - unmapped: completely unused. (0 value) */
+ * - unmapped: completely unused. (0 value) */
 static inline bool pte_is_present(pte_t pte)
 {
        return *(kpte_t*)pte & PTE_P ? TRUE : FALSE;
index 70d14ad..2d62920 100644 (file)
@@ -1,19 +1,19 @@
 #include <arch/arch.h>
-#include <trap.h>
-#include <process.h>
 #include <pmap.h>
+#include <process.h>
 #include <smp.h>
+#include <trap.h>
 
-#include <string.h>
 #include <assert.h>
 #include <stdio.h>
+#include <string.h>
 
 void proc_pop_ctx(struct user_context *ctx)
 {
        struct hw_trapframe *tf = &ctx->tf.hw_tf;
        assert(ctx->type == ROS_HW_CTX);
-       extern void pop_hw_tf(struct hw_trapframe *tf)
-         __attribute__((noreturn));    /* in asm */
+       extern void pop_hw_tf(struct hw_trapframe * tf)
+           __attribute__((noreturn)); /* in asm */
        pop_hw_tf(tf);
 }
 
@@ -25,23 +25,25 @@ void proc_init_ctx(struct user_context *ctx, uint32_t vcoreid, uintptr_t entryp,
        ctx->type = ROS_HW_CTX;
 
        /* TODO: If you'd like, take tls_desc and save it in the ctx somehow, so
-        * that proc_pop_ctx will set up that TLS before launching.  If you do this,
-        * you can change _start.c to not reset the TLS in userspace.
+        * that proc_pop_ctx will set up that TLS before launching.  If you do
+        * this, you can change _start.c to not reset the TLS in userspace.
         *
-        * This is a bigger deal on amd64, where we take a (fast) syscall to change
-        * the TLS desc, right after the kernel just 0'd out the TLS desc.  If you
-        * can change your HW TLS desc with negligible overhead, then feel free to
-        * do whatever.  Long term, it might be better to do whatever amd64 does. */
+        * This is a bigger deal on amd64, where we take a (fast) syscall to
+        * change the TLS desc, right after the kernel just 0'd out the TLS
+        * desc.  If you can change your HW TLS desc with negligible overhead,
+        * then feel free to do whatever.  Long term, it might be better to do
+        * whatever amd64 does. */
 
        memset(tf, 0, sizeof(*tf));
 
-       tf->gpr[GPR_SP] = stack_top-64;
+       tf->gpr[GPR_SP] = stack_top - 64;
        tf->sr = SR_U64 | SR_EF;
 
        tf->epc = entryp;
 
-       /* Coupled closely with user's entry.S.  id is the vcoreid, which entry.S
-        * uses to determine what to do.  vcoreid == 0 is the main core/context. */
+       /* Coupled closely with user's entry.S.  id is the vcoreid, which
+        * entry.S uses to determine what to do.  vcoreid == 0 is the main
+        * core/context. */
        tf->gpr[GPR_A0] = vcoreid;
 }
 
index c1819c9..262de7f 100644 (file)
@@ -25,8 +25,8 @@ read_pc(void)
 static inline uintptr_t
 read_bp(void)
 {
-       /* frame pointer.  yes, read_bp is a shitty name.  i'll change all of them
-        * to read_fp when you read this and implement the function.  =) */
+       /* frame pointer.  yes, read_bp is a shitty name.  i'll change all of
+        * them to read_fp when you read this and implement the function.  =) */
        return 0;
 }
 
index 5fa6717..3fa3f48 100644 (file)
@@ -1,6 +1,6 @@
 #pragma once
 
-#define MAX_NUM_CORES                          16 // it's safe to change this as needed
+#define MAX_NUM_CORES          16 // it's safe to change this as needed
 
 #ifndef __ASSEMBLER__
 
index dcfdc6c..8accdc7 100644 (file)
@@ -10,5 +10,5 @@
 
 #pragma once
 
-#define CPU_FEAT_RISCV_FOO                             (__CPU_FEAT_ARCH_START + 0)
-#define __NR_CPU_FEAT                                  (__CPU_FEAT_ARCH_START + 64)
+#define CPU_FEAT_RISCV_FOO     (__CPU_FEAT_ARCH_START + 0)
+#define __NR_CPU_FEAT          (__CPU_FEAT_ARCH_START + 64)
index d8bf3bb..c9bf1fa 100644 (file)
@@ -11,7 +11,7 @@
 # define KERNBASE       0xFFFFFC0000000000
 # define ULIM           0x0000040000000000
 # define KERN_LOAD_ADDR 0xFFFFFFFF80000000
-# define KERN_VMAP_TOP         KERN_LOAD_ADDR // upper 2GB reserved (see mmu_init)
+# define KERN_VMAP_TOP      KERN_LOAD_ADDR // upper 2GB reserved (see mmu_init)
 # define NPTLEVELS                       3
 # define L1PGSHIFT              (13+10+10)
 # define L1PGSIZE        (1L << L1PGSHIFT)
@@ -25,7 +25,7 @@
 # define KERNBASE               0x80000000
 # define ULIM                   0x7F000000
 # define KERN_LOAD_ADDR           KERNBASE
-# define KERN_VMAP_TOP                 0xfec00000
+# define KERN_VMAP_TOP          0xfec00000
 # define NPTLEVELS                       2
 # define L1PGSHIFT                 (13+11)
 # define L1PGSIZE         (1 << L1PGSHIFT)
index b5025a6..5901e10 100644 (file)
@@ -49,8 +49,9 @@ static inline uintptr_t get_hwtf_pc(struct hw_trapframe *hw_tf)
 
 static inline uintptr_t get_hwtf_fp(struct hw_trapframe *hw_tf)
 {
-       /* do you even have frame pointers?  this is used for backtrace, but if you
-        * don't use FPs, we'll need to change up our parameters or something. */
+       /* do you even have frame pointers?  this is used for backtrace, but if
+        * you don't use FPs, we'll need to change up our parameters or
+        * something. */
        #warning "fix me"
        return 0;
        //return hw_tf->tf_rbp;
@@ -58,8 +59,9 @@ static inline uintptr_t get_hwtf_fp(struct hw_trapframe *hw_tf)
 
 static inline uintptr_t get_hwtf_sp(struct hw_trapframe *hw_tf)
 {
-       /* do you even have frame pointers?  this is used for backtrace, but if you
-        * don't use FPs, we'll need to change up our parameters or something. */
+       /* do you even have frame pointers?  this is used for backtrace, but if
+        * you don't use FPs, we'll need to change up our parameters or
+        * something. */
        #warning "fix me"
        return 0;
        //return hw_tf->tf_rsp;
index d064c64..2126bbf 100644 (file)
@@ -1,44 +1,42 @@
-#include <smp.h>
 #include <arch/arch.h>
 #include <arch/smp.h>
-#include <stdio.h>
-#include <string.h>
-#include <error.h>
 #include <assert.h>
 #include <atomic.h>
+#include <error.h>
 #include <pmap.h>
+#include <smp.h>
+#include <stdio.h>
+#include <string.h>
 
 volatile uint32_t num_cores_booted = 0;
 
-void
-smp_boot(void)
+void smp_boot(void)
 {
        smp_percpu_init();
        num_cores_booted = 1;
-       while(num_cores_booted < num_cores);
+       while (num_cores_booted < num_cores)
+               ;
        printd("%d cores reporting!\n", num_cores);
 }
 
-void
-smp_init(void)
+void smp_init(void)
 {
        smp_percpu_init();
 
        __sync_fetch_and_add(&num_cores_booted, 1);
-       printd("Good morning, Vietnam! (core id = %d)\n",core_id());
+       printd("Good morning, Vietnam! (core id = %d)\n", core_id());
 
        smp_idle();
 }
 
-handler_wrapper_t*
-smp_make_wrapper()
+handler_wrapper_t *smp_make_wrapper(void)
 {
-       static handler_wrapper_t
-       wrapper_pool[MAX_NUM_CORES*8] = {{{0},SPINLOCK_INITIALIZER}};
+       static handler_wrapper_t wrapper_pool[MAX_NUM_CORES * 8] = {
+           {{0}, SPINLOCK_INITIALIZER}};
 
        size_t i;
-       for(i = 0; i < sizeof(wrapper_pool)/sizeof(wrapper_pool[0]); i++)
-               if(spin_trylock(&wrapper_pool[i].lock) == 0)
+       for (i = 0; i < sizeof(wrapper_pool) / sizeof(wrapper_pool[0]); i++)
+               if (spin_trylock(&wrapper_pool[i].lock) == 0)
                        return &wrapper_pool[i];
        return NULL;
 }
@@ -46,39 +44,38 @@ smp_make_wrapper()
 void smp_call_wrapper(uint32_t src, isr_t handler, handler_wrapper_t *wrapper,
                       void *data)
 {
-       if(wrapper)
+       if (wrapper)
                wrapper->wait_list[core_id()] = 0;
        handler(0, data);
 }
 
-int smp_call_function_self(isr_t handler, voiddata,
-                           handler_wrapper_t** wait_wrapper)
+int smp_call_function_self(isr_t handler, void *data,
+                           handler_wrapper_t **wait_wrapper)
 {
        return smp_call_function_single(core_id(), handler, data, wait_wrapper);
 }
 
-int smp_call_function_all(isr_t handler, voiddata,
-                          handler_wrapper_t** wait_wrapper)
+int smp_call_function_all(isr_t handler, void *data,
+                          handler_wrapper_t **wait_wrapper)
 {
        int8_t state = 0;
        int i, me;
-       handler_wrapper_twrapper = 0;
-       if(wait_wrapper)
-       {
+       handler_wrapper_t *wrapper = 0;
+
+       if (wait_wrapper) {
                wrapper = *wait_wrapper = smp_make_wrapper();
-               if(!wrapper)
+               if (!wrapper)
                        return -ENOMEM;
 
-               for(i = 0; i < num_cores; i++)
+               for (i = 0; i < num_cores; i++)
                        wrapper->wait_list[i] = 1;
        }
 
        enable_irqsave(&state);
 
        // send to others
-       for(i = 0, me = core_id(); i < num_cores; i++)
-       {
-               if(i == me)
+       for (i = 0, me = core_id(); i < num_cores; i++) {
+               if (i == me)
                        continue;
 
                send_kernel_message(i, (amr_t)smp_call_wrapper, (long)handler,
@@ -96,15 +93,15 @@ int smp_call_function_all(isr_t handler, void* data,
        return 0;
 }
 
-int smp_call_function_single(uint32_t dest, isr_t handler, voiddata,
-                             handler_wrapper_t** wait_wrapper)
+int smp_call_function_single(uint32_t dest, isr_t handler, void *data,
+                             handler_wrapper_t **wait_wrapper)
 {
        int8_t state = 0;
-       handler_wrapper_twrapper = 0;
-       if(wait_wrapper)
-       {
+       handler_wrapper_t *wrapper = 0;
+
+       if (wait_wrapper) {
                wrapper = *wait_wrapper = smp_make_wrapper();
-               if(!wrapper)
+               if (!wrapper)
                        return -ENOMEM;
                wrapper->wait_list[dest] = 1;
        }
@@ -121,11 +118,13 @@ int smp_call_function_single(uint32_t dest, isr_t handler, void* data,
        return 0;
 }
 
-int smp_call_wait(handler_wrapper_twrapper)
+int smp_call_wait(handler_wrapper_t *wrapper)
 {
        int i;
-       for(i = 0; i < num_cores; i++)
-               while(wrapper->wait_list[i]);
+
+       for (i = 0; i < num_cores; i++)
+               while (wrapper->wait_list[i])
+                       ;
 
        spin_unlock(&wrapper->lock);
        return 0;
@@ -136,11 +135,11 @@ int smp_call_wait(handler_wrapper_t* wrapper)
  * smp_boot process. */
 void __arch_pcpu_init(uint32_t coreid)
 {
-       // Switch to the real L1 page table, rather than the boot page table which
-       // has the [0,KERNSIZE-1] identity mapping.
+       // Switch to the real L1 page table, rather than the boot page table
+       // which has the [0,KERNSIZE-1] identity mapping.
        extern pte_t l1pt[NPTENTRIES];
        lcr3(PADDR(l1pt));
 
-       register uintptr_t sp asm ("sp");
+       register uintptr_t sp asm("sp");
        set_stack_top(ROUNDUP(sp, PGSIZE));
 }
index c03b80e..7de6071 100644 (file)
@@ -1,61 +1,54 @@
-#include <arch/time.h>
-#include <ros/common.h>
-#include <trap.h>
 #include <arch/arch.h>
-#include <stdio.h>
+#include <arch/time.h>
 #include <assert.h>
+#include <ros/common.h>
 #include <ros/procinfo.h>
+#include <stdio.h>
+#include <trap.h>
 
-void
-timer_init(void)
+void timer_init(void)
 {
        __proc_global_info.tsc_freq = TSC_HZ;
        cprintf("TSC Frequency: %llu\n", __proc_global_info.tsc_freq);
 }
 
-void
-set_core_timer(uint32_t usec, bool periodic)
+void set_core_timer(uint32_t usec, bool periodic)
 {
        // we could implement periodic timers using one-shot timers,
        // but for now we only support one-shot
        assert(!periodic);
 
-       if (usec)
-       {
-               uint32_t clocks =  (uint64_t)usec*TSC_HZ/1000000;
+       if (usec) {
+               uint32_t clocks = (uint64_t)usec * TSC_HZ / 1000000;
 
                int8_t irq_state = 0;
                disable_irqsave(&irq_state);
 
                mtpcr(PCR_COUNT, 0);
                mtpcr(PCR_COMPARE, clocks);
-               mtpcr(PCR_SR, mfpcr(PCR_SR) | (1 << (IRQ_TIMER+SR_IM_SHIFT)));
+               mtpcr(PCR_SR, mfpcr(PCR_SR) | (1 << (IRQ_TIMER + SR_IM_SHIFT)));
 
                enable_irqsave(&irq_state);
-       }
-       else
-       {
-               mtpcr(PCR_SR, mfpcr(PCR_SR) & ~(1 << (IRQ_TIMER+SR_IM_SHIFT)));
+       } else {
+               mtpcr(PCR_SR,
+                     mfpcr(PCR_SR) & ~(1 << (IRQ_TIMER + SR_IM_SHIFT)));
        }
 }
 
-void
-udelay(uint64_t usec)
+void udelay(uint64_t usec)
 {
-       if (__proc_global_info.tsc_freq != 0)
-       {
+       if (__proc_global_info.tsc_freq != 0) {
                uint64_t start, end, now;
 
                start = read_tsc();
                end = start + (__proc_global_info.tsc_freq * usec) / 1000000;
 
-               do
-               {
+               do {
                        cpu_relax();
                        now = read_tsc();
                } while (now < end || (now > start && end < start));
-       }
-       else panic("udelay() was called before timer_init(), moron!");
+       } else
+               panic("udelay() was called before timer_init(), moron!");
 }
 
 uint64_t read_persistent_clock(void)
index 125a2ca..0e8a980 100644 (file)
@@ -1,18 +1,18 @@
 #include <arch/arch.h>
-#include <assert.h>
-#include <trap.h>
 #include <arch/console.h>
-#include <string.h>
-#include <process.h>
-#include <syscall.h>
-#include <monitor.h>
+#include <assert.h>
 #include <manager.h>
-#include <stdio.h>
-#include <smp.h>
-#include <slab.h>
 #include <mm.h>
-#include <umem.h>
+#include <monitor.h>
 #include <pmap.h>
+#include <process.h>
+#include <slab.h>
+#include <smp.h>
+#include <stdio.h>
+#include <string.h>
+#include <syscall.h>
+#include <trap.h>
+#include <umem.h>
 
 /* These are the stacks the kernel will load when it receives a trap from user
  * space.  The deal is that they get set right away in entry.S, and can always
@@ -25,8 +25,7 @@
  * per_cpu_info. */
 uintptr_t core_stacktops[MAX_NUM_CORES] = {0xcafebabe, 0};
 
-void
-advance_pc(struct hw_trapframe *state)
+void advance_pc(struct hw_trapframe *state)
 {
        state->epc += 4;
 }
@@ -41,14 +40,13 @@ void set_stack_top(uintptr_t stacktop)
 /* Note the assertion assumes we are in the top page of the stack. */
 uintptr_t get_stack_top(void)
 {
-       register uintptr_t sp asm ("sp");
+       register uintptr_t sp asm("sp");
        uintptr_t stacktop = core_stacktops[core_id()];
        assert(ROUNDUP(sp, PGSIZE) == stacktop);
        return stacktop;
 }
 
-void
-idt_init(void)
+void idt_init(void)
 {
 }
 
@@ -76,38 +74,35 @@ static void set_current_ctx_sw(struct per_cpu_info *pcpui,
        pcpui->cur_ctx = &pcpui->actual_ctx;
 }
 
-static int
-format_trapframe(struct hw_trapframe *hw_tf, char* buf, int bufsz)
+static int format_trapframe(struct hw_trapframe *hw_tf, char *buf, int bufsz)
 {
        // slightly hackish way to read out the instruction that faulted.
        // not guaranteed to be right 100% of the time
        uint32_t insn;
-       if(!(current && !memcpy_from_user(current,&insn,(void*)hw_tf->epc,4)))
+       if (!(current &&
+             !memcpy_from_user(current, &insn, (void *)hw_tf->epc, 4)))
                insn = -1;
 
-       int len = snprintf(buf,bufsz,"TRAP frame at %p on core %d\n",
-                          hw_tf, core_id());
-       static const char* regnames[] = {
-         "z ", "ra", "s0", "s1", "s2", "s3", "s4", "s5",
-         "s6", "s7", "s8", "s9", "sA", "sB", "sp", "tp",
-         "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5",
-         "a6", "a7", "a8", "a9", "aA", "aB", "aC", "aD"
-       };
+       int len = snprintf(buf, bufsz, "TRAP frame at %p on core %d\n", hw_tf,
+                          core_id());
+       static const char *regnames[] = {
+           "z ", "ra", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8",
+           "s9", "sA", "sB", "sp", "tp", "v0", "v1", "a0", "a1", "a2", "a3",
+           "a4", "a5", "a6", "a7", "a8", "a9", "aA", "aB", "aC", "aD"};
 
        hw_tf->gpr[0] = 0;
 
-       for(int i = 0; i < 32; i+=4)
-       {
-               for(int j = 0; j < 4; j++)
-                       len += snprintf(buf+len, bufsz-len,
-                                       "%s %016lx%c", regnames[i+j], hw_tf->gpr[i+j],
+       for (int i = 0; i < 32; i += 4) {
+               for (int j = 0; j < 4; j++)
+                       len += snprintf(buf + len, bufsz - len, "%s %016lx%c",
+                                       regnames[i + j], hw_tf->gpr[i + j],
                                        j < 3 ? ' ' : '\n');
        }
-       len += snprintf(buf+len, bufsz-len,
+       len += snprintf(buf + len, bufsz - len,
                        "sr %016lx pc %016lx va %016lx insn       %08x\n",
-                                       hw_tf->sr, hw_tf->epc, hw_tf->badvaddr, insn);
+                       hw_tf->sr, hw_tf->epc, hw_tf->badvaddr, insn);
 
-       buf[bufsz-1] = 0;
+       buf[bufsz - 1] = 0;
        return len;
 }
 
@@ -115,32 +110,32 @@ void print_trapframe(struct hw_trapframe *hw_tf)
 {
        char buf[1024];
        int len = format_trapframe(hw_tf, buf, sizeof(buf));
-       cputbuf(buf,len);
+       cputbuf(buf, len);
 }
 
 void print_swtrapframe(struct sw_trapframe *sw_tf)
 {
-       #warning "fix me"
+#warning "fix me"
 }
 
 void print_vmtrapframe(struct vm_trapframe *vm_tf)
 {
-       #warning "fix me"
+#warning "fix me"
 }
 
 static void exit_halt_loop(struct hw_trapframe *hw_tf)
 {
        extern char after_cpu_halt;
-       if ((char*)hw_tf->epc >= (char*)&cpu_halt &&
-           (char*)hw_tf->epc < &after_cpu_halt)
+       if ((char *)hw_tf->epc >= (char *)&cpu_halt &&
+           (char *)hw_tf->epc < &after_cpu_halt)
                hw_tf->epc = hw_tf->gpr[GPR_RA];
 }
 
 static void handle_keypress(char c)
 {
-       #warning "fix me"
-       /* TODO: does cons_init need to be before cons_add_char?  Also, do something
-        * with CTRL-G, Q, and B. */
+#warning "fix me"
+       /* TODO: does cons_init need to be before cons_add_char?  Also, do
+        * something with CTRL-G, Q, and B. */
        cons_add_char(c);
 
        cons_init();
@@ -149,11 +144,14 @@ static void handle_keypress(char c)
 static void handle_host_interrupt(struct hw_trapframe *hw_tf)
 {
        uintptr_t fh = mtpcr(PCR_FROMHOST, 0);
-       switch (fh >> 56)
-       {
-         case 0x00: return;
-         case 0x01: handle_keypress(fh); return;
-         default: assert(0);
+       switch (fh >> 56) {
+       case 0x00:
+               return;
+       case 0x01:
+               handle_keypress(fh);
+               return;
+       default:
+               assert(0);
        }
 }
 
@@ -169,23 +167,20 @@ static void handle_interprocessor_interrupt(struct hw_trapframe *hw_tf)
        handle_kmsg_ipi(hw_tf, 0);
 }
 
-static void
-unhandled_trap(struct hw_trapframe *state, const char* name)
+static void unhandled_trap(struct hw_trapframe *state, const char *name)
 {
        static spinlock_t screwup_lock = SPINLOCK_INITIALIZER;
        spin_lock(&screwup_lock);
 
-       if(in_kernel(state))
-       {
+       if (in_kernel(state)) {
                print_trapframe(state);
                panic("Unhandled trap in kernel!\nTrap type: %s", name);
-       }
-       else
-       {
+       } else {
                char tf_buf[1024];
                format_trapframe(state, tf_buf, sizeof(tf_buf));
 
-               warn("Unhandled trap in user!\nTrap type: %s\n%s", name, tf_buf);
+               warn("Unhandled trap in user!\nTrap type: %s\n%s", name,
+                    tf_buf);
                backtrace();
                spin_unlock(&screwup_lock);
 
@@ -194,45 +189,39 @@ unhandled_trap(struct hw_trapframe *state, const char* name)
        }
 }
 
-static void
-handle_misaligned_fetch(struct hw_trapframe *state)
+static void handle_misaligned_fetch(struct hw_trapframe *state)
 {
        unhandled_trap(state, "Misaligned Fetch");
 }
 
-static void
-handle_misaligned_load(struct hw_trapframe *state)
+static void handle_misaligned_load(struct hw_trapframe *state)
 {
        unhandled_trap(state, "Misaligned Load");
 }
 
-static void
-handle_misaligned_store(struct hw_trapframe *state)
+static void handle_misaligned_store(struct hw_trapframe *state)
 {
        unhandled_trap(state, "Misaligned Store");
 }
 
-static void
-handle_fault_fetch(struct hw_trapframe *state)
+static void handle_fault_fetch(struct hw_trapframe *state)
 {
-       if(in_kernel(state))
-       {
+       if (in_kernel(state)) {
                print_trapframe(state);
-               panic("Instruction Page Fault in the Kernel at %p!", state->epc);
+               panic("Instruction Page Fault in the Kernel at %p!",
+                     state->epc);
        }
 
        set_current_ctx_hw(&per_cpu_info[core_id()], state);
 
 #warning "returns EAGAIN if you should reflect the fault"
-       if(handle_page_fault(current, state->epc, PROT_EXEC))
+       if (handle_page_fault(current, state->epc, PROT_EXEC))
                unhandled_trap(state, "Instruction Page Fault");
 }
 
-static void
-handle_fault_load(struct hw_trapframe *state)
+static void handle_fault_load(struct hw_trapframe *state)
 {
-       if(in_kernel(state))
-       {
+       if (in_kernel(state)) {
                print_trapframe(state);
                panic("Load Page Fault in the Kernel at %p!", state->badvaddr);
        }
@@ -240,34 +229,30 @@ handle_fault_load(struct hw_trapframe *state)
        set_current_ctx_hw(&per_cpu_info[core_id()], state);
 
 #warning "returns EAGAIN if you should reflect the fault"
-       if(handle_page_fault(current, state->badvaddr, PROT_READ))
+       if (handle_page_fault(current, state->badvaddr, PROT_READ))
                unhandled_trap(state, "Load Page Fault");
 }
 
-static void
-handle_fault_store(struct hw_trapframe *state)
+static void handle_fault_store(struct hw_trapframe *state)
 {
-       if(in_kernel(state))
-       {
+       if (in_kernel(state)) {
                print_trapframe(state);
                panic("Store Page Fault in the Kernel at %p!", state->badvaddr);
        }
 
        set_current_ctx_hw(&per_cpu_info[core_id()], state);
 
-       if(handle_page_fault(current, state->badvaddr, PROT_WRITE))
+       if (handle_page_fault(current, state->badvaddr, PROT_WRITE))
                unhandled_trap(state, "Store Page Fault");
 }
 
-static void
-handle_illegal_instruction(struct hw_trapframe *state)
+static void handle_illegal_instruction(struct hw_trapframe *state)
 {
        assert(!in_kernel(state));
 
        struct per_cpu_info *pcpui = &per_cpu_info[core_id()];
        set_current_ctx_hw(pcpui, state);
-       if (emulate_fpu(state) == 0)
-       {
+       if (emulate_fpu(state) == 0) {
                advance_pc(&pcpui->cur_ctx->tf.hw_tf);
                return;
        }
@@ -275,8 +260,7 @@ handle_illegal_instruction(struct hw_trapframe *state)
        unhandled_trap(state, "Illegal Instruction");
 }
 
-static void
-handle_syscall(struct hw_trapframe *state)
+static void handle_syscall(struct hw_trapframe *state)
 {
        uintptr_t a0 = state->gpr[GPR_A0];
        uintptr_t a1 = state->gpr[GPR_A1];
@@ -284,43 +268,40 @@ handle_syscall(struct hw_trapframe *state)
        advance_pc(state);
        set_current_ctx_hw(&per_cpu_info[core_id()], state);
        enable_irq();
-       prep_syscalls(current, (struct syscall*)a0, a1);
+       prep_syscalls(current, (struct syscall *)a0, a1);
 }
 
-static void
-handle_breakpoint(struct hw_trapframe *state)
+static void handle_breakpoint(struct hw_trapframe *state)
 {
        advance_pc(state);
        monitor(state);
 }
 
-void
-handle_trap(struct hw_trapframe *hw_tf)
+void handle_trap(struct hw_trapframe *hw_tf)
 {
        static void (*const trap_handlers[])(struct hw_trapframe *) = {
-         [CAUSE_MISALIGNED_FETCH] = handle_misaligned_fetch,
-         [CAUSE_FAULT_FETCH] = handle_fault_fetch,
-         [CAUSE_ILLEGAL_INSTRUCTION] = handle_illegal_instruction,
-         [CAUSE_PRIVILEGED_INSTRUCTION] = handle_illegal_instruction,
-         [CAUSE_SYSCALL] = handle_syscall,
-         [CAUSE_BREAKPOINT] = handle_breakpoint,
-         [CAUSE_MISALIGNED_LOAD] = handle_misaligned_load,
-         [CAUSE_MISALIGNED_STORE] = handle_misaligned_store,
-         [CAUSE_FAULT_LOAD] = handle_fault_load,
-         [CAUSE_FAULT_STORE] = handle_fault_store,
+           [CAUSE_MISALIGNED_FETCH] = handle_misaligned_fetch,
+           [CAUSE_FAULT_FETCH] = handle_fault_fetch,
+           [CAUSE_ILLEGAL_INSTRUCTION] = handle_illegal_instruction,
+           [CAUSE_PRIVILEGED_INSTRUCTION] = handle_illegal_instruction,
+           [CAUSE_SYSCALL] = handle_syscall,
+           [CAUSE_BREAKPOINT] = handle_breakpoint,
+           [CAUSE_MISALIGNED_LOAD] = handle_misaligned_load,
+           [CAUSE_MISALIGNED_STORE] = handle_misaligned_store,
+           [CAUSE_FAULT_LOAD] = handle_fault_load,
+           [CAUSE_FAULT_STORE] = handle_fault_store,
        };
 
        static void (*const irq_handlers[])(struct hw_trapframe *) = {
-         [IRQ_TIMER] = handle_timer_interrupt,
-         [IRQ_HOST] = handle_host_interrupt,
-         [IRQ_IPI] = handle_interprocessor_interrupt,
+           [IRQ_TIMER] = handle_timer_interrupt,
+           [IRQ_HOST] = handle_host_interrupt,
+           [IRQ_IPI] = handle_interprocessor_interrupt,
        };
 
        struct per_cpu_info *pcpui = &per_cpu_info[core_id()];
-       if (hw_tf->cause < 0)
-       {
+       if (hw_tf->cause < 0) {
                uint8_t irq = hw_tf->cause;
-               assert(irq < sizeof(irq_handlers)/sizeof(irq_handlers[0]) &&
+               assert(irq < sizeof(irq_handlers) / sizeof(irq_handlers[0]) &&
                       irq_handlers[irq]);
 
                if (in_kernel(hw_tf))
@@ -331,10 +312,9 @@ handle_trap(struct hw_trapframe *hw_tf)
                inc_irq_depth(pcpui);
                irq_handlers[irq](hw_tf);
                dec_irq_depth(pcpui);
-       }
-       else
-       {
-               assert(hw_tf->cause < sizeof(trap_handlers)/sizeof(trap_handlers[0]) &&
+       } else {
+               assert(hw_tf->cause <
+                          sizeof(trap_handlers) / sizeof(trap_handlers[0]) &&
                       trap_handlers[hw_tf->cause]);
                if (in_kernel(hw_tf)) {
                        inc_ktrap_depth(pcpui);
@@ -343,14 +323,14 @@ handle_trap(struct hw_trapframe *hw_tf)
                } else {
                        trap_handlers[hw_tf->cause](hw_tf);
                }
-               #warning "if a trap wasn't handled fully, like an MCP pf, reflect it
+#warning "if a trap wasn't handled fully, like an MCP pf, reflect it
                reflect_unhandled_trap(hw_tf->tf_trapno, hw_tf->tf_err, aux);
        }
 
-       extern void pop_hw_tf(struct hw_trapframe *tf); /* in asm */
-       /* Return to the current process, which should be runnable.  If we're the
-        * kernel, we should just return naturally.  Note that current and tf need
-        * to still be okay (might not be after blocking) */
+       extern void pop_hw_tf(struct hw_trapframe * tf); /* in asm */
+       /* Return to the current process, which should be runnable.  If we're
+        * the kernel, we should just return naturally.  Note that current and
+        * tf need to still be okay (might not be after blocking) */
        if (in_kernel(hw_tf))
                pop_hw_tf(hw_tf);
        else
index 8b91715..16194f5 100644 (file)
@@ -26,11 +26,11 @@ struct extable_ip_fixup {
        uint64_t fixup;
 };
 
-#define _ASM_EXTABLE(from, to)                                                                 \
-       " .pushsection \"__ex_table\",\"a\"\n"                                          \
-       " .balign 16\n"                                                                                         \
-       " .quad (" #from ") - .\n"                                                                      \
-       " .quad (" #to ") - .\n"                                                                        \
+#define _ASM_EXTABLE(from, to)                                         \
+       " .pushsection \"__ex_table\",\"a\"\n"                          \
+       " .balign 16\n"                                                 \
+       " .quad (" #from ") - .\n"                                      \
+       " .quad (" #to ") - .\n"                                        \
        " .popsection\n"
 
 static inline int __put_user(void *dst, const void *src, unsigned int count)
index e030647..9eadd5b 100644 (file)
 
 bool lapic_check_spurious(int trap_nr)
 {
-       /* FYI: lapic_spurious is 255 on qemu and 15 on the nehalem..  We actually
-        * can set bits 4-7, and P6s have 0-3 hardwired to 0.  YMMV.  NxM seems to
-        * say the lower 3 bits are usually 1.  We'll see if the assert trips.
+       /* FYI: lapic_spurious is 255 on qemu and 15 on the nehalem..  We
+        * actually can set bits 4-7, and P6s have 0-3 hardwired to 0.  YMMV.
+        * NxM seems to say the lower 3 bits are usually 1.  We'll see if the
+        * assert trips.
         *
-        * The SDM recommends not using the spurious vector for any other IRQs (LVT
-        * or IOAPIC RTE), since the handlers don't send an EOI.  However, our check
-        * here allows us to use the vector since we can tell the diff btw a
-        * spurious and a real IRQ. */
+        * The SDM recommends not using the spurious vector for any other IRQs
+        * (LVT or IOAPIC RTE), since the handlers don't send an EOI.  However,
+        * our check here allows us to use the vector since we can tell the diff
+        * btw a spurious and a real IRQ. */
        assert(IdtLAPIC_SPURIOUS == (apicrget(MSR_LAPIC_SPURIOUS) & 0xff));
        /* Note the lapic's vectors are not shifted by an offset. */
        if ((trap_nr == IdtLAPIC_SPURIOUS) &&
@@ -77,6 +78,7 @@ bool lapic_get_irr_bit(uint8_t vector)
 void lapic_mask_irq(struct irq_handler *unused, int apic_vector)
 {
        uintptr_t mm_reg;
+
        if (apic_vector < IdtLAPIC || IdtLAPIC + 4 < apic_vector) {
                warn("Bad apic vector %d\n", apic_vector);
                return;
@@ -88,6 +90,7 @@ void lapic_mask_irq(struct irq_handler *unused, int apic_vector)
 void lapic_unmask_irq(struct irq_handler *unused, int apic_vector)
 {
        uintptr_t mm_reg;
+
        if (apic_vector < IdtLAPIC || IdtLAPIC + 4 < apic_vector) {
                warn("Bad apic vector %d\n", apic_vector);
                return;
@@ -116,8 +119,9 @@ bool ipi_is_pending(uint8_t vector)
 void __lapic_set_timer(uint32_t ticks, uint8_t vec, bool periodic, uint8_t div)
 {
 #ifdef CONFIG_LOUSY_LAPIC_TIMER
-       /* qemu without kvm seems to delay timer IRQs on occasion, and needs extra
-        * IRQs from any source to get them delivered.  periodic does the trick. */
+       /* qemu without kvm seems to delay timer IRQs on occasion, and needs
+        * extra IRQs from any source to get them delivered.  periodic does the
+        * trick. */
        periodic = TRUE;
 #endif
        // clears bottom bit and then set divider
@@ -126,23 +130,20 @@ void __lapic_set_timer(uint32_t ticks, uint8_t vec, bool periodic, uint8_t div)
        // set LVT with interrupt handling information.  also unmasks.
        apicrput(MSR_LAPIC_LVT_TIMER, vec | (periodic << 17));
        apicrput(MSR_LAPIC_INITIAL_COUNT, ticks);
-       // For debugging when we expand this
-       //cprintf("LAPIC LVT Timer: 0x%08x\n", apicrget(MSR_LAPIC_LVT_TIMER));
-       //cprintf("LAPIC Init Count: 0x%08x\n", apicrget(MSR_LAPIC_INITIAL_COUNT));
-       //cprintf("LAPIC Current Count: 0x%08x\n",
-       //        apicrget(MSR_LAPIC_CURRENT_COUNT));
 }
 
 void lapic_set_timer(uint32_t usec, bool periodic)
 {
-       /* If we overflowed a uint32, send in the max timer possible.  The lapic can
-        * only handle a 32 bit.  We could muck with changing the divisor, but even
-        * then, we might not be able to match 4000 sec (based on the bus speed).
-        * The kernel alarm code can handle spurious timer interrupts, so we just
-        * set the timer for as close as we can get to the desired time. */
+       /* If we overflowed a uint32, send in the max timer possible.  The lapic
+        * can only handle a 32 bit.  We could muck with changing the divisor,
+        * but even then, we might not be able to match 4000 sec (based on the
+        * bus speed).  The kernel alarm code can handle spurious timer
+        * interrupts, so we just set the timer for as close as we can get to
+        * the desired time. */
        uint64_t ticks64 = (usec * __proc_global_info.bus_freq)
                           / LAPIC_TIMER_DIVISOR_VAL / 1000000;
        uint32_t ticks32 = ((ticks64 >> 32) ? 0xffffffff : ticks64);
+
        assert(ticks32 > 0);
        __lapic_set_timer(ticks32, IdtLAPIC_TIMER, periodic,
                          LAPIC_TIMER_DIVISOR_BITS);
@@ -151,6 +152,7 @@ void lapic_set_timer(uint32_t usec, bool periodic)
 uint32_t lapic_get_default_id(void)
 {
        uint32_t ebx;
+       
        cpuid(0x1, 0x0, 0, &ebx, 0, 0);
        // p6 family only uses 4 bits here, and 0xf is reserved for the IOAPIC
        return (ebx & 0xFF000000) >> 24;
index fc0fd97..5752b89 100644 (file)
@@ -23,8 +23,8 @@
  * spaces.  We just happen to have a slight 'hole' in addressable physical
  * memory.  We can move the PBASE, but we're limited to 32 bit (physical)
  * addresses. */
-#define LAPIC_PBASE                                    0xfee00000      /* default *physical* address */
-#define LAPIC_LVT_MASK                                 0x00010000
+#define LAPIC_PBASE            0xfee00000      /* default *physical* address */
+#define LAPIC_LVT_MASK         0x00010000
 
 /* Quick note on the divisor.  The LAPIC timer ticks once per divisor-bus ticks
  * (system bus or APIC bus, depending on the model).  Ex: A divisor of 128 means
 #define LAPIC_TIMER_DIVISOR_BITS       0x8     /* Div = 32 */
 
 // IPI Interrupt Command Register
-#define LAPIC_IPI_ICR_LOWER                            0x30
-#define LAPIC_IPI_ICR_UPPER                            0x31
+#define LAPIC_IPI_ICR_LOWER    0x30
+#define LAPIC_IPI_ICR_UPPER    0x31
 /* Interrupts being serviced (in-service) and pending (interrupt request reg).
  * Note these registers are not normal bitmaps, but instead are 8 separate
  * 32-bit registers, spaced/aligned on 16 byte boundaries in the LAPIC address
  * space. */
-#define LAPIC_ISR                                      0x10
-#define LAPIC_IRR                                      0x20
-#define LAPIC_DFR                                      0x0e
+#define LAPIC_ISR              0x10
+#define LAPIC_IRR              0x20
+#define LAPIC_DFR              0x0e
 
 struct irq_handler;    /* include loops */
 
@@ -129,7 +129,6 @@ static inline void lapic_disable_timer(void)
 static inline void lapic_disable(void)
 {
        apicrput(MSR_LAPIC_SPURIOUS, apicrget(MSR_LAPIC_SPURIOUS) & 0xffffefff);
-       //write_msr(IA32_APIC_BASE, read_msr(IA32_APIC_BASE) & ~MSR_APIC_ENABLE);
 }
 
 static inline void lapic_enable(void)
@@ -203,15 +202,15 @@ static inline void __send_nmi(uint8_t hw_coreid)
  */
 
 struct ioapic {
-       spinlock_t lock;                        /* IOAPIC: register access */
-       uintptr_t addr;                         /* IOAPIC: register base */
-       uintptr_t paddr;                        /* register base */
-       int nrdt;                                       /* IOAPIC: size of RDT */
-       int ibase;                                      /* global interrupt base */
+       spinlock_t lock;        /* IOAPIC: register access */
+       uintptr_t addr;         /* IOAPIC: register base */
+       uintptr_t paddr;        /* register base */
+       int nrdt;               /* IOAPIC: size of RDT */
+       int ibase;              /* global interrupt base */
 };
 
 struct lapic {
-       int machno;                                     /* similar to os_coreid, unused */
+       int machno;             /* similar to os_coreid, unused */
 
        uint32_t lvt[8];
        int nlvt;
@@ -244,7 +243,7 @@ enum {
  * [16] Interrupt Mask
  */
 enum {
-       MTf = 0x00000000,                       /* Fixed */
+       MTf = 0x00000000,       /* Fixed */
        MTlp = 0x00000100,      /* Lowest Priority */
        MTsmi = 0x00000200,     /* SMI */
        MTrr = 0x00000300,      /* Remote Read */
index 569ba71..e5eb11e 100644 (file)
@@ -38,13 +38,13 @@ static char *apicregnames[] = {
        [MSR_LAPIC_LVT_THERMAL] "Thermal Sensor",
 };
 
-enum {                                                 /* Siv */
-       Swen = 0x00000100,                      /* Software Enable */
+enum {                         /* Siv */
+       Swen = 0x00000100,      /* Software Enable */
        Fdis = 0x00000200,      /* Focus Disable */
 };
 
-enum {                                                 /* Iclo */
-       Lassert = 0x00004000,           /* Assert level */
+enum {                         /* Iclo */
+       Lassert = 0x00004000,   /* Assert level */
 
        DSnone = 0x00000000,    /* Use Destination Field */
        DSself = 0x00040000,    /* Self is only destination */
@@ -52,12 +52,12 @@ enum {                                                      /* Iclo */
        DSallexc = 0x000c0000,  /* All Excluding self */
 };
 
-enum {                                                 /* Tlvt */
-       Periodic = 0x00020000,          /* Periodic Timer Mode */
+enum {                         /* Tlvt */
+       Periodic = 0x00020000,  /* Periodic Timer Mode */
 };
 
-enum {                                                 /* Tdc */
-       DivX2 = 0x00000000,                     /* Divide by 2 */
+enum {                         /* Tdc */
+       DivX2 = 0x00000000,     /* Divide by 2 */
        DivX4 = 0x00000001,     /* Divide by 4 */
        DivX8 = 0x00000002,     /* Divide by 8 */
        DivX16 = 0x00000003,    /* Divide by 16 */
@@ -87,16 +87,18 @@ static void __apic_ir_dump(uint64_t r)
        for (i = 7; i >= 0; i--) {
                val = apicrget(r+i);
                if (val) {
-                       printk("Register at range (%d,%d]: 0x%08x\n", ((i+1)*32),
-                              i*32, val);
+                       printk("Register at range (%d,%d]: 0x%08x\n",
+                              ((i + 1) * 32), i * 32, val);
                }
        }
 }
+
 void apic_isr_dump(void)
 {
        printk("ISR DUMP\n");
        __apic_ir_dump(MSR_LAPIC_ISR_START);
 }
+
 void apic_irr_dump(void)
 {
        printk("IRR DUMP\n");
@@ -152,6 +154,7 @@ void apicinit(int apicno, uintptr_t pa, int isbp)
 {
        struct apic *apic;
        uint64_t msr_val;
+
        /*
         * Mark the APIC useable if it has a good ID
         * and the registers can be mapped.
@@ -209,8 +212,8 @@ char *apicdump(char *start, char *end)
        if (!2)
                return start;
 
-       start =
-               seprintf(start, end, "apicbase %#p apmachno %d\n", apicbase, apmachno);
+       start = seprintf(start, end, "apicbase %#p apmachno %d\n", apicbase,
+                        apmachno);
        for (i = 0; i < Napic; i++)
                start = apicdump0(start, end, xlapic + i, i);
        for (i = 0; i < Napic; i++)
@@ -221,6 +224,7 @@ char *apicdump(char *start, char *end)
 void handle_lapic_error(struct hw_trapframe *hw_tf, void *data)
 {
        uint32_t err;
+
        apicrput(MSR_LAPIC_ESR, 0);
        err = apicrget(MSR_LAPIC_ESR);
        /* i get a shitload of these on my nehalem, many with err == 0 */
@@ -247,7 +251,8 @@ int apiconline(void)
        apic = &xlapic[apicno];
        /* The addr check tells us if it is an IOAPIC or not... */
        if (!apic->useable || apic->addr) {
-               printk("Unsuitable apicno %d on HW core %d!!\n", apicno, hw_core_id());
+               printk("Unsuitable apicno %d on HW core %d!!\n", apicno,
+                      hw_core_id());
                return 0;
        }
        /* Things that can only be done when on the processor owning the APIC,
@@ -262,8 +267,8 @@ int apiconline(void)
        apic->nlvt = nlvt;
        apic->ver = ver & 0xff;
 
-       /* These don't really matter in Physical mode; set the defaults anyway.  If
-        * we have problems with logical IPIs on AMD, check this out: */
+       /* These don't really matter in Physical mode; set the defaults anyway.
+        * If we have problems with logical IPIs on AMD, check this out: */
        //if (memcmp(m->cpuinfo, "AuthenticAMD", 12) == 0)
        //      dfr = 0xf0000000;
        //else
@@ -271,32 +276,32 @@ int apiconline(void)
        //apicrput(Df, dfr);
        //apicrput(MSR_LAPIC_LDR, 0x00000000);
 
-       /* Disable interrupts until ready by setting the Task Priority register to
-        * 0xff. */
+       /* Disable interrupts until ready by setting the Task Priority register
+        * to 0xff. */
        apicrput(MSR_LAPIC_TPR, 0xff);
 
-       /* Software-enable the APIC in the Spurious Interrupt Vector register and
-        * set the vector number. The vector number must have bits 3-0 0x0f unless
-        * the Extended Spurious Vector Enable bit is set in the HyperTransport
-        * Transaction Control register. */
+       /* Software-enable the APIC in the Spurious Interrupt Vector register
+        * and set the vector number. The vector number must have bits 3-0 0x0f
+        * unless the Extended Spurious Vector Enable bit is set in the
+        * HyperTransport Transaction Control register. */
        apicrput(MSR_LAPIC_SPURIOUS, Swen | IdtLAPIC_SPURIOUS);
 
        /* Acknowledge any outstanding interrupts. */
        apicrput(MSR_LAPIC_EOI, 0);
 
        /* Mask interrupts on Performance Counter overflow and Thermal Sensor if
-        * implemented, and on Lintr0 (Legacy INTR), Lintr1 (Legacy NMI), and the
-        * Timer.  Clear any Error Status (write followed by read) and enable the
-        * Error interrupt. */
+        * implemented, and on Lintr0 (Legacy INTR), Lintr1 (Legacy NMI), and
+        * the Timer.  Clear any Error Status (write followed by read) and
+        * enable the Error interrupt. */
        switch (apic->nlvt) {
-               case 6:
-                       apicrput(MSR_LAPIC_LVT_THERMAL, Im);
-                       /* fall-through */
-               case 5:
-                       apicrput(MSR_LAPIC_LVT_PERFMON, Im);
-                       /* fall-through */
-               default:
-                       break;
+       case 6:
+               apicrput(MSR_LAPIC_LVT_THERMAL, Im);
+               /* fall-through */
+       case 5:
+               apicrput(MSR_LAPIC_LVT_PERFMON, Im);
+               /* fall-through */
+       default:
+               break;
        }
        /* lvt[0] and [1] were set to 0 in the BSS */
        apicrput(MSR_LAPIC_LVT_LINT1, apic->lvt[1] | Im | IdtLAPIC_LINT1);
index 0d3e935..b4c06fb 100644 (file)
@@ -76,12 +76,14 @@ static inline void mwait(void *eax)
        asm volatile("xorq %%rcx, %%rcx;"
                     "xorq %%rdx, %%rdx;"
                     "monitor;"
-                                /* this is racy, generically.  we never check if the write to
-                                 * the monitored address happened already. */
+                                /* this is racy, generically.  we never check
+                                 * if the write to the monitored address
+                                 * happened already. */
                     "movq $0, %%rax;"  /* c-state hint.  this is C1 */
                     "mwait;"
                     : : "a"(eax));
 }
+
 /* Check out k/a/x86/rdtsc_test.c for more info */
 static inline uint64_t read_tsc_serialized(void)
 {
@@ -107,9 +109,10 @@ static inline void enable_irqsave(int8_t *state)
        // < 0 means more disabled calls have been made
        // Mostly doing this so we can call disable_irqsave first if we want
 
-       // one side or another "gets a point" if interrupts were already the
-       // way it wanted to go.  o/w, state stays at 0.  if the state was not 0
-       // then, enabling/disabling isn't even an option.  just increment/decrement
+       // one side or another "gets a point" if interrupts were already the way
+       // it wanted to go.  o/w, state stays at 0.  if the state was not 0
+       // then, enabling/disabling isn't even an option.  just
+       // increment/decrement
 
        // if enabling is winning or tied, make sure it's enabled
        if ((*state == 0) && !irq_is_enabled())
@@ -149,6 +152,7 @@ static inline void cache_flush(void)
 static inline void reboot(void)
 {
        uint8_t cf9 = inb(0xcf9) & ~6;
+
        outb(0x92, 0x3);
        outb(0xcf9, cf9 | 2);
        outb(0xcf9, cf9 | 6);
@@ -192,11 +196,11 @@ static inline void swap_gs(void)
 static inline void __attribute__((noreturn))
 __reset_stack_pointer(void *arg, uintptr_t sp, void (*f)(void *))
 {
-       /* FP must be zeroed before SP.  Ideally, we'd do both atomically.  If we
-        * take an IRQ/NMI in between and set SP first, then a backtrace would be
-        * confused since FP points *below* the SP that the *IRQ handler* is now
-        * using.  By zeroing FP first, at least we won't BT at all (though FP is
-        * still out of sync with SP). */
+       /* FP must be zeroed before SP.  Ideally, we'd do both atomically.  If
+        * we take an IRQ/NMI in between and set SP first, then a backtrace
+        * would be confused since FP points *below* the SP that the *IRQ
+        * handler* is now using.  By zeroing FP first, at least we won't BT at
+        * all (though FP is still out of sync with SP). */
        asm volatile ("mov $0x0, %%rbp;"
                      "mov %0, %%rsp;"
                      "jmp *%%rdx;"
index a7766d8..54dca37 100644 (file)
@@ -132,18 +132,17 @@ static inline bool spin_locked(spinlock_t *lock)
 static inline void __spin_lock_raw(volatile uint32_t *rlock)
 {
        uint8_t dicks = 0;
-       asm volatile(
-                       "1:                       "
-                       "       cmpb $0, %0;          "
-                       "       je 2f;                "
-                       "       pause;                "
-                       "       jmp 1b;               "
-                       "2:                       "
-                       "       movb $1, %1;          "
-                       "       xchgb %1, %0;         "
-                       "       cmpb $0, %1;          "
-                       "       jne 1b;               "
-               : : "m"(*rlock), "r"(dicks) : "cc");
+       asm volatile("1:                      "
+                    "  cmpb $0, %0;          "
+                    "  je 2f;                "
+                    "  pause;                "
+                    "  jmp 1b;               "
+                    "2:                      "
+                    "  movb $1, %1;          "
+                    "  xchgb %1, %0;         "
+                    "  cmpb $0, %1;          "
+                    "  jne 1b;               "
+                    : : "m"(*rlock), "r"(dicks) : "cc");
        cmb();  /* need cmb(), the CPU mb() was handled by the xchg */
 }
 
@@ -154,8 +153,8 @@ static inline void __spin_lock(spinlock_t *lock)
 
 static inline bool __spin_trylock(spinlock_t *lock)
 {
-       /* since this is an or, we're not going to clobber the top bytes (if that
-        * matters) */
+       /* since this is an or, we're not going to clobber the top bytes (if
+        * that matters) */
        return !__sync_fetch_and_or(&lock->rlock, 1);
 }
 
index a42d289..5b68e3f 100644 (file)
@@ -36,8 +36,7 @@
 void readsect(void*, uint32_t);
 void readseg(uint32_t, uint32_t, uint32_t);
 
-void
-cmain(void)
+void cmain(void)
 {
        proghdr_t *ph, *eph;
 
@@ -67,8 +66,7 @@ bad:
 
 // Read 'count' bytes at 'offset' from kernel into virtual address 'va'.
 // Might copy more than asked
-void
-readseg(uint32_t va, uint32_t count, uint32_t offset)
+void readseg(uint32_t va, uint32_t count, uint32_t offset)
 {
        uint32_t end_va;
 
@@ -91,16 +89,14 @@ readseg(uint32_t va, uint32_t count, uint32_t offset)
        }
 }
 
-void
-waitdisk(void)
+void waitdisk(void)
 {
        // wait for disk ready
        while ((inb(0x1F7) & 0xC0) != 0x40)
                /* do nothing */;
 }
 
-void
-readsect(void *dst, uint32_t offset)
+void readsect(void *dst, uint32_t offset)
 {
        // wait for disk to be ready
        waitdisk();
@@ -112,14 +108,14 @@ readsect(void *dst, uint32_t offset)
           Offset is 28 bytes long
        */
 
-       outb(0x1F2, 1);                         // number of sectors to read
-       outb(0x1F3, offset);                    // bits 0-7 (low bits) of 28-bit offset
-       outb(0x1F4, offset >> 8);               // bits 8-15 of 28-bit offset
-       outb(0x1F5, offset >> 16);              // bits 16-23 of 28-bit offset
-       outb(0x1F6, (offset >> 24) | 0xE0);     // bits 24-27 of 28-bit offset
-                                               // bit 28 (= 0) means Disk 0
-                                               // other bits (29-31) must be set to one
-       outb(0x1F7, 0x20);                      // cmd 0x20 - read sectors
+       outb(0x1F2, 1);                 // number of sectors to read
+       outb(0x1F3, offset);            // bits 0-7 (low bits) of 28-bit offset
+       outb(0x1F4, offset >> 8);       // bits 8-15 of 28-bit offset
+       outb(0x1F5, offset >> 16);      // bits 16-23 of 28-bit offset
+       outb(0x1F6, (offset >> 24) | 0xE0); // bits 24-27 of 28-bit offset
+                                       // bit 28 (= 0) means Disk 0
+                                       // other bits (29-31) must be set to one
+       outb(0x1F7, 0x20);              // cmd 0x20 - read sectors
 
        // wait for disk to be ready
        waitdisk();
index 43118de..9c4bd5c 100644 (file)
 
 /***** Serial I/O code *****/
 
-#define COM1                   0x3F8   /* irq 4 */
-#define COM2                   0x2F8   /* irq 3 */
-#define COM3                   0x3E8   /* irq 4 */
-#define COM4                   0x2E8   /* irq 3 */
-
-#define        COM_RX                  0               // In:  Receive buffer (DLAB=0)
-#define COM_DLL                        0               // Out: Divisor Latch Low (DLAB=1)
-#define COM_DLM                        1               // Out: Divisor Latch High (DLAB=1)
-#define COM_IER                        1               // Out: Interrupt Enable Register
-#define        COM_IER_RDI             0x01    //   Enable receiver data interrupt
-#define COM_IIR                        2               // In:  Interrupt ID Register
-#define COM_FCR                        2               // Out: FIFO Control Register
-#define COM_LCR                        3               // Out: Line Control Register
+#define COM1           0x3F8   /* irq 4 */
+#define COM2           0x2F8   /* irq 3 */
+#define COM3           0x3E8   /* irq 4 */
+#define COM4           0x2E8   /* irq 3 */
+
+#define        COM_RX          0       // In:  Receive buffer (DLAB=0)
+#define COM_DLL                0       // Out: Divisor Latch Low (DLAB=1)
+#define COM_DLM                1       // Out: Divisor Latch High (DLAB=1)
+#define COM_IER                1       // Out: Interrupt Enable Register
+#define        COM_IER_RDI     0x01    //   Enable receiver data interrupt
+#define COM_IIR                2       // In:  Interrupt ID Register
+#define COM_FCR                2       // Out: FIFO Control Register
+#define COM_LCR                3       // Out: Line Control Register
 #define        COM_LCR_DLAB    0x80    //   Divisor latch access bit
 #define        COM_LCR_WLEN8   0x03    //   Wordlength: 8 bits
-#define COM_MCR                        4               // Out: Modem Control Register
-#define        COM_MCR_RTS             0x02    // RTS complement
-#define        COM_MCR_DTR             0x01    // DTR complement
+#define COM_MCR                4       // Out: Modem Control Register
+#define        COM_MCR_RTS     0x02    // RTS complement
+#define        COM_MCR_DTR     0x01    // DTR complement
 #define        COM_MCR_OUT2    0x08    // Out2 complement
 #define        COM_MCR_GLB_IRQ 0x08    /* global irq controlled via MCR */
-#define COM_LSR                        5               // In:  Line Status Register
+#define COM_LSR                5       // In:  Line Status Register
 #define COM_LSR_DATA   0x01    //   Data available
 #define COM_LSR_READY  0x20    //   Ready to send
-#define COM_SCRATCH            7               /* Scratch register */
+#define COM_SCRATCH    7       /* Scratch register */
 
 /* List of all initialized console devices */
 struct cons_dev_slist cdev_list = SLIST_HEAD_INITIALIZER(cdev_list);
@@ -50,9 +50,10 @@ static int __serial_get_char(int com, uint8_t *data)
        if (!(inb(com + COM_LSR) & COM_LSR_DATA))
                return -1;
        *data = inb(com + COM_RX);
-       /* serial input sends \r a lot, but we interpret them as \n later on.  this
-        * will help userspace too, which isn't expecting the \rs.  the right answer
-        * might involve telling userspace what sort of console this is. */
+       /* serial input sends \r a lot, but we interpret them as \n later on.
+        * this will help userspace too, which isn't expecting the \rs.  the
+        * right answer might involve telling userspace what sort of console
+        * this is. */
        if (*data == '\r')
                *data = '\n';
        return 0;
@@ -74,30 +75,30 @@ static void __serial_put_char(int com, uint8_t c)
 static void serial_put_char(struct cons_dev *cdev, uint8_t c)
 {
        assert(cdev->type == CONS_SER_DEV);
-       /* We do some funky editing of a few chars, to suit what minicom seems to
-        * expect (at least for brho). */
+       /* We do some funky editing of a few chars, to suit what minicom seems
+        * to expect (at least for brho). */
        switch (c & 0xff) {
-               case '\b':
-               case 0x7f:
-               #ifdef CONFIG_PRINTK_NO_BACKSPACE
-                       __serial_put_char(cdev->val, (uint8_t)('^'));
-                       __serial_put_char(cdev->val, (uint8_t)('H'));
-               #else
-                       __serial_put_char(cdev->val, '\b');
-                       __serial_put_char(cdev->val, (uint8_t)(' '));
-                       __serial_put_char(cdev->val, '\b');
-               #endif /* CONFIG_PRINTK_NO_BACKSPACE */
-                       break;
-               case '\n':
-                       __serial_put_char(cdev->val, (uint8_t)('\n'));
-                       __serial_put_char(cdev->val, (uint8_t)('\r'));
-                       break;
-               case '\r':
-                       __serial_put_char(cdev->val, (uint8_t)('\r'));
-                       break;
-               default:
-                       __serial_put_char(cdev->val, (uint8_t)(c & 0xff));
-                       break;
+       case '\b':
+       case 0x7f:
+       #ifdef CONFIG_PRINTK_NO_BACKSPACE
+               __serial_put_char(cdev->val, (uint8_t)('^'));
+               __serial_put_char(cdev->val, (uint8_t)('H'));
+       #else
+               __serial_put_char(cdev->val, '\b');
+               __serial_put_char(cdev->val, (uint8_t)(' '));
+               __serial_put_char(cdev->val, '\b');
+       #endif /* CONFIG_PRINTK_NO_BACKSPACE */
+               break;
+       case '\n':
+               __serial_put_char(cdev->val, (uint8_t)('\n'));
+               __serial_put_char(cdev->val, (uint8_t)('\r'));
+               break;
+       case '\r':
+               __serial_put_char(cdev->val, (uint8_t)('\r'));
+               break;
+       default:
+               __serial_put_char(cdev->val, (uint8_t)(c & 0xff));
+               break;
        }
 }
 
@@ -105,6 +106,7 @@ static void serial_put_char(struct cons_dev *cdev, uint8_t c)
 static void serial_spam_char(int c)
 {
        struct cons_dev *i;
+
        SLIST_FOREACH(i, &cdev_list, next) {
                if (i->type == CONS_SER_DEV)
                        serial_put_char(i, c);
@@ -119,6 +121,7 @@ static char *__serial_detect_type(int com)
 {
        uint8_t val;
        char *model = 0;
+
        /* First, check that the port actually exists.  I haven't seen any
         * documentation of the LSR 0xff check, but it seems to work on qemu and
         * hardware (brho's nehalem).  Perhaps 0xff is the default state for
@@ -126,8 +129,8 @@ static char *__serial_detect_type(int com)
        /* Serial port doesn't exist if COM_LSR returns 0xff */
        if (inb(com + COM_LSR) == 0xff)
                return model;
-       /* Try to set FIFO, then based on the bits enabled, we can tell what model
-        * it is */
+       /* Try to set FIFO, then based on the bits enabled, we can tell what
+        * model it is */
        outb(com + COM_FCR, 0xe7);
        val = inb(com + COM_IIR);
        if (val & (1 << 6)) {
@@ -163,17 +166,17 @@ static void serial_com_init(struct cons_dev *cdev, int com)
        cdev->type = CONS_SER_DEV;
        cdev->val = com;
        switch (com) {
-               case (COM1):
-               case (COM3):
-                       cdev->irq = 4;
-                       break;
-               case (COM2):
-               case (COM4):
-                       cdev->irq = 3;
-                       break;
-               default:
-                       /* not that printing is the safest thing right now... */
-                       panic("Unknown COM %d", com);
+       case COM1:
+       case COM3:
+               cdev->irq = 4;
+               break;
+       case COM2:
+       case COM4:
+               cdev->irq = 3;
+               break;
+       default:
+               /* not that printing is the safest thing right now... */
+               panic("Unknown COM %d", com);
        }
        cdev->getc = serial_get_char;
        /* Turn off the FIFO (not sure this is needed) */
@@ -185,11 +188,12 @@ static void serial_com_init(struct cons_dev *cdev, int com)
        outb(com + COM_DLM, 0);
        /* 8 data bits, 1 stop bit, parity off; turn off DLAB latch */
        outb(com + COM_LCR, COM_LCR_WLEN8 & ~COM_LCR_DLAB);
-       /* This should turn on hardware flow control and make sure the global irq
-        * bit is on.  This bit is definitely used some hardware's 16550As, though
-        * not for qemu.  Also, on both qemu and hardware, this whole line is a
-        * noop, since the COM_MCR is already 0x0b, so we're just making sure the
-        * three bits are still turned on (and leaving other bits unchanged) */
+       /* This should turn on hardware flow control and make sure the global
+        * irq bit is on.  This bit is definitely used some hardware's 16550As,
+        * though not for qemu.  Also, on both qemu and hardware, this whole
+        * line is a noop, since the COM_MCR is already 0x0b, so we're just
+        * making sure the three bits are still turned on (and leaving other
+        * bits unchanged) */
        outb(com + COM_MCR, inb(com + COM_MCR) | COM_MCR_RTS | COM_MCR_DTR |
                                                 COM_MCR_GLB_IRQ);
        /* Enable rx interrupts */
@@ -215,8 +219,7 @@ static void serial_init(void)
 // page.
 
 // Stupid I/O delay routine necessitated by historical PC design flaws
-static void
-delay(void)
+static void delay(void)
 {
        inb(0x84);
        inb(0x84);
@@ -224,8 +227,7 @@ delay(void)
        inb(0x84);
 }
 
-static void
-lpt_putc(int c)
+static void lpt_putc(int c)
 {
        int i;
 
@@ -259,8 +261,7 @@ static uint16_t scrolling_crt_buf[SCROLLING_CRT_SIZE];
 static uint16_t scrolling_crt_pos;
 static uint8_t current_crt_buf;
 
-void
-cga_init(void)
+void cga_init(void)
 {
        volatile uint16_t *cp;
        uint16_t was;
@@ -298,7 +299,8 @@ static void set_screen(uint8_t screen_num)
        int offset = scrolling_crt_pos + leftovers - (screen_num + 1)*CRT_SIZE;
        offset = (offset > 0) ? offset : 0;
 
-       memcpy(crt_buf, scrolling_crt_buf + offset, CRT_SIZE * sizeof(uint16_t));
+       memcpy(crt_buf, scrolling_crt_buf + offset,
+              CRT_SIZE * sizeof(uint16_t));
 }
 
 static void scroll_screen_up(void)
@@ -321,8 +323,7 @@ static void reset_screen(void)
        set_screen(current_crt_buf);
 }
 
-void
-cga_putc(int c)
+void cga_putc(int c)
 {
        // if no attribute given, then use black on white
        if (!(c & ~0xFF))
@@ -364,13 +365,14 @@ cga_putc(int c)
                break;
        }
 
-       // The purpose of this is to allow the screen to appear as if it is scrolling as
-       // more lines are added beyond the size of the monitor.  The top line is dropped
-       // and everything is shifted up by one.
+       // The purpose of this is to allow the screen to appear as if it is
+       // scrolling as more lines are added beyond the size of the monitor.
+       // The top line is dropped and everything is shifted up by one.
        if (crt_pos >= CRT_SIZE) {
                int i;
 
-               memcpy(crt_buf, crt_buf + CRT_COLS, (CRT_SIZE - CRT_COLS) * sizeof(uint16_t));
+               memcpy(crt_buf, crt_buf + CRT_COLS,
+                      (CRT_SIZE - CRT_COLS) * sizeof(uint16_t));
                for (i = CRT_SIZE - CRT_COLS; i < CRT_SIZE; i++)
                        crt_buf[i] = 0x0700 | ' ';
                crt_pos -= CRT_COLS;
@@ -381,7 +383,8 @@ cga_putc(int c)
 
                memcpy(scrolling_crt_buf, scrolling_crt_buf + CRT_COLS,
                       (SCROLLING_CRT_SIZE - CRT_COLS) * sizeof(uint16_t));
-               for (i = SCROLLING_CRT_SIZE - CRT_COLS; i < SCROLLING_CRT_SIZE; i++)
+               for (i = SCROLLING_CRT_SIZE - CRT_COLS; i < SCROLLING_CRT_SIZE;
+                    i++)
                        scrolling_crt_buf[i] = 0x0700 | ' ';
                scrolling_crt_pos -= CRT_COLS;
        }
@@ -399,7 +402,7 @@ cga_putc(int c)
 
 #define NO             0
 
-#define SHIFT  (1<<0)
+#define SHIFT          (1<<0)
 #define CTL            (1<<1)
 #define ALT            (1<<2)
 
@@ -502,8 +505,7 @@ static uint32_t shift;
 static bool crt_scrolled = FALSE;
 
 /* TODO: i'm concerned about the (lack of) locking when scrolling the screen. */
-static int
-kbd_proc_data(void)
+static int kbd_proc_data(void)
 {
 #ifdef CONFIG_X86_DISABLE_KEYBOARD
        /* on some machines with usb keyboards, any keyboard input triggers SMM
@@ -667,22 +669,19 @@ void cons_putc(int c)
 
 // `High'-level console I/O.  Used by readline and cprintf.
 
-void
-cputchar(int c)
+void cputchar(int c)
 {
        cons_putc(c);
 }
 
-void
-cputbuf(const char*buf, int len)
+void cputbuf(const char*buf, int len)
 {
        int i;
        for(i = 0; i < len; i++)
                cons_putc(buf[i]);
 }
 
-int
-getchar(void)
+int getchar(void)
 {
        int c;
 
@@ -691,8 +690,7 @@ getchar(void)
        return c;
 }
 
-int
-iscons(int fdnum)
+int iscons(int fdnum)
 {
        // used by readline
        return 1;
index 54d7615..e2660f8 100644 (file)
 
 /* Types of console devices */
 #define CONS_KB_DEV            1
-#define CONS_SER_DEV   2
+#define CONS_SER_DEV           2
 
 struct cons_dev;
 /* Interrupt-driven console input devices */
 struct cons_dev {
        SLIST_ENTRY(cons_dev)           next;
-       int                                                     type;           /* e.g., CONS_KB_DEV */
-       int                                                     val;            /* e.g., COM1 */
-       int                                                     irq;            /* desired irq */
-       char                                            *model;         /* descriptive string */
+       int                             type;   /* e.g., CONS_KB_DEV */
+       int                             val;    /* e.g., COM1 */
+       int                             irq;    /* desired irq */
+       char                            *model; /* descriptive string */
        int (*getc)(struct cons_dev *, uint8_t *);
 };
 SLIST_HEAD(cons_dev_slist, cons_dev);
index 0e16f75..1594252 100644 (file)
@@ -50,8 +50,8 @@ void print_cpuinfo(void)
                cpu_set_feat(CPU_FEAT_X86_VENDOR_AMD);
 
 
-       /* intel supports a way to hide the upper leaves of cpuid, beyond 3.  the
-        * bios might have done this, so we'll make sure it is off. */
+       /* intel supports a way to hide the upper leaves of cpuid, beyond 3.
+        * the bios might have done this, so we'll make sure it is off. */
        if (cpu_has_feat(CPU_FEAT_X86_VENDOR_INTEL)) {
                msr_val = read_msr(IA32_MISC_ENABLE);
                if (msr_val & (1 << 22))
@@ -218,19 +218,21 @@ void show_mapping(pgdir_t pgdir, uintptr_t start, size_t size)
 
        printk("   %sVirtual    %sPhysical  Ps Dr Ac G CD WT U W P EPTE\n",
               BIT_SPACING, BIT_SPACING);
-       printk("-------------------------------------------------%s\n", BIT_DASHES);
+       printk("-------------------------------------------------%s\n",
+              BIT_DASHES);
        for(i = 0; i < size; i += PGSIZE, start += PGSIZE) {
                pte = pgdir_walk(pgdir, (void*)start, 0);
                printk("%p  ", start);
                if (pte_walk_okay(pte)) {
-                       /* A note on PTE perms.  If you look at just the PTE, you don't get
-                        * the full picture for W and U.  Those are the intersection of all
-                        * bits.  In Akaros, we do U or not at the earliest point (PML4
-                        * entries).  All other PTEs have U set.  For W, it's the opposite.
-                        * The PTE for the actual page has W or not, and all others has W
-                        * set.  W needs to be more fine-grained, but U doesn't.  Plus the
-                        * UVPT mapping requires the U to see interior pages (but have W
-                        * off). */
+                       /* A note on PTE perms.  If you look at just the PTE,
+                        * you don't get the full picture for W and U.  Those
+                        * are the intersection of all bits.  In Akaros, we do U
+                        * or not at the earliest point (PML4 entries).  All
+                        * other PTEs have U set.  For W, it's the opposite.
+                        * The PTE for the actual page has W or not, and all
+                        * others has W set.  W needs to be more fine-grained,
+                        * but U doesn't.  Plus the UVPT mapping requires the U
+                        * to see interior pages (but have W off). */
                        perm = get_va_perms(pgdir, (void*)start);
                        printk("%p  %1d  %1d  %1d  %1d %1d  %1d  %1d %1d %1d 0x%llx\n",
                               pte_get_paddr(pte),
index a70c96f..a40c622 100644 (file)
@@ -51,8 +51,8 @@ static struct {
        spinlock_t lock;
        struct io_map *map;
        struct io_map *free;
-       struct io_map maps[32];                         // some initial free maps
-       qlock_t ql;                                     // lock for reading map
+       struct io_map maps[32];         // some initial free maps
+       qlock_t ql;                     // lock for reading map
 } iomap;
 
 enum {
@@ -99,13 +99,14 @@ static struct address_range msr_rd_wlist[] = {
 };
 static struct address_range msr_wr_wlist[] = {
        ADDRESS_RANGE(MSR_IA32_PERFCTR0,
-                                 MSR_IA32_PERFCTR0 + MSR_MAX_VAR_COUNTERS - 1),
+                     MSR_IA32_PERFCTR0 + MSR_MAX_VAR_COUNTERS - 1),
        ADDRESS_RANGE(MSR_ARCH_PERFMON_EVENTSEL0,
-                                 MSR_ARCH_PERFMON_EVENTSEL0 + MSR_MAX_VAR_COUNTERS - 1),
+                     MSR_ARCH_PERFMON_EVENTSEL0 + MSR_MAX_VAR_COUNTERS - 1),
        ADDRESS_RANGE(MSR_IA32_PERF_CTL, MSR_IA32_PERF_CTL),
        ADDRESS_RANGE(MSR_CORE_PERF_FIXED_CTR0,
-                                 MSR_CORE_PERF_FIXED_CTR0 + MSR_MAX_FIX_COUNTERS - 1),
-       ADDRESS_RANGE(MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL),
+                     MSR_CORE_PERF_FIXED_CTR0 + MSR_MAX_FIX_COUNTERS - 1),
+       ADDRESS_RANGE(MSR_CORE_PERF_FIXED_CTR_CTRL,
+                     MSR_CORE_PERF_GLOBAL_OVF_CTRL),
        ADDRESS_RANGE(MSR_IA32_MPERF, MSR_IA32_APERF),
 };
 int gdbactive = 0;
@@ -150,7 +151,8 @@ int ioalloc(int port, int size, int align, char *tag)
                        map = *l;
                        if (map->end <= port)
                                continue;
-                       if (map->reserved && map->start == port && map->end == port + size) {
+                       if (map->reserved && map->start == port &&
+                           map->end == port + size) {
                                map->reserved = 0;
                                spin_unlock(&(&iomap)->lock);
                                return map->start;
@@ -393,73 +395,73 @@ static long arch_perf_write(struct perf_context *pc, const void *udata,
        ktop = kptr + usize;
        error_assert(EBADMSG, (kptr + 1) <= ktop);
        switch (*kptr++) {
-               case PERFMON_CMD_COUNTER_OPEN: {
-                       int ped;
-                       struct perfmon_event pev;
-                       struct core_set cset;
-
-                       error_assert(EBADMSG, (kptr + 3 * sizeof(uint64_t)) <= ktop);
-                       perfmon_init_event(&pev);
-                       kptr = get_le_u64(kptr, &pev.event);
-                       kptr = get_le_u64(kptr, &pev.flags);
-                       kptr = get_le_u64(kptr, &pev.trigger_count);
-                       kptr = get_le_u64(kptr, &pev.user_data);
-                       kptr = arch_read_core_set(&cset, kptr, ktop);
-
-                       ped = perfmon_open_event(&cset, pc->ps, &pev);
-
-                       pc->resp_size = sizeof(uint32_t);
-                       pc->resp = kmalloc(pc->resp_size, MEM_WAIT);
-                       put_le_u32(pc->resp, (uint32_t) ped);
-                       break;
-               }
-               case PERFMON_CMD_COUNTER_STATUS: {
-                       uint32_t ped;
-                       uint8_t *rptr;
-                       struct perfmon_status *pef;
-
-                       error_assert(EBADMSG, (kptr + sizeof(uint32_t)) <= ktop);
-                       kptr = get_le_u32(kptr, &ped);
-
-                       pef = perfmon_get_event_status(pc->ps, (int) ped);
-
-                       pc->resp_size = sizeof(uint32_t) + num_cores * sizeof(uint64_t);
-                       pc->resp = kmalloc(pc->resp_size, MEM_WAIT);
-                       rptr = put_le_u32(pc->resp, num_cores);
-                       for (int i = 0; i < num_cores; i++)
-                               rptr = put_le_u64(rptr, pef->cores_values[i]);
+       case PERFMON_CMD_COUNTER_OPEN: {
+               int ped;
+               struct perfmon_event pev;
+               struct core_set cset;
+
+               error_assert(EBADMSG, (kptr + 3 * sizeof(uint64_t)) <= ktop);
+               perfmon_init_event(&pev);
+               kptr = get_le_u64(kptr, &pev.event);
+               kptr = get_le_u64(kptr, &pev.flags);
+               kptr = get_le_u64(kptr, &pev.trigger_count);
+               kptr = get_le_u64(kptr, &pev.user_data);
+               kptr = arch_read_core_set(&cset, kptr, ktop);
+
+               ped = perfmon_open_event(&cset, pc->ps, &pev);
+
+               pc->resp_size = sizeof(uint32_t);
+               pc->resp = kmalloc(pc->resp_size, MEM_WAIT);
+               put_le_u32(pc->resp, (uint32_t) ped);
+               break;
+       }
+       case PERFMON_CMD_COUNTER_STATUS: {
+               uint32_t ped;
+               uint8_t *rptr;
+               struct perfmon_status *pef;
 
-                       perfmon_free_event_status(pef);
-                       break;
-               }
-               case PERFMON_CMD_COUNTER_CLOSE: {
-                       uint32_t ped;
+               error_assert(EBADMSG, (kptr + sizeof(uint32_t)) <= ktop);
+               kptr = get_le_u32(kptr, &ped);
 
-                       error_assert(EBADMSG, (kptr + sizeof(uint32_t)) <= ktop);
-                       kptr = get_le_u32(kptr, &ped);
+               pef = perfmon_get_event_status(pc->ps, (int) ped);
 
-                       perfmon_close_event(pc->ps, (int) ped);
-                       break;
-               }
-               case PERFMON_CMD_CPU_CAPS: {
-                       uint8_t *rptr;
-                       struct perfmon_cpu_caps pcc;
+               pc->resp_size = sizeof(uint32_t) + num_cores * sizeof(uint64_t);
+               pc->resp = kmalloc(pc->resp_size, MEM_WAIT);
+               rptr = put_le_u32(pc->resp, num_cores);
+               for (int i = 0; i < num_cores; i++)
+                       rptr = put_le_u64(rptr, pef->cores_values[i]);
 
-                       perfmon_get_cpu_caps(&pcc);
+               perfmon_free_event_status(pef);
+               break;
+       }
+       case PERFMON_CMD_COUNTER_CLOSE: {
+               uint32_t ped;
 
-                       pc->resp_size = 6 * sizeof(uint32_t);
-                       pc->resp = kmalloc(pc->resp_size, MEM_WAIT);
+               error_assert(EBADMSG, (kptr + sizeof(uint32_t)) <= ktop);
+               kptr = get_le_u32(kptr, &ped);
 
-                       rptr = put_le_u32(pc->resp, pcc.perfmon_version);
-                       rptr = put_le_u32(rptr, pcc.proc_arch_events);
-                       rptr = put_le_u32(rptr, pcc.bits_x_counter);
-                       rptr = put_le_u32(rptr, pcc.counters_x_proc);
-                       rptr = put_le_u32(rptr, pcc.bits_x_fix_counter);
-                       rptr = put_le_u32(rptr, pcc.fix_counters_x_proc);
-                       break;
-               }
-               default:
-                       error(EINVAL, "Invalid perfmon command: 0x%x", kptr[-1]);
+               perfmon_close_event(pc->ps, (int) ped);
+               break;
+       }
+       case PERFMON_CMD_CPU_CAPS: {
+               uint8_t *rptr;
+               struct perfmon_cpu_caps pcc;
+
+               perfmon_get_cpu_caps(&pcc);
+
+               pc->resp_size = 6 * sizeof(uint32_t);
+               pc->resp = kmalloc(pc->resp_size, MEM_WAIT);
+
+               rptr = put_le_u32(pc->resp, pcc.perfmon_version);
+               rptr = put_le_u32(rptr, pcc.proc_arch_events);
+               rptr = put_le_u32(rptr, pcc.bits_x_counter);
+               rptr = put_le_u32(rptr, pcc.counters_x_proc);
+               rptr = put_le_u32(rptr, pcc.bits_x_fix_counter);
+               rptr = put_le_u32(rptr, pcc.fix_counters_x_proc);
+               break;
+       }
+       default:
+               error(EINVAL, "Invalid perfmon command: 0x%x", kptr[-1]);
        }
        poperror();
        qunlock(&pc->resp_lock);
@@ -472,12 +474,12 @@ static struct chan *archopen(struct chan *c, int omode)
 {
        c = devopen(c, omode, archdir, Qmax, devgen);
        switch ((uint32_t) c->qid.path) {
-               case Qperf:
-                       if (!perfmon_supported())
-                               error(ENODEV, "perf is not supported");
-                       assert(!c->aux);
-                       c->aux = arch_create_perf_context();
-                       break;
+       case Qperf:
+               if (!perfmon_supported())
+                       error(ENODEV, "perf is not supported");
+               assert(!c->aux);
+               c->aux = arch_create_perf_context();
+               break;
        }
 
        return c;
@@ -486,12 +488,12 @@ static struct chan *archopen(struct chan *c, int omode)
 static void archclose(struct chan *c)
 {
        switch ((uint32_t) c->qid.path) {
-               case Qperf:
-                       if (c->aux) {
-                               arch_free_perf_context((struct perf_context *) c->aux);
-                               c->aux = NULL;
-                       }
-                       break;
+       case Qperf:
+               if (c->aux) {
+                       arch_free_perf_context((struct perf_context *) c->aux);
+                       c->aux = NULL;
+               }
+               break;
        }
 }
 
@@ -508,96 +510,99 @@ static size_t archread(struct chan *c, void *a, size_t n, off64_t offset)
        struct msr_value msrv;
 
        switch ((uint32_t) c->qid.path) {
-               case Qdir:
-                       return devdirread(c, a, n, archdir, Qmax, devgen);
-               case Qgdb:
-                       p = gdbactive ? "1" : "0";
-                       return readstr(offset, a, n, p);
-               case Qiob:
-                       port = offset;
-                       checkport(offset, offset + n);
-                       for (p = a; port < offset + n; port++)
-                               *p++ = inb(port);
-                       return n;
-               case Qiow:
-                       if (n & 1)
-                               error(EINVAL, ERROR_FIXME);
-                       checkport(offset, offset + n);
-                       sp = a;
-                       for (port = offset; port < offset + n; port += 2)
-                               *sp++ = inw(port);
-                       return n;
-               case Qiol:
-                       if (n & 3)
-                               error(EINVAL, ERROR_FIXME);
-                       checkport(offset, offset + n);
-                       lp = a;
-                       for (port = offset; port < offset + n; port += 4)
-                               *lp++ = inl(port);
-                       return n;
-               case Qioalloc:
-                       break;
-               case Qrealmem:
-                       return readmem(offset, a, n, KADDR(0), REAL_MEM_SIZE);
-               case Qmsr:
-                       if (!address_range_find(msr_rd_wlist, ARRAY_SIZE(msr_rd_wlist),
-                                               (uintptr_t) offset))
-                               error(EPERM, "MSR 0x%x not in read whitelist", offset);
-                       core_set_init(&cset);
-                       core_set_fill_available(&cset);
-                       msr_set_address(&msra, (uint32_t) offset);
-                       values = kzmalloc(num_cores * sizeof(uint64_t),
-                                         MEM_WAIT);
-                       if (!values)
-                               error(ENOMEM, ERROR_FIXME);
-                       msr_set_values(&msrv, values, num_cores);
-
-                       err = msr_cores_read(&cset, &msra, &msrv);
-
-                       if (likely(!err)) {
-                               if (n >= num_cores * sizeof(uint64_t)) {
-                                       if (!memcpy_to_user_errno(current, a, values,
-                                                                 num_cores * sizeof(uint64_t)))
-                                               n = num_cores * sizeof(uint64_t);
-                                       else
-                                               n = -1;
-                               } else {
-                                       kfree(values);
-                                       error(ERANGE, "Not enough space for MSR read");
-                               }
-                       } else {
-                               switch (-err) {
-                               case (EFAULT):
-                                       error(-err, "read_msr() faulted on MSR 0x%x", offset);
-                               case (ERANGE):
-                                       error(-err, "Not enough space for MSR read");
-                               };
-                               error(-err, "MSR read failed");
-                       }
-                       kfree(values);
-                       return n;
-               case Qperf: {
-                       struct perf_context *pc = (struct perf_context *) c->aux;
-
-                       assert(pc);
-                       qlock(&pc->resp_lock);
-                       if (pc->resp && ((size_t) offset < pc->resp_size)) {
-                               n = MIN(n, (long) pc->resp_size - (long) offset);
-                               if (memcpy_to_user_errno(current, a, pc->resp + offset, n))
+       case Qdir:
+               return devdirread(c, a, n, archdir, Qmax, devgen);
+       case Qgdb:
+               p = gdbactive ? "1" : "0";
+               return readstr(offset, a, n, p);
+       case Qiob:
+               port = offset;
+               checkport(offset, offset + n);
+               for (p = a; port < offset + n; port++)
+                       *p++ = inb(port);
+               return n;
+       case Qiow:
+               if (n & 1)
+                       error(EINVAL, ERROR_FIXME);
+               checkport(offset, offset + n);
+               sp = a;
+               for (port = offset; port < offset + n; port += 2)
+                       *sp++ = inw(port);
+               return n;
+       case Qiol:
+               if (n & 3)
+                       error(EINVAL, ERROR_FIXME);
+               checkport(offset, offset + n);
+               lp = a;
+               for (port = offset; port < offset + n; port += 4)
+                       *lp++ = inl(port);
+               return n;
+       case Qioalloc:
+               break;
+       case Qrealmem:
+               return readmem(offset, a, n, KADDR(0), REAL_MEM_SIZE);
+       case Qmsr:
+               if (!address_range_find(msr_rd_wlist, ARRAY_SIZE(msr_rd_wlist),
+                                       (uintptr_t) offset))
+                       error(EPERM, "MSR 0x%x not in read whitelist", offset);
+               core_set_init(&cset);
+               core_set_fill_available(&cset);
+               msr_set_address(&msra, (uint32_t) offset);
+               values = kzmalloc(num_cores * sizeof(uint64_t),
+                                 MEM_WAIT);
+               if (!values)
+                       error(ENOMEM, ERROR_FIXME);
+               msr_set_values(&msrv, values, num_cores);
+
+               err = msr_cores_read(&cset, &msra, &msrv);
+
+               if (likely(!err)) {
+                       if (n >= num_cores * sizeof(uint64_t)) {
+                               if (!memcpy_to_user_errno(current, a, values,
+                                                         num_cores *
+                                                         sizeof(uint64_t)))
+                                       n = num_cores * sizeof(uint64_t);
+                               else
                                        n = -1;
                        } else {
-                               n = 0;
+                               kfree(values);
+                               error(ERANGE, "Not enough space for MSR read");
                        }
-                       qunlock(&pc->resp_lock);
-
-                       return n;
-               case Qcstate:
-                       return readnum_hex(offset, a, n, get_cstate(), NUMSIZE32);
-               case Qpstate:
-                       return readnum_hex(offset, a, n, get_pstate(), NUMSIZE32);
+               } else {
+                       switch (-err) {
+                       case (EFAULT):
+                               error(-err, "read_msr() faulted on MSR 0x%x",
+                                     offset);
+                       case (ERANGE):
+                               error(-err, "Not enough space for MSR read");
+                       };
+                       error(-err, "MSR read failed");
                }
-               default:
-                       error(EINVAL, ERROR_FIXME);
+               kfree(values);
+               return n;
+       case Qperf: {
+               struct perf_context *pc = (struct perf_context *) c->aux;
+
+               assert(pc);
+               qlock(&pc->resp_lock);
+               if (pc->resp && ((size_t) offset < pc->resp_size)) {
+                       n = MIN(n, (long) pc->resp_size - (long) offset);
+                       if (memcpy_to_user_errno(current, a, pc->resp + offset,
+                                                n))
+                               n = -1;
+               } else {
+                       n = 0;
+               }
+               qunlock(&pc->resp_lock);
+
+               return n;
+       case Qcstate:
+               return readnum_hex(offset, a, n, get_cstate(), NUMSIZE32);
+       case Qpstate:
+               return readnum_hex(offset, a, n, get_pstate(), NUMSIZE32);
+       }
+       default:
+               error(EINVAL, ERROR_FIXME);
        }
 
        if ((buf = kzmalloc(n, 0)) == NULL)
@@ -607,18 +612,19 @@ static size_t archread(struct chan *c, void *a, size_t n, off64_t offset)
        offset = offset / Linelen;
 
        switch ((uint32_t) c->qid.path) {
-               case Qioalloc:
-                       spin_lock(&(&iomap)->lock);
-                       for (map = iomap.map; n > 0 && map != NULL; map = map->next) {
-                               if (offset-- > 0)
-                                       continue;
-                               snprintf(p, n * Linelen, "%#8p %#8p %-12.12s\n", map->start,
-                                        map->end - 1, map->tag);
-                               p += Linelen;
-                               n--;
-                       }
-                       spin_unlock(&(&iomap)->lock);
-                       break;
+       case Qioalloc:
+               spin_lock(&(&iomap)->lock);
+               for (map = iomap.map; n > 0 && map != NULL; map = map->next) {
+                       if (offset-- > 0)
+                               continue;
+                       snprintf(p, n * Linelen, "%#8p %#8p %-12.12s\n",
+                                map->start,
+                                map->end - 1, map->tag);
+                       p += Linelen;
+                       n--;
+               }
+               spin_unlock(&(&iomap)->lock);
+               break;
        }
 
        n = p - buf;
@@ -666,77 +672,78 @@ static size_t archwrite(struct chan *c, void *a, size_t n, off64_t offset)
        struct msr_value msrv;
 
        switch ((uint32_t) c->qid.path) {
-               case Qgdb:
-                       p = a;
-                       if (n != 1)
-                               error(EINVAL, "Gdb: Write one byte, '1' or '0'");
-                       if (*p == '1')
-                               gdbactive = 1;
-                       else if (*p == '0')
-                               gdbactive = 0;
-                       else
-                               error(EINVAL, "Gdb: must be 1 or 0");
-                       return 1;
-               case Qiob:
-                       p = a;
-                       checkport(offset, offset + n);
-                       for (port = offset; port < offset + n; port++)
-                               outb(port, *p++);
-                       return n;
-               case Qiow:
-                       if (n & 1)
-                               error(EINVAL, ERROR_FIXME);
-                       checkport(offset, offset + n);
-                       sp = a;
-                       for (port = offset; port < offset + n; port += 2)
-                               outw(port, *sp++);
-                       return n;
-               case Qiol:
-                       if (n & 3)
-                               error(EINVAL, ERROR_FIXME);
-                       checkport(offset, offset + n);
-                       lp = a;
-                       for (port = offset; port < offset + n; port += 4)
-                               outl(port, *lp++);
-                       return n;
-               case Qmsr:
-                       if (!address_range_find(msr_wr_wlist, ARRAY_SIZE(msr_wr_wlist),
-                                               (uintptr_t) offset))
-                               error(EPERM, "MSR 0x%x not in write whitelist", offset);
-                       if (n != sizeof(uint64_t))
-                               error(EINVAL, "Tried to write more than a u64 (%p)", n);
-                       if (memcpy_from_user_errno(current, &value, a, sizeof(value)))
-                               return -1;
-
-                       core_set_init(&cset);
-                       core_set_fill_available(&cset);
-                       msr_set_address(&msra, (uint32_t) offset);
-                       msr_set_value(&msrv, value);
-
-                       err = msr_cores_write(&cset, &msra, &msrv);
-                       if (unlikely(err)) {
-                               switch (-err) {
-                               case (EFAULT):
-                                       error(-err, "write_msr() faulted on MSR 0x%x", offset);
-                               case (ERANGE):
-                                       error(-err, "Not enough space for MSR write");
-                               };
-                               error(-err, "MSR write failed");
-                       }
-                       return sizeof(uint64_t);
-               case Qperf: {
-                       struct perf_context *pc = (struct perf_context *) c->aux;
-
-                       assert(pc);
+       case Qgdb:
+               p = a;
+               if (n != 1)
+                       error(EINVAL, "Gdb: Write one byte, '1' or '0'");
+               if (*p == '1')
+                       gdbactive = 1;
+               else if (*p == '0')
+                       gdbactive = 0;
+               else
+                       error(EINVAL, "Gdb: must be 1 or 0");
+               return 1;
+       case Qiob:
+               p = a;
+               checkport(offset, offset + n);
+               for (port = offset; port < offset + n; port++)
+                       outb(port, *p++);
+               return n;
+       case Qiow:
+               if (n & 1)
+                       error(EINVAL, ERROR_FIXME);
+               checkport(offset, offset + n);
+               sp = a;
+               for (port = offset; port < offset + n; port += 2)
+                       outw(port, *sp++);
+               return n;
+       case Qiol:
+               if (n & 3)
+                       error(EINVAL, ERROR_FIXME);
+               checkport(offset, offset + n);
+               lp = a;
+               for (port = offset; port < offset + n; port += 4)
+                       outl(port, *lp++);
+               return n;
+       case Qmsr:
+               if (!address_range_find(msr_wr_wlist, ARRAY_SIZE(msr_wr_wlist),
+                                       (uintptr_t) offset))
+                       error(EPERM, "MSR 0x%x not in write whitelist", offset);
+               if (n != sizeof(uint64_t))
+                       error(EINVAL, "Tried to write more than a u64 (%p)", n);
+               if (memcpy_from_user_errno(current, &value, a, sizeof(value)))
+                       return -1;
 
-                       return arch_perf_write(pc, a, n);
+               core_set_init(&cset);
+               core_set_fill_available(&cset);
+               msr_set_address(&msra, (uint32_t) offset);
+               msr_set_value(&msrv, value);
+
+               err = msr_cores_write(&cset, &msra, &msrv);
+               if (unlikely(err)) {
+                       switch (-err) {
+                       case (EFAULT):
+                               error(-err, "write_msr() faulted on MSR 0x%x",
+                                     offset);
+                       case (ERANGE):
+                               error(-err, "Not enough space for MSR write");
+                       };
+                       error(-err, "MSR write failed");
                }
-               case Qcstate:
-                       return cstate_write(a, n, 0);
-               case Qpstate:
-                       return pstate_write(a, n, 0);
-               default:
-                       error(EINVAL, ERROR_FIXME);
+               return sizeof(uint64_t);
+       case Qperf: {
+               struct perf_context *pc = (struct perf_context *) c->aux;
+
+               assert(pc);
+
+               return arch_perf_write(pc, a, n);
+       }
+       case Qcstate:
+               return cstate_write(a, n, 0);
+       case Qpstate:
+               return pstate_write(a, n, 0);
+       default:
+               error(EINVAL, ERROR_FIXME);
        }
        return 0;
 }
index 202016d..101de50 100644 (file)
@@ -12,10 +12,12 @@ static unsigned int x86_cstate;
 void cpu_halt(void)
 {
        if (cpu_has_feat(CPU_FEAT_X86_MWAIT)) {
-               /* TODO: since we're monitoring anyway, x86 could use monitor/mwait for
-                * KMSGs, instead of relying on IPIs.  (Maybe only for ROUTINE). */
+               /* TODO: since we're monitoring anyway, x86 could use
+                * monitor/mwait for KMSGs, instead of relying on IPIs.  (Maybe
+                * only for ROUTINE). */
                asm volatile("monitor" : : "a"(KERNBASE), "c"(0), "d"(0));
-               asm volatile("sti; mwait" : : "c"(0x0), "a"(x86_cstate) : "memory");
+               asm volatile("sti; mwait" : : "c"(0x0), "a"(x86_cstate)
+                            : "memory");
        } else {
                asm volatile("sti; hlt" : : : "memory");
        }
@@ -28,13 +30,15 @@ void cpu_halt(void)
 void cpu_halt_notif_pending(struct preempt_data *vcpd)
 {
        if (cpu_has_feat(CPU_FEAT_X86_MWAIT))
-               asm volatile("monitor" : : "a"(&vcpd->notif_pending), "c"(0), "d"(0));
+               asm volatile("monitor" :
+                            : "a"(&vcpd->notif_pending), "c"(0), "d"(0));
        if (vcpd->notif_pending)
                return;
-       /* Note we don't use the ecx=1 setting - we actually want to sti so that we
-        * handle the IRQ and not just wake from it. */
+       /* Note we don't use the ecx=1 setting - we actually want to sti so that
+        * we handle the IRQ and not just wake from it. */
        if (cpu_has_feat(CPU_FEAT_X86_MWAIT))
-               asm volatile("sti; mwait" : : "c"(0x0), "a"(x86_cstate) : "memory");
+               asm volatile("sti; mwait" :
+                            : "c"(0x0), "a"(x86_cstate) : "memory");
        else
                asm volatile("sti; hlt" : : : "memory");
        disable_irq();
@@ -44,9 +48,9 @@ void set_pstate(unsigned int pstate)
 {
        uint64_t perf_ctl;
 
-       /* This MSR was introduced in 0f_03 (family/model), so checking cpuid should
-        * suffice.  Though my Qemu says it is a later generation and still fails to
-        * support it (patches pending, I hear). */
+       /* This MSR was introduced in 0f_03 (family/model), so checking cpuid
+        * should suffice.  Though my Qemu says it is a later generation and
+        * still fails to support it (patches pending, I hear). */
        if (read_msr_safe(MSR_IA32_PERF_CTL, &perf_ctl))
                return;
        /* The p-state ratio is actually at 15:8, AFAIK, for both PERF_CTL and
@@ -65,7 +69,8 @@ void set_fastest_pstate(void)
         * lieu of a full per-model driver, we can just take a peak. */
        if (read_msr_safe(MSR_TURBO_RATIO_LIMIT, &turbo_ratio_limit))
                return;
-       /* The lowest byte is the max turbo ratio achievable by one active core. */
+       /* The lowest byte is the max turbo ratio achievable by one active core.
+        */
        set_pstate(turbo_ratio_limit & 0xff);
 }
 
@@ -91,8 +96,8 @@ unsigned int get_actual_pstate(void)
 
 void set_cstate(unsigned int cstate)
 {
-       /* No real need to lock for an assignment.  Any core can set this, and other
-        * cores will notice the next time they halt. */
+       /* No real need to lock for an assignment.  Any core can set this, and
+        * other cores will notice the next time they halt. */
        x86_cstate = cstate;
 }
 
index 5cf6076..965b15f 100644 (file)
@@ -29,25 +29,28 @@ static void irq_console(struct hw_trapframe *hw_tf, void *data)
                return;
        /* Control code intercepts */
        switch (c) {
-               case capchar2ctl('G'):
-                       /* traditional 'ctrl-g', will put you in the monitor gracefully */
-                       send_kernel_message(core_id(), __run_mon, 0, 0, 0, KMSG_ROUTINE);
-                       return;
-               case capchar2ctl('Q'):
-                       /* force you into the monitor.  you might deadlock. */
-                       printk("\nForcing entry to the monitor\n");
-                       monitor(hw_tf);
-                       return;
-               case capchar2ctl('B'):
-                       /* backtrace / debugging for the core receiving the irq */
-                       printk("\nForced trapframe and backtrace for core %d\n", core_id());
-                       if (!hw_tf) {
-                               printk("(no hw_tf, we probably polled the console)\n");
-                               return;
-                       }
-                       print_trapframe(hw_tf);
-                       backtrace_hwtf(hw_tf);
+       case capchar2ctl('G'):
+               /* traditional 'ctrl-g', will put you in the monitor gracefully
+                */
+               send_kernel_message(core_id(), __run_mon, 0, 0, 0,
+                                   KMSG_ROUTINE);
+               return;
+       case capchar2ctl('Q'):
+               /* force you into the monitor.  you might deadlock. */
+               printk("\nForcing entry to the monitor\n");
+               monitor(hw_tf);
+               return;
+       case capchar2ctl('B'):
+               /* backtrace / debugging for the core receiving the irq */
+               printk("\nForced trapframe and backtrace for core %d\n",
+                      core_id());
+               if (!hw_tf) {
+                       printk("(no hw_tf, we probably polled the console)\n");
                        return;
+               }
+               print_trapframe(hw_tf);
+               backtrace_hwtf(hw_tf);
+               return;
        }
        cons_add_char(c);
 }
@@ -74,7 +77,8 @@ static void cons_irq_init(void)
 void ancillary_state_init(void)
 {
        uint32_t eax, ebx, ecx, edx;
-       uint64_t proc_supported_features; /* proc supported user state components */
+       /* proc supported user state components */
+       uint64_t proc_supported_features;
 
        // If you don't at least have FXSAVE and FXRSTOR
        // (includes OSFXSR), you don't boot.
@@ -83,7 +87,8 @@ void ancillary_state_init(void)
 
        if (cpu_has_feat(CPU_FEAT_X86_XSAVE)) {
                // Next determine the user state components supported
-               // by the processor and set x86_default_xcr0 in proc_global_info.
+               // by the processor and set x86_default_xcr0 in
+               // proc_global_info.
                cpuid(0x0d, 0x00, &eax, 0, 0, &edx);
                proc_supported_features = ((uint64_t)edx << 32) | eax;
 
@@ -93,25 +98,27 @@ void ancillary_state_init(void)
                                                      proc_supported_features;
 
                /*
-                * Make sure CR4.OSXSAVE is set and set the local xcr0 to the default.
-                * We will do both of these things again during per-cpu init,
-                * but we are about to use XSAVE to build our default extended state
-                * record, so we need them enabled.
-                * You must set CR4_OSXSAVE before setting xcr0, or a #UD fault occurs.
+                * Make sure CR4.OSXSAVE is set and set the local xcr0 to the
+                * default.  We will do both of these things again during
+                * per-cpu init, but we are about to use XSAVE to build our
+                * default extended state record, so we need them enabled.  You
+                * must set CR4_OSXSAVE before setting xcr0, or a #UD fault
+                * occurs.
                 */
                lcr4(rcr4() | CR4_OSXSAVE);
                lxcr0(__proc_global_info.x86_default_xcr0);
 
-               /* Build a default set of extended state values that we can later use
-                * to initialize extended state on other cores, or restore on this
-                * core.  FNINIT won't actually do it - if you xsave after fninit, x87
-                * will show up as active in xstate_bv[0].  Instead, we just need
-                * the xstate_bv bits zeroed (and memset the rest for sanity's sake).
+               /* Build a default set of extended state values that we can
+                * later use to initialize extended state on other cores, or
+                * restore on this core.  FNINIT won't actually do it - if you
+                * xsave after fninit, x87 will show up as active in
+                * xstate_bv[0].  Instead, we just need the xstate_bv bits
+                * zeroed (and memset the rest for sanity's sake).
                 */
                memset(&x86_default_fpu, 0x00, sizeof(struct ancillary_state));
 
-               /* We must set the MXCSR field in the default state struct to its
-                * power-on value of 0x1f80. This masks all SIMD floating
+               /* We must set the MXCSR field in the default state struct to
+                * its power-on value of 0x1f80. This masks all SIMD floating
                 * point exceptions and clears all SIMD floating-point exception
                 * flags, sets rounding control to round-nearest, disables
                 * flush-to-zero mode, and disables denormals-are-zero mode.
@@ -132,13 +139,14 @@ void ancillary_state_init(void)
                __proc_global_info.x86_default_xcr0 = 0x0;
 
                /*
-                * Build a default set of extended state values that we can later use to
-                * initialize extended state on other cores, or restore on this core.
-                * We need to use FNINIT to reset the FPU before saving, in case boot
-                * agents used the FPU or it is dirty for some reason. An old comment
-                * that used to be here said "had this happen on c89, which had a full
-                * FP stack after booting." Note that FNINIT does not clear the data
-                * registers, but it tags them all as empty (0b11).
+                * Build a default set of extended state values that we can
+                * later use to initialize extended state on other cores, or
+                * restore on this core.  We need to use FNINIT to reset the FPU
+                * before saving, in case boot agents used the FPU or it is
+                * dirty for some reason. An old comment that used to be here
+                * said "had this happen on c89, which had a full FP stack after
+                * booting." Note that FNINIT does not clear the data registers,
+                * but it tags them all as empty (0b11).
                 */
 
                // Zero the default extended state memory region before saving.
@@ -146,12 +154,14 @@ void ancillary_state_init(void)
                memset(&x86_default_fpu, 0x00, sizeof(struct ancillary_state));
 
                /*
-                * FNINIT clears FIP and FDP and, even though it is technically a
-                * control instruction, it clears FOP while initializing the FPU.
+                * FNINIT clears FIP and FDP and, even though it is technically
+                * a control instruction, it clears FOP while initializing the
+                * FPU.
                 *
-                * This marks the STX/MMX registers as empty in the FPU tag word,
-                * but does not actually clear the values in the registers,
-                * so we manually clear them in the xsave area after saving.
+                * This marks the STX/MMX registers as empty in the FPU tag
+                * word, but does not actually clear the values in the
+                * registers, so we manually clear them in the xsave area after
+                * saving.
                 */
                asm volatile ("fninit");
 
@@ -159,7 +169,8 @@ void ancillary_state_init(void)
                asm volatile("fxsave64 %0" : : "m"(x86_default_fpu));
 
                /*
-                * Clear junk that might have been saved from the STX/MMX registers.
+                * Clear junk that might have been saved from the STX/MMX
+                * registers.
                 *
                 * FXSAVE may have also saved junk from the XMM registers,
                 * depending on how the hardware was implemented and the setting
index da6d120..6960e6a 100644 (file)
@@ -30,7 +30,8 @@ static void lpc_init_pci(struct pci_device *pcidev)
        pmbase &= ~1; /* clear bit 0 */
        uint32_t smi_ctl = inl(pmbase + 0x30);
        #if 0
-       /* halt the tco timer: this busts things, and won't work with the lock on */
+       /* halt the tco timer: this busts things, and won't work with the lock
+        * on */
        uint16_t tco1 = inw(pmbase + 0x60 + 0x08);
        if (tco1 & (1 << 12)) {
                printk("\t\tTCO_LOCK is on!\n");
@@ -44,9 +45,10 @@ static void lpc_init_pci(struct pci_device *pcidev)
        smi_ctl = inl(pmbase + 0x30);
 }
 
-void intel_lpc_init()
+void intel_lpc_init(void)
 {
        struct pci_device *i;
+
        STAILQ_FOREACH(i, &pci_devices, all_dev) {
                if ((i->dev == 0x1f) && (i->func == 0x00))
                        lpc_init_pci(i);
index b077731..43a1591 100644 (file)
@@ -53,8 +53,8 @@ enum {
 /*
  * PCI support code.
  */
-enum {                                                 /* type 0 and type 1 pre-defined header */
-       PciVID = 0x00,                          /* vendor ID */
+enum {                 /* type 0 and type 1 pre-defined header */
+       PciVID = 0x00,  /* vendor ID */
        PciDID = 0x02,  /* device ID */
        PciPCR = 0x04,  /* command */
        PciPSR = 0x06,  /* status */
@@ -78,16 +78,16 @@ enum {                                                      /* type 0 and type 1 pre-defined header */
 
 /* ccrb (base class code) values; controller types */
 enum {
-       Pcibcpci1 = 0,                          /* pci 1.0; no class codes defined */
-       Pcibcstore = 1, /* mass storage */
-       Pcibcnet = 2,   /* network */
-       Pcibcdisp = 3,  /* display */
+       Pcibcpci1 = 0,          /* pci 1.0; no class codes defined */
+       Pcibcstore = 1,         /* mass storage */
+       Pcibcnet = 2,           /* network */
+       Pcibcdisp = 3,          /* display */
        Pcibcmmedia = 4,        /* multimedia */
-       Pcibcmem = 5,   /* memory */
+       Pcibcmem = 5,           /* memory */
        Pcibcbridge = 6,        /* bridge */
-       Pcibccomm = 7,  /* simple comms (e.g., serial) */
+       Pcibccomm = 7,          /* simple comms (e.g., serial) */
        Pcibcbasesys = 8,       /* base system */
-       Pcibcinput = 9, /* input */
+       Pcibcinput = 9,         /* input */
        Pcibcdock = 0xa,        /* docking stations */
        Pcibcproc = 0xb,        /* processors */
        Pcibcserial = 0xc,      /* serial bus (e.g., USB) */
@@ -101,17 +101,17 @@ enum {
 /* ccru (sub-class code) values; common cases only */
 enum {
        /* mass storage */
-       Pciscscsi = 0,                          /* SCSI */
-       Pciscide = 1,   /* IDE (ATA) */
-       Pciscsata = 6,  /* SATA */
+       Pciscscsi = 0,          /* SCSI */
+       Pciscide = 1,           /* IDE (ATA) */
+       Pciscsata = 6,          /* SATA */
 
        /* network */
-       Pciscether = 0, /* Ethernet */
+       Pciscether = 0,         /* Ethernet */
 
        /* display */
-       Pciscvga = 0,   /* VGA */
-       Pciscxga = 1,   /* XGA */
-       Pcisc3d = 2,    /* 3D */
+       Pciscvga = 0,           /* VGA */
+       Pciscxga = 1,           /* XGA */
+       Pcisc3d = 2,            /* 3D */
 
        /* bridges */
        Pcischostpci = 0,       /* host/pci */
@@ -125,17 +125,17 @@ enum {
        Pciscusb = 3,   /* USB */
 };
 
-enum {                                                 /* type 0 pre-defined header */
-       PciCIS = 0x28,                          /* cardbus CIS pointer */
+enum {                 /* type 0 pre-defined header */
+       PciCIS = 0x28,  /* cardbus CIS pointer */
        PciSVID = 0x2C, /* subsystem vendor ID */
        PciSID = 0x2E,  /* cardbus CIS pointer */
-       PciEBAR0 = 0x30,        /* expansion ROM base address */
+       PciEBAR0 = 0x30,/* expansion ROM base address */
        PciMGNT = 0x3E, /* burst period length */
        PciMLT = 0x3F,  /* maximum latency between bursts */
 };
 
-enum {                                                 /* type 1 pre-defined header */
-       PciPBN = 0x18,                          /* primary bus number */
+enum {                 /* type 1 pre-defined header */
+       PciPBN = 0x18,  /* primary bus number */
        PciSBN = 0x19,  /* secondary bus number */
        PciUBN = 0x1A,  /* subordinate bus number */
        PciSLTR = 0x1B, /* secondary latency timer */
@@ -150,11 +150,11 @@ enum {                                                    /* type 1 pre-defined header */
        PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
        PciIUBR = 0x30, /* I/O base upper 16 bits */
        PciIULR = 0x32, /* I/O limit upper 16 bits */
-       PciEBAR1 = 0x28,        /* expansion ROM base address */
+       PciEBAR1 = 0x28,/* expansion ROM base address */
        PciBCR = 0x3E,  /* bridge control register */
 };
 
-enum {                                                 /* type 2 pre-defined header */
+enum {                         /* type 2 pre-defined header */
        PciCBExCA = 0x10,
        PciCBSPSR = 0x16,
        PciCBPBN = 0x18,        /* primary bus number */
@@ -176,7 +176,7 @@ enum {                                                      /* type 2 pre-defined header */
 
 /* capabilities */
 enum {
-       PciCapPMG = 0x01,                       /* power management */
+       PciCapPMG = 0x01,       /* power management */
        PciCapAGP = 0x02,
        PciCapVPD = 0x03,       /* vital product data */
        PciCapSID = 0x04,       /* slot id */
index c4d760c..68f83e8 100644 (file)
@@ -33,23 +33,23 @@ struct Rbus {
 struct Rdt {
        struct apic *apic;
        int intin;
-       uint32_t lo;                            /* matches the lo in the intin, incl Im */
-       uint32_t hi;                            /* matches the hi in the intin, incl routing */
+       uint32_t lo;            /* matches the lo in the intin, incl Im */
+       uint32_t hi;            /* matches the hi in the intin, incl routing */
 
-       int ref;                                        /* could map to multiple busses */
-       int enabled;                            /* times enabled */
+       int ref;                /* could map to multiple busses */
+       int enabled;            /* times enabled */
 };
 
-enum {                                                 /* IOAPIC registers */
-       Ioregsel = 0x00,                        /* indirect register address */
-       Iowin = 0x10,   /* indirect register data */
-       Ioipa = 0x08,   /* IRQ Pin Assertion */
-       Ioeoi = 0x10,   /* EOI */
+enum {                         /* IOAPIC registers */
+       Ioregsel = 0x00,        /* indirect register address */
+       Iowin = 0x10,           /* indirect register data */
+       Ioipa = 0x08,           /* IRQ Pin Assertion */
+       Ioeoi = 0x10,           /* EOI */
 
        Ioapicid = 0x00,        /* Identification */
        Ioapicver = 0x01,       /* Version */
        Ioapicarb = 0x02,       /* Arbitration */
-       Ioabcfg = 0x03, /* Boot Coniguration */
+       Ioabcfg = 0x03,         /* Boot Coniguration */
        Ioredtbl = 0x10,        /* Redirection Table */
 };
 
@@ -109,6 +109,7 @@ struct Rdt *rdtlookup(struct apic *apic, int intin)
 struct Rdt *rbus_get_rdt(int busno, int devno)
 {
        struct Rbus *rbus;
+
        for (rbus = rdtbus[busno]; rbus != NULL; rbus = rbus->next) {
                if (rbus->devno == devno)
                        return rbus->rdt;
@@ -150,10 +151,11 @@ void ioapicintrinit(int busno, int ioapicno, int intin, int devno, int lo)
                rdt->lo = lo;
                rdt->hi = 0;
        } else {
-               /* Polarity/trigger check.  Stored lo also has the vector in 0xff */
+               /* Polarity/trigger check.  Stored lo also has the vector in
+                * 0xff */
                if (lo != (rdt->lo & ~0xff)) {
-                       printk("multiple irq botch bus %d %d/%d/%d lo %d vs %d\n",
-                                  busno, ioapicno, intin, devno, lo, rdt->lo);
+                       printk("multi-irq botch bus %d %d/%d/%d lo %d vs %d\n",
+                              busno, ioapicno, intin, devno, lo, rdt->lo);
                        return;
                }
        }
@@ -180,11 +182,13 @@ static int acpi_irq2ioapic(int irq)
        struct apic *ioapic;
        /* with acpi, the ioapics map a global interrupt space.  each covers a
         * window of the space from [ibase, ibase + nrdt). */
-       for (ioapic = xioapic; ioapic < &xioapic[Napic]; ioapic++, ioapic_idx++) {
+       for (ioapic = xioapic; ioapic < &xioapic[Napic]; ioapic++, ioapic_idx++)
+       {
                /* addr check is just for sanity */
                if (!ioapic->useable || !ioapic->addr)
                        continue;
-               if ((ioapic->ibase <= irq) && (irq < ioapic->ibase + ioapic->nrdt))
+               if ((ioapic->ibase <= irq) &&
+                   (irq < ioapic->ibase + ioapic->nrdt))
                        return ioapic_idx;
        }
        return -1;
@@ -198,20 +202,20 @@ static int acpi_irq2ioapic(int irq)
  *
  * From Brendan http://f.osdev.org/viewtopic.php?f=1&t=25951:
  *
- *             Before parsing the MADT you should begin by assuming that redirection
- *             entries 0 to 15 are used for ISA IRQs 0 to 15. The MADT's "Interrupt
- *             Source Override Structures" will tell you when this initial/default
- *             assumption is wrong. For example, the MADT might tell you that ISA IRQ 9
- *             is connected to IO APIC 44 and is level triggered; and (in this case)
- *             it'd be silly to assume that ISA IRQ 9 is also connected to IO APIC
- *             input 9 just because IO APIC input 9 is not listed.
+ *     Before parsing the MADT you should begin by assuming that redirection
+ *     entries 0 to 15 are used for ISA IRQs 0 to 15. The MADT's "Interrupt
+ *     Source Override Structures" will tell you when this initial/default
+ *     assumption is wrong. For example, the MADT might tell you that ISA IRQ 9
+ *     is connected to IO APIC 44 and is level triggered; and (in this case)
+ *     it'd be silly to assume that ISA IRQ 9 is also connected to IO APIC
+ *     input 9 just because IO APIC input 9 is not listed.
  *
- *             For PCI IRQs, the MADT tells you nothing and you can't assume anything
- *             at all. Sadly, you have to interpret the ACPI AML to determine how PCI
- *             IRQs are connected to IO APIC inputs (or find some other work-around;
- *             like implementing a motherboard driver for each different motherboard,
- *             or some complex auto-detection scheme, or just configure PCI devices to
- *             use MSI instead). */
+ *     For PCI IRQs, the MADT tells you nothing and you can't assume anything
+ *     at all. Sadly, you have to interpret the ACPI AML to determine how PCI
+ *     IRQs are connected to IO APIC inputs (or find some other work-around;
+ *     like implementing a motherboard driver for each different motherboard,
+ *     or some complex auto-detection scheme, or just configure PCI devices to
+ *     use MSI instead). */
 static int acpi_make_rdt(int tbdf, int irq, int busno, int devno)
 {
        struct Atable *at;
@@ -249,13 +253,15 @@ static int acpi_make_rdt(int tbdf, int irq, int busno, int devno)
                        gsi_irq = irq;
                } else {
                        /* Need to query ACPI at some point to handle this */
-                       printk("Non-ISA IRQ %d not found in MADT, aborting\n", irq);
+                       printk("Non-ISA IRQ %d not found in MADT, aborting\n",
+                              irq);
                        return -1;
                }
        }
        ioapic_nr = acpi_irq2ioapic(gsi_irq);
        if (ioapic_nr < 0) {
-               printk("Could not find an IOAPIC for global irq %d!\n", gsi_irq);
+               printk("Could not find an IOAPIC for global irq %d!\n",
+                      gsi_irq);
                return -1;
        }
        ioapicintrinit(busno, ioapic_nr, gsi_irq - xioapic[ioapic_nr].ibase,
@@ -268,7 +274,8 @@ void ioapicinit(int id, int ibase, uintptr_t pa)
        struct apic *apic;
        static int base;
 
-       assert((IOAPIC_PBASE <= pa) && (pa + PGSIZE <= IOAPIC_PBASE + APIC_SIZE));
+       assert((IOAPIC_PBASE <= pa) &&
+              (pa + PGSIZE <= IOAPIC_PBASE + APIC_SIZE));
        /*
         * Mark the IOAPIC useable if it has a good ID
         * and the registers can be mapped.
@@ -291,8 +298,8 @@ void ioapicinit(int id, int ibase, uintptr_t pa)
        spin_lock(&apic->lock);
        write_mmreg32(apic->addr + Ioregsel, Ioapicver);
        apic->nrdt = ((read_mmreg32(apic->addr + Iowin) >> 16) & 0xff) + 1;
-       /* the ibase is the global system interrupt base, told to us by ACPI.  if
-        * it's -1, we're called from mpparse, and just guess/make up our own
+       /* the ibase is the global system interrupt base, told to us by ACPI.
+        * if it's -1, we're called from mpparse, and just guess/make up our own
         * assignments. */
        if (ibase != -1)
                apic->ibase = ibase;
@@ -320,13 +327,15 @@ char *ioapicdump(char *start, char *end)
                apic = &xioapic[i];
                if (!apic->useable || apic->addr == 0)
                        continue;
-               start = seprintf(start, end, "ioapic %d addr %p nrdt %d ibase %d\n",
-                                                i, apic->addr, apic->nrdt, apic->ibase);
+               start = seprintf(start, end,
+                                "ioapic %d addr %p nrdt %d ibase %d\n",
+                                i, apic->addr, apic->nrdt, apic->ibase);
                for (n = 0; n < apic->nrdt; n++) {
                        spin_lock(&apic->lock);
                        rtblget(apic, n, &hi, &lo);
                        spin_unlock(&apic->lock);
-                       start = seprintf(start, end, " rdt %2.2d %p %p\n", n, hi, lo);
+                       start = seprintf(start, end, " rdt %2.2d %p %p\n",
+                                        n, hi, lo);
                }
        }
        for (i = 0; i < Nbus; i++) {
@@ -336,9 +345,10 @@ char *ioapicdump(char *start, char *end)
                for (; rbus != NULL; rbus = rbus->next) {
                        rdt = rbus->rdt;
                        start = seprintf(start, end,
-                                                        " apic %ld devno %p(%d %d) intin %d hi %p lo %p\n",
-                                                        rdt->apic - xioapic, rbus->devno, rbus->devno >> 2,
-                                                        rbus->devno & 0x03, rdt->intin, rdt->hi, rdt->lo);
+                                        " apic %ld devno %p(%d %d) intin %d hi %p lo %p\n",
+                                        rdt->apic - xioapic, rbus->devno,
+                                        rbus->devno >> 2, rbus->devno & 0x03,
+                                        rdt->intin, rdt->hi, rdt->lo);
                }
        }
        return start;
@@ -449,12 +459,14 @@ static int msi_irq_enable(struct irq_handler *irq_h, struct pci_device *p)
 static struct Rdt *ioapic_vector2rdt(int apic_vector)
 {
        struct Rdt *rdt;
+
        if (apic_vector < IdtIOAPIC || apic_vector > MaxIdtIOAPIC) {
                warn("ioapic vector %d out of range", apic_vector);
                return 0;
        }
-       /* Fortunately rdtvecno[vecno] is static once assigned. o/w, we'll need some
-        * global sync for the callers, both for lookup and keeping rdt valid. */
+       /* Fortunately rdtvecno[vecno] is static once assigned. o/w, we'll need
+        * some global sync for the callers, both for lookup and keeping rdt
+        * valid. */
        rdt = rdtvecno[apic_vector];
        if (!rdt) {
                warn("vector %d has no RDT! (did you enable it?)", apic_vector);
@@ -470,6 +482,7 @@ static void ioapic_route_irq(struct irq_handler *unused, int apic_vector,
                              int hw_coreid)
 {
        struct Rdt *rdt = ioapic_vector2rdt(apic_vector);
+
        if (!rdt) {
                printk("Missing IOAPIC route for vector!\n", apic_vector);
                return;
@@ -491,6 +504,7 @@ static void ioapic_mask_irq(struct irq_handler *unused, int apic_vector)
 {
        /* could store the rdt in the irq_h */
        struct Rdt *rdt = ioapic_vector2rdt(apic_vector);
+
        if (!rdt)
                return;
        spin_lock(&rdt->apic->lock);
@@ -555,72 +569,74 @@ int bus_irq_setup(struct irq_handler *irq_h)
                }
        }
        switch (BUSTYPE(irq_h->tbdf)) {
-               case BusLAPIC:
-                       /* nxm used to set the initial 'isr' method (i think equiv to our
-                        * check_spurious) to apiceoi for non-spurious lapic vectors.  in
-                        * effect, i think they were sending the EOI early, and their eoi
-                        * method was 0.  we're not doing that (unless we have to). */
-                       irq_h->check_spurious = lapic_check_spurious;
-                       irq_h->eoi = lapic_send_eoi;
-                       irq_h->mask = lapic_mask_irq;
-                       irq_h->unmask = lapic_unmask_irq;
-                       irq_h->route_irq = 0;
-                       irq_h->type = "lapic";
-                       /* For the LAPIC, irq == vector */
-                       return irq_h->dev_irq;
-               case BusIPI:
-                       /* similar to LAPIC, but we don't actually have LVT entries */
-                       irq_h->check_spurious = lapic_check_spurious;
-                       irq_h->eoi = lapic_send_eoi;
-                       irq_h->mask = 0;
-                       irq_h->unmask = 0;
-                       irq_h->route_irq = 0;
-                       irq_h->type = "IPI";
-                       return irq_h->dev_irq;
-               case BusISA:
-                       if (mpisabusno == -1)
-                               panic("No ISA bus allocated");
-                       busno = mpisabusno;
-                       /* need to track the irq in devno in PCI interrupt assignment entry
-                        * format (see mp.c or MP spec D.3). */
-                       devno = irq_h->dev_irq << 2;
-                       break;
-               case BusPCI:
-                       pcidev = pci_match_tbdf(irq_h->tbdf);
-                       if (!pcidev) {
-                               warn("No PCI dev for tbdf %p!", irq_h->tbdf);
-                               return -1;
-                       }
-                       if ((vecno = msi_irq_enable(irq_h, pcidev)) != -1)
-                               return vecno;
-                       busno = BUSBNO(irq_h->tbdf);
-                       assert(busno == pcidev->bus);
-                       devno = pcidev_read8(pcidev, PciINTP);
-
-                       /* this might not be a big deal - some PCI devices have no INTP.  if
-                        * so, change our devno - 1 below. */
-                       if (devno == 0)
-                               panic("no INTP for tbdf %p", irq_h->tbdf);
-                       /* remember, devno is the device shifted with irq pin in bits 0-1.
-                        * we subtract 1, since the PCI intp maps 1 -> INTA, 2 -> INTB, etc,
-                        * and the MP spec uses 0 -> INTA, 1 -> INTB, etc. */
-                       devno = BUSDNO(irq_h->tbdf) << 2 | (devno - 1);
-                       break;
-               default:
-                       panic("Unknown bus type, TBDF %p", irq_h->tbdf);
+       case BusLAPIC:
+               /* nxm used to set the initial 'isr' method (i think equiv to
+                * our check_spurious) to apiceoi for non-spurious lapic
+                * vectors.  in effect, i think they were sending the EOI early,
+                * and their eoi method was 0.  we're not doing that (unless we
+                * have to). */
+               irq_h->check_spurious = lapic_check_spurious;
+               irq_h->eoi = lapic_send_eoi;
+               irq_h->mask = lapic_mask_irq;
+               irq_h->unmask = lapic_unmask_irq;
+               irq_h->route_irq = 0;
+               irq_h->type = "lapic";
+               /* For the LAPIC, irq == vector */
+               return irq_h->dev_irq;
+       case BusIPI:
+               /* similar to LAPIC, but we don't actually have LVT entries */
+               irq_h->check_spurious = lapic_check_spurious;
+               irq_h->eoi = lapic_send_eoi;
+               irq_h->mask = 0;
+               irq_h->unmask = 0;
+               irq_h->route_irq = 0;
+               irq_h->type = "IPI";
+               return irq_h->dev_irq;
+       case BusISA:
+               if (mpisabusno == -1)
+                       panic("No ISA bus allocated");
+               busno = mpisabusno;
+               /* need to track the irq in devno in PCI interrupt assignment
+                * entry format (see mp.c or MP spec D.3). */
+               devno = irq_h->dev_irq << 2;
+               break;
+       case BusPCI:
+               pcidev = pci_match_tbdf(irq_h->tbdf);
+               if (!pcidev) {
+                       warn("No PCI dev for tbdf %p!", irq_h->tbdf);
+                       return -1;
+               }
+               if ((vecno = msi_irq_enable(irq_h, pcidev)) != -1)
+                       return vecno;
+               busno = BUSBNO(irq_h->tbdf);
+               assert(busno == pcidev->bus);
+               devno = pcidev_read8(pcidev, PciINTP);
+
+               /* this might not be a big deal - some PCI devices have no INTP.
+                * if so, change our devno - 1 below. */
+               if (devno == 0)
+                       panic("no INTP for tbdf %p", irq_h->tbdf);
+               /* remember, devno is the device shifted with irq pin in bits
+                * 0-1.  we subtract 1, since the PCI intp maps 1 -> INTA, 2 ->
+                * INTB, etc, and the MP spec uses 0 -> INTA, 1 -> INTB, etc. */
+               devno = BUSDNO(irq_h->tbdf) << 2 | (devno - 1);
+               break;
+       default:
+               panic("Unknown bus type, TBDF %p", irq_h->tbdf);
        }
-       /* busno and devno are set, regardless of the bustype, enough to find rdt.
-        * these may differ from the values in tbdf. */
+       /* busno and devno are set, regardless of the bustype, enough to find
+        * rdt.  these may differ from the values in tbdf. */
        rdt = rbus_get_rdt(busno, devno);
        if (!rdt) {
-               /* second chance.  if we didn't find the item the first time, then (if
-                * it exists at all), it wasn't in the MP tables (or we had no tables).
-                * So maybe we can figure it out via ACPI. */
+               /* second chance.  if we didn't find the item the first time,
+                * then (if it exists at all), it wasn't in the MP tables (or we
+                * had no tables).  So maybe we can figure it out via ACPI. */
                acpi_make_rdt(irq_h->tbdf, irq_h->dev_irq, busno, devno);
                rdt = rbus_get_rdt(busno, devno);
        }
        if (!rdt) {
-               printk("Unable to build IOAPIC route for irq %d\n", irq_h->dev_irq);
+               printk("Unable to build IOAPIC route for irq %d\n",
+                      irq_h->dev_irq);
                return -1;
        }
        /*
@@ -636,15 +652,16 @@ int bus_irq_setup(struct irq_handler *irq_h)
         * rather than putting a Lock in each entry.
         */
        spin_lock(&rdt->apic->lock);
-       /* if a destination has already been picked, we store it in the lo.  this
-        * stays around regardless of enabled/disabled, since we don't reap vectors
-        * yet.  nor do we really mess with enabled... */
+       /* if a destination has already been picked, we store it in the lo.
+        * this stays around regardless of enabled/disabled, since we don't reap
+        * vectors yet.  nor do we really mess with enabled... */
        if ((rdt->lo & 0xff) == 0) {
                vecno = nextvec();
                rdt->lo |= vecno;
                rdtvecno[vecno] = rdt;
        } else {
-               printd("%p: mutiple irq bus %d dev %d\n", irq_h->tbdf, busno, devno);
+               printd("%p: mutiple irq bus %d dev %d\n", irq_h->tbdf, busno,
+                      devno);
        }
        rdt->enabled++;
        rdt->hi = 0;                    /* route to 0 by default */
index a04ed91..ab439ed 100644 (file)
@@ -44,13 +44,13 @@ enum {
        ApicLOGICAL     = 0x00000800,
 
        ApicDELIVS      = 0x00001000,   /* [12] Delivery Status (RO) */
-       ApicHIGH        = 0x00000000,   /* [13] Interrupt Input Pin Polarity (RW) */
+       ApicHIGH        = 0x00000000,   /* [13] IRQ Input Pin Polarity (RW) */
        ApicLOW         = 0x00002000,
        ApicRemoteIRR   = 0x00004000,   /* [14] Remote IRR (RO) */
        ApicEDGE        = 0x00000000,   /* [15] Trigger Mode (RW) */
        ApicLEVEL       = 0x00008000,
        ApicIMASK       = 0x00010000,   /* [16] Interrupt Mask */
-       IOAPIC_PBASE    = 0xfec00000, /* default *physical* address */
+       IOAPIC_PBASE    = 0xfec00000,   /* default *physical* address */
 };
 
 extern int mpisabusno;
index d31becb..7f5d1ad 100644 (file)
@@ -6,23 +6,23 @@
 #include <arch/x86.h>
 #include <atomic.h>
 
-#define        CMOS_RTC_SELECT                         0x70
-#define        CMOS_RTC_DATA                           0x71
+#define        CMOS_RTC_SELECT                 0x70
+#define        CMOS_RTC_DATA                   0x71
 
 #define RTC_A_UPDATE_IN_PROGRESS       (1 << 7)
-#define RTC_B_24HOUR_MODE                      (1 << 1)
-#define RTC_B_BINARY_MODE                      (1 << 2)
-#define RTC_12_HOUR_PM                         (1 << 7)
-#define CMOS_RTC_SECOND                                0x00
-#define CMOS_RTC_MINUTE                                0x02
-#define CMOS_RTC_HOUR                          0x04
-#define CMOS_RTC_WEEKDAY                       0x06
-#define CMOS_RTC_DAY                           0x07
-#define CMOS_RTC_MONTH                         0x08
-#define CMOS_RTC_YEAR                          0x09
-#define CMOS_RTC_CENTURY                       0x32
-#define CMOS_RTC_STATUS_A                      0x0A
-#define CMOS_RTC_STATUS_B                      0x0B
+#define RTC_B_24HOUR_MODE              (1 << 1)
+#define RTC_B_BINARY_MODE              (1 << 2)
+#define RTC_12_HOUR_PM                 (1 << 7)
+#define CMOS_RTC_SECOND                        0x00
+#define CMOS_RTC_MINUTE                        0x02
+#define CMOS_RTC_HOUR                  0x04
+#define CMOS_RTC_WEEKDAY               0x06
+#define CMOS_RTC_DAY                   0x07
+#define CMOS_RTC_MONTH                 0x08
+#define CMOS_RTC_YEAR                  0x09
+#define CMOS_RTC_CENTURY               0x32
+#define CMOS_RTC_STATUS_A              0x0A
+#define CMOS_RTC_STATUS_B              0x0B
 
 /* If we ever disable NMIs, we'll need to make sure we don't reenable them here.
  * (Top bit of the CMOS_RTC_SELECT selector). */
index 64187e6..2484e3a 100644 (file)
@@ -51,15 +51,16 @@ size_t backtrace_list(uintptr_t pc, uintptr_t fp, uintptr_t *pcs,
                if (!fp)