Lindent on the new APIC/ACPI files
authorBarret Rhoden <brho@cs.berkeley.edu>
Tue, 4 Mar 2014 18:59:06 +0000 (10:59 -0800)
committerBarret Rhoden <brho@cs.berkeley.edu>
Wed, 5 Mar 2014 01:30:25 +0000 (17:30 -0800)
And the MP tables!  Oh, and devarch.

kern/arch/x86/apic.h
kern/arch/x86/apic9.c
kern/arch/x86/devarch.c
kern/arch/x86/io.h
kern/arch/x86/ioapic.c
kern/arch/x86/mp.c
kern/arch/x86/mpacpi.c
kern/drivers/dev/acpi.c
kern/drivers/dev/pci.c
kern/include/acpi.h

index d1fc60b..68e2b33 100644 (file)
@@ -42,7 +42,7 @@
  * spaces.  We just happen to have a slight 'hole' in addressable physical
  * memory.  We can move the PBASE, but we're limited to 32 bit (physical)
  * addresses. */
  * spaces.  We just happen to have a slight 'hole' in addressable physical
  * memory.  We can move the PBASE, but we're limited to 32 bit (physical)
  * addresses. */
-#define LAPIC_PBASE                                    0xfee00000 /* default *physical* address */
+#define LAPIC_PBASE                                    0xfee00000      /* default *physical* address */
 #define LAPIC_EOI                                      (LAPIC_BASE + 0x0b0)
 #define LAPIC_SPURIOUS                         (LAPIC_BASE + 0x0f0)
 #define LAPIC_VERSION                          (LAPIC_BASE + 0x030)
 #define LAPIC_EOI                                      (LAPIC_BASE + 0x0b0)
 #define LAPIC_SPURIOUS                         (LAPIC_BASE + 0x0f0)
 #define LAPIC_VERSION                          (LAPIC_BASE + 0x030)
@@ -61,7 +61,7 @@
 #define LAPIC_TIMER_INIT                       (LAPIC_BASE + 0x380)
 #define LAPIC_TIMER_CURRENT                    (LAPIC_BASE + 0x390)
 #define LAPIC_TIMER_DIVIDE                     (LAPIC_BASE + 0x3e0)
 #define LAPIC_TIMER_INIT                       (LAPIC_BASE + 0x380)
 #define LAPIC_TIMER_CURRENT                    (LAPIC_BASE + 0x390)
 #define LAPIC_TIMER_DIVIDE                     (LAPIC_BASE + 0x3e0)
-#define LAPIC_TIMER_DEFAULT_VECTOR     0xeb            /* Aka 235, IRQ203 */
+#define LAPIC_TIMER_DEFAULT_VECTOR     0xeb    /* Aka 235, IRQ203 */
 /* Quick note on the divisor.  The LAPIC timer ticks once per divisor-bus ticks
  * (system bus or APIC bus, depending on the model).  Ex: A divisor of 128 means
  * 128 bus ticks results in 1 timer tick.  The divisor increases the time range
 /* Quick note on the divisor.  The LAPIC timer ticks once per divisor-bus ticks
  * (system bus or APIC bus, depending on the model).  Ex: A divisor of 128 means
  * 128 bus ticks results in 1 timer tick.  The divisor increases the time range
 
 #define PIT_FREQ                                       1193182
 
 
 #define PIT_FREQ                                       1193182
 
-#define IO_TIMER1   0x40        /* 8253 Timer #1 */
+#define IO_TIMER1   0x40       /* 8253 Timer #1 */
 #define TIMER_CNTR0 (IO_TIMER1 + TIMER_REG_CNTR0)
 #define TIMER_CNTR1 (IO_TIMER1 + TIMER_REG_CNTR1)
 #define TIMER_CNTR2 (IO_TIMER1 + TIMER_REG_CNTR2)
 #define TIMER_CNTR0 (IO_TIMER1 + TIMER_REG_CNTR0)
 #define TIMER_CNTR1 (IO_TIMER1 + TIMER_REG_CNTR1)
 #define TIMER_CNTR2 (IO_TIMER1 + TIMER_REG_CNTR2)
@@ -163,7 +163,7 @@ static inline void lapic_send_eoi(void);
 static inline uint32_t lapic_get_version(void);
 static inline uint32_t lapic_get_error(void);
 static inline uint32_t lapic_get_id(void);
 static inline uint32_t lapic_get_version(void);
 static inline uint32_t lapic_get_error(void);
 static inline uint32_t lapic_get_id(void);
-static inline void lapic_set_id(uint8_t id); // Careful, may not actually work
+static inline void lapic_set_id(uint8_t id);   // Careful, may not actually work
 static inline uint8_t lapic_get_logid(void);
 static inline void lapic_set_logid(uint8_t id);
 static inline void lapic_disable_timer(void);
 static inline uint8_t lapic_get_logid(void);
 static inline void lapic_set_logid(uint8_t id);
 static inline void lapic_disable_timer(void);
@@ -191,7 +191,7 @@ static inline void lapic_send_eoi(void)
 
 static inline uint32_t lapic_get_version(void)
 {
 
 static inline uint32_t lapic_get_version(void)
 {
-       return read_mmreg32(LAPIC_VERSION);     
+       return read_mmreg32(LAPIC_VERSION);
 }
 
 static inline uint32_t lapic_get_error(void)
 }
 
 static inline uint32_t lapic_get_error(void)
@@ -239,7 +239,7 @@ static inline void lapic_disable(void)
  */
 static inline void lapic_wait_to_send(void)
 {
  */
 static inline void lapic_wait_to_send(void)
 {
-       while(read_mmreg32(LAPIC_IPI_ICR_LOWER) & 0x1000)
+       while (read_mmreg32(LAPIC_IPI_ICR_LOWER) & 0x1000)
                __cpu_relax();
 }
 
                __cpu_relax();
 }
 
@@ -307,7 +307,6 @@ static inline void __send_nmi(uint8_t hw_coreid)
        write_msr(IA32_APIC_BASE, msr_val);
 */
 
        write_msr(IA32_APIC_BASE, msr_val);
 */
 
-
 /* 
  * This file is part of the UCB release of Plan 9. It is subject to the license
  * terms in the LICENSE file found in the top-level directory of this
 /* 
  * This file is part of the UCB release of Plan 9. It is subject to the license
  * terms in the LICENSE file found in the top-level directory of this
@@ -326,37 +325,37 @@ static inline void __send_nmi(uint8_t hw_coreid)
  */
 
 struct ioapic {
  */
 
 struct ioapic {
-       spinlock_t lock;                                        /* IOAPIC: register access */
-       uint32_t*       addr;                           /* IOAPIC: register base */
-       uintptr_t paddr;                        /* register base */
-       int     nrdt;                           /* IOAPIC: size of RDT */
-       int     gsib;                           /* IOAPIC: global RDT index */
-       int     ibase;                          /* global interrupt base */
+       spinlock_t lock;                        /* IOAPIC: register access */
+       uint32_t *addr;                         /* IOAPIC: register base */
+       uintptr_t paddr;                        /* register base */
+       int nrdt;                                       /* IOAPIC: size of RDT */
+       int gsib;                                       /* IOAPIC: global RDT index */
+       int ibase;                                      /* global interrupt base */
 };
 
 struct lapic {
 };
 
 struct lapic {
-       int     machno;                         /* APIC */
+       int machno;                                     /* APIC */
 
 
-       uint32_t        lvt[6];
-       int     nlvt;
-       int     ver;
+       uint32_t lvt[6];
+       int nlvt;
+       int ver;
 
 
-       int64_t hz;                             /* APIC Timer frequency */
-       int64_t max;
-       int64_t min;
-       int64_t div;
+       int64_t hz;                                     /* APIC Timer frequency */
+       int64_t max;
+       int64_t min;
+       int64_t div;
 };
 
 struct apic {
 };
 
 struct apic {
-       int     useable;                        /* en */
+       int useable;                            /* en */
        struct ioapic;
        struct lapic;
 };
 
 enum {
        struct ioapic;
        struct lapic;
 };
 
 enum {
-       Nbus            = 256,
-       Napic           = 254,                  /* xAPIC architectural limit */
-       Nrdt            = 64,
+       Nbus = 256,
+       Napic = 254,    /* xAPIC architectural limit */
+       Nrdt = 64,
 };
 
 /*
 };
 
 /*
@@ -373,29 +372,29 @@ enum {
  * [16] Interrupt Mask
  */
 enum {
  * [16] Interrupt Mask
  */
 enum {
-       MTf             = 0x00000000,           /* Fixed */
-       MTlp            = 0x00000100,           /* Lowest Priority */
-       MTsmi           = 0x00000200,           /* SMI */
-       MTrr            = 0x00000300,           /* Remote Read */
-       MTnmi           = 0x00000400,           /* NMI */
-       MTir            = 0x00000500,           /* INIT/RESET */
-       MTsipi          = 0x00000600,           /* Startup IPI */
-       MTei            = 0x00000700,           /* ExtINT */
-
-       Pm              = 0x00000000,           /* Physical Mode */
-       Lm              = 0x00000800,           /* Logical Mode */
-
-       Ds              = 0x00001000,           /* Delivery Status */
-       IPhigh          = 0x00000000,           /* IIPP High */
-       IPlow           = 0x00002000,           /* IIPP Low */
-       Rirr            = 0x00004000,           /* Remote IRR */
-       TMedge          = 0x00000000,           /* Trigger Mode Edge */
-       TMlevel         = 0x00008000,           /* Trigger Mode Level */
-       Im              = 0x00010000,           /* Interrupt Mask */
+       MTf = 0x00000000,                       /* Fixed */
+       MTlp = 0x00000100,      /* Lowest Priority */
+       MTsmi = 0x00000200,     /* SMI */
+       MTrr = 0x00000300,      /* Remote Read */
+       MTnmi = 0x00000400,     /* NMI */
+       MTir = 0x00000500,      /* INIT/RESET */
+       MTsipi = 0x00000600,    /* Startup IPI */
+       MTei = 0x00000700,      /* ExtINT */
+
+       Pm = 0x00000000,        /* Physical Mode */
+       Lm = 0x00000800,        /* Logical Mode */
+
+       Ds = 0x00001000,        /* Delivery Status */
+       IPhigh = 0x00000000,    /* IIPP High */
+       IPlow = 0x00002000,     /* IIPP Low */
+       Rirr = 0x00004000,      /* Remote IRR */
+       TMedge = 0x00000000,    /* Trigger Mode Edge */
+       TMlevel = 0x00008000,   /* Trigger Mode Level */
+       Im = 0x00010000,        /* Interrupt Mask */
 };
 
 };
 
-extern struct apic     xlapic[Napic];
-extern struct apic     xioapic[Napic];
+extern struct apic xlapic[Napic];
+extern struct apic xioapic[Napic];
 
 #define l16get(p)      (((p)[1]<<8)|(p)[0])
 #define        l32get(p)       (((uint32_t)l16get(p+2)<<16)|l16get(p))
 
 #define l16get(p)      (((p)[1]<<8)|(p)[0])
 #define        l32get(p)       (((uint32_t)l16get(p+2)<<16)|l16get(p))
index af82c18..e5282a0 100644 (file)
 #include <ip.h>
 #include <arch/io.h>
 
 #include <ip.h>
 #include <arch/io.h>
 
-enum {                                         /* Local APIC registers */
-       Id              = 0x0020,               /* Identification */
-       Ver             = 0x0030,               /* Version */
-       Tp              = 0x0080,               /* Task Priority */
-       Ap              = 0x0090,               /* Arbitration Priority */
-       Pp              = 0x00a0,               /* Processor Priority */
-       Eoi             = 0x00b0,               /* EOI */
-       Ld              = 0x00d0,               /* Logical Destination */
-       Df              = 0x00e0,               /* Destination Format */
-       Siv             = 0x00f0,               /* Spurious Interrupt Vector */
-       Is              = 0x0100,               /* Interrupt Status (8) */
-       Tm              = 0x0180,               /* Trigger Mode (8) */
-       Ir              = 0x0200,               /* Interrupt Request (8) */
-       Es              = 0x0280,               /* Error Status */
-       Iclo            = 0x0300,               /* Interrupt Command */
-       Ichi            = 0x0310,               /* Interrupt Command [63:32] */
-       Lvt0            = 0x0320,               /* Local Vector Table 0 */
-       Lvt5            = 0x0330,               /* Local Vector Table 5 */
-       Lvt4            = 0x0340,               /* Local Vector Table 4 */
-       Lvt1            = 0x0350,               /* Local Vector Table 1 */
-       Lvt2            = 0x0360,               /* Local Vector Table 2 */
-       Lvt3            = 0x0370,               /* Local Vector Table 3 */
-       Tic             = 0x0380,               /* Timer Initial Count */
-       Tcc             = 0x0390,               /* Timer Current Count */
-       Tdc             = 0x03e0,               /* Timer Divide Configuration */
-
-       Tlvt            = Lvt0,                 /* Timer */
-       Lint0           = Lvt1,                 /* Local Interrupt 0 */
-       Lint1           = Lvt2,                 /* Local Interrupt 1 */
-       Elvt            = Lvt3,                 /* Error */
-       Pclvt           = Lvt4,                 /* Performance Counter */
-       Tslvt           = Lvt5,                 /* Thermal Sensor */
+enum {                                                 /* Local APIC registers */
+       Id = 0x0020,                            /* Identification */
+       Ver = 0x0030,   /* Version */
+       Tp = 0x0080,    /* Task Priority */
+       Ap = 0x0090,    /* Arbitration Priority */
+       Pp = 0x00a0,    /* Processor Priority */
+       Eoi = 0x00b0,   /* EOI */
+       Ld = 0x00d0,    /* Logical Destination */
+       Df = 0x00e0,    /* Destination Format */
+       Siv = 0x00f0,   /* Spurious Interrupt Vector */
+       Is = 0x0100,    /* Interrupt Status (8) */
+       Tm = 0x0180,    /* Trigger Mode (8) */
+       Ir = 0x0200,    /* Interrupt Request (8) */
+       Es = 0x0280,    /* Error Status */
+       Iclo = 0x0300,  /* Interrupt Command */
+       Ichi = 0x0310,  /* Interrupt Command [63:32] */
+       Lvt0 = 0x0320,  /* Local Vector Table 0 */
+       Lvt5 = 0x0330,  /* Local Vector Table 5 */
+       Lvt4 = 0x0340,  /* Local Vector Table 4 */
+       Lvt1 = 0x0350,  /* Local Vector Table 1 */
+       Lvt2 = 0x0360,  /* Local Vector Table 2 */
+       Lvt3 = 0x0370,  /* Local Vector Table 3 */
+       Tic = 0x0380,   /* Timer Initial Count */
+       Tcc = 0x0390,   /* Timer Current Count */
+       Tdc = 0x03e0,   /* Timer Divide Configuration */
+
+       Tlvt = Lvt0,    /* Timer */
+       Lint0 = Lvt1,   /* Local Interrupt 0 */
+       Lint1 = Lvt2,   /* Local Interrupt 1 */
+       Elvt = Lvt3,    /* Error */
+       Pclvt = Lvt4,   /* Performance Counter */
+       Tslvt = Lvt5,   /* Thermal Sensor */
 };
 
 };
 
-
 static char *apicregnames[] = {
 static char *apicregnames[] = {
-       [Id]    "Identification",
-       [Ver]   "Version",
-       [Tp]    "Task Priority",
-       [Ap]    "Arbitration Priority",
-       [Pp]    "Processor Priority",
-       [Eoi]   "EOI",
-       [Ld]    "Logical Destination",
-       [Df]    "Destination Format",
-       [Siv]   "Spurious Interrupt Vector",
-       [Is]    "Interrupt Status (8)",
-       [Tm]    "Trigger Mode (8)",
-       [Ir]    "Interrupt Request (8)",
-       [Es]    "Error Status",
-       [Iclo]  "Interrupt Command",
-       [Ichi]  "Interrupt Command [63:32]",
-       [Lvt0]  "Local Vector Table 0",
-       [Lvt5]  "Local Vector Table 5",
-       [Lvt4]  "Local Vector Table 4",
-       [Lvt1]  "Local Vector Table 1",
-       [Lvt2]  "Local Vector Table 2",
-       [Lvt3]  "Local Vector Table 3",
-       [Tic]   "Timer Initial Count",
-       [Tcc]   "Timer Current Count",
-       [Tdc]   "Timer Divide Configuration",
-
-       [Tlvt]  "Timer",
-       [Lint0] "Local Interrupt 0",
-       [Lint1] "Local Interrupt 1",
-       [Elvt]  "Error",
-       [Pclvt] "Performance Counter",
-       [Tslvt] "Thermal Sensor",
+       [Id] "Identification",
+       [Ver] "Version",
+       [Tp] "Task Priority",
+       [Ap] "Arbitration Priority",
+       [Pp] "Processor Priority",
+       [Eoi] "EOI",
+       [Ld] "Logical Destination",
+       [Df] "Destination Format",
+       [Siv] "Spurious Interrupt Vector",
+       [Is] "Interrupt Status (8)",
+       [Tm] "Trigger Mode (8)",
+       [Ir] "Interrupt Request (8)",
+       [Es] "Error Status",
+       [Iclo] "Interrupt Command",
+       [Ichi] "Interrupt Command [63:32]",
+       [Lvt0] "Local Vector Table 0",
+       [Lvt5] "Local Vector Table 5",
+       [Lvt4] "Local Vector Table 4",
+       [Lvt1] "Local Vector Table 1",
+       [Lvt2] "Local Vector Table 2",
+       [Lvt3] "Local Vector Table 3",
+       [Tic] "Timer Initial Count",
+       [Tcc] "Timer Current Count",
+       [Tdc] "Timer Divide Configuration",
+
+       [Tlvt] "Timer",
+       [Lint0] "Local Interrupt 0",
+       [Lint1] "Local Interrupt 1",
+       [Elvt] "Error",
+       [Pclvt] "Performance Counter",
+       [Tslvt] "Thermal Sensor",
 };
 
 };
 
-
-enum {                                         /* Siv */
-       Swen            = 0x00000100,           /* Software Enable */
-       Fdis            = 0x00000200,           /* Focus Disable */
+enum {                                                 /* Siv */
+       Swen = 0x00000100,                      /* Software Enable */
+       Fdis = 0x00000200,      /* Focus Disable */
 };
 
 };
 
-enum {                                         /* Iclo */
-       Lassert         = 0x00004000,           /* Assert level */
+enum {                                                 /* Iclo */
+       Lassert = 0x00004000,           /* Assert level */
 
 
-       DSnone          = 0x00000000,           /* Use Destination Field */
-       DSself          = 0x00040000,           /* Self is only destination */
-       DSallinc        = 0x00080000,           /* All including self */
-       DSallexc        = 0x000c0000,           /* All Excluding self */
+       DSnone = 0x00000000,    /* Use Destination Field */
+       DSself = 0x00040000,    /* Self is only destination */
+       DSallinc = 0x00080000,  /* All including self */
+       DSallexc = 0x000c0000,  /* All Excluding self */
 };
 
 };
 
-enum {                                         /* Tlvt */
-       Periodic        = 0x00020000,           /* Periodic Timer Mode */
+enum {                                                 /* Tlvt */
+       Periodic = 0x00020000,          /* Periodic Timer Mode */
 };
 
 };
 
-enum {                                         /* Tdc */
-       DivX2           = 0x00000000,           /* Divide by 2 */
-       DivX4           = 0x00000001,           /* Divide by 4 */
-       DivX8           = 0x00000002,           /* Divide by 8 */
-       DivX16          = 0x00000003,           /* Divide by 16 */
-       DivX32          = 0x00000008,           /* Divide by 32 */
-       DivX64          = 0x00000009,           /* Divide by 64 */
-       DivX128         = 0x0000000a,           /* Divide by 128 */
-       DivX1           = 0x0000000b,           /* Divide by 1 */
+enum {                                                 /* Tdc */
+       DivX2 = 0x00000000,                     /* Divide by 2 */
+       DivX4 = 0x00000001,     /* Divide by 4 */
+       DivX8 = 0x00000002,     /* Divide by 8 */
+       DivX16 = 0x00000003,    /* Divide by 16 */
+       DivX32 = 0x00000008,    /* Divide by 32 */
+       DivX64 = 0x00000009,    /* Divide by 64 */
+       DivX128 = 0x0000000a,   /* Divide by 128 */
+       DivX1 = 0x0000000b,     /* Divide by 1 */
 };
 
 };
 
-static uint8_tapicbase;
+static uint8_t *apicbase;
 static int apmachno = 1;
 
 static int apmachno = 1;
 
-struct apic    xlapic[Napic];
+struct apic xlapic[Napic];
 
 
-static uint32_t
-apicrget(int r)
+static uint32_t apicrget(int r)
 {
        uint32_t val;
 {
        uint32_t val;
-       if (! apicbase)
+       if (!apicbase)
                panic("apicrget: no apic");
                panic("apicrget: no apic");
-       val = *((uint32_t*)(apicbase+r));
+       val = *((uint32_t *) (apicbase + r));
        printk("apicrget: %s returns %p\n", apicregnames[r], val);
        printk("apicrget: %s returns %p\n", apicregnames[r], val);
-       return *((uint32_t*)(apicbase+r));
+       return *((uint32_t *) (apicbase + r));
        return val;
 }
 
        return val;
 }
 
-static void
-apicrput(int r, uint32_t data)
+static void apicrput(int r, uint32_t data)
 {
 {
-       if (! apicbase)
+       if (!apicbase)
                panic("apicrput: no apic");
        printk("apicrput: %s = %p\n", apicregnames[r], data);
                panic("apicrput: no apic");
        printk("apicrput: %s = %p\n", apicregnames[r], data);
-       *((uint32_t*)(apicbase+r)) = data;
+       *((uint32_t *) (apicbase + r)) = data;
 }
 
 }
 
-int
-apiceoi(int vecno)
+int apiceoi(int vecno)
 {
        apicrput(Eoi, 0);
 
        return vecno;
 }
 
 {
        apicrput(Eoi, 0);
 
        return vecno;
 }
 
-int
-apicisr(int vecno)
+int apicisr(int vecno)
 {
        int isr;
 
 {
        int isr;
 
-       isr = apicrget(Is + (vecno/32)*16);
+       isr = apicrget(Is + (vecno / 32) * 16);
 
 
-       return isr & (1<<(vecno%32));
+       return isr & (1 << (vecno % 32));
 }
 
 }
 
-void
-apicinit(int apicno, uintptr_t pa, int isbp)
+void apicinit(int apicno, uintptr_t pa, int isbp)
 {
        struct apic *apic;
 
 {
        struct apic *apic;
 
@@ -170,11 +163,11 @@ apicinit(int apicno, uintptr_t pa, int isbp)
         * to be dealt with sometime.
         */
        printk("apicinit: apicno %d pa %#p isbp %d\n", apicno, pa, isbp);
         * to be dealt with sometime.
         */
        printk("apicinit: apicno %d pa %#p isbp %d\n", apicno, pa, isbp);
-       if(apicno >= Napic){
+       if (apicno >= Napic) {
                printd("apicinit%d: out of range\n", apicno);
                return;
        }
                printd("apicinit%d: out of range\n", apicno);
                return;
        }
-       if((apic = &xlapic[apicno])->useable){
+       if ((apic = &xlapic[apicno])->useable) {
                printd("apicinit%d: already initialised\n", apicno);
                return;
        }
                printd("apicinit%d: already initialised\n", apicno);
                return;
        }
@@ -189,69 +182,70 @@ apicinit(int apicno, uintptr_t pa, int isbp)
         * Machno 0 is always the bootstrap processor.
         */
 
         * Machno 0 is always the bootstrap processor.
         */
 
-       if(isbp){
+       if (isbp) {
                apic->machno = 0;
 #warning "where in pcpui do we put the apicno?"
                //m->apicno = apicno;
                apic->machno = 0;
 #warning "where in pcpui do we put the apicno?"
                //m->apicno = apicno;
-       }
-       else
+       } else
                apic->machno = apmachno++;
 }
 
                apic->machno = apmachno++;
 }
 
-static char *
-apicdump0(char *start, char *end, struct apic *apic, int i)
+static char *apicdump0(char *start, char *end, struct apic *apic, int i)
 {
 {
-       if(!apic->useable || apic->addr != 0)
+       if (!apic->useable || apic->addr != 0)
                return start;
                return start;
-       start = seprintf(start, end, "apic%d: machno %d lint0 %#8.8p lint1 %#8.8p\n",
-               i, apic->machno, apic->lvt[0], apic->lvt[1]);
-       start = seprintf(start, end, " tslvt %#8.8p pclvt %#8.8p elvt %#8.8p\n",
-               apicrget(Tslvt), apicrget(Pclvt), apicrget(Elvt));
-       start = seprintf(start, end, " tlvt %#8.8p lint0 %#8.8p lint1 %#8.8p siv %#8.8p\n",
-               apicrget(Tlvt), apicrget(Lint0),
-               apicrget(Lint1), apicrget(Siv));
+       start =
+               seprintf(start, end, "apic%d: machno %d lint0 %#8.8p lint1 %#8.8p\n", i,
+                                apic->machno, apic->lvt[0], apic->lvt[1]);
+       start =
+               seprintf(start, end, " tslvt %#8.8p pclvt %#8.8p elvt %#8.8p\n",
+                                apicrget(Tslvt), apicrget(Pclvt), apicrget(Elvt));
+       start =
+               seprintf(start, end,
+                                " tlvt %#8.8p lint0 %#8.8p lint1 %#8.8p siv %#8.8p\n",
+                                apicrget(Tlvt), apicrget(Lint0), apicrget(Lint1),
+                                apicrget(Siv));
        return start;
 }
 
        return start;
 }
 
-char *
-apicdump(char *start, char *end)
+char *apicdump(char *start, char *end)
 {
        int i;
 
 {
        int i;
 
-       if(!2)
+       if (!2)
                return start;
 
                return start;
 
-       start = seprintf(start, end, "apicbase %#p apmachno %d\n", apicbase, apmachno);
-       for(i = 0; i < Napic; i++)
+       start =
+               seprintf(start, end, "apicbase %#p apmachno %d\n", apicbase, apmachno);
+       for (i = 0; i < Napic; i++)
                start = apicdump0(start, end, xlapic + i, i);
        /* endxioapic?
                start = apicdump0(start, end, xlapic + i, i);
        /* endxioapic?
-       for(i = 0; i < Napic; i++)
-               start = apicdump0(start, endxioapic + i, i);
-       */
+          for(i = 0; i < Napic; i++)
+          start = apicdump0(start, endxioapic + i, i);
+        */
        return start;
 }
        return start;
 }
+
 #if 0
 #if 0
-static void
-apictimer(Ureg* ureg, void*)
+static void apictimer(Ureg * ureg, void *)
 {
        timerintr(ureg, 0);
 }
 
 #endif
 {
        timerintr(ureg, 0);
 }
 
 #endif
-int
-apiconline(void)
+int apiconline(void)
 {
        struct apic *apic;
        uint64_t tsc;
        uint32_t dfr, ver;
        int apicno, nlvt;
 
 {
        struct apic *apic;
        uint64_t tsc;
        uint32_t dfr, ver;
        int apicno, nlvt;
 
-       if(apicbase == NULL)
+       if (apicbase == NULL)
                return 0;
                return 0;
-       if((apicno = ((apicrget(Id)>>24) & 0xff)) >= Napic)
+       if ((apicno = ((apicrget(Id) >> 24) & 0xff)) >= Napic)
                return 0;
        apic = &xlapic[apicno];
                return 0;
        apic = &xlapic[apicno];
-       if(!apic->useable || apic->addr != NULL)
+       if (!apic->useable || apic->addr != NULL)
                return 0;
 
        /*
                return 0;
 
        /*
@@ -260,10 +254,10 @@ apiconline(void)
         * processor.
         */
        ver = apicrget(Ver);
         * processor.
         */
        ver = apicrget(Ver);
-       nlvt = ((ver>>16) & 0xff) + 1;
-       if(nlvt > ARRAY_SIZE(apic->lvt)){
+       nlvt = ((ver >> 16) & 0xff) + 1;
+       if (nlvt > ARRAY_SIZE(apic->lvt)) {
                printk("apiconline%d: nlvt %d > max (%d)\n",
                printk("apiconline%d: nlvt %d > max (%d)\n",
-                       apicno, nlvt, ARRAY_SIZE(apic->lvt));
+                          apicno, nlvt, ARRAY_SIZE(apic->lvt));
                nlvt = ARRAY_SIZE(apic->lvt);
        }
        apic->nlvt = nlvt;
                nlvt = ARRAY_SIZE(apic->lvt);
        }
        apic->nlvt = nlvt;
@@ -272,11 +266,11 @@ apiconline(void)
        /*
         * These don't really matter in Physical mode;
         * set the defaults anyway.
        /*
         * These don't really matter in Physical mode;
         * set the defaults anyway.
-       if(memcmp(m->cpuinfo, "AuthenticAMD", 12) == 0)
-               dfr = 0xf0000000;
-       else
+        if(memcmp(m->cpuinfo, "AuthenticAMD", 12) == 0)
+        dfr = 0xf0000000;
+        else
         */
         */
-               dfr = 0xffffffff;
+       dfr = 0xffffffff;
        apicrput(Df, dfr);
        apicrput(Ld, 0x00000000);
 
        apicrput(Df, dfr);
        apicrput(Ld, 0x00000000);
 
@@ -292,7 +286,7 @@ apiconline(void)
         * bits 3-0 0x0f unless the Extended Spurious Vector Enable bit
         * is set in the HyperTransport Transaction Control register.
         */
         * bits 3-0 0x0f unless the Extended Spurious Vector Enable bit
         * is set in the HyperTransport Transaction Control register.
         */
-       apicrput(Siv, Swen|IdtSPURIOUS);
+       apicrput(Siv, Swen | IdtSPURIOUS);
 
        /*
         * Acknowledge any outstanding interrupts.
 
        /*
         * Acknowledge any outstanding interrupts.
@@ -307,20 +301,20 @@ apiconline(void)
        apicrput(Tdc, DivX1);
        apicrput(Tlvt, Im);
        // system_timing.tsc_freq? is that valid yet?
        apicrput(Tdc, DivX1);
        apicrput(Tlvt, Im);
        // system_timing.tsc_freq? is that valid yet?
-       tsc = read_tsc() + 2*1024*(1048576/10) /*m->cpuhz/10*/ ;
+       tsc = read_tsc() + 2 * 1024 * (1048576 / 10) /*m->cpuhz/10 */ ;
        apicrput(Tic, 0xffffffff);
 
        apicrput(Tic, 0xffffffff);
 
-       while(read_tsc() < tsc)
-               ;
+       while (read_tsc() < tsc) ;
 #define HZ 60
 #define HZ 60
-       apic->hz = (0xffffffff-apicrget(Tcc))*10;
-       apic->max = apic->hz/HZ;
-       apic->min = apic->hz/(100*HZ);
-       apic->div = ((2ULL*1024*1048576 /*m->cpuhz*/ /apic->max)+HZ/2)/HZ;
+       apic->hz = (0xffffffff - apicrget(Tcc)) * 10;
+       apic->max = apic->hz / HZ;
+       apic->min = apic->hz / (100 * HZ);
+       apic->div =
+               ((2ULL * 1024 * 1048576 /*m->cpuhz */  / apic->max) + HZ / 2) / HZ;
 
 
-       if(/*m->machno == 0 ||*/ 2){
+       if ( /*m->machno == 0 || */ 2) {
                printk("apic%d: hz %lld max %lld min %lld div %lld\n", apicno,
                printk("apic%d: hz %lld max %lld min %lld div %lld\n", apicno,
-                       apic->hz, apic->max, apic->min, apic->div);
+                          apic->hz, apic->max, apic->min, apic->div);
        }
 
        /*
        }
 
        /*
@@ -330,18 +324,16 @@ apiconline(void)
         * Clear any Error Status (write followed by read) and enable
         * the Error interrupt.
         */
         * Clear any Error Status (write followed by read) and enable
         * the Error interrupt.
         */
-       switch(apic->nlvt){
-       case 6:
-               apicrput(Tslvt, Im);
-               /*FALLTHROUGH*/
-       case 5:
-               apicrput(Pclvt, Im);
-               /*FALLTHROUGH*/
-       default:
-               break;
+       switch (apic->nlvt) {
+               case 6:
+                       apicrput(Tslvt, Im);
+                /*FALLTHROUGH*/ case 5:
+                       apicrput(Pclvt, Im);
+                /*FALLTHROUGH*/ default:
+                       break;
        }
        }
-       apicrput(Lint1, apic->lvt[1]|Im|IdtLINT1);
-       apicrput(Lint0, apic->lvt[0]|Im|IdtLINT0);
+       apicrput(Lint1, apic->lvt[1] | Im | IdtLINT1);
+       apicrput(Lint0, apic->lvt[0] | Im | IdtLINT0);
 
        apicrput(Es, 0);
        apicrget(Es);
 
        apicrput(Es, 0);
        apicrget(Es);
@@ -351,10 +343,10 @@ apiconline(void)
         * Issue an INIT Level De-Assert to synchronise arbitration ID's.
         * (Necessary in this implementation? - not if Pentium 4 or Xeon
         * (APIC Version >= 0x14), or AMD).
         * Issue an INIT Level De-Assert to synchronise arbitration ID's.
         * (Necessary in this implementation? - not if Pentium 4 or Xeon
         * (APIC Version >= 0x14), or AMD).
-       apicrput(Ichi, 0);
-       apicrput(Iclo, DSallinc|Lassert|MTir);
-       while(apicrget(Iclo) & Ds)
-               ;
+        apicrput(Ichi, 0);
+        apicrput(Iclo, DSallinc|Lassert|MTir);
+        while(apicrget(Iclo) & Ds)
+        ;
         */
 
 #warning "not reloading the timer"
         */
 
 #warning "not reloading the timer"
@@ -362,18 +354,17 @@ apiconline(void)
         * Reload the timer to de-synchronise the processors,
         * then lower the task priority to allow interrupts to be
         * accepted by the APIC.
         * Reload the timer to de-synchronise the processors,
         * then lower the task priority to allow interrupts to be
         * accepted by the APIC.
-       microdelay((TK2MS(1)*1000/apmachno) * m->machno);
+        microdelay((TK2MS(1)*1000/apmachno) * m->machno);
         */
 
 #if 0
         */
 
 #if 0
-       if(apic->machno == 0){
+       if (apic->machno == 0) {
                apicrput(Tic, apic->max);
                intrenable(IdtTIMER, apictimer, 0, -1, "APIC timer");
                apicrput(Tic, apic->max);
                intrenable(IdtTIMER, apictimer, 0, -1, "APIC timer");
-               apicrput(Tlvt, Periodic|IrqTIMER);
+               apicrput(Tlvt, Periodic | IrqTIMER);
        }
        }
-
 #endif
 #endif
-       if(node_id() /*m->machno*/ == 0)
+       if (node_id() /*m->machno */  == 0)
                apicrput(Tp, 0);
 
 #warning "map from apicno to cpu info not installed"
                apicrput(Tp, 0);
 
 #warning "map from apicno to cpu info not installed"
@@ -387,39 +378,37 @@ apiconline(void)
 
 #if 0
 /* To start timers on TCs as part of the boot process. */
 
 #if 0
 /* To start timers on TCs as part of the boot process. */
-void
-apictimerenab(void)
+void apictimerenab(void)
 {
        struct apic *apic;
 
 {
        struct apic *apic;
 
-       apic = &xlapic[(apicrget(Id)>>24) & 0xff];
+       apic = &xlapic[(apicrget(Id) >> 24) & 0xff];
 
        apiceoi(IdtTIMER);
        apicrput(Tic, apic->max);
 
        apiceoi(IdtTIMER);
        apicrput(Tic, apic->max);
-       apicrput(Tlvt, Periodic|IrqTIMER);
+       apicrput(Tlvt, Periodic | IrqTIMER);
 
 }
 
 
 }
 
-void
-apictimerset(uint64_t next)
+void apictimerset(uint64_t next)
 {
        Mpl pl;
        struct apic *apic;
        int64_t period;
 
 {
        Mpl pl;
        struct apic *apic;
        int64_t period;
 
-       apic = &xlapic[(apicrget(Id)>>24) & 0xff];
+       apic = &xlapic[(apicrget(Id) >> 24) & 0xff];
 
        pl = splhi();
        spin_lock(&(&m->apictimerlock)->lock);
 
        period = apic->max;
 
        pl = splhi();
        spin_lock(&(&m->apictimerlock)->lock);
 
        period = apic->max;
-       if(next != 0){
+       if (next != 0) {
                period = next - fastticks(NULL);        /* fastticks is just rdtsc() */
                period /= apic->div;
 
                period = next - fastticks(NULL);        /* fastticks is just rdtsc() */
                period /= apic->div;
 
-               if(period < apic->min)
+               if (period < apic->min)
                        period = apic->min;
                        period = apic->min;
-               else if(period > apic->max - apic->min)
+               else if (period > apic->max - apic->min)
                        period = apic->max;
        }
        apicrput(Tic, period);
                        period = apic->max;
        }
        apicrput(Tic, period);
@@ -428,8 +417,7 @@ apictimerset(uint64_t next)
        splx(pl);
 }
 
        splx(pl);
 }
 
-void
-apicsipi(int apicno, uintptr_t pa)
+void apicsipi(int apicno, uintptr_t pa)
 {
        int i;
        uint32_t crhi, crlo;
 {
        int i;
        uint32_t crhi, crlo;
@@ -438,32 +426,29 @@ apicsipi(int apicno, uintptr_t pa)
         * SIPI - Start-up IPI.
         * To do: checks on apic validity.
         */
         * SIPI - Start-up IPI.
         * To do: checks on apic validity.
         */
-       crhi = apicno<<24;
+       crhi = apicno << 24;
        apicrput(Ichi, crhi);
        apicrput(Ichi, crhi);
-       apicrput(Iclo, DSnone|TMlevel|Lassert|MTir);
+       apicrput(Iclo, DSnone | TMlevel | Lassert | MTir);
        microdelay(200);
        microdelay(200);
-       apicrput(Iclo, DSnone|TMlevel|MTir);
+       apicrput(Iclo, DSnone | TMlevel | MTir);
        millidelay(10);
 
        millidelay(10);
 
-       crlo = DSnone|TMedge|MTsipi|((uint32_t)pa/(4*KiB));
-       for(i = 0; i < 2; i++){
+       crlo = DSnone | TMedge | MTsipi | ((uint32_t) pa / (4 * KiB));
+       for (i = 0; i < 2; i++) {
                apicrput(Ichi, crhi);
                apicrput(Iclo, crlo);
                microdelay(200);
        }
 }
 
                apicrput(Ichi, crhi);
                apicrput(Iclo, crlo);
                microdelay(200);
        }
 }
 
-void
-apicipi(int apicno)
+void apicipi(int apicno)
 {
 {
-       apicrput(Ichi, apicno<<24);
-       apicrput(Iclo, DSnone|TMedge|Lassert|MTf|IdtIPI);
-       while(apicrget(Iclo) & Ds)
-               ;
+       apicrput(Ichi, apicno << 24);
+       apicrput(Iclo, DSnone | TMedge | Lassert | MTf | IdtIPI);
+       while (apicrget(Iclo) & Ds) ;
 }
 
 }
 
-void
-apicpri(int pri)
+void apicpri(int pri)
 {
        apicrput(Tp, pri);
 }
 {
        apicrput(Tp, pri);
 }
index 7c60738..5de6de8 100644 (file)
 #include <time.h>
 
 typedef struct IOMap IOMap;
 #include <time.h>
 
 typedef struct IOMap IOMap;
-struct IOMap
-{
-       IOMap   *next;
-       int     reserved;
-       char    tag[13];
-       uint32_t        start;
-       uint32_t        end;
+struct IOMap {
+       IOMap *next;
+       int reserved;
+       char tag[13];
+       uint32_t start;
+       uint32_t end;
 };
 
 };
 
-static struct
-{
+static struct {
        spinlock_t lock;
        spinlock_t lock;
-       IOMap   *map;
-       IOMap   *free;
-       IOMap   maps[32];               // some initial free maps
+       IOMap *map;
+       IOMap *free;
+       IOMap maps[32];                         // some initial free maps
 
 
-       qlock_t ql;                     // lock for reading map
+       qlock_t ql;                                     // lock for reading map
 } iomap;
 
 enum {
 } iomap;
 
 enum {
@@ -56,22 +54,23 @@ enum {
        Qmax = 16,
 };
 
        Qmax = 16,
 };
 
-typedef long Rdwrfn(struct chan*, void*, long, int64_t);
+typedef long Rdwrfn(struct chan *, void *, long, int64_t);
 
 static Rdwrfn *readfn[Qmax];
 static Rdwrfn *writefn[Qmax];
 
 static struct dirtab archdir[Qmax] = {
 
 static Rdwrfn *readfn[Qmax];
 static Rdwrfn *writefn[Qmax];
 
 static struct dirtab archdir[Qmax] = {
-       {".",           { Qdir, 0, QTDIR },     0,      0555},
-       {"ioalloc",     { Qioalloc, 0 },        0,      0444},
-       {"iob",         { Qiob, 0 },            0,      0660},
-       {"iow",         { Qiow, 0 },            0,      0660},
-       {"iol",         { Qiol, 0 },            0,      0660},
-       {"gdb",         { Qgdb, 0},             0,      0660},
-       {"mapram",      { Qmapram, 0 }, 0,      0444},
-       {"realmodemem", { Qrealmem, 0 },        0,      0660},
+       {".", {Qdir, 0, QTDIR}, 0, 0555},
+       {"ioalloc", {Qioalloc, 0}, 0, 0444},
+       {"iob", {Qiob, 0}, 0, 0660},
+       {"iow", {Qiow, 0}, 0, 0660},
+       {"iol", {Qiol, 0}, 0, 0660},
+       {"gdb", {Qgdb, 0}, 0, 0660},
+       {"mapram", {Qmapram, 0}, 0, 0444},
+       {"realmodemem", {Qrealmem, 0}, 0, 0660},
 };
 };
-spinlock_t archwlock;  /* the lock is only for changing archdir */
+
+spinlock_t archwlock;                  /* the lock is only for changing archdir */
 int narchdir = Qbase;
 int gdbactive = 0;
 
 int narchdir = Qbase;
 int gdbactive = 0;
 
@@ -81,25 +80,24 @@ int gdbactive = 0;
  * and you get a pointer to the Dirtab entry so you can do things
  * like change the Qid version.  Changing the Qid path is disallowed.
  */
  * and you get a pointer to the Dirtab entry so you can do things
  * like change the Qid version.  Changing the Qid path is disallowed.
  */
-struct dirtab*
-addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
+struct dirtab *addarchfile(char *name, int perm, Rdwrfn * rdfn, Rdwrfn * wrfn)
 {
        int i;
        struct dirtab d;
        struct dirtab *dp;
 
        memset(&d, 0, sizeof d);
 {
        int i;
        struct dirtab d;
        struct dirtab *dp;
 
        memset(&d, 0, sizeof d);
-       strncpy(d.name,  name, sizeof(d.name));
+       strncpy(d.name, name, sizeof(d.name));
        d.perm = perm;
 
        spin_lock(&archwlock);
        d.perm = perm;
 
        spin_lock(&archwlock);
-       if(narchdir >= Qmax){
+       if (narchdir >= Qmax) {
                spin_unlock(&archwlock);
                return NULL;
        }
 
                spin_unlock(&archwlock);
                return NULL;
        }
 
-       for(i=0; i<narchdir; i++)
-               if(strcmp(archdir[i].name, name) == 0){
+       for (i = 0; i < narchdir; i++)
+               if (strcmp(archdir[i].name, name) == 0) {
                        spin_unlock(&archwlock);
                        return NULL;
                }
                        spin_unlock(&archwlock);
                        return NULL;
                }
@@ -114,35 +112,34 @@ addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
        return dp;
 }
 
        return dp;
 }
 
-void
-ioinit(void)
+void ioinit(void)
 {
        int i;
        char *excluded = "";
 
 {
        int i;
        char *excluded = "";
 
-       for(i = 0; i < ARRAY_SIZE(iomap.maps)-1; i++)
-               iomap.maps[i].next = &iomap.maps[i+1];
+       for (i = 0; i < ARRAY_SIZE(iomap.maps) - 1; i++)
+               iomap.maps[i].next = &iomap.maps[i + 1];
        iomap.maps[i].next = NULL;
        iomap.free = iomap.maps;
        char *s;
        iomap.maps[i].next = NULL;
        iomap.free = iomap.maps;
        char *s;
-       
+
        s = excluded;
        while (s && *s != '\0' && *s != '\n') {
                char *ends;
                int io_s, io_e;
        s = excluded;
        while (s && *s != '\0' && *s != '\n') {
                char *ends;
                int io_s, io_e;
-               
+
                io_s = (int)strtol(s, &ends, 0);
                if (ends == NULL || ends == s || *ends != '-') {
                        printd("ioinit: cannot parse option string\n");
                        break;
                }
                s = ++ends;
                io_s = (int)strtol(s, &ends, 0);
                if (ends == NULL || ends == s || *ends != '-') {
                        printd("ioinit: cannot parse option string\n");
                        break;
                }
                s = ++ends;
-               
+
                io_e = (int)strtol(s, &ends, 0);
                if (ends && *ends == ',')
                        *ends++ = '\0';
                s = ends;
                io_e = (int)strtol(s, &ends, 0);
                if (ends && *ends == ',')
                        *ends++ = '\0';
                s = ends;
-               
+
 #warning "how do we do io allocate"
                //ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
        }
 #warning "how do we do io allocate"
                //ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
        }
@@ -151,8 +148,7 @@ ioinit(void)
 // Reserve a range to be ioalloced later.
 // This is in particular useful for exchangable cards, such
 // as pcmcia and cardbus cards.
 // Reserve a range to be ioalloced later.
 // This is in particular useful for exchangable cards, such
 // as pcmcia and cardbus cards.
-int
-ioreserve( int unused_int, int size, int align, char *tag)
+int ioreserve(int unused_int, int size, int align, char *tag)
 {
        IOMap *map, **l;
        int i, port;
 {
        IOMap *map, **l;
        int i, port;
@@ -160,24 +156,24 @@ ioreserve( int unused_int, int size, int align, char *tag)
        spin_lock(&(&iomap)->lock);
        // find a free port above 0x400 and below 0x1000
        port = 0x400;
        spin_lock(&(&iomap)->lock);
        // find a free port above 0x400 and below 0x1000
        port = 0x400;
-       for(l = &iomap.map; *l; l = &(*l)->next){
+       for (l = &iomap.map; *l; l = &(*l)->next) {
                map = *l;
                if (map->start < 0x400)
                        continue;
                i = map->start - port;
                map = *l;
                if (map->start < 0x400)
                        continue;
                i = map->start - port;
-               if(i > size)
+               if (i > size)
                        break;
                        break;
-               if(align > 0)
-                       port = ((port+align-1)/align)*align;
+               if (align > 0)
+                       port = ((port + align - 1) / align) * align;
                else
                        port = map->end;
        }
                else
                        port = map->end;
        }
-       if(*l == NULL){
+       if (*l == NULL) {
                spin_unlock(&(&iomap)->lock);
                return -1;
        }
        map = iomap.free;
                spin_unlock(&(&iomap)->lock);
                return -1;
        }
        map = iomap.free;
-       if(map == NULL){
+       if (map == NULL) {
                printd("ioalloc: out of maps");
                spin_unlock(&(&iomap)->lock);
                return port;
                printd("ioalloc: out of maps");
                spin_unlock(&(&iomap)->lock);
                return port;
@@ -188,7 +184,7 @@ ioreserve( int unused_int, int size, int align, char *tag)
        map->end = port + size;
        map->reserved = 1;
        strncpy(map->tag, tag, sizeof(map->tag));
        map->end = port + size;
        map->reserved = 1;
        strncpy(map->tag, tag, sizeof(map->tag));
-       map->tag[sizeof(map->tag)-1] = 0;
+       map->tag[sizeof(map->tag) - 1] = 0;
        *l = map;
 
        archdir[0].qid.vers++;
        *l = map;
 
        archdir[0].qid.vers++;
@@ -198,59 +194,58 @@ ioreserve( int unused_int, int size, int align, char *tag)
 }
 
 //
 }
 
 //
-//     alloc some io port space and remember who it was
-//     alloced to.  if port < 0, find a free region.
+//  alloc some io port space and remember who it was
+//  alloced to.  if port < 0, find a free region.
 //
 //
-int
-ioalloc(int port, int size, int align, char *tag)
+int ioalloc(int port, int size, int align, char *tag)
 {
        IOMap *map, **l;
        int i;
 
        spin_lock(&(&iomap)->lock);
 {
        IOMap *map, **l;
        int i;
 
        spin_lock(&(&iomap)->lock);
-       if(port < 0){
+       if (port < 0) {
                // find a free port above 0x400 and below 0x1000
                port = 0x400;
                // find a free port above 0x400 and below 0x1000
                port = 0x400;
-               for(l = &iomap.map; *l; l = &(*l)->next){
+               for (l = &iomap.map; *l; l = &(*l)->next) {
                        map = *l;
                        if (map->start < 0x400)
                                continue;
                        i = map->start - port;
                        map = *l;
                        if (map->start < 0x400)
                                continue;
                        i = map->start - port;
-                       if(i > size)
+                       if (i > size)
                                break;
                                break;
-                       if(align > 0)
-                               port = ((port+align-1)/align)*align;
+                       if (align > 0)
+                               port = ((port + align - 1) / align) * align;
                        else
                                port = map->end;
                }
                        else
                                port = map->end;
                }
-               if(*l == NULL){
+               if (*l == NULL) {
                        spin_unlock(&(&iomap)->lock);
                        return -1;
                }
        } else {
                // Only 64KB I/O space on the x86.
                        spin_unlock(&(&iomap)->lock);
                        return -1;
                }
        } else {
                // Only 64KB I/O space on the x86.
-               if((port+size) > 0x10000){
+               if ((port + size) > 0x10000) {
                        spin_unlock(&(&iomap)->lock);
                        return -1;
                }
                // see if the space clashes with previously allocated ports
                        spin_unlock(&(&iomap)->lock);
                        return -1;
                }
                // see if the space clashes with previously allocated ports
-               for(l = &iomap.map; *l; l = &(*l)->next){
+               for (l = &iomap.map; *l; l = &(*l)->next) {
                        map = *l;
                        map = *l;
-                       if(map->end <= port)
+                       if (map->end <= port)
                                continue;
                                continue;
-                       if(map->reserved && map->start == port && map->end == port + size) {
+                       if (map->reserved && map->start == port && map->end == port + size) {
                                map->reserved = 0;
                                spin_unlock(&(&iomap)->lock);
                                return map->start;
                        }
                                map->reserved = 0;
                                spin_unlock(&(&iomap)->lock);
                                return map->start;
                        }
-                       if(map->start >= port+size)
+                       if (map->start >= port + size)
                                break;
                        spin_unlock(&(&iomap)->lock);
                        return -1;
                }
        }
        map = iomap.free;
                                break;
                        spin_unlock(&(&iomap)->lock);
                        return -1;
                }
        }
        map = iomap.free;
-       if(map == NULL){
+       if (map == NULL) {
                printd("ioalloc: out of maps");
                spin_unlock(&(&iomap)->lock);
                return port;
                printd("ioalloc: out of maps");
                spin_unlock(&(&iomap)->lock);
                return port;
@@ -260,7 +255,7 @@ ioalloc(int port, int size, int align, char *tag)
        map->start = port;
        map->end = port + size;
        strncpy(map->tag, tag, sizeof(map->tag));
        map->start = port;
        map->end = port + size;
        strncpy(map->tag, tag, sizeof(map->tag));
-       map->tag[sizeof(map->tag)-1] = 0;
+       map->tag[sizeof(map->tag) - 1] = 0;
        *l = map;
 
        archdir[0].qid.vers++;
        *l = map;
 
        archdir[0].qid.vers++;
@@ -269,90 +264,81 @@ ioalloc(int port, int size, int align, char *tag)
        return map->start;
 }
 
        return map->start;
 }
 
-void
-iofree(int port)
+void iofree(int port)
 {
        IOMap *map, **l;
 
        spin_lock(&(&iomap)->lock);
 {
        IOMap *map, **l;
 
        spin_lock(&(&iomap)->lock);
-       for(l = &iomap.map; *l; l = &(*l)->next){
-               if((*l)->start == port){
+       for (l = &iomap.map; *l; l = &(*l)->next) {
+               if ((*l)->start == port) {
                        map = *l;
                        *l = map->next;
                        map->next = iomap.free;
                        iomap.free = map;
                        break;
                }
                        map = *l;
                        *l = map->next;
                        map->next = iomap.free;
                        iomap.free = map;
                        break;
                }
-               if((*l)->start > port)
+               if ((*l)->start > port)
                        break;
        }
        archdir[0].qid.vers++;
        spin_unlock(&(&iomap)->lock);
 }
 
                        break;
        }
        archdir[0].qid.vers++;
        spin_unlock(&(&iomap)->lock);
 }
 
-int
-iounused(int start, int end)
+int iounused(int start, int end)
 {
        IOMap *map;
 
 {
        IOMap *map;
 
-       for(map = iomap.map; map; map = map->next){
-               if(((start >= map->start) && (start < map->end))
-                  || ((start <= map->start) && (end > map->start)))
+       for (map = iomap.map; map; map = map->next) {
+               if (((start >= map->start) && (start < map->end))
+                       || ((start <= map->start) && (end > map->start)))
                        return 0;
        }
        return 1;
 }
 
                        return 0;
        }
        return 1;
 }
 
-static void
-checkport(int start, int end)
+static void checkport(int start, int end)
 {
        /* standard vga regs are OK */
 {
        /* standard vga regs are OK */
-       if(start >= 0x2b0 && end <= 0x2df+1)
+       if (start >= 0x2b0 && end <= 0x2df + 1)
                return;
                return;
-       if(start >= 0x3c0 && end <= 0x3da+1)
+       if (start >= 0x3c0 && end <= 0x3da + 1)
                return;
 
                return;
 
-       if(iounused(start, end))
+       if (iounused(start, end))
                return;
        error(Eperm);
 }
 
                return;
        error(Eperm);
 }
 
-static struct chan*
-archattach(char* spec)
+static struct chan *archattach(char *spec)
 {
        return devattach('P', spec);
 }
 
 {
        return devattach('P', spec);
 }
 
-struct walkqid*
-archwalk(struct chan* c, struct chan *nc, char** name, int nname)
+struct walkqid *archwalk(struct chan *c, struct chan *nc, char **name,
+                                                int nname)
 {
        return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
 }
 
 {
        return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
 }
 
-static int
-archstat(struct chan* c, uint8_t* dp, int n)
+static int archstat(struct chan *c, uint8_t * dp, int n)
 {
        return devstat(c, dp, n, archdir, narchdir, devgen);
 }
 
 {
        return devstat(c, dp, n, archdir, narchdir, devgen);
 }
 
-static struct chan*
-archopen(struct chan* c, int omode)
+static struct chan *archopen(struct chan *c, int omode)
 {
        return devopen(c, omode, archdir, narchdir, devgen);
 }
 
 {
        return devopen(c, omode, archdir, narchdir, devgen);
 }
 
-static void
-archclose(struct chan*unused)
+static void archclose(struct chan *unused)
 {
 }
 
 {
 }
 
-enum
-{
-       Linelen= 31,
+enum {
+       Linelen = 31,
 };
 
 };
 
-static long
-archread(struct chan *c, void *a, long n, int64_t offset)
+static long archread(struct chan *c, void *a, long n, int64_t offset)
 {
        char *buf, *p;
        int port;
 {
        char *buf, *p;
        int port;
@@ -361,70 +347,71 @@ archread(struct chan *c, void *a, long n, int64_t offset)
        IOMap *map;
        Rdwrfn *fn;
 
        IOMap *map;
        Rdwrfn *fn;
 
-       switch((uint32_t)c->qid.path){
-
-       case Qdir:
-               return devdirread(c, a, n, archdir, narchdir, devgen);
-
-       case Qgdb:
-               p = gdbactive ? "1" : "0";
-               return readstr(offset, a, n, p);
-       case Qiob:
-               port = offset;
-               checkport(offset, offset+n);
-               for(p = a; port < offset+n; port++)
-                       *p++ = inb(port);
-               return n;
-
-       case Qiow:
-               if(n & 1)
-                       error(Ebadarg);
-               checkport(offset, offset+n);
-               sp = a;
-               for(port = offset; port < offset+n; port += 2)
-                       *sp++ = inw(port);
-               return n;
-
-       case Qiol:
-               if(n & 3)
-                       error(Ebadarg);
-               checkport(offset, offset+n);
-               lp = a;
-               for(port = offset; port < offset+n; port += 4)
-                       *lp++ = inl(port);
-               return n;
-
-       case Qioalloc:
-               break;
-
-       default:
-               if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
-                       return fn(c, a, n, offset);
-               error(Eperm);
-               break;
+       switch ((uint32_t) c->qid.path) {
+
+               case Qdir:
+                       return devdirread(c, a, n, archdir, narchdir, devgen);
+
+               case Qgdb:
+                       p = gdbactive ? "1" : "0";
+                       return readstr(offset, a, n, p);
+               case Qiob:
+                       port = offset;
+                       checkport(offset, offset + n);
+                       for (p = a; port < offset + n; port++)
+                               *p++ = inb(port);
+                       return n;
+
+               case Qiow:
+                       if (n & 1)
+                               error(Ebadarg);
+                       checkport(offset, offset + n);
+                       sp = a;
+                       for (port = offset; port < offset + n; port += 2)
+                               *sp++ = inw(port);
+                       return n;
+
+               case Qiol:
+                       if (n & 3)
+                               error(Ebadarg);
+                       checkport(offset, offset + n);
+                       lp = a;
+                       for (port = offset; port < offset + n; port += 4)
+                               *lp++ = inl(port);
+                       return n;
+
+               case Qioalloc:
+                       break;
+
+               default:
+                       if (c->qid.path < narchdir && (fn = readfn[c->qid.path]))
+                               return fn(c, a, n, offset);
+                       error(Eperm);
+                       break;
        }
 
        }
 
-       if((buf = kzmalloc(n, 0)) == NULL)
+       if ((buf = kzmalloc(n, 0)) == NULL)
                error(Enomem);
        p = buf;
                error(Enomem);
        p = buf;
-       n = n/Linelen;
-       offset = offset/Linelen;
-
-       switch((uint32_t)c->qid.path){
-       case Qioalloc:
-               spin_lock(&(&iomap)->lock);
-               for(map = iomap.map; n > 0 && map != NULL; map = map->next){
-                       if(offset-- > 0)
-                               continue;
-                       snprintf(p, n*Linelen, "%#8p %#8p %-12.12s\n", map->start, map->end-1, map->tag);
-                       p += Linelen;
-                       n--;
-               }
-               spin_unlock(&(&iomap)->lock);
-               break;
-       case Qmapram:
-               error("Not yet");
-               break;
+       n = n / Linelen;
+       offset = offset / Linelen;
+
+       switch ((uint32_t) c->qid.path) {
+               case Qioalloc:
+                       spin_lock(&(&iomap)->lock);
+                       for (map = iomap.map; n > 0 && map != NULL; map = map->next) {
+                               if (offset-- > 0)
+                                       continue;
+                               snprintf(p, n * Linelen, "%#8p %#8p %-12.12s\n", map->start,
+                                                map->end - 1, map->tag);
+                               p += Linelen;
+                               n--;
+                       }
+                       spin_unlock(&(&iomap)->lock);
+                       break;
+               case Qmapram:
+                       error("Not yet");
+                       break;
        }
 
        n = p - buf;
        }
 
        n = p - buf;
@@ -434,8 +421,7 @@ archread(struct chan *c, void *a, long n, int64_t offset)
        return n;
 }
 
        return n;
 }
 
-static long
-archwrite(struct chan *c, void *a, long n, int64_t offset)
+static long archwrite(struct chan *c, void *a, long n, int64_t offset)
 {
        char *p;
        int port;
 {
        char *p;
        int port;
@@ -443,50 +429,50 @@ archwrite(struct chan *c, void *a, long n, int64_t offset)
        uint32_t *lp;
        Rdwrfn *fn;
 
        uint32_t *lp;
        Rdwrfn *fn;
 
-       switch((uint32_t)c->qid.path){
+       switch ((uint32_t) c->qid.path) {
 
 
-       case Qgdb:
-               p = a;
-               if (n != 1)
-                       error("Gdb: Write one byte, '1' or '0'");
-               if (*p == '1')
-                       gdbactive = 1;
-               else if (*p == '0')
-                       gdbactive = 0;
-               else
-                       error("Gdb: must be 1 or 0");
-               return 1;
-
-       case Qiob:
-               p = a;
-               checkport(offset, offset+n);
-               for(port = offset; port < offset+n; port++)
-                       outb(port, *p++);
-               return n;
-
-       case Qiow:
-               if(n & 1)
-                       error(Ebadarg);
-               checkport(offset, offset+n);
-               sp = a;
-               for(port = offset; port < offset+n; port += 2)
-                       outw(port, *sp++);
-               return n;
-
-       case Qiol:
-               if(n & 3)
-                       error(Ebadarg);
-               checkport(offset, offset+n);
-               lp = a;
-               for(port = offset; port < offset+n; port += 4)
-                       outl(port, *lp++);
-               return n;
-
-       default:
-               if(c->qid.path < narchdir && (fn = writefn[c->qid.path]))
-                       return fn(c, a, n, offset);
-               error(Eperm);
-               break;
+               case Qgdb:
+                       p = a;
+                       if (n != 1)
+                               error("Gdb: Write one byte, '1' or '0'");
+                       if (*p == '1')
+                               gdbactive = 1;
+                       else if (*p == '0')
+                               gdbactive = 0;
+                       else
+                               error("Gdb: must be 1 or 0");
+                       return 1;
+
+               case Qiob:
+                       p = a;
+                       checkport(offset, offset + n);
+                       for (port = offset; port < offset + n; port++)
+                               outb(port, *p++);
+                       return n;
+
+               case Qiow:
+                       if (n & 1)
+                               error(Ebadarg);
+                       checkport(offset, offset + n);
+                       sp = a;
+                       for (port = offset; port < offset + n; port += 2)
+                               outw(port, *sp++);
+                       return n;
+
+               case Qiol:
+                       if (n & 3)
+                               error(Ebadarg);
+                       checkport(offset, offset + n);
+                       lp = a;
+                       for (port = offset; port < offset + n; port += 4)
+                               outl(port, *lp++);
+                       return n;
+
+               default:
+                       if (c->qid.path < narchdir && (fn = writefn[c->qid.path]))
+                               return fn(c, a, n, offset);
+                       error(Eperm);
+                       break;
        }
        return 0;
 }
        }
        return 0;
 }
@@ -514,8 +500,7 @@ struct dev archdevtab = {
 
 /*
  */
 
 /*
  */
-void
-nop(void)
+void nop(void)
 {
 }
 
 {
 }
 
@@ -523,74 +508,66 @@ nop(void)
 #warning "need memory fence"
 #define coherence()
 
 #warning "need memory fence"
 #define coherence()
 
-
-static long
-cputyperead(struct chan*unused, void *a, long n, int64_t off)
+static long cputyperead(struct chan *unused, void *a, long n, int64_t off)
 {
        char buf[512], *s, *e;
        int i, k;
        error("unimplemented");
 #if 0
 {
        char buf[512], *s, *e;
        int i, k;
        error("unimplemented");
 #if 0
-       e = buf+sizeof buf;
+       e = buf + sizeof buf;
        s = seprintf(buf, e, "%s %d\n", "AMD64", 0);
        k = m->ncpuinfoe - m->ncpuinfos;
        s = seprintf(buf, e, "%s %d\n", "AMD64", 0);
        k = m->ncpuinfoe - m->ncpuinfos;
-       if(k > 4)
+       if (k > 4)
                k = 4;
                k = 4;
-       for(i = 0; i < k; i++)
+       for (i = 0; i < k; i++)
                s = seprintf(s, e, "%#8.8ux %#8.8ux %#8.8ux %#8.8ux\n",
                s = seprintf(s, e, "%#8.8ux %#8.8ux %#8.8ux %#8.8ux\n",
-                       m->cpuinfo[i][0], m->cpuinfo[i][1],
-                       m->cpuinfo[i][2], m->cpuinfo[i][3]);
+                                        m->cpuinfo[i][0], m->cpuinfo[i][1],
+                                        m->cpuinfo[i][2], m->cpuinfo[i][3]);
        return readstr(off, a, n, buf);
 #endif
 }
 
        return readstr(off, a, n, buf);
 #endif
 }
 
-
-static long
-rmemrw(int isr, void *a, long n, int64_t off)
+static long rmemrw(int isr, void *a, long n, int64_t off)
 {
 {
-       if(off < 0)
+       if (off < 0)
                error("offset must be >= 0");
                error("offset must be >= 0");
-       if(n < 0)
+       if (n < 0)
                error("count must be >= 0");
                error("count must be >= 0");
-       if(isr){
-               if(off >= MB)
+       if (isr) {
+               if (off >= MB)
                        error("offset must be < 1MB");
                        error("offset must be < 1MB");
-               if(off+n >= MB)
+               if (off + n >= MB)
                        n = MB - off;
                        n = MB - off;
-               memmove(a, KADDR((uint32_t)off), n);
+               memmove(a, KADDR((uint32_t) off), n);
        } else {
                /* realmode buf page ok, allow vga framebuf's access */
        } else {
                /* realmode buf page ok, allow vga framebuf's access */
-               if(off >= MB)
+               if (off >= MB)
                        error("offset must be < 1MB");
                        error("offset must be < 1MB");
-               if(off+n > MB && (off < 0xA0000 || off+n > 0xB0000+0x10000))
+               if (off + n > MB && (off < 0xA0000 || off + n > 0xB0000 + 0x10000))
                        error("bad offset/count in write");
                        error("bad offset/count in write");
-               memmove(KADDR((uint32_t)off), a, n);
+               memmove(KADDR((uint32_t) off), a, n);
        }
        return n;
 }
 
        }
        return n;
 }
 
-static long
-rmemread(struct chan*unused, void *a, long n, int64_t off)
+static long rmemread(struct chan *unused, void *a, long n, int64_t off)
 {
        return rmemrw(1, a, n, off);
 }
 
 {
        return rmemrw(1, a, n, off);
 }
 
-static long
-rmemwrite(struct chan*unused, void *a, long n, int64_t off)
+static long rmemwrite(struct chan *unused, void *a, long n, int64_t off)
 {
        return rmemrw(0, a, n, off);
 }
 
 {
        return rmemrw(0, a, n, off);
 }
 
-void
-archinit(void)
+void archinit(void)
 {
        spinlock_init(&archwlock);
        addarchfile("cputype", 0444, cputyperead, NULL);
        addarchfile("realmodemem", 0660, rmemread, rmemwrite);
 }
 
 {
        spinlock_init(&archwlock);
        addarchfile("cputype", 0444, cputyperead, NULL);
        addarchfile("realmodemem", 0660, rmemread, rmemwrite);
 }
 
-void
-archreset(void)
+void archreset(void)
 {
        int i;
 
 {
        int i;
 
@@ -600,15 +577,15 @@ archreset(void)
         * The reset register (0xcf9) is usually in one of the bridge
         * chips. The actual location and sequence could be extracted from
         * ACPI but why bother, this is the end of the line anyway.
         * The reset register (0xcf9) is usually in one of the bridge
         * chips. The actual location and sequence could be extracted from
         * ACPI but why bother, this is the end of the line anyway.
-       print("Takes a licking and keeps on ticking...\n");
+        print("Takes a licking and keeps on ticking...\n");
         */
         */
-       i = inb(0xcf9);                                 /* ICHx reset control */
+       i = inb(0xcf9); /* ICHx reset control */
        i &= 0x06;
        i &= 0x06;
-       outb(0xcf9, i|0x02);                            /* SYS_RST */
+       outb(0xcf9, i | 0x02);  /* SYS_RST */
        udelay(1000);
        udelay(1000);
-       outb(0xcf9, i|0x06);                            /* RST_CPU transition */
+       outb(0xcf9, i | 0x06);  /* RST_CPU transition */
 
 
-       udelay(100*1000);
+       udelay(100 * 1000);
 
        /* some broken hardware -- as well as qemu -- might
         * never reboot anyway with cf9. This is a standard
 
        /* some broken hardware -- as well as qemu -- might
         * never reboot anyway with cf9. This is a standard
@@ -616,10 +593,9 @@ archreset(void)
         * broken stuff -- like qemu. If there is no
         * keyboard it will do no harm.
         */
         * broken stuff -- like qemu. If there is no
         * keyboard it will do no harm.
         */
-       for(;;){
-               (void) inb(0x64);
+       for (;;) {
+               (void)inb(0x64);
                outb(0x64, 0xFE);
                outb(0x64, 0xFE);
-               udelay(100*1000);
+               udelay(100 * 1000);
        }
 }
        }
 }
-
index 38f70eb..086d2fd 100644 (file)
  */
 
 enum {
  */
 
 enum {
-       VectorNMI       = 2,            /* non-maskable interrupt */
-       VectorBPT       = 3,            /* breakpoint */
-       VectorUD        = 6,            /* invalid opcode exception */
-       VectorCNA       = 7,            /* coprocessor not available */
-       Vector2F        = 8,            /* double fault */
-       VectorCSO       = 9,            /* coprocessor segment overrun */
-       VectorPF        = 14,           /* page fault */
-       Vector15        = 15,           /* reserved */
-       VectorCERR      = 16,           /* coprocessor error */
-
-       VectorPIC       = 32,           /* external i8259 interrupts */
-       IrqCLOCK        = 0,
-       IrqKBD          = 1,
-       IrqUART1        = 3,
-       IrqUART0        = 4,
-       IrqPCMCIA       = 5,
-       IrqFLOPPY       = 6,
-       IrqLPT          = 7,
-       IrqIRQ7         = 7,
-       IrqAUX          = 12,           /* PS/2 port */
-       IrqIRQ13        = 13,           /* coprocessor on 386 */
-       IrqATA0         = 14,
-       IrqATA1         = 15,
-       MaxIrqPIC       = 15,
-
-       VectorLAPIC     = VectorPIC+16, /* local APIC interrupts */
-       IrqLINT0        = VectorLAPIC+0,
-       IrqLINT1        = VectorLAPIC+1,
-       IrqTIMER        = VectorLAPIC+2,
-       IrqERROR        = VectorLAPIC+3,
-       IrqPCINT        = VectorLAPIC+4,
-       IrqSPURIOUS     = VectorLAPIC+15,
-       MaxIrqLAPIC     = VectorLAPIC+15,
-
-       VectorSYSCALL   = 64,
-
-       VectorAPIC      = 65,           /* external APIC interrupts */
-       MaxVectorAPIC   = 255,
+       VectorNMI = 2,                          /* non-maskable interrupt */
+       VectorBPT = 3,  /* breakpoint */
+       VectorUD = 6,   /* invalid opcode exception */
+       VectorCNA = 7,  /* coprocessor not available */
+       Vector2F = 8,   /* double fault */
+       VectorCSO = 9,  /* coprocessor segment overrun */
+       VectorPF = 14,  /* page fault */
+       Vector15 = 15,  /* reserved */
+       VectorCERR = 16,        /* coprocessor error */
+
+       VectorPIC = 32, /* external i8259 interrupts */
+       IrqCLOCK = 0,
+       IrqKBD = 1,
+       IrqUART1 = 3,
+       IrqUART0 = 4,
+       IrqPCMCIA = 5,
+       IrqFLOPPY = 6,
+       IrqLPT = 7,
+       IrqIRQ7 = 7,
+       IrqAUX = 12,    /* PS/2 port */
+       IrqIRQ13 = 13,  /* coprocessor on 386 */
+       IrqATA0 = 14,
+       IrqATA1 = 15,
+       MaxIrqPIC = 15,
+
+       VectorLAPIC = VectorPIC + 16,   /* local APIC interrupts */
+       IrqLINT0 = VectorLAPIC + 0,
+       IrqLINT1 = VectorLAPIC + 1,
+       IrqTIMER = VectorLAPIC + 2,
+       IrqERROR = VectorLAPIC + 3,
+       IrqPCINT = VectorLAPIC + 4,
+       IrqSPURIOUS = VectorLAPIC + 15,
+       MaxIrqLAPIC = VectorLAPIC + 15,
+
+       VectorSYSCALL = 64,
+
+       VectorAPIC = 65,        /* external APIC interrupts */
+       MaxVectorAPIC = 255,
 };
 
 enum {
 };
 
 enum {
-       IdtPIC          = 32,                   /* external i8259 interrupts */
+       IdtPIC = 32,                            /* external i8259 interrupts */
 
 
-       IdtLINT0        = 48,                   /* local APIC interrupts */
-       IdtLINT1        = 49,
-       IdtTIMER        = 50,
-       IdtERROR        = 51,
-       IdtPCINT        = 52,
+       IdtLINT0 = 48,  /* local APIC interrupts */
+       IdtLINT1 = 49,
+       IdtTIMER = 50,
+       IdtERROR = 51,
+       IdtPCINT = 52,
 
 
-       IdtIPI          = 62,
-       IdtSPURIOUS     = 63,
+       IdtIPI = 62,
+       IdtSPURIOUS = 63,
 
 
-       IdtSYSCALL      = 64,
+       IdtSYSCALL = 64,
 
 
-       IdtIOAPIC       = 65,                   /* external APIC interrupts */
+       IdtIOAPIC = 65, /* external APIC interrupts */
 
 
-       IdtMAX          = 255,
+       IdtMAX = 255,
 };
 
 struct Vkey {
 };
 
 struct Vkey {
-       int     tbdf;                   /* pci: ioapic or msi sources */
-       int     irq;                    /* 8259-emulating sources */
+       int tbdf;                                       /* pci: ioapic or msi sources */
+       int irq;                                        /* 8259-emulating sources */
 };
 
 typedef struct Vctl {
 };
 
 typedef struct Vctl {
-       struct Vctl*    next;                   /* handlers on this vector */
+       struct Vctl *next;                      /* handlers on this vector */
 
 
-       int     isintr;                 /* interrupt or fault/trap */
+       int isintr;                                     /* interrupt or fault/trap */
 
        struct Vkey;                            /* source-specific key; tbdf for pci */
 
        struct Vkey;                            /* source-specific key; tbdf for pci */
-       void    (*f)(void*, void*);     /* handler to call */
-       void*   a;                      /* argument to call it with */
-       char    name[KNAMELEN];         /* of driver */
-       char    *type;
-
-       int     (*isr)(int);            /* get isr bit for this irq */
-       int     (*eoi)(int);            /* eoi */
-       int     (*mask)(struct Vkey*, int);     /* interrupt enable returns masked vector */
-       int     vno;
+       void (*f) (void *, void *);     /* handler to call */
+       void *a;                                        /* argument to call it with */
+       char name[KNAMELEN];            /* of driver */
+       char *type;
+
+       int (*isr) (int);                       /* get isr bit for this irq */
+       int (*eoi) (int);                       /* eoi */
+       int (*mask) (struct Vkey *, int);       /* interrupt enable returns masked vector */
+       int vno;
 } Vctl;
 
 struct ACVctl {
 } Vctl;
 
 struct ACVctl {
-       //char* (*f)(Ureg*,void*);
-       void*   a;
-       int     vno;
-       char    name[KNAMELEN];         /* of driver */
+       //char* (*f)(Ureg*,void*);
+       void *a;
+       int vno;
+       char name[KNAMELEN];            /* of driver */
 };
 
 enum {
 };
 
 enum {
-       BusCBUS         = 0,            /* Corollary CBUS */
-       BusCBUSII,                      /* Corollary CBUS II */
-       BusEISA,                        /* Extended ISA */
-       BusFUTURE,                      /* IEEE Futurebus */
-       BusINTERN,                      /* Internal bus */
-       BusISA,                         /* Industry Standard Architecture */
-       BusMBI,                         /* Multibus I */
-       BusMBII,                        /* Multibus II */
-       BusMCA,                         /* Micro Channel Architecture */
-       BusMPI,                         /* MPI */
-       BusMPSA,                        /* MPSA */
-       BusNUBUS,                       /* Apple Macintosh NuBus */
-       BusPCI,                         /* Peripheral Component Interconnect */
-       BusPCMCIA,                      /* PC Memory Card International Association */
-       BusTC,                          /* DEC TurboChannel */
-       BusVL,                          /* VESA Local bus */
-       BusVME,                         /* VMEbus */
-       BusXPRESS,                      /* Express System Bus */
+       BusCBUS = 0,                            /* Corollary CBUS */
+       BusCBUSII,      /* Corollary CBUS II */
+       BusEISA,        /* Extended ISA */
+       BusFUTURE,      /* IEEE Futurebus */
+       BusINTERN,      /* Internal bus */
+       BusISA, /* Industry Standard Architecture */
+       BusMBI, /* Multibus I */
+       BusMBII,        /* Multibus II */
+       BusMCA, /* Micro Channel Architecture */
+       BusMPI, /* MPI */
+       BusMPSA,        /* MPSA */
+       BusNUBUS,       /* Apple Macintosh NuBus */
+       BusPCI, /* Peripheral Component Interconnect */
+       BusPCMCIA,      /* PC Memory Card International Association */
+       BusTC,  /* DEC TurboChannel */
+       BusVL,  /* VESA Local bus */
+       BusVME, /* VMEbus */
+       BusXPRESS,      /* Express System Bus */
 };
 
 #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
 };
 
 #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
@@ -126,191 +126,189 @@ enum {
 #define BUSUNKNOWN     (-1)
 
 enum {
 #define BUSUNKNOWN     (-1)
 
 enum {
-       MaxEISA         = 16,
-       CfgEISA         = 0xC80,
+       MaxEISA = 16,
+       CfgEISA = 0xC80,
 };
 
 /*
  * PCI support code.
  */
 };
 
 /*
  * PCI support code.
  */
-enum {                                 /* type 0 and type 1 pre-defined header */
-       PciVID          = 0x00,         /* vendor ID */
-       PciDID          = 0x02,         /* device ID */
-       PciPCR          = 0x04,         /* command */
-       PciPSR          = 0x06,         /* status */
-       PciRID          = 0x08,         /* revision ID */
-       PciCCRp         = 0x09,         /* programming interface class code */
-       PciCCRu         = 0x0A,         /* sub-class code */
-       PciCCRb         = 0x0B,         /* base class code */
-       PciCLS          = 0x0C,         /* cache line size */
-       PciLTR          = 0x0D,         /* latency timer */
-       PciHDT          = 0x0E,         /* header type */
-       PciBST          = 0x0F,         /* BIST */
-
-       PciBAR0         = 0x10,         /* base address */
-       PciBAR1         = 0x14,
-
-       PciCP           = 0x34,         /* capabilities pointer */
-
-       PciINTL         = 0x3C,         /* interrupt line */
-       PciINTP         = 0x3D,         /* interrupt pin */
+enum {                                                 /* type 0 and type 1 pre-defined header */
+       PciVID = 0x00,                          /* vendor ID */
+       PciDID = 0x02,  /* device ID */
+       PciPCR = 0x04,  /* command */
+       PciPSR = 0x06,  /* status */
+       PciRID = 0x08,  /* revision ID */
+       PciCCRp = 0x09, /* programming interface class code */
+       PciCCRu = 0x0A, /* sub-class code */
+       PciCCRb = 0x0B, /* base class code */
+       PciCLS = 0x0C,  /* cache line size */
+       PciLTR = 0x0D,  /* latency timer */
+       PciHDT = 0x0E,  /* header type */
+       PciBST = 0x0F,  /* BIST */
+
+       PciBAR0 = 0x10, /* base address */
+       PciBAR1 = 0x14,
+
+       PciCP = 0x34,   /* capabilities pointer */
+
+       PciINTL = 0x3C, /* interrupt line */
+       PciINTP = 0x3D, /* interrupt pin */
 };
 
 /* ccrb (base class code) values; controller types */
 enum {
 };
 
 /* ccrb (base class code) values; controller types */
 enum {
-       Pcibcpci1       = 0,            /* pci 1.0; no class codes defined */
-       Pcibcstore      = 1,            /* mass storage */
-       Pcibcnet        = 2,            /* network */
-       Pcibcdisp       = 3,            /* display */
-       Pcibcmmedia     = 4,            /* multimedia */
-       Pcibcmem        = 5,            /* memory */
-       Pcibcbridge     = 6,            /* bridge */
-       Pcibccomm       = 7,            /* simple comms (e.g., serial) */
-       Pcibcbasesys    = 8,            /* base system */
-       Pcibcinput      = 9,            /* input */
-       Pcibcdock       = 0xa,          /* docking stations */
-       Pcibcproc       = 0xb,          /* processors */
-       Pcibcserial     = 0xc,          /* serial bus (e.g., USB) */
-       Pcibcwireless   = 0xd,          /* wireless */
-       Pcibcintell     = 0xe,          /* intelligent i/o */
-       Pcibcsatcom     = 0xf,          /* satellite comms */
-       Pcibccrypto     = 0x10,         /* encryption/decryption */
-       Pcibcdacq       = 0x11,         /* data acquisition & signal proc. */
+       Pcibcpci1 = 0,                          /* pci 1.0; no class codes defined */
+       Pcibcstore = 1, /* mass storage */
+       Pcibcnet = 2,   /* network */
+       Pcibcdisp = 3,  /* display */
+       Pcibcmmedia = 4,        /* multimedia */
+       Pcibcmem = 5,   /* memory */
+       Pcibcbridge = 6,        /* bridge */
+       Pcibccomm = 7,  /* simple comms (e.g., serial) */
+       Pcibcbasesys = 8,       /* base system */
+       Pcibcinput = 9, /* input */
+       Pcibcdock = 0xa,        /* docking stations */
+       Pcibcproc = 0xb,        /* processors */
+       Pcibcserial = 0xc,      /* serial bus (e.g., USB) */
+       Pcibcwireless = 0xd,    /* wireless */
+       Pcibcintell = 0xe,      /* intelligent i/o */
+       Pcibcsatcom = 0xf,      /* satellite comms */
+       Pcibccrypto = 0x10,     /* encryption/decryption */
+       Pcibcdacq = 0x11,       /* data acquisition & signal proc. */
 };
 
 /* ccru (sub-class code) values; common cases only */
 enum {
        /* mass storage */
 };
 
 /* ccru (sub-class code) values; common cases only */
 enum {
        /* mass storage */
-       Pciscscsi       = 0,            /* SCSI */
-       Pciscide        = 1,            /* IDE (ATA) */
-       Pciscsata       = 6,            /* SATA */
+       Pciscscsi = 0,                          /* SCSI */
+       Pciscide = 1,   /* IDE (ATA) */
+       Pciscsata = 6,  /* SATA */
 
        /* network */
 
        /* network */
-       Pciscether      = 0,            /* Ethernet */
+       Pciscether = 0, /* Ethernet */
 
        /* display */
 
        /* display */
-       Pciscvga        = 0,            /* VGA */
-       Pciscxga        = 1,            /* XGA */
-       Pcisc3d         = 2,            /* 3D */
+       Pciscvga = 0,   /* VGA */
+       Pciscxga = 1,   /* XGA */
+       Pcisc3d = 2,    /* 3D */
 
        /* bridges */
 
        /* bridges */
-       Pcischostpci    = 0,            /* host/pci */
-       Pciscpcicpci    = 1,            /* pci/pci */
+       Pcischostpci = 0,       /* host/pci */
+       Pciscpcicpci = 1,       /* pci/pci */
 
        /* simple comms */
 
        /* simple comms */
-       Pciscserial     = 0,            /* 16450, etc. */
-       Pciscmultiser   = 1,            /* multiport serial */
+       Pciscserial = 0,        /* 16450, etc. */
+       Pciscmultiser = 1,      /* multiport serial */
 
        /* serial bus */
 
        /* serial bus */
-       Pciscusb        = 3,            /* USB */
+       Pciscusb = 3,   /* USB */
 };
 
 };
 
-enum {                                 /* type 0 pre-defined header */
-       PciCIS          = 0x28,         /* cardbus CIS pointer */
-       PciSVID         = 0x2C,         /* subsystem vendor ID */
-       PciSID          = 0x2E,         /* cardbus CIS pointer */
-       PciEBAR0        = 0x30,         /* expansion ROM base address */
-       PciMGNT         = 0x3E,         /* burst period length */
-       PciMLT          = 0x3F,         /* maximum latency between bursts */
+enum {                                                 /* type 0 pre-defined header */
+       PciCIS = 0x28,                          /* cardbus CIS pointer */
+       PciSVID = 0x2C, /* subsystem vendor ID */
+       PciSID = 0x2E,  /* cardbus CIS pointer */
+       PciEBAR0 = 0x30,        /* expansion ROM base address */
+       PciMGNT = 0x3E, /* burst period length */
+       PciMLT = 0x3F,  /* maximum latency between bursts */
 };
 
 };
 
-enum {                                 /* type 1 pre-defined header */
-       PciPBN          = 0x18,         /* primary bus number */
-       PciSBN          = 0x19,         /* secondary bus number */
-       PciUBN          = 0x1A,         /* subordinate bus number */
-       PciSLTR         = 0x1B,         /* secondary latency timer */
-       PciIBR          = 0x1C,         /* I/O base */
-       PciILR          = 0x1D,         /* I/O limit */
-       PciSPSR         = 0x1E,         /* secondary status */
-       PciMBR          = 0x20,         /* memory base */
-       PciMLR          = 0x22,         /* memory limit */
-       PciPMBR         = 0x24,         /* prefetchable memory base */
-       PciPMLR         = 0x26,         /* prefetchable memory limit */
-       PciPUBR         = 0x28,         /* prefetchable base upper 32 bits */
-       PciPULR         = 0x2C,         /* prefetchable limit upper 32 bits */
-       PciIUBR         = 0x30,         /* I/O base upper 16 bits */
-       PciIULR         = 0x32,         /* I/O limit upper 16 bits */
-       PciEBAR1        = 0x28,         /* expansion ROM base address */
-       PciBCR          = 0x3E,         /* bridge control register */
+enum {                                                 /* type 1 pre-defined header */
+       PciPBN = 0x18,                          /* primary bus number */
+       PciSBN = 0x19,  /* secondary bus number */
+       PciUBN = 0x1A,  /* subordinate bus number */
+       PciSLTR = 0x1B, /* secondary latency timer */
+       PciIBR = 0x1C,  /* I/O base */
+       PciILR = 0x1D,  /* I/O limit */
+       PciSPSR = 0x1E, /* secondary status */
+       PciMBR = 0x20,  /* memory base */
+       PciMLR = 0x22,  /* memory limit */
+       PciPMBR = 0x24, /* prefetchable memory base */
+       PciPMLR = 0x26, /* prefetchable memory limit */
+       PciPUBR = 0x28, /* prefetchable base upper 32 bits */
+       PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
+       PciIUBR = 0x30, /* I/O base upper 16 bits */
+       PciIULR = 0x32, /* I/O limit upper 16 bits */
+       PciEBAR1 = 0x28,        /* expansion ROM base address */
+       PciBCR = 0x3E,  /* bridge control register */
 };
 
 };
 
-enum {                                 /* type 2 pre-defined header */
-       PciCBExCA       = 0x10,
-       PciCBSPSR       = 0x16,
-       PciCBPBN        = 0x18,         /* primary bus number */
-       PciCBSBN        = 0x19,         /* secondary bus number */
-       PciCBUBN        = 0x1A,         /* subordinate bus number */
-       PciCBSLTR       = 0x1B,         /* secondary latency timer */
-       PciCBMBR0       = 0x1C,
-       PciCBMLR0       = 0x20,
-       PciCBMBR1       = 0x24,
-       PciCBMLR1       = 0x28,
-       PciCBIBR0       = 0x2C,         /* I/O base */
-       PciCBILR0       = 0x30,         /* I/O limit */
-       PciCBIBR1       = 0x34,         /* I/O base */
-       PciCBILR1       = 0x38,         /* I/O limit */
-       PciCBSVID       = 0x40,         /* subsystem vendor ID */
-       PciCBSID        = 0x42,         /* subsystem ID */
-       PciCBLMBAR      = 0x44,         /* legacy mode base address */
+enum {                                                 /* type 2 pre-defined header */
+       PciCBExCA = 0x10,
+       PciCBSPSR = 0x16,
+       PciCBPBN = 0x18,        /* primary bus number */
+       PciCBSBN = 0x19,        /* secondary bus number */
+       PciCBUBN = 0x1A,        /* subordinate bus number */
+       PciCBSLTR = 0x1B,       /* secondary latency timer */
+       PciCBMBR0 = 0x1C,
+       PciCBMLR0 = 0x20,
+       PciCBMBR1 = 0x24,
+       PciCBMLR1 = 0x28,
+       PciCBIBR0 = 0x2C,       /* I/O base */
+       PciCBILR0 = 0x30,       /* I/O limit */
+       PciCBIBR1 = 0x34,       /* I/O base */
+       PciCBILR1 = 0x38,       /* I/O limit */
+       PciCBSVID = 0x40,       /* subsystem vendor ID */
+       PciCBSID = 0x42,        /* subsystem ID */
+       PciCBLMBAR = 0x44,      /* legacy mode base address */
 };
 
 /* capabilities */
 enum {
 };
 
 /* capabilities */
 enum {
-       PciCapPMG       = 0x01,         /* power management */
-       PciCapAGP       = 0x02,
-       PciCapVPD       = 0x03,         /* vital product data */
-       PciCapSID       = 0x04,         /* slot id */
-       PciCapMSI       = 0x05,
-       PciCapCHS       = 0x06,         /* compact pci hot swap */
-       PciCapPCIX      = 0x07,
-       PciCapHTC       = 0x08,         /* hypertransport irq conf */
-       PciCapVND       = 0x09,         /* vendor specific information */
-       PciCapPCIe      = 0x10,
-       PciCapMSIX      = 0x11,
-       PciCapSATA      = 0x12,
-       PciCapHSW       = 0x0c,         /* hot swap */
+       PciCapPMG = 0x01,                       /* power management */
+       PciCapAGP = 0x02,
+       PciCapVPD = 0x03,       /* vital product data */
+       PciCapSID = 0x04,       /* slot id */
+       PciCapMSI = 0x05,
+       PciCapCHS = 0x06,       /* compact pci hot swap */
+       PciCapPCIX = 0x07,
+       PciCapHTC = 0x08,       /* hypertransport irq conf */
+       PciCapVND = 0x09,       /* vendor specific information */
+       PciCapPCIe = 0x10,
+       PciCapMSIX = 0x11,
+       PciCapSATA = 0x12,
+       PciCapHSW = 0x0c,       /* hot swap */
 };
 #if 0
 };
 #if 0
-struct Pcisiz
-{
-//     Pcidev* dev;
-       int     siz;
-       int     bar;
+struct Pcisiz {
+//  Pcidev* dev;
+       int siz;
+       int bar;
 };
 
 };
 
-struct Pcidev
-{
-       int     tbdf;                   /* type+bus+device+function */
-       ushort  vid;                    /* vendor ID */
-       ushort  did;                    /* device ID */
+struct Pcidev {
+       int tbdf;                                       /* type+bus+device+function */
+       ushort vid;                                     /* vendor ID */
+       ushort did;                                     /* device ID */
 
 
-       ushort  pcr;
+       ushort pcr;
 
 
-       uchar   rid;
-       uchar   ccrp;
-       uchar   ccru;
-       uchar   ccrb;
-       uchar   cls;
-       uchar   ltr;
+       uchar rid;
+       uchar ccrp;
+       uchar ccru;
+       uchar ccrb;
+       uchar cls;
+       uchar ltr;
 
        struct {
 
        struct {
-               ulong   bar;            /* base address */
-               int     size;
+               ulong bar;                              /* base address */
+               int size;
        } mem[6];
 
        struct {
        } mem[6];
 
        struct {
-               ulong   bar;
-               int     size;
+               ulong bar;
+               int size;
        } rom;
        } rom;
-       uchar   intl;                   /* interrupt line */
+       uchar intl;                                     /* interrupt line */
 
 
-       Pcidevlist;
-       Pcidev* link;                   /* next device on this bno */
+       Pcidev *list;
+       Pcidev *link;                           /* next device on this bno */
 
 
-       Pcidev* bridge;                 /* down a bus */
+       Pcidev *bridge;                         /* down a bus */
        struct {
        struct {
-               ulong   bar;
-               int     size;
+               ulong bar;
+               int size;
        } ioa, mema;
 };
 #endif
        } ioa, mema;
 };
 #endif
@@ -318,4 +316,3 @@ struct Pcidev
 #define PCIWADDR(va)   (PADDR(va)+PCIWINDOW)
 #define ISAWINDOW      0
 #define ISAWADDR(va)   (PADDR(va)+ISAWINDOW)
 #define PCIWADDR(va)   (PADDR(va)+PCIWINDOW)
 #define ISAWINDOW      0
 #define ISAWADDR(va)   (PADDR(va)+ISAWINDOW)
-
index 118a778..fb9deb1 100644 (file)
 #include <acpi.h>
 
 struct Rbus {
 #include <acpi.h>
 
 struct Rbus {
-       struct Rbus     *next;
-       int     devno;
-       struct Rdt      *rdt;
+       struct Rbus *next;
+       int devno;
+       struct Rdt *rdt;
 };
 
 struct Rdt {
 };
 
 struct Rdt {
-       struct apic     *apic;
-       int     intin;
-       uint32_t        lo;
+       struct apic *apic;
+       int intin;
+       uint32_t lo;
 
 
-       int     ref;                            /* could map to multiple busses */
-       int     enabled;                                /* times enabled */
+       int ref;                                        /* could map to multiple busses */
+       int enabled;                            /* times enabled */
 };
 
 };
 
-enum {                                         /* IOAPIC registers */
-       Ioregsel        = 0x00,                 /* indirect register address */
-       Iowin           = 0x04,                 /* indirect register data */
-       Ioipa           = 0x08,                 /* IRQ Pin Assertion */
-       Ioeoi           = 0x10,                 /* EOI */
-
-       Ioapicid        = 0x00,                 /* Identification */
-       Ioapicver       = 0x01,                 /* Version */
-       Ioapicarb       = 0x02,                 /* Arbitration */
-       Ioabcfg         = 0x03,                 /* Boot Coniguration */
-       Ioredtbl        = 0x10,                 /* Redirection Table */
+enum {                                                 /* IOAPIC registers */
+       Ioregsel = 0x00,                        /* indirect register address */
+       Iowin = 0x04,   /* indirect register data */
+       Ioipa = 0x08,   /* IRQ Pin Assertion */
+       Ioeoi = 0x10,   /* EOI */
+
+       Ioapicid = 0x00,        /* Identification */
+       Ioapicver = 0x01,       /* Version */
+       Ioapicarb = 0x02,       /* Arbitration */
+       Ioabcfg = 0x03, /* Boot Coniguration */
+       Ioredtbl = 0x10,        /* Redirection Table */
 };
 
 static struct Rdt rdtarray[Nrdt];
 static int nrdtarray;
 };
 
 static struct Rdt rdtarray[Nrdt];
 static int nrdtarray;
-static struct Rbusrdtbus[Nbus];
-static struct Rdt* rdtvecno[IdtMAX+1];
+static struct Rbus *rdtbus[Nbus];
+static struct Rdt *rdtvecno[IdtMAX + 1];
 
 static spinlock_t idtnolock;
 static int idtno = IdtIOAPIC;
 
 
 static spinlock_t idtnolock;
 static int idtno = IdtIOAPIC;
 
-struct apic    xioapic[Napic];
+struct apic xioapic[Napic];
 int apiceoi(int);
 int apicisr(int);
 int apiceoi(int);
 int apicisr(int);
-static void
-rtblget(struct apic* apic, int sel, uint32_t* hi, uint32_t* lo)
+static void rtblget(struct apic *apic, int sel, uint32_t * hi, uint32_t * lo)
 {
 {
-       sel = Ioredtbl + 2*sel;
+       sel = Ioredtbl + 2 * sel;
 
 
-       *(apic->addr+Ioregsel) = sel+1;
-       *hi = *(apic->addr+Iowin);
-       *(apic->addr+Ioregsel) = sel;
-       *lo = *(apic->addr+Iowin);
+       *(apic->addr + Ioregsel) = sel + 1;
+       *hi = *(apic->addr + Iowin);
+       *(apic->addr + Ioregsel) = sel;
+       *lo = *(apic->addr + Iowin);
 }
 
 }
 
-static void
-rtblput(struct apic* apic, int sel, uint32_t hi, uint32_t lo)
+static void rtblput(struct apic *apic, int sel, uint32_t hi, uint32_t lo)
 {
 {
-       sel = Ioredtbl + 2*sel;
+       sel = Ioredtbl + 2 * sel;
 
 
-       *(apic->addr+Ioregsel) = sel+1;
-       *(apic->addr+Iowin) = hi;
-       *(apic->addr+Ioregsel) = sel;
-       *(apic->addr+Iowin) = lo;
+       *(apic->addr + Ioregsel) = sel + 1;
+       *(apic->addr + Iowin) = hi;
+       *(apic->addr + Ioregsel) = sel;
+       *(apic->addr + Iowin) = lo;
 }
 
 }
 
-struct Rdt*
-rdtlookup(struct apic *apic, int intin)
+struct Rdt *rdtlookup(struct apic *apic, int intin)
 {
        int i;
        struct Rdt *r;
 
 {
        int i;
        struct Rdt *r;
 
-       for(i = 0; i < nrdtarray; i++){
+       for (i = 0; i < nrdtarray; i++) {
                r = rdtarray + i;
                r = rdtarray + i;
-               if(apic == r->apic && intin == r->intin)
+               if (apic == r->apic && intin == r->intin)
                        return r;
        }
        return NULL;
                        return r;
        }
        return NULL;
@@ -107,37 +104,37 @@ rdtlookup(struct apic *apic, int intin)
  * to compute this from acpi. We used to get it from the
  * mptable but we would like to avoid that.
  */
  * to compute this from acpi. We used to get it from the
  * mptable but we would like to avoid that.
  */
-void
-ioapicintrinit(int busno, int apicno, int intin, int devno, int lo)
+void ioapicintrinit(int busno, int apicno, int intin, int devno, int lo)
 {
        struct Rbus *rbus;
        struct Rdt *rdt;
        struct apic *apic;
 {
        struct Rbus *rbus;
        struct Rdt *rdt;
        struct apic *apic;
-printk("%s: busno %d apicno %d intin %d devno %p lo %p\n", __func__,
-       busno, apicno, intin, devno, lo);
+       printk("%s: busno %d apicno %d intin %d devno %p lo %p\n", __func__,
+                  busno, apicno, intin, devno, lo);
 
 
-       if(busno >= Nbus || apicno >= Napic || nrdtarray >= Nrdt){
+       if (busno >= Nbus || apicno >= Napic || nrdtarray >= Nrdt) {
                printk("FAIL 1\n");
                return;
        }
        apic = &xioapic[apicno];
                printk("FAIL 1\n");
                return;
        }
        apic = &xioapic[apicno];
-       if(!apic->useable || intin >= apic->nrdt){
-               printk("apic->usable %d intin %d apic->nrdt %d OOR\n", apic->useable, intin,
-                       apic->nrdt);
+       if (!apic->useable || intin >= apic->nrdt) {
+               printk("apic->usable %d intin %d apic->nrdt %d OOR\n", apic->useable,
+                          intin, apic->nrdt);
                return;
        }
 
        rdt = rdtlookup(apic, intin);
                return;
        }
 
        rdt = rdtlookup(apic, intin);
-       if(rdt == NULL){
-printk("NO RDT, install it for apic %d intin %d lo %p\n", apicno, intin, lo);
+       if (rdt == NULL) {
+               printk("NO RDT, install it for apic %d intin %d lo %p\n", apicno, intin,
+                          lo);
                rdt = &rdtarray[nrdtarray++];
                rdt->apic = apic;
                rdt->intin = intin;
                rdt->lo = lo;
                rdt = &rdtarray[nrdtarray++];
                rdt->apic = apic;
                rdt->intin = intin;
                rdt->lo = lo;
-       }else{
-               if(lo != rdt->lo){
+       } else {
+               if (lo != rdt->lo) {
                        printd("mutiple irq botch bus %d %d/%d/%d lo %d vs %d\n",
                        printd("mutiple irq botch bus %d %d/%d/%d lo %d vs %d\n",
-                              busno, apicno, intin, devno, lo, rdt->lo);
+                                  busno, apicno, intin, devno, lo, rdt->lo);
                        return;
                }
                printk("dup rdt %d %d %d %d %.8p\n", busno, apicno, intin, devno, lo);
                        return;
                }
                printk("dup rdt %d %d %d %d %.8p\n", busno, apicno, intin, devno, lo);
@@ -157,8 +154,8 @@ static int map_polarity[4] = {
 static int map_edge_level[4] = {
        -1, TMedge, -1, TMlevel
 };
 static int map_edge_level[4] = {
        -1, TMedge, -1, TMlevel
 };
-int
-ioapic_route_irq(int irq, int apicno, int devno)
+
+int ioapic_route_irq(int irq, int apicno, int devno)
 {
        extern struct Madt *apics;
        struct Madt *a = apics;
 {
        extern struct Madt *apics;
        struct Madt *a = apics;
@@ -167,37 +164,37 @@ ioapic_route_irq(int irq, int apicno, int devno)
        int pol, edge_level;
        printk("%s(%d,%d);\n", __func__, irq, apicno);
        /* find it. */
        int pol, edge_level;
        printk("%s(%d,%d);\n", __func__, irq, apicno);
        /* find it. */
-       for(st = apics->st; st != NULL; st = st->next){
+       for (st = apics->st; st != NULL; st = st->next) {
                printk("Check %d, ", st->type);
                printk("Check %d, ", st->type);
-               if (st->type == ASintovr){
+               if (st->type == ASintovr) {
                        printk("irq of st is %d\n", st->intovr.irq);
                        if (st->intovr.irq == irq)
                                break;
                }
        }
                        printk("irq of st is %d\n", st->intovr.irq);
                        if (st->intovr.irq == irq)
                                break;
                }
        }
-       if (! st) {
+       if (!st) {
                printk("IRQ %d not found in MADT\n", irq);
                return -1;
        }
                printk("IRQ %d not found in MADT\n", irq);
                return -1;
        }
-       
+
        pol = map_polarity[st->intovr.flags & AFpmask];
        if (pol < 0) {
                printk("BAD POLARITY\n");
                return -1;
        }
        pol = map_polarity[st->intovr.flags & AFpmask];
        if (pol < 0) {
                printk("BAD POLARITY\n");
                return -1;
        }
-       
-       edge_level = map_edge_level[(st->intovr.flags&AFlevel)>>2];
+
+       edge_level = map_edge_level[(st->intovr.flags & AFlevel) >> 2];
        if (edge_level < 0) {
                printk("BAD edge/level\n");
                return -1;
        }
        lo = pol | edge_level;
        if (edge_level < 0) {
                printk("BAD edge/level\n");
                return -1;
        }
        lo = pol | edge_level;
-       ioapicintrinit(0, 0, 0/*st->intovr.intr*/, devno, lo);
+       ioapicintrinit(0, 0, 0 /*st->intovr.intr */ , devno, lo);
        printk("FOUND the MADT for %d\n", irq);
        return 0;
 }
        printk("FOUND the MADT for %d\n", irq);
        return 0;
 }
-void
-ioapicinit(int id, int ibase, uintptr_t pa)
+
+void ioapicinit(int id, int ibase, uintptr_t pa)
 {
        struct apic *apic;
        static int base;
 {
        struct apic *apic;
        static int base;
@@ -206,12 +203,12 @@ ioapicinit(int id, int ibase, uintptr_t pa)
         * Mark the IOAPIC useable if it has a good ID
         * and the registers can be mapped.
         */
         * Mark the IOAPIC useable if it has a good ID
         * and the registers can be mapped.
         */
-       if(id >= Napic)
+       if (id >= Napic)
                return;
 
        apic = &xioapic[id];
        apic->addr = IOAPIC_BASE;
                return;
 
        apic = &xioapic[id];
        apic->addr = IOAPIC_BASE;
-       if(apic->useable)
+       if (apic->useable)
                return;
        apic->useable = 1;
        apic->paddr = pa;
                return;
        apic->useable = 1;
        apic->paddr = pa;
@@ -222,21 +219,20 @@ ioapicinit(int id, int ibase, uintptr_t pa)
         * responsibility of the O/S to set the APIC ID.
         */
        spin_lock(&apic->lock);
         * responsibility of the O/S to set the APIC ID.
         */
        spin_lock(&apic->lock);
-       *(apic->addr+Ioregsel) = Ioapicver;
-       apic->nrdt = ((*(apic->addr+Iowin)>>16) & 0xff) + 1;
-       if(ibase != -1)
+       *(apic->addr + Ioregsel) = Ioapicver;
+       apic->nrdt = ((*(apic->addr + Iowin) >> 16) & 0xff) + 1;
+       if (ibase != -1)
                apic->ibase = ibase;
                apic->ibase = ibase;
-       else{
+       else {
                apic->ibase = base;
                base += apic->nrdt;
        }
                apic->ibase = base;
                base += apic->nrdt;
        }
-       *(apic->addr+Ioregsel) = Ioapicid;
-       *(apic->addr+Iowin) = id<<24;
+       *(apic->addr + Ioregsel) = Ioapicid;
+       *(apic->addr + Iowin) = id << 24;
        spin_unlock(&apic->lock);
 }
 
        spin_unlock(&apic->lock);
 }
 
-char *
-ioapicdump(char *start, char *end)
+char *ioapicdump(char *start, char *end)
 {
        int i, n;
        struct Rbus *rbus;
 {
        int i, n;
        struct Rbus *rbus;
@@ -244,46 +240,45 @@ ioapicdump(char *start, char *end)
        struct apic *apic;
        uint32_t hi, lo;
 
        struct apic *apic;
        uint32_t hi, lo;
 
-       if(!2)
+       if (!2)
                return start;
                return start;
-       for(i = 0; i < Napic; i++){
+       for (i = 0; i < Napic; i++) {
                apic = &xioapic[i];
                apic = &xioapic[i];
-               if(!apic->useable || apic->addr == 0)
+               if (!apic->useable || apic->addr == 0)
                        continue;
                start = seprintf(start, end, "ioapic %d addr %#p nrdt %d ibase %d\n",
                        continue;
                start = seprintf(start, end, "ioapic %d addr %#p nrdt %d ibase %d\n",
-                                i, apic->addr, apic->nrdt, apic->ibase);
-               for(n = 0; n < apic->nrdt; n++){
+                                                i, apic->addr, apic->nrdt, apic->ibase);
+               for (n = 0; n < apic->nrdt; n++) {
                        spin_lock(&apic->lock);
                        rtblget(apic, n, &hi, &lo);
                        spin_unlock(&apic->lock);
                        start = seprintf(start, end, " rdt %2.2d %p %p\n", n, hi, lo);
                }
        }
                        spin_lock(&apic->lock);
                        rtblget(apic, n, &hi, &lo);
                        spin_unlock(&apic->lock);
                        start = seprintf(start, end, " rdt %2.2d %p %p\n", n, hi, lo);
                }
        }
-       for(i = 0; i < Nbus; i++){
-               if((rbus = rdtbus[i]) == NULL)
+       for (i = 0; i < Nbus; i++) {
+               if ((rbus = rdtbus[i]) == NULL)
                        continue;
                start = seprintf(start, end, "iointr bus %d:\n", i);
                        continue;
                start = seprintf(start, end, "iointr bus %d:\n", i);
-               for(; rbus != NULL; rbus = rbus->next){
+               for (; rbus != NULL; rbus = rbus->next) {
                        rdt = rbus->rdt;
                        start = seprintf(start, end,
                        rdt = rbus->rdt;
                        start = seprintf(start, end,
-                                        " apic %ld devno %#p (%d %d) intin %d lo %#p ref %d\n",
-                                        rdt->apic-xioapic, rbus->devno, rbus->devno>>2,
-                                        rbus->devno & 0x03, rdt->intin, rdt->lo, rdt->ref);
+                                                        " apic %ld devno %#p (%d %d) intin %d lo %#p ref %d\n",
+                                                        rdt->apic - xioapic, rbus->devno, rbus->devno >> 2,
+                                                        rbus->devno & 0x03, rdt->intin, rdt->lo, rdt->ref);
                }
        }
        return start;
 }
 
                }
        }
        return start;
 }
 
-void
-ioapiconline(void)
+void ioapiconline(void)
 {
        int i;
        struct apic *apic;
 
 {
        int i;
        struct apic *apic;
 
-       for(apic = xioapic; apic < &xioapic[Napic]; apic++){
-               if(!apic->useable || apic->addr == NULL)
+       for (apic = xioapic; apic < &xioapic[Napic]; apic++) {
+               if (!apic->useable || apic->addr == NULL)
                        continue;
                        continue;
-               for(i = 0; i < apic->nrdt; i++){
+               for (i = 0; i < apic->nrdt; i++) {
                        spin_lock(&apic->lock);
                        rtblput(apic, i, 0, Im);
                        spin_unlock(&apic->lock);
                        spin_lock(&apic->lock);
                        rtblput(apic, i, 0, Im);
                        spin_unlock(&apic->lock);
@@ -293,8 +288,7 @@ ioapiconline(void)
 
 static int dfpolicy = 0;
 
 
 static int dfpolicy = 0;
 
-static void
-ioapicintrdd(uint32_t* hi, uint32_t* lo)
+static void ioapicintrdd(uint32_t * hi, uint32_t * lo)
 {
        int i;
        static int df;
 {
        int i;
        static int df;
@@ -316,51 +310,50 @@ ioapicintrdd(uint32_t* hi, uint32_t* lo)
         *
         * Interrupt routing policy can be set here.
         */
         *
         * Interrupt routing policy can be set here.
         */
-       switch(dfpolicy){
-       default:                                /* noise core 0 */
+       switch (dfpolicy) {
+               default:        /* noise core 0 */
 #warning "sys->machptr[0]->apicno --- what is this in Akaros?"
 #warning "sys->machptr[0]->apicno --- what is this in Akaros?"
-               *hi = 0; //sys->machptr[0]->apicno<<24;
-               break;
-       case 1:                                 /* round-robin */
-               /*
-                * Assign each interrupt to a different CPU on a round-robin
-                * Some idea of the packages/cores/thread topology would be
-                * useful here, e.g. to not assign interrupts to more than one
-                * thread in a core. But, as usual, Intel make that an onerous
-                * task.
-                */
-               spin_lock(&dflock);
-               for(;;){
+                       *hi = 0;        //sys->machptr[0]->apicno<<24;
+                       break;
+               case 1: /* round-robin */
+                       /*
+                        * Assign each interrupt to a different CPU on a round-robin
+                        * Some idea of the packages/cores/thread topology would be
+                        * useful here, e.g. to not assign interrupts to more than one
+                        * thread in a core. But, as usual, Intel make that an onerous
+                        * task.
+                        */
+                       spin_lock(&dflock);
+                       for (;;) {
 #if 0
 #if 0
-                       i = df++;
-                       if(df >= sys->nmach+1)
-                               df = 0;
-                       if(sys->machptr[i] == NULL || !sys->machptr[i]->online)
-                               continue;
-                       i = sys->machptr[i]->apicno;
+                               i = df++;
+                               if (df >= sys->nmach + 1)
+                                       df = 0;
+                               if (sys->machptr[i] == NULL || !sys->machptr[i]->online)
+                                       continue;
+                               i = sys->machptr[i]->apicno;
 #endif
 #warning "always picking acpino 0"
 #endif
 #warning "always picking acpino 0"
-                       i = 0;
-                       if(xlapic[i].useable && xlapic[i].addr == 0)
-                               break;
-               }
-               spin_unlock(&dflock);
+                               i = 0;
+                               if (xlapic[i].useable && xlapic[i].addr == 0)
+                                       break;
+                       }
+                       spin_unlock(&dflock);
 
 
-               *hi = i<<24;
-               break;
+                       *hi = i << 24;
+                       break;
        }
        }
-       *lo |= Pm|MTf;
+       *lo |= Pm | MTf;
 }
 
 }
 
-int
-nextvec(void)
+int nextvec(void)
 {
        unsigned int vecno;
 
        spin_lock(&idtnolock);
        vecno = idtno;
 {
        unsigned int vecno;
 
        spin_lock(&idtnolock);
        vecno = idtno;
-       idtno = (idtno+8) % IdtMAX;
-       if(idtno < IdtIOAPIC)
+       idtno = (idtno + 8) % IdtMAX;
+       if (idtno < IdtIOAPIC)
                idtno += IdtIOAPIC;
        spin_unlock(&idtnolock);
 
                idtno += IdtIOAPIC;
        spin_unlock(&idtnolock);
 
@@ -368,14 +361,13 @@ nextvec(void)
 }
 
 #warning "no msi mask yet"
 }
 
 #warning "no msi mask yet"
-static int
-msimask(struct Vkey *v, int mask)
+static int msimask(struct Vkey *v, int mask)
 {
 #if 0
        Pcidev *p;
 {
 #if 0
        Pcidev *p;
-       
+
        p = pcimatchtbdf(v->tbdf);
        p = pcimatchtbdf(v->tbdf);
-       if(p == NULL)
+       if (p == NULL)
                return -1;
        return pcimsimask(p, mask);
 #else
                return -1;
        return pcimsimask(p, mask);
 #else
@@ -385,8 +377,7 @@ msimask(struct Vkey *v, int mask)
 
 #warning "No msi yet"
 #if 0
 
 #warning "No msi yet"
 #if 0
-static int
-intrenablemsi(struct vctl* v, Pcidev *p)
+static int intrenablemsi(struct vctl *v, Pcidev * p)
 {
        unsigned int vno, lo, hi;
        uint64_t msivec;
 {
        unsigned int vno, lo, hi;
        uint64_t msivec;
@@ -396,11 +387,11 @@ intrenablemsi(struct vctl* v, Pcidev *p)
        lo = IPlow | TMedge | vno;
        ioapicintrdd(&hi, &lo);
 
        lo = IPlow | TMedge | vno;
        ioapicintrdd(&hi, &lo);
 
-       if(lo & Lm)
+       if (lo & Lm)
                lo |= MTlp;
 
                lo |= MTlp;
 
-       msivec = (uint64_t)hi<<32 | lo;
-       if(pcimsienable(p, msivec) == -1)
+       msivec = (uint64_t) hi << 32 | lo;
+       if (pcimsienable(p, msivec) == -1)
                return -1;
        v->isr = apicisr;
        v->eoi = apiceoi;
                return -1;
        v->isr = apicisr;
        v->eoi = apiceoi;
@@ -408,22 +399,21 @@ intrenablemsi(struct vctl* v, Pcidev *p)
        v->type = "msi";
        v->mask = msimask;
 
        v->type = "msi";
        v->mask = msimask;
 
-       printk("msiirq: %T: enabling %.16llp %s irq %d vno %d\n", p->tbdf, msivec, v->name, v->irq, vno);
+       printk("msiirq: %T: enabling %.16llp %s irq %d vno %d\n", p->tbdf, msivec,
+                  v->name, v->irq, vno);
        return vno;
 }
 #endif
 #warning "no disable msi yet"
 #if 0
        return vno;
 }
 #endif
 #warning "no disable msi yet"
 #if 0
-int
-disablemsi(Vctl*, Pcidev *p)
+int disablemsi(Vctl *, Pcidev * p)
 {
 {
-       if(p == NULL)
+       if (p == NULL)
                return -1;
        return pcimsimask(p, 1);
 }
 #endif
                return -1;
        return pcimsimask(p, 1);
 }
 #endif
-int
-ioapicintrenable(Vctl* v)
+int ioapicintrenable(Vctl * v)
 {
        struct Rbus *rbus;
        struct Rdt *rdt;
 {
        struct Rbus *rbus;
        struct Rdt *rdt;
@@ -434,16 +424,15 @@ ioapicintrenable(Vctl* v)
  * Bridge between old and unspecified new scheme,
  * the work in progress...
  */
  * Bridge between old and unspecified new scheme,
  * the work in progress...
  */
-       if(v->tbdf == BUSUNKNOWN){
-printk("%s; BUSUNKNOWN\n", __func__);
-               if(v->irq >= IrqLINT0 && v->irq <= MaxIrqLAPIC){
-                       if(v->irq != IrqSPURIOUS)
+       if (v->tbdf == BUSUNKNOWN) {
+               printk("%s; BUSUNKNOWN\n", __func__);
+               if (v->irq >= IrqLINT0 && v->irq <= MaxIrqLAPIC) {
+                       if (v->irq != IrqSPURIOUS)
                                v->isr = apiceoi;
                        v->type = "lapic";
                        return v->irq;
                                v->isr = apiceoi;
                        v->type = "lapic";
                        return v->irq;
-               }
-               else{
-printk("%s; legacy isa\n", __func__);
+               } else {
+                       printk("%s; legacy isa\n", __func__);
 
                        /*
                         * Legacy ISA.
 
                        /*
                         * Legacy ISA.
@@ -452,17 +441,16 @@ printk("%s; legacy isa\n", __func__);
                         */
 #if 0
                        extern int mpisabusno;
                         */
 #if 0
                        extern int mpisabusno;
-                       
-                       if(mpisabusno == -1)
+
+                       if (mpisabusno == -1)
                                panic("no ISA bus allocated");
                        busno = mpisabusno;
 #endif
                        busno = 0;
                                panic("no ISA bus allocated");
                        busno = mpisabusno;
 #endif
                        busno = 0;
-                       devno = v->irq<<2;
+                       devno = v->irq << 2;
                }
                }
-       }
-       else if(BUSTYPE(v->tbdf) == BusPCI){
-printk("%s; BusPCI \n", __func__);
+       } else if (BUSTYPE(v->tbdf) == BusPCI) {
+               printk("%s; BusPCI \n", __func__);
                /*
                 * PCI.
                 * Make a devno from BUSDNO(tbdf) and pcidev->intp.
                /*
                 * PCI.
                 * Make a devno from BUSDNO(tbdf) and pcidev->intp.
@@ -470,75 +458,74 @@ printk("%s; BusPCI \n", __func__);
                /* we'll assume it's there. */
 #if 0
                Pcidev *pcidev;
                /* we'll assume it's there. */
 #if 0
                Pcidev *pcidev;
-               
+
                busno = BUSBNO(v->tbdf);
                busno = BUSBNO(v->tbdf);
-               if((pcidev = pcimatchtbdf(v->tbdf)) == NULL)
+               if ((pcidev = pcimatchtbdf(v->tbdf)) == NULL)
                        panic("no PCI dev for tbdf %p", v->tbdf);
                        panic("no PCI dev for tbdf %p", v->tbdf);
-               if((vecno = intrenablemsi(v, pcidev)) != -1)
+               if ((vecno = intrenablemsi(v, pcidev)) != -1)
                        return vecno;
                disablemsi(v, pcidev);
 #endif
 
                struct pci_device pcidev;
                        return vecno;
                disablemsi(v, pcidev);
 #endif
 
                struct pci_device pcidev;
-               
+
                explode_tbdf(v->tbdf);
                devno = pcidev_read8(&pcidev, PciINTP);
                explode_tbdf(v->tbdf);
                devno = pcidev_read8(&pcidev, PciINTP);
-printk("INTP is %d\n", devno);
+               printk("INTP is %d\n", devno);
 
 
-               if(devno == 0)
+               if (devno == 0)
                        panic("no INTP for tbdf %p", v->tbdf);
                        panic("no INTP for tbdf %p", v->tbdf);
-               devno = BUSDNO(v->tbdf)<<2|(devno-1);
-printk("devno is %08lx\n", devno);
+               devno = BUSDNO(v->tbdf) << 2 | (devno - 1);
+               printk("devno is %08lx\n", devno);
                printk("ioapicintrenable: tbdf %p busno %d devno %d\n",
                printk("ioapicintrenable: tbdf %p busno %d devno %d\n",
-                      v->tbdf, busno, devno);
-       }
-       else{
+                          v->tbdf, busno, devno);
+       } else {
                //SET(busno, devno);
                busno = devno = 0;
                panic("unknown tbdf %px", v->tbdf);
        }
                //SET(busno, devno);
                busno = devno = 0;
                panic("unknown tbdf %px", v->tbdf);
        }
-       
+
        rdt = NULL;
        rdt = NULL;
-       for(rbus = rdtbus[busno]; rbus != NULL; rbus = rbus->next){
+       for (rbus = rdtbus[busno]; rbus != NULL; rbus = rbus->next) {
                printk("Check rbus->devno %p devno %p\n", rbus->devno, devno);
                printk("Check rbus->devno %p devno %p\n", rbus->devno, devno);
-               if(rbus->devno == devno){
+               if (rbus->devno == devno) {
                        rdt = rbus->rdt;
                        break;
                }
        }
                        rdt = rbus->rdt;
                        break;
                }
        }
-       if(rdt == NULL){
+       if (rdt == NULL) {
                // install it? Who knows?
                // install it? Who knows?
-int ioapic_route_irq(int irq, int apicno, int devno);
+               int ioapic_route_irq(int irq, int apicno, int devno);
                ioapic_route_irq(v->irq, 0, devno);
                extern int mpisabusno;
                ioapic_route_irq(v->irq, 0, devno);
                extern int mpisabusno;
-printk("rdt is NULLLLLLLLLLLLLLLLLLLLLL\n");
-               
+               printk("rdt is NULLLLLLLLLLLLLLLLLLLLLL\n");
+
                /*
                 * First crack in the smooth exterior of the new code:
                 * some BIOS make an MPS table where the PCI devices
                 * are just defaulted to ISA.  Rewrite this to be
                 * cleaner.
                 * no MPS table in akaros.
                /*
                 * First crack in the smooth exterior of the new code:
                 * some BIOS make an MPS table where the PCI devices
                 * are just defaulted to ISA.  Rewrite this to be
                 * cleaner.
                 * no MPS table in akaros.
-               if((busno = mpisabusno) == -1)
-                       return -1;
+                if((busno = mpisabusno) == -1)
+                return -1;
 
 
-               devno = v->irq<<2;
+                devno = v->irq<<2;
                 */
                 */
-               for(rbus = rdtbus[busno]; rbus != NULL; rbus = rbus->next)
-                       if(rbus->devno == devno){
-printk("rbus->devno = %p, devno %p\n", rbus->devno, devno);
+               for (rbus = rdtbus[busno]; rbus != NULL; rbus = rbus->next)
+                       if (rbus->devno == devno) {
+                               printk("rbus->devno = %p, devno %p\n", rbus->devno, devno);
                                rdt = rbus->rdt;
                                break;
                        }
                printk("isa: tbdf %p busno %d devno %d %#p\n",
                                rdt = rbus->rdt;
                                break;
                        }
                printk("isa: tbdf %p busno %d devno %d %#p\n",
-                      v->tbdf, busno, devno, rdt);
+                          v->tbdf, busno, devno, rdt);
        }
        }
-       if(rdt == NULL){
+       if (rdt == NULL) {
                printk("RDT Is STILL NULL!\n");
                return -1;
        }
                printk("RDT Is STILL NULL!\n");
                return -1;
        }
-       
-printk("Second crack\n");
+
+       printk("Second crack\n");
        /*
         * Second crack:
         * what to do about devices that intrenable/intrdisable frequently?
        /*
         * Second crack:
         * what to do about devices that intrenable/intrdisable frequently?
@@ -552,12 +539,13 @@ printk("Second crack\n");
         * rather than putting a Lock in each entry.
         */
        spin_lock(&rdt->apic->lock);
         * rather than putting a Lock in each entry.
         */
        spin_lock(&rdt->apic->lock);
-       printk("%p: %ld/%d/%d (%d)\n", v->tbdf, rdt->apic - xioapic, rbus->devno, rdt->intin, devno);
-       if((rdt->lo & 0xff) == 0){
+       printk("%p: %ld/%d/%d (%d)\n", v->tbdf, rdt->apic - xioapic, rbus->devno,
+                  rdt->intin, devno);
+       if ((rdt->lo & 0xff) == 0) {
                vecno = nextvec();
                rdt->lo |= vecno;
                rdtvecno[vecno] = rdt;
                vecno = nextvec();
                rdt->lo |= vecno;
                rdtvecno[vecno] = rdt;
-       }else
+       } else
                printk("%p: mutiple irq bus %d dev %d\n", v->tbdf, busno, devno);
 
        rdt->enabled++;
                printk("%p: mutiple irq bus %d dev %d\n", v->tbdf, busno, devno);
 
        rdt->enabled++;
@@ -568,7 +556,7 @@ printk("Second crack\n");
        spin_unlock(&rdt->apic->lock);
 
        printk("busno %d devno %d hi %p lo %p vecno %d\n",
        spin_unlock(&rdt->apic->lock);
 
        printk("busno %d devno %d hi %p lo %p vecno %d\n",
-              busno, devno, hi, lo, vecno);
+                  busno, devno, hi, lo, vecno);
        v->isr = apicisr;
        v->eoi = apiceoi;
        v->vno = vecno;
        v->isr = apicisr;
        v->eoi = apiceoi;
        v->vno = vecno;
@@ -577,8 +565,7 @@ printk("Second crack\n");
        return vecno;
 }
 
        return vecno;
 }
 
-int
-ioapicintrdisable(int vecno)
+int ioapicintrdisable(int vecno)
 {
        struct Rdt *rdt;
 
 {
        struct Rdt *rdt;
 
@@ -590,36 +577,34 @@ ioapicintrdisable(int vecno)
         *
         * What about any pending interrupts?
         */
         *
         * What about any pending interrupts?
         */
-       if(vecno < 0 || vecno > MaxVectorAPIC){
+       if (vecno < 0 || vecno > MaxVectorAPIC) {
                panic("ioapicintrdisable: vecno %d out of range", vecno);
                return -1;
        }
                panic("ioapicintrdisable: vecno %d out of range", vecno);
                return -1;
        }
-       if((rdt = rdtvecno[vecno]) == NULL){
+       if ((rdt = rdtvecno[vecno]) == NULL) {
                panic("ioapicintrdisable: vecno %d has no rdt", vecno);
                return -1;
        }
                panic("ioapicintrdisable: vecno %d has no rdt", vecno);
                return -1;
        }
-       
+
        spin_lock(&rdt->apic->lock);
        rdt->enabled--;
        spin_lock(&rdt->apic->lock);
        rdt->enabled--;
-       if(rdt->enabled == 0)
+       if (rdt->enabled == 0)
                rtblput(rdt->apic, rdt->intin, 0, rdt->lo);
        spin_unlock(&rdt->apic->lock);
                rtblput(rdt->apic, rdt->intin, 0, rdt->lo);
        spin_unlock(&rdt->apic->lock);
-       
+
        return 0;
 }
 
 spinlock_t vctllock;
 
        return 0;
 }
 
 spinlock_t vctllock;
 
-void*
-intrenable(int irq, void (*f)(void*, void*), void* a, int tbdf)
+void *intrenable(int irq, void (*f) (void *, void *), void *a, int tbdf)
 {
        int vno;
        Vctl *v;
 {
        int vno;
        Vctl *v;
-       extern int ioapicintrenable(Vctl*);
+       extern int ioapicintrenable(Vctl *);
 
 
-       if(f == NULL){
-               printk("intrenable: nil handler for %d, tbdf %p\n",
-                      irq, tbdf);
+       if (f == NULL) {
+               printk("intrenable: nil handler for %d, tbdf %p\n", irq, tbdf);
                return NULL;
        }
 
                return NULL;
        }
 
@@ -633,19 +618,19 @@ intrenable(int irq, void (*f)(void*, void*), void* a, int tbdf)
        //spilock(&vctllock);
        vno = ioapicintrenable(v);
        printk("INTRENABLE, vno is %d\n", vno);
        //spilock(&vctllock);
        vno = ioapicintrenable(v);
        printk("INTRENABLE, vno is %d\n", vno);
-       if(vno == -1){
+       if (vno == -1) {
                //iunlock(&vctllock);
                printk("intrenable: couldn't enable irq %d, tbdf %p for %s\n",
                //iunlock(&vctllock);
                printk("intrenable: couldn't enable irq %d, tbdf %p for %s\n",
-                       irq, tbdf, v->name);
+                          irq, tbdf, v->name);
                kfree(v);
                return NULL;
        }
 #if 0
                kfree(v);
                return NULL;
        }
 #if 0
-       if(vctl[vno]){
-               if(vctl[v->vno]->isr != v->isr || vctl[v->vno]->eoi != v->eoi)
+       if (vctl[vno]) {
+               if (vctl[v->vno]->isr != v->isr || vctl[v->vno]->eoi != v->eoi)
                        panic("intrenable: handler: %s %s %#p %#p %#p %#p",
                        panic("intrenable: handler: %s %s %#p %#p %#p %#p",
-                               vctl[v->vno]->name, v->name,
-                               vctl[v->vno]->isr, v->isr, vctl[v->vno]->eoi, v->eoi);
+                                 vctl[v->vno]->name, v->name,
+                                 vctl[v->vno]->isr, v->isr, vctl[v->vno]->eoi, v->eoi);
        }
 
        v->vno = vno;
        }
 
        v->vno = vno;
@@ -654,7 +639,7 @@ intrenable(int irq, void (*f)(void*, void*), void* a, int tbdf)
 #endif
        //iunlock(&vctllock);
 
 #endif
        //iunlock(&vctllock);
 
-       if(v->mask)
+       if (v->mask)
                v->mask(v, 0);
 
        /*
                v->mask(v, 0);
 
        /*
index df656dd..1e4a164 100644 (file)
  * MultiProcessor Specification Version 1.[14].
  */
 typedef struct {                               /* MP Floating Pointer */
  * MultiProcessor Specification Version 1.[14].
  */
 typedef struct {                               /* MP Floating Pointer */
-       uint8_t signature[4];                   /* "_MP_" */
-       uint8_t addr[4];                        /* PCMP */
-       uint8_t length;                         /* 1 */
-       uint8_t revision;                       /* [14] */
-       uint8_t checksum;
-       uint8_t feature[5];
+       uint8_t signature[4];           /* "_MP_" */
+       uint8_t addr[4];                        /* PCMP */
+       uint8_t length;                         /* 1 */
+       uint8_t revision;                       /* [14] */
+       uint8_t checksum;
+       uint8_t feature[5];
 } _MP_;
 
 typedef struct {                               /* MP Configuration Table */
 } _MP_;
 
 typedef struct {                               /* MP Configuration Table */
-       uint8_t signature[4];                   /* "PCMP" */
-       uint8_t length[2];
-       uint8_t revision;                       /* [14] */
-       uint8_t checksum;
-       uint8_t string[20];                     /* OEM + Product ID */
-       uint8_t oaddr[4];                       /* OEM table pointer */
-       uint8_t olength[2];                     /* OEM table length */
-       uint8_t entry[2];                       /* entry count */
-       uint8_t apicpa[4];                      /* local APIC address */
-       uint8_t xlength[2];                     /* extended table length */
-       uint8_t xchecksum;                      /* extended table checksum */
-       uint8_t reserved;
-
-       uint8_t entries[];
+       uint8_t signature[4];           /* "PCMP" */
+       uint8_t length[2];
+       uint8_t revision;                       /* [14] */
+       uint8_t checksum;
+       uint8_t string[20];                     /* OEM + Product ID */
+       uint8_t oaddr[4];                       /* OEM table pointer */
+       uint8_t olength[2];                     /* OEM table length */
+       uint8_t entry[2];                       /* entry count */
+       uint8_t apicpa[4];                      /* local APIC address */
+       uint8_t xlength[2];                     /* extended table length */
+       uint8_t xchecksum;                      /* extended table checksum */
+       uint8_t reserved;
+
+       uint8_t entries[];
 } PCMP;
 
 typedef struct {
 } PCMP;
 
 typedef struct {
-       char    type[6];
-       int     polarity;                       /* default for this bus */
-       int     trigger;                        /* default for this bus */
+       char type[6];
+       int polarity;                           /* default for this bus */
+       int trigger;                            /* default for this bus */
 } Mpbus;
 
 static Mpbus mpbusdef[] = {
 } Mpbus;
 
 static Mpbus mpbusdef[] = {
-       { "PCI   ", IPlow, TMlevel, },
-       { "ISA   ", IPhigh, TMedge, },
+       {"PCI   ", IPlow, TMlevel,},
+       {"ISA   ", IPhigh, TMedge,},
 };
 };
-static Mpbus* mpbus[Nbus];
+
+static Mpbus *mpbus[Nbus];
 int mpisabusno = -1;
 
 int mpisabusno = -1;
 
-static void
-mpintrprint(char* s, uint8_t* p)
+static void mpintrprint(char *s, uint8_t * p)
 {
        char buf[128], *b, *e;
        char format[] = " type %d flags %p bus %d IRQ %d APIC %d INTIN %d\n";
 {
        char buf[128], *b, *e;
        char format[] = " type %d flags %p bus %d IRQ %d APIC %d INTIN %d\n";
@@ -70,13 +70,12 @@ mpintrprint(char* s, uint8_t* p)
        printd(buf);
 */
        printk("mpparse: intr:");
        printd(buf);
 */
        printk("mpparse: intr:");
-       if(s != NULL)
+       if (s != NULL)
                printk(" %s:", s);
                printk(" %s:", s);
-       printk(format, p[1], l16get(p+2), p[4], p[5], p[6], p[7]);
+       printk(format, p[1], l16get(p + 2), p[4], p[5], p[6], p[7]);
 }
 
 }
 
-static uint32_t
-mpmkintr(uint8_t* p)
+static uint32_t mpmkintr(uint8_t * p)
 {
        uint32_t v;
        struct apic *apic;
 {
        uint32_t v;
        struct apic *apic;
@@ -91,45 +90,45 @@ mpmkintr(uint8_t* p)
         * to imagine routing a signal to all IOAPICs, the
         * usual case is routing NMI and ExtINT to all LAPICs.
         */
         * to imagine routing a signal to all IOAPICs, the
         * usual case is routing NMI and ExtINT to all LAPICs.
         */
-       if(mpbus[p[4]] == NULL){
+       if (mpbus[p[4]] == NULL) {
                mpintrprint("no source bus", p);
                return 0;
        }
                mpintrprint("no source bus", p);
                return 0;
        }
-       if(p[6] != 0xff){
-               if(Napic < 256 && p[6] >= Napic){
+       if (p[6] != 0xff) {
+               if (Napic < 256 && p[6] >= Napic) {
                        mpintrprint("APIC ID out of range", p);
                        return 0;
                }
                        mpintrprint("APIC ID out of range", p);
                        return 0;
                }
-               switch(p[0]){
-               default:
-                       mpintrprint("INTIN botch", p);
-                       return 0;
-               case 3:                         /* IOINTR */
-                       apic = &xioapic[p[6]];
-                       if(!apic->useable){
-                               mpintrprint("unuseable ioapic", p);
+               switch (p[0]) {
+                       default:
+                               mpintrprint("INTIN botch", p);
                                return 0;
                                return 0;
-                       }
-                       if(p[7] >= apic->nrdt){
-                               mpintrprint("IO INTIN out of range", p);
-                               return 0;
-                       }
-                       break;
-               case 4:                         /* LINTR */
-                       apic = &xlapic[p[6]];
-                       if(!apic->useable){
-                               mpintrprint("unuseable lapic", p);
-                               return 0;
-                       }
-                       if(p[7] >= ARRAY_SIZE(apic->lvt)){
-                               mpintrprint("LOCAL INTIN out of range", p);
-                               return 0;
-                       }
-                       break;
+                       case 3: /* IOINTR */
+                               apic = &xioapic[p[6]];
+                               if (!apic->useable) {
+                                       mpintrprint("unuseable ioapic", p);
+                                       return 0;
+                               }
+                               if (p[7] >= apic->nrdt) {
+                                       mpintrprint("IO INTIN out of range", p);
+                                       return 0;
+                               }
+                               break;
+                       case 4: /* LINTR */
+                               apic = &xlapic[p[6]];
+                               if (!apic->useable) {
+                                       mpintrprint("unuseable lapic", p);
+                                       return 0;
+                               }
+                               if (p[7] >= ARRAY_SIZE(apic->lvt)) {
+                                       mpintrprint("LOCAL INTIN out of range", p);
+                                       return 0;
+                               }
+                               break;
                }
        }
                }
        }
-       n = l16get(p+2);
-       if((polarity = (n & 0x03)) == 2 || (trigger = ((n>>2) & 0x03)) == 2){
+       n = l16get(p + 2);
+       if ((polarity = (n & 0x03)) == 2 || (trigger = ((n >> 2) & 0x03)) == 2) {
                mpintrprint("invalid polarity/trigger", p);
                return 0;
        }
                mpintrprint("invalid polarity/trigger", p);
                return 0;
        }
@@ -143,189 +142,188 @@ mpmkintr(uint8_t* p)
         * whether INT is Fixed or Lowest Priority is left until later.
         */
        v = Im;
         * whether INT is Fixed or Lowest Priority is left until later.
         */
        v = Im;
-       switch(p[1]){
-       default:
-               mpintrprint("invalid type", p);
-               return 0;
-       case 0:                                 /* INT */
-               switch(polarity){
-               case 0:
-                       v |= mpbus[p[4]]->polarity;
-                       break;
-               case 1:
-                       v |= IPhigh;
-                       break;
-               case 3:
-                       v |= IPlow;
+       switch (p[1]) {
+               default:
+                       mpintrprint("invalid type", p);
+                       return 0;
+               case 0: /* INT */
+                       switch (polarity) {
+                               case 0:
+                                       v |= mpbus[p[4]]->polarity;
+                                       break;
+                               case 1:
+                                       v |= IPhigh;
+                                       break;
+                               case 3:
+                                       v |= IPlow;
+                                       break;
+                       }
+                       switch (trigger) {
+                               case 0:
+                                       v |= mpbus[p[4]]->trigger;
+                                       break;
+                               case 1:
+                                       v |= TMedge;
+                                       break;
+                               case 3:
+                                       v |= TMlevel;
+                                       break;
+                       }
                        break;
                        break;
-               }
-               switch(trigger){
-               case 0:
-                       v |= mpbus[p[4]]->trigger;
+               case 1: /* NMI */
+                       v |= TMedge | IPhigh | MTnmi;
                        break;
                        break;
-               case 1:
-                       v |= TMedge;
+               case 2: /* SMI */
+                       v |= TMedge | IPhigh | MTsmi;
                        break;
                        break;
-               case 3:
-                       v |= TMlevel;
+               case 3: /* ExtINT */
+                       v |= TMedge | IPhigh | MTei;
                        break;
                        break;
-               }
-               break;
-       case 1:                                 /* NMI */
-               v |= TMedge|IPhigh|MTnmi;
-               break;
-       case 2:                                 /* SMI */
-               v |= TMedge|IPhigh|MTsmi;
-               break;
-       case 3:                                 /* ExtINT */
-               v |= TMedge|IPhigh|MTei;
-               break;
        }
 
        return v;
 }
 
        }
 
        return v;
 }
 
-static int
-mpparse(PCMP* pcmp, int maxcores)
+static int mpparse(PCMP * pcmp, int maxcores)
 {
        uint32_t lo;
        uint8_t *e, *p;
        int devno, i, n;
 
        p = pcmp->entries;
 {
        uint32_t lo;
        uint8_t *e, *p;
        int devno, i, n;
 
        p = pcmp->entries;
-       e = (( uint8_t *)pcmp)+l16get(pcmp->length);
-       while(p < e) switch(*p){
-       default:
-               printd("mpparse: unknown PCMP type %d (e-p %#ld)\n", *p, e-p);
-               for(i = 0; p < e; i++){
-                       if(i && ((i & 0x0f) == 0))
+       e = ((uint8_t *) pcmp) + l16get(pcmp->length);
+       while (p < e)
+               switch (*p) {
+                       default:
+                               printd("mpparse: unknown PCMP type %d (e-p %#ld)\n", *p, e - p);
+                               for (i = 0; p < e; i++) {
+                                       if (i && ((i & 0x0f) == 0))
+                                               printd("\n");
+                                       printd(" %#2.2ux", *p);
+                                       p++;
+                               }
                                printd("\n");
                                printd("\n");
-                       printd(" %#2.2ux", *p);
-                       p++;
-               }
-               printd("\n");
-               break;
-       case 0:                                 /* processor */
-               /*
-                * Initialise the APIC if it is enabled (p[3] & 0x01).
-                * p[1] is the APIC ID, the memory mapped address comes
-                * from the PCMP structure as the addess is local to the
-                * CPU and identical for all. Indicate whether this is
-                * the bootstrap processor (p[3] & 0x02).
-                */
-               printk("mpparse: cpu %d pa %p bp %d\n",
-                       p[1], l32get(pcmp->apicpa), p[3] & 0x02);
-               if((p[3] & 0x01) != 0 && maxcores > 0){
-                               maxcores--;
-                               apicinit(p[1], l32get(pcmp->apicpa), p[3] & 0x02);
-               }
-               p += 20;
-               break;
-       case 1:                                 /* bus */
-               printk("mpparse: bus: %d type %6.6s\n", p[1], ( char *)p+2);
-               if(p[1] >= Nbus){
-                       printd("mpparse: bus %d out of range\n", p[1]);
-                       p += 8;
-                       break;
-               }
-               if(mpbus[p[1]] != NULL){
-                       printd("mpparse: bus %d already allocated\n", p[1]);
-                       p += 8;
-                       break;
-               }
-               for(i = 0; i < ARRAY_SIZE(mpbusdef); i++){
-                       if(memcmp(p+2, mpbusdef[i].type, 6) != 0)
-                               continue;
-                       if(memcmp(p+2, "ISA   ", 6) == 0){
-                               if(mpisabusno != -1){
-                                       printd("mpparse: bus %d already have ISA bus %d\n",
-                                               p[1], mpisabusno);
-                                       continue;
+                               break;
+                       case 0: /* processor */
+                               /*
+                                * Initialise the APIC if it is enabled (p[3] & 0x01).
+                                * p[1] is the APIC ID, the memory mapped address comes
+                                * from the PCMP structure as the addess is local to the
+                                * CPU and identical for all. Indicate whether this is
+                                * the bootstrap processor (p[3] & 0x02).
+                                */
+                               printk("mpparse: cpu %d pa %p bp %d\n",
+                                          p[1], l32get(pcmp->apicpa), p[3] & 0x02);
+                               if ((p[3] & 0x01) != 0 && maxcores > 0) {
+                                       maxcores--;
+                                       apicinit(p[1], l32get(pcmp->apicpa), p[3] & 0x02);
                                }
                                }
-                               mpisabusno = p[1];
-                       }
-                       mpbus[p[1]] = &mpbusdef[i];
-                       break;
-               }
-               if(mpbus[p[1]] == NULL)
-                       printd("mpparse: bus %d type %6.6s unknown\n",
-                               p[1], ( char *unused_char_p_t)p+2);
-
-               p += 8;
-               break;
-       case 2:                                 /* IOAPIC */
-               /*
-                * Initialise the IOAPIC if it is enabled (p[3] & 0x01).
-                * p[1] is the APIC ID, p[4-7] is the memory mapped address.
-                */
-               if(p[3] & 0x01)
-                       ioapicinit(p[1], -1, l32get(p+4));
-
-               p += 8;
-               break;
-       case 3:                                 /* IOINTR */
-               /*
-                * p[1] is the interrupt type;
-                * p[2-3] contains the polarity and trigger mode;
-                * p[4] is the source bus;
-                * p[5] is the IRQ on the source bus;
-                * p[6] is the destination APIC;
-                * p[7] is the INITIN pin on the destination APIC.
-                */
-               if(p[6] == 0xff){
-                       mpintrprint("routed to all IOAPICs", p);
-                       p += 8;
-                       break;
-               }
-               if((lo = mpmkintr(p)) == 0){
-                       p += 8;
-                       break;
-               }
-               if(2)
-                       mpintrprint(NULL, p);
-
-               /*
-                * Always present the device number in the style
-                * of a PCI Interrupt Assignment Entry. For the ISA
-                * bus the IRQ is the device number but unencoded.
-                * May need to handle other buses here in the future
-                * (but unlikely).
-                */
-               devno = p[5];
-               if(memcmp(mpbus[p[4]]->type, "PCI   ", 6) != 0)
-                       devno <<= 2;
-       void
-               ioapicintrinit(int busno, int apicno, int intin, int devno, int lo);
-       ioapicintrinit(p[4], p[6], p[7], devno, lo);
-
-               p += 8;
-               break;
-       case 4:                                 /* LINTR */
-               /*
-                * Format is the same as IOINTR above.
-                */
-               if((lo = mpmkintr(p)) == 0){
-                       p += 8;
-                       break;
-               }
-               if(2)
-                       mpintrprint(NULL, p);
-
-               /*
-                * Everything was checked in mpmkintr above.
-                */
-               if(p[6] == 0xff){
-                       for(i = 0; i < Napic; i++){
-                               if(!xlapic[i].useable || xlapic[i].addr != NULL)
-                                       continue;
-                               xlapic[i].lvt[p[7]] = lo;
-                       }
+                               p += 20;
+                               break;
+                       case 1: /* bus */
+                               printk("mpparse: bus: %d type %6.6s\n", p[1], (char *)p + 2);
+                               if (p[1] >= Nbus) {
+                                       printd("mpparse: bus %d out of range\n", p[1]);
+                                       p += 8;
+                                       break;
+                               }
+                               if (mpbus[p[1]] != NULL) {
+                                       printd("mpparse: bus %d already allocated\n", p[1]);
+                                       p += 8;
+                                       break;
+                               }
+                               for (i = 0; i < ARRAY_SIZE(mpbusdef); i++) {
+                                       if (memcmp(p + 2, mpbusdef[i].type, 6) != 0)
+                                               continue;
+                                       if (memcmp(p + 2, "ISA   ", 6) == 0) {
+                                               if (mpisabusno != -1) {
+                                                       printd("mpparse: bus %d already have ISA bus %d\n",
+                                                                  p[1], mpisabusno);
+                                                       continue;
+                                               }
+                                               mpisabusno = p[1];
+                                       }
+                                       mpbus[p[1]] = &mpbusdef[i];
+                                       break;
+                               }
+                               if (mpbus[p[1]] == NULL)
+                                       printd("mpparse: bus %d type %6.6s unknown\n",
+                                                  p[1], (char *unused_char_p_t)p + 2);
+
+                               p += 8;
+                               break;
+                       case 2: /* IOAPIC */
+                               /*
+                                * Initialise the IOAPIC if it is enabled (p[3] & 0x01).
+                                * p[1] is the APIC ID, p[4-7] is the memory mapped address.
+                                */
+                               if (p[3] & 0x01)
+                                       ioapicinit(p[1], -1, l32get(p + 4));
+
+                               p += 8;
+                               break;
+                       case 3: /* IOINTR */
+                               /*
+                                * p[1] is the interrupt type;
+                                * p[2-3] contains the polarity and trigger mode;
+                                * p[4] is the source bus;
+                                * p[5] is the IRQ on the source bus;
+                                * p[6] is the destination APIC;
+                                * p[7] is the INITIN pin on the destination APIC.
+                                */
+                               if (p[6] == 0xff) {
+                                       mpintrprint("routed to all IOAPICs", p);
+                                       p += 8;
+                                       break;
+                               }
+                               if ((lo = mpmkintr(p)) == 0) {
+                                       p += 8;
+                                       break;
+                               }
+                               if (2)
+                                       mpintrprint(NULL, p);
+
+                               /*
+                                * Always present the device number in the style
+                                * of a PCI Interrupt Assignment Entry. For the ISA
+                                * bus the IRQ is the device number but unencoded.
+                                * May need to handle other buses here in the future
+                                * (but unlikely).
+                                */
+                               devno = p[5];
+                               if (memcmp(mpbus[p[4]]->type, "PCI   ", 6) != 0)
+                                       devno <<= 2;
+                               void ioapicintrinit(int busno, int apicno, int intin, int devno,
+                                                                       int lo);
+                               ioapicintrinit(p[4], p[6], p[7], devno, lo);
+
+                               p += 8;
+                               break;
+                       case 4: /* LINTR */
+                               /*
+                                * Format is the same as IOINTR above.
+                                */
+                               if ((lo = mpmkintr(p)) == 0) {
+                                       p += 8;
+                                       break;
+                               }
+                               if (2)
+                                       mpintrprint(NULL, p);
+
+                               /*
+                                * Everything was checked in mpmkintr above.
+                                */
+                               if (p[6] == 0xff) {
+                                       for (i = 0; i < Napic; i++) {
+                                               if (!xlapic[i].useable || xlapic[i].addr != NULL)
+                                                       continue;
+                                               xlapic[i].lvt[p[7]] = lo;
+                                       }
+                               } else
+                                       xlapic[p[6]].lvt[p[7]] = lo;
+                               p += 8;
+                               break;
                }
                }
-               else
-                       xlapic[p[6]].lvt[p[7]] = lo;
-               p += 8;
-               break;
-       }
 
        /*
         * There's nothing of interest in the extended table,
 
        /*
         * There's nothing of interest in the extended table,
@@ -333,62 +331,60 @@ mpparse(PCMP* pcmp, int maxcores)
         */
        p = e;
        e = p + l16get(pcmp->xlength);
         */
        p = e;
        e = p + l16get(pcmp->xlength);
-       while(p < e) switch(*p){
-       default:
-               n = p[1];
-               printd("mpparse: unknown extended entry %d length %d\n", *p, n);
-               for(i = 0; i < n; i++){
-                       if(i && ((i & 0x0f) == 0))
+       while (p < e)
+               switch (*p) {
+                       default:
+                               n = p[1];
+                               printd("mpparse: unknown extended entry %d length %d\n", *p, n);
+                               for (i = 0; i < n; i++) {
+                                       if (i && ((i & 0x0f) == 0))
+                                               printd("\n");
+                                       printd(" %#2.2ux", *p);
+                                       p++;
+                               }
                                printd("\n");
                                printd("\n");
-                       printd(" %#2.2ux", *p);
-                       p++;
+                               break;
+                       case 128:
+                               printk("address space mapping\n");
+                               printk(" bus %d type %d base %#llux length %#llux\n",
+                                          p[2], p[3], l64get(p + 4), l64get(p + 12));
+                               p += p[1];
+                               break;
+                       case 129:
+                               printk("bus hierarchy descriptor\n");
+                               printk(" bus %d sd %d parent bus %d\n", p[2], p[3], p[4]);
+                               p += p[1];
+                               break;
+                       case 130:
+                               printk("compatibility bus address space modifier\n");
+                               printk(" bus %d pr %d range list %d\n",
+                                          p[2], p[3], l32get(p + 4));
+                               p += p[1];
+                               break;
                }
                }
-               printd("\n");
-               break;
-       case 128:
-               printk("address space mapping\n");
-               printk(" bus %d type %d base %#llux length %#llux\n",
-                       p[2], p[3], l64get(p+4), l64get(p+12));
-               p += p[1];
-               break;
-       case 129:
-               printk("bus hierarchy descriptor\n");
-               printk(" bus %d sd %d parent bus %d\n",
-                       p[2], p[3], p[4]);
-               p += p[1];
-               break;
-       case 130:
-               printk("compatibility bus address space modifier\n");
-               printk(" bus %d pr %d range list %d\n",
-                       p[2], p[3], l32get(p+4));
-               p += p[1];
-               break;
-       }
        return maxcores;
 }
 
        return maxcores;
 }
 
-static int
-sigchecksum(void* address, int length)
+static int sigchecksum(void *address, int length)
 {
        uint8_t *p, sum;
 
        sum = 0;
 {
        uint8_t *p, sum;
 
        sum = 0;
-       for(p = address; length-- > 0; p++)
+       for (p = address; length-- > 0; p++)
                sum += *p;
 
        return sum;
 }
 
                sum += *p;
 
        return sum;
 }
 
-static void*
-sigscan(uint8_t* address, int length, char* signature)
+static void *sigscan(uint8_t * address, int length, char *signature)
 {
        uint8_t *e, *p;
        int siglength;
 
 {
        uint8_t *e, *p;
        int siglength;
 
-       e = address+length;
+       e = address + length;
        siglength = strlen(signature);
        siglength = strlen(signature);
-       for(p = address; p+siglength < e; p += 16){
-               if(memcmp(p, signature, siglength))
+       for (p = address; p + siglength < e; p += 16) {
+               if (memcmp(p, signature, siglength))
                        continue;
                return p;
        }
                        continue;
                return p;
        }
@@ -396,8 +392,7 @@ sigscan(uint8_t* address, int length, char* signature)
        return NULL;
 }
 
        return NULL;
 }
 
-static void*
-sigsearch(char* signature)
+static void *sigsearch(char *signature)
 {
        uintptr_t p;
        uint8_t *bda;
 {
        uintptr_t p;
        uint8_t *bda;
@@ -410,83 +405,82 @@ sigsearch(char* signature)
         * 3) in the BIOS ROM between 0xe0000 and 0xfffff.
         */
        bda = BIOSSEG(0x40);
         * 3) in the BIOS ROM between 0xe0000 and 0xfffff.
         */
        bda = BIOSSEG(0x40);
-       if(memcmp(KADDR(0xfffd9), "EISA", 4) == 0){
-               if((p = (bda[0x0f]<<8)|bda[0x0e])){
-                       if((r = sigscan(BIOSSEG(p), 1024, signature)) != NULL)
+       if (memcmp(KADDR(0xfffd9), "EISA", 4) == 0) {
+               if ((p = (bda[0x0f] << 8) | bda[0x0e])) {
+                       if ((r = sigscan(BIOSSEG(p), 1024, signature)) != NULL)
                                return r;
                }
        }
 
                                return r;
                }
        }
 
-       p = ((bda[0x14]<<8)|bda[0x13])*1024;
-       if((r = sigscan(KADDR(p-1024), 1024, signature)) != NULL)
+       p = ((bda[0x14] << 8) | bda[0x13]) * 1024;
+       if ((r = sigscan(KADDR(p - 1024), 1024, signature)) != NULL)
                return r;
 #endif
        r = sigscan(KADDR(0xe0000), 0x20000, signature);
        printk("Found mp table at %p\n", r);
                return r;
 #endif
        r = sigscan(KADDR(0xe0000), 0x20000, signature);
        printk("Found mp table at %p\n", r);
-       if(r != NULL)
+       if (r != NULL)
                return r;
 
        return NULL;
        /* and virtualbox hidden mp tables... */
                return r;
 
        return NULL;
        /* and virtualbox hidden mp tables... */
-//     return sigscan(KADDR(0xa0000 - 1024), 1024, signature);
+//  return sigscan(KADDR(0xa0000 - 1024), 1024, signature);
 }
 
 }
 
-int
-mpsinit(int maxcores)
+int mpsinit(int maxcores)
 {
        uint8_t *p;
        int i, n, ncleft = 254;
        _MP_ *mp;
        PCMP *pcmp;
 
 {
        uint8_t *p;
        int i, n, ncleft = 254;
        _MP_ *mp;
        PCMP *pcmp;
 
-       if((mp = sigsearch("_MP_")) == NULL){
+       if ((mp = sigsearch("_MP_")) == NULL) {
                printd("no mp tables\n");
                return ncleft;
        }
 
                printd("no mp tables\n");
                return ncleft;
        }
 
-       if(2){
+       if (2) {
                printk("_MP_ @ %#p, addr %p length %ud rev %d",
                printk("_MP_ @ %#p, addr %p length %ud rev %d",
-                       mp, l32get(mp->addr), mp->length, mp->revision);
-               for(i = 0; i < sizeof(mp->feature); i++)
+                          mp, l32get(mp->addr), mp->length, mp->revision);
+               for (i = 0; i < sizeof(mp->feature); i++)
                        printk(" %2.2p", mp->feature[i]);
                printk("\n");
        }
                        printk(" %2.2p", mp->feature[i]);
                printk("\n");
        }
-       if(mp->revision != 1 && mp->revision != 4)
+       if (mp->revision != 1 && mp->revision != 4)
                return ncleft;
                return ncleft;
-       if(sigchecksum(mp, mp->length*16) != 0)
+       if (sigchecksum(mp, mp->length * 16) != 0)
                return ncleft;
 #define vmap(x,y) KADDR((x))
                return ncleft;
 #define vmap(x,y) KADDR((x))
-#define vunmap(x,y) 
+#define vunmap(x,y)
 
 
-       if((pcmp = vmap(l32get(mp->addr), sizeof(PCMP))) == NULL)
+       if ((pcmp = vmap(l32get(mp->addr), sizeof(PCMP))) == NULL)
                return ncleft;
                return ncleft;
-       if(pcmp->revision != 1 && pcmp->revision != 4){
+       if (pcmp->revision != 1 && pcmp->revision != 4) {
                return ncleft;
        }
        n = l16get(pcmp->length) + l16get(pcmp->xlength);
        vunmap(pcmp, sizeof(PCMP));
                return ncleft;
        }
        n = l16get(pcmp->length) + l16get(pcmp->xlength);
        vunmap(pcmp, sizeof(PCMP));
-       if((pcmp = vmap(l32get(mp->addr), n)) == NULL)
+       if ((pcmp = vmap(l32get(mp->addr), n)) == NULL)
                return ncleft;
                return ncleft;
-       if(sigchecksum(pcmp, l16get(pcmp->length)) != 0){
+       if (sigchecksum(pcmp, l16get(pcmp->length)) != 0) {
                vunmap(pcmp, n);
                return ncleft;
        }
                vunmap(pcmp, n);
                return ncleft;
        }
-       if(2){
+       if (2) {
                printk("PCMP @ %#p length %p revision %d\n",
                printk("PCMP @ %#p length %p revision %d\n",
-                       pcmp, l16get(pcmp->length), pcmp->revision);
+                          pcmp, l16get(pcmp->length), pcmp->revision);
                printk(" %20.20s oaddr %p olength %p\n",
                printk(" %20.20s oaddr %p olength %p\n",
-                       char *)pcmp->string, l32get(pcmp->oaddr),
-                       l16get(pcmp->olength));
+                          (char *)pcmp->string, l32get(pcmp->oaddr),
+                          l16get(pcmp->olength));
                printk(" entry %d apicpa %p\n",
                printk(" entry %d apicpa %p\n",
-                       l16get(pcmp->entry), l32get(pcmp->apicpa));
+                          l16get(pcmp->entry), l32get(pcmp->apicpa));
 
                printk(" xlength %p xchecksum %p\n",
 
                printk(" xlength %p xchecksum %p\n",
-                       l16get(pcmp->xlength), pcmp->xchecksum);
+                          l16get(pcmp->xlength), pcmp->xchecksum);
        }
        }
-       if(pcmp->xchecksum != 0){
-               p = (( uint8_t *)pcmp) + l16get(pcmp->length);
+       if (pcmp->xchecksum != 0) {
+               p = ((uint8_t *) pcmp) + l16get(pcmp->length);
                i = sigchecksum(p, l16get(pcmp->xlength));
                i = sigchecksum(p, l16get(pcmp->xlength));
-               if(((i+pcmp->xchecksum) & 0xff) != 0){
+               if (((i + pcmp->xchecksum) & 0xff) != 0) {
                        printd("extended table checksums to %p\n", i);
                        vunmap(pcmp, n);
                        return ncleft;
                        printd("extended table checksums to %p\n", i);
                        vunmap(pcmp, n);
                        return ncleft;
@@ -500,8 +494,8 @@ mpsinit(int maxcores)
         */
        ncleft = mpparse(pcmp, maxcores);
        return ncleft;
         */
        ncleft = mpparse(pcmp, maxcores);
        return ncleft;
-//     mpacpi(ncleft);
+//  mpacpi(ncleft);
 
 
-//     apicdump();
-//     ioapicdump();
+//  apicdump();
+//  ioapicdump();
 }
 }
index cb3b4e3..a713352 100644 (file)
 #include <arch/ioapic.h>
 #include <arch/coreid.h>
 
 #include <arch/ioapic.h>
 #include <arch/coreid.h>
 
-extern struct Madt     *apics;
+extern struct Madt *apics;
 
 
-int
-mpacpi(int ncleft)
+int mpacpi(int ncleft)
 {
        char *already;
        int np, bp;
 {
        char *already;
        int np, bp;
@@ -31,49 +30,52 @@ mpacpi(int ncleft)
                return ncleft;
 
        printd("APIC lapic paddr %#.8llux, flags %#.8ux\n",
                return ncleft;
 
        printd("APIC lapic paddr %#.8llux, flags %#.8ux\n",
-               apics->lapicpa, apics->pcat);
+                  apics->lapicpa, apics->pcat);
        np = 0;
        printd("apics->st %p\n", apics->st);
        np = 0;
        printd("apics->st %p\n", apics->st);
-       for(st = apics->st; st != NULL; st = st->next){
+       for (st = apics->st; st != NULL; st = st->next) {
                already = "";
                already = "";
-               switch(st->type){
-               case ASlapic:
-                       printd("ASlapic %d\n", st->lapic.id);
-                       /* this table is supposed to have all of them if it exists */
-                       if(st->lapic.id > MaxAPICNO)
-                               break;
-                       apic = xlapic + st->lapic.id;
-                       bp = (np++ == 0);
-                       if(apic->useable){
-                               already = "(mp)";
-                       }
-                       else if(ncleft != 0){
-                               ncleft--;
-                               printk("apicinit(%d, %p, %d);\n", st->lapic.id, apics->lapicpa, bp);
-                               apicinit(st->lapic.id, apics->lapicpa, bp);
-                       } else
-                               already = "(off)";
+               switch (st->type) {
+                       case ASlapic:
+                               printd("ASlapic %d\n", st->lapic.id);
+                               /* this table is supposed to have all of them if it exists */
+                               if (st->lapic.id > MaxAPICNO)
+                                       break;
+                               apic = xlapic + st->lapic.id;
+                               bp = (np++ == 0);
+                               if (apic->useable) {
+                                       already = "(mp)";
+                               } else if (ncleft != 0) {
+                                       ncleft--;
+                                       printk("apicinit(%d, %p, %d);\n", st->lapic.id,
+                                                  apics->lapicpa, bp);
+                                       apicinit(st->lapic.id, apics->lapicpa, bp);
+                               } else
+                                       already = "(off)";
 
 
-                       printd("apic proc %d/%d apicid %d %s\n", np-1, apic->machno, st->lapic.id, already);
-monitor(NULL);
-                       break;
-               case ASioapic:
-                       printd("ASioapic %d\n", st->ioapic.id);
-                       if(st->ioapic.id > Napic)
+                               printd("apic proc %d/%d apicid %d %s\n", np - 1, apic->machno,
+                                          st->lapic.id, already);
+                               monitor(NULL);
+                               break;
+                       case ASioapic:
+                               printd("ASioapic %d\n", st->ioapic.id);
+                               if (st->ioapic.id > Napic)
+                                       break;
+                               apic = xioapic + st->ioapic.id;
+                               if (apic->useable) {
+                                       apic->ibase = st->ioapic.ibase; /* gnarly */
+                                       already = "(mp)";
+                                       goto pr1;
+                               }
+                               printk("ioapicinit(%d, %p, %p);\n", st->lapic.id,
+                                          apics->lapicpa, st->ioapic.addr);
+                               ioapicinit(st->ioapic.id, st->ioapic.ibase, st->ioapic.addr);
+                               monitor(NULL);
+pr1:
+                               printd("ioapic %d ", st->ioapic.id);
+                               printd("addr %p base %d %s\n", apic->paddr, apic->ibase,
+                                          already);
                                break;
                                break;
-                       apic = xioapic + st->ioapic.id;
-                       if(apic->useable){
-                               apic->ibase = st->ioapic.ibase; /* gnarly */
-                               already = "(mp)";
-                               goto pr1;
-                       }
-                       printk("ioapicinit(%d, %p, %p);\n", st->lapic.id, apics->lapicpa, st->ioapic.addr);
-                       ioapicinit(st->ioapic.id, st->ioapic.ibase, st->ioapic.addr);
-monitor(NULL);
-               pr1:
-                       printd("ioapic %d ", st->ioapic.id);
-                       printd("addr %p base %d %s\n", apic->paddr, apic->ibase, already);
-                       break;
                }
        }
        return ncleft;
                }
        }
        return ncleft;
index 7d948f0..7037ba9 100644 (file)
  * for the user-level interpreter.
  */
 
  * for the user-level interpreter.
  */
 
-
 #define l16get(p)      (((p)[1]<<8)|(p)[0])
 #define l32get(p)      (((uint32_t)l16get(p+2)<<16)|l16get(p))
 #define l16get(p)      (((p)[1]<<8)|(p)[0])
 #define l32get(p)      (((uint32_t)l16get(p+2)<<16)|l16get(p))
-static struct Atable* acpifadt( uint8_t *, int);
-static struct Atable* acpitable( uint8_t *, int);
-static struct Atable* acpimadt( uint8_t *, int);
-static struct Atable* acpimsct( uint8_t *, int);
-static struct Atable* acpisrat( uint8_t *, int);
-static struct Atable* acpislit( uint8_t *, int);
-
-
-static struct cmdtab ctls[] =
-{
-       {CMregion,      "region",       6},
-       {CMgpe,         "gpe",          3},
+static struct Atable *acpifadt(uint8_t *, int);
+static struct Atable *acpitable(uint8_t *, int);
+static struct Atable *acpimadt(uint8_t *, int);
+static struct Atable *acpimsct(uint8_t *, int);
+static struct Atable *acpisrat(uint8_t *, int);
+static struct Atable *acpislit(uint8_t *, int);
+
+static struct cmdtab ctls[] = {
+       {CMregion, "region", 6},
+       {CMgpe, "gpe", 3},
 };
 
 };
 
-static struct dirtab acpidir[]={
-       {".",           {Qdir, 0, QTDIR},       0,      DMDIR|0555},
-       {"acpictl",     {Qctl},                 0,      0666},
-       {"acpitbl",     {Qtbl},                 0,      0444},
-       {"acpiregio",   {Qio},                  0,      0666},
-       {"acpipretty",  {Qpretty},              0,      0444},
-       {"ioapic",      {Qioapic},              0,      0444},
-       {"apic",        {Qapic},                0,      0444},
+static struct dirtab acpidir[] = {
+       {".", {Qdir, 0, QTDIR}, 0, DMDIR | 0555},
+       {"acpictl", {Qctl}, 0, 0666},
+       {"acpitbl", {Qtbl}, 0, 0444},
+       {"acpiregio", {Qio}, 0, 0666},
+       {"acpipretty", {Qpretty}, 0, 0444},
+       {"ioapic", {Qioapic}, 0, 0444},
+       {"apic", {Qapic}, 0, 0444},
 };
 
 /*
 };
 
 /*
@@ -67,155 +64,136 @@ static struct dirtab acpidir[]={
  * Other tables are given to the user level interpreter for
  * execution.
  */
  * Other tables are given to the user level interpreter for
  * execution.
  */
-static struct Parse ptables[] =
-{
+static struct Parse ptables[] = {
        {"FACP", acpifadt},
        {"FACP", acpifadt},
-       {"APIC",        acpimadt,},
-       {"SRAT",        acpisrat,},
-       {"SLIT",        acpislit,},
-       {"MSCT",        acpimsct,},
+       {"APIC", acpimadt,},
+       {"SRAT", acpisrat,},
+       {"SLIT", acpislit,},
+       {"MSCT", acpimsct,},
        {"SSDT", acpitable,},
 };
 
        {"SSDT", acpitable,},
 };
 
-static struct Facs*    facs;   /* Firmware ACPI control structure */
-static struct Fadt     fadt;   /* Fixed ACPI description. To reach ACPI registers */
-static struct Xsdt*    xsdt;   /* XSDT table */
-static struct Atable*  tfirst; /* loaded DSDT/SSDT/... tables */
-static struct Atable*  tlast;  /* pointer to last table */
-struct Madt*   apics;  /* APIC info */
-static struct Srat*    srat;   /* System resource affinity, used by physalloc */
-static struct Slit*    slit;   /* System locality information table used by the scheduler */
-static struct Msct*    msct;   /* Maximum system characteristics table */
-static struct Reg*     reg;    /* region used for I/O */
-static struct Gpe*     gpes;   /* General purpose events */
-static int     ngpes;
-
-static charregnames[] = {
+static struct Facs *facs;              /* Firmware ACPI control structure */
+static struct Fadt fadt;               /* Fixed ACPI description. To reach ACPI registers */
+static struct Xsdt *xsdt;              /* XSDT table */
+static struct Atable *tfirst;  /* loaded DSDT/SSDT/... tables */
+static struct Atable *tlast;   /* pointer to last table */
+struct Madt *apics;                            /* APIC info */
+static struct Srat *srat;              /* System resource affinity, used by physalloc */
+static struct Slit *slit;              /* System locality information table used by the scheduler */
+static struct Msct *msct;              /* Maximum system characteristics table */
+static struct Reg *reg;                        /* region used for I/O */
+static struct Gpe *gpes;               /* General purpose events */
+static int ngpes;
+
+static char *regnames[] = {
        "mem", "io", "pcicfg", "embed",
        "smb", "cmos", "pcibar",
 };
 
        "mem", "io", "pcicfg", "embed",
        "smb", "cmos", "pcibar",
 };
 
-static char *
-dumpGas(char *start, char *end, char *prefix, struct Gas *g);
+static char *dumpGas(char *start, char *end, char *prefix, struct Gas *g);
 
 
-static char*
-acpiregstr(int id)
+static char *acpiregstr(int id)
 {
 {
-       static char buf[20];    /* BUG */
+       static char buf[20];            /* BUG */
 
 
-       if(id >= 0 && id < ARRAY_SIZE(regnames)) {
+       if (id >= 0 && id < ARRAY_SIZE(regnames)) {
                return regnames[id];
        }
                return regnames[id];
        }
-       seprintf(buf, buf+sizeof(buf), "spc:%#x", id);
+       seprintf(buf, buf + sizeof(buf), "spc:%#x", id);
        return buf;
 }
 
        return buf;
 }
 
-static int
-acpiregid(char *s)
+static int acpiregid(char *s)
 {
        int i;
 
 {
        int i;
 
-       for(i = 0; i < ARRAY_SIZE(regnames); i++)
-               if(strcmp(regnames[i], s) == 0) {
+       for (i = 0; i < ARRAY_SIZE(regnames); i++)
+               if (strcmp(regnames[i], s) == 0) {
                        return i;
                }
        return -1;
 }
 
                        return i;
                }
        return -1;
 }
 
-static uint8_t
-mget8(uintptr_t p, void*unused)
+static uint8_t mget8(uintptr_t p, void *unused)
 {
 {
-       uint8_t *cp = (uint8_t*)p;
+       uint8_t *cp = (uint8_t *) p;
        return *cp;
 }
 
        return *cp;
 }
 
-static void
-mset8(uintptr_t p, uint8_t v, void*unused)
+static void mset8(uintptr_t p, uint8_t v, void *unused)
 {
 {
-       uint8_t *cp = (uint8_t*)p;
+       uint8_t *cp = (uint8_t *) p;
        *cp = v;
 }
 
        *cp = v;
 }
 
-static uint16_t
-mget16(uintptr_t p, void*unused)
+static uint16_t mget16(uintptr_t p, void *unused)
 {
 {
-       uint16_t *cp = (uint16_t*)p;
+       uint16_t *cp = (uint16_t *) p;
        return *cp;
 }
 
        return *cp;
 }
 
-static void
-mset16(uintptr_t p, uint16_t v, void*unused)
+static void mset16(uintptr_t p, uint16_t v, void *unused)
 {
 {
-       uint16_t *cp = (uint16_t*)p;
+       uint16_t *cp = (uint16_t *) p;
        *cp = v;
 }
 
        *cp = v;
 }
 
-static uint32_t
-mget32(uintptr_t p, void*unused)
+static uint32_t mget32(uintptr_t p, void *unused)
 {
 {
-       uint32_t *cp = (uint32_t*)p;
+       uint32_t *cp = (uint32_t *) p;
        return *cp;
 }
 
        return *cp;
 }
 
-static void
-mset32(uintptr_t p, uint32_t v, void*unused)
+static void mset32(uintptr_t p, uint32_t v, void *unused)
 {
 {
-       uint32_t *cp = (uint32_t*)p;
+       uint32_t *cp = (uint32_t *) p;
        *cp = v;
 }
 
        *cp = v;
 }
 
-static uint64_t
-mget64(uintptr_t p, void*unused)
+static uint64_t mget64(uintptr_t p, void *unused)
 {
 {
-       uint64_t *cp = (uint64_t*)p;
+       uint64_t *cp = (uint64_t *) p;
        return *cp;
 }
 
        return *cp;
 }
 
-static void
-mset64(uintptr_t p, uint64_t v, void*unused)
+static void mset64(uintptr_t p, uint64_t v, void *unused)
 {
 {
-       uint64_t *cp = (uint64_t*)p;
+       uint64_t *cp = (uint64_t *) p;
        *cp = v;
 }
 
        *cp = v;
 }
 
-static uint8_t
-ioget8(uintptr_t p, void*unused)
+static uint8_t ioget8(uintptr_t p, void *unused)
 {
        return inb(p);
 }
 
 {
        return inb(p);
 }
 
-static void
-ioset8(uintptr_t p, uint8_t v, void*unused)
+static void ioset8(uintptr_t p, uint8_t v, void *unused)
 {
        outb(p, v);
 }
 
 {
        outb(p, v);
 }
 
-static uint16_t
-ioget16(uintptr_t p, void*unused)
+static uint16_t ioget16(uintptr_t p, void *unused)
 {
        return inw(p);
 }
 
 {
        return inw(p);
 }
 
-static void
-ioset16(uintptr_t p, uint16_t v, void*unused)
+static void ioset16(uintptr_t p, uint16_t v, void *unused)
 {
        outw(p, v);
 }
 
 {
        outw(p, v);
 }
 
-static uint32_t
-ioget32(uintptr_t p, void*unused)
+static uint32_t ioget32(uintptr_t p, void *unused)
 {
        return inl(p);
 }
 
 {
        return inl(p);
 }
 
-static void
-ioset32(uintptr_t p, uint32_t v, void*unused)
+static void ioset32(uintptr_t p, uint32_t v, void *unused)
 {
        outl(p, v);
 }
 
 {
        outl(p, v);
 }
 
-static uint8_t
-cfgget8(uintptr_t p, void* r)
+static uint8_t cfgget8(uintptr_t p, void *r)
 {
        struct Reg *ro = r;
        struct pci_device pcidev;
 {
        struct Reg *ro = r;
        struct pci_device pcidev;
@@ -224,8 +202,7 @@ cfgget8(uintptr_t p, void* r)
        return pcidev_read8(&pcidev, p);
 }
 
        return pcidev_read8(&pcidev, p);
 }
 
-static void
-cfgset8(uintptr_t p, uint8_t v, void* r)
+static void cfgset8(uintptr_t p, uint8_t v, void *r)
 {
        struct Reg *ro = r;
        struct pci_device pcidev;
 {
        struct Reg *ro = r;
        struct pci_device pcidev;
@@ -234,8 +211,7 @@ cfgset8(uintptr_t p, uint8_t v, void* r)
        pcidev_write8(&pcidev, p, v);
 }
 
        pcidev_write8(&pcidev, p, v);
 }
 
-static uint16_t
-cfgget16(uintptr_t p, void* r)
+static uint16_t cfgget16(uintptr_t p, void *r)
 {
        struct Reg *ro = r;
        struct pci_device pcidev;
 {
        struct Reg *ro = r;
        struct pci_device pcidev;
@@ -244,8 +220,7 @@ cfgget16(uintptr_t p, void* r)
        return pcidev_read16(&pcidev, p);
 }
 
        return pcidev_read16(&pcidev, p);
 }
 
-static void
-cfgset16(uintptr_t p, uint16_t v, void* r)
+static void cfgset16(uintptr_t p, uint16_t v, void *r)
 {
        struct Reg *ro = r;
        struct pci_device pcidev;
 {
        struct Reg *ro = r;
        struct pci_device pcidev;
@@ -254,8 +229,7 @@ cfgset16(uintptr_t p, uint16_t v, void* r)
        pcidev_write16(&pcidev, p, v);
 }
 
        pcidev_write16(&pcidev, p, v);
 }
 
-static uint32_t
-cfgget32(uintptr_t p, void* r)
+static uint32_t cfgget32(uintptr_t p, void *r)
 {
        struct Reg *ro = r;
        struct pci_device pcidev;
 {
        struct Reg *ro = r;
        struct pci_device pcidev;
@@ -264,8 +238,7 @@ cfgget32(uintptr_t p, void* r)
        return pcidev_read32(&pcidev, p);
 }
 
        return pcidev_read32(&pcidev, p);
 }
 
-static void
-cfgset32(uintptr_t p, uint32_t v, void* r)
+static void cfgset32(uintptr_t p, uint32_t v, void *r)
 {
        struct Reg *ro = r;
        struct pci_device pcidev;
 {
        struct Reg *ro = r;
        struct pci_device pcidev;
@@ -274,22 +247,19 @@ cfgset32(uintptr_t p, uint32_t v, void* r)
        pcidev_write32(&pcidev, p, v);
 }
 
        pcidev_write32(&pcidev, p, v);
 }
 
-static struct Regio memio = 
-{
+static struct Regio memio = {
        NULL,
        mget8, mset8, mget16, mset16,
        mget32, mset32, mget64, mset64
 };
 
        NULL,
        mget8, mset8, mget16, mset16,
        mget32, mset32, mget64, mset64
 };
 
-static struct Regio ioio = 
-{
+static struct Regio ioio = {
        NULL,
        ioget8, ioset8, ioget16, ioset16,
        ioget32, ioset32, NULL, NULL
 };
 
        NULL,
        ioget8, ioset8, ioget16, ioset16,
        ioget32, ioset32, NULL, NULL
 };
 
-static struct Regio cfgio = 
-{
+static struct Regio cfgio = {
        NULL,
        cfgget8, cfgset8, cfgget16, cfgset16,
        cfgget32, cfgset32, NULL, NULL
        NULL,
        cfgget8, cfgset8, cfgget16, cfgset16,
        cfgget32, cfgset32, NULL, NULL
@@ -300,173 +270,169 @@ static struct Regio cfgio =
  */
 static long
 regcpy(struct Regio *dio, uintptr_t da, struct Regio *sio,
  */
 static long
 regcpy(struct Regio *dio, uintptr_t da, struct Regio *sio,
-       uintptr_t sa, long len, int align)
+          uintptr_t sa, long len, int align)
 {
        int n, i;
 
        printk("regcpy %#p %#p %#p %#p\n", da, sa, len, align);
 {
        int n, i;
 
        printk("regcpy %#p %#p %#p %#p\n", da, sa, len, align);
-       if((len%align) != 0)
+       if ((len % align) != 0)
                printd("regcpy: bug: copy not aligned. truncated\n");
                printd("regcpy: bug: copy not aligned. truncated\n");
-       n = len/align;
-       for(i = 0; i < n; i++){
-               switch(align){
-               case 1:
-                       printk("cpy8 %#p %#p\n", da, sa);
-                       dio->set8(da, sio->get8(sa, sio->arg), dio->arg);
-                       break;
-               case 2:
-                       printk("cpy16 %#p %#p\n", da, sa);
-                       dio->set16(da, sio->get16(sa, sio->arg), dio->arg);
-                       break;
-               case 4:
-                       printk("cpy32 %#p %#p\n", da, sa);
-                       dio->set32(da, sio->get32(sa, sio->arg), dio->arg);
-                       break;
-               case 8:
-                       printk("cpy64 %#p %#p\n", da, sa);
-               //      dio->set64(da, sio->get64(sa, sio->arg), dio->arg);
-                       break;
-               default:
-                       panic("regcpy: align bug");
+       n = len / align;
+       for (i = 0; i < n; i++) {
+               switch (align) {
+                       case 1:
+                               printk("cpy8 %#p %#p\n", da, sa);
+                               dio->set8(da, sio->get8(sa, sio->arg), dio->arg);
+                               break;
+                       case 2:
+                               printk("cpy16 %#p %#p\n", da, sa);
+                               dio->set16(da, sio->get16(sa, sio->arg), dio->arg);
+                               break;
+                       case 4:
+                               printk("cpy32 %#p %#p\n", da, sa);
+                               dio->set32(da, sio->get32(sa, sio->arg), dio->arg);
+                               break;
+                       case 8:
+                               printk("cpy64 %#p %#p\n", da, sa);
+                               //  dio->set64(da, sio->get64(sa, sio->arg), dio->arg);
+                               break;
+                       default:
+                               panic("regcpy: align bug");
                }
                da += align;
                sa += align;
        }
                }
                da += align;
                sa += align;
        }
-       return n*align;
+       return n * align;
 }
 
 // until we know.
 //#define vmap(x,y) (void *)vmap_pmem((x),(y))
 //#define vunmap(x,y) vunmap_vmem((uintptr_t)(x),(y))
 #define vmap(x,y) KADDR((x))
 }
 
 // until we know.
 //#define vmap(x,y) (void *)vmap_pmem((x),(y))
 //#define vunmap(x,y) vunmap_vmem((uintptr_t)(x),(y))
 #define vmap(x,y) KADDR((x))
-#define vunmap(x,y) 
+#define vunmap(x,y)
 /*
  * Perform I/O within region in access units of accsz bytes.
  * All units in bytes.
  */
 /*
  * Perform I/O within region in access units of accsz bytes.
  * All units in bytes.
  */
-static long
-regio(struct Reg *r, void *p, uint32_t len, uintptr_t off, int iswr)
+static long regio(struct Reg *r, void *p, uint32_t len, uintptr_t off, int iswr)
 {
        struct Regio rio;
        uintptr_t rp;
 
        printk("reg%s %s %#p %#p %#lx sz=%d\n",
 {
        struct Regio rio;
        uintptr_t rp;
 
        printk("reg%s %s %#p %#p %#lx sz=%d\n",
-               iswr ? "out" : "in", r->name, p, off, len, r->accsz);
+                  iswr ? "out" : "in", r->name, p, off, len, r->accsz);
        rp = 0;
        rp = 0;
-       if(off + len > r->len){
+       if (off + len > r->len) {
                printd("regio: access outside limits");
                len = r->len - off;
        }
                printd("regio: access outside limits");
                len = r->len - off;
        }
-       if(len <= 0){
+       if (len <= 0) {
                printd("regio: zero len\n");
                return 0;
        }
                printd("regio: zero len\n");
                return 0;
        }
-       switch(r->spc){
-       case Rsysmem:
-               // XXX should map only what we are going to use
-               // A region might be too large.
-               // we don't have this nonsense in akaros, right? 
-               if(r->p == NULL)
-                       r->p = vmap(r->base, len);
-               if(r->p == NULL)
-                       error("regio: vmap failed");
-               rp = (uintptr_t)r->p + off;
-               rio = memio;
-               break;
-       case Rsysio:
-               rp = r->base + off;
-               rio = ioio;
-               break;
-       case Rpcicfg:
-               rp = r->base + off;
-               rio = cfgio;
-               rio.arg = r;
-               break;
-       case Rpcibar:
-       case Rembed:
-       case Rsmbus:
-       case Rcmos:
-       case Ripmi:
-       case Rfixedhw:
-               printd("regio: reg %s not supported\n", acpiregstr(r->spc));
-               error("region not supported");
+       switch (r->spc) {
+               case Rsysmem:
+                       // XXX should map only what we are going to use
+                       // A region might be too large.
+                       // we don't have this nonsense in akaros, right? 
+                       if (r->p == NULL)
+                               r->p = vmap(r->base, len);
+                       if (r->p == NULL)
+                               error("regio: vmap failed");
+                       rp = (uintptr_t) r->p + off;
+                       rio = memio;
+                       break;
+               case Rsysio:
+                       rp = r->base + off;
+                       rio = ioio;
+                       break;
+               case Rpcicfg:
+                       rp = r->base + off;
+                       rio = cfgio;
+                       rio.arg = r;
+                       break;
+               case Rpcibar:
+               case Rembed:
+               case Rsmbus:
+               case Rcmos:
+               case Ripmi:
+               case Rfixedhw:
+                       printd("regio: reg %s not supported\n", acpiregstr(r->spc));
+                       error("region not supported");
        }
        }
-       if(iswr)
-               regcpy(&rio, rp, &memio, (uintptr_t)p, len, r->accsz);
+       if (iswr)
+               regcpy(&rio, rp, &memio, (uintptr_t) p, len, r->accsz);
        else
        else
-               regcpy(&memio, (uintptr_t)p, &rio, rp, len, r->accsz);
+               regcpy(&memio, (uintptr_t) p, &rio, rp, len, r->accsz);
        return len;
 }
 
        return len;
 }
 
-static struct Atable*
-newtable(uint8_t *p)
+static struct Atable *newtable(uint8_t * p)
 {
        struct Atable *t;
        struct Sdthdr *h;
 
        t = kzmalloc(sizeof(struct Atable), 0);
 {
        struct Atable *t;
        struct Sdthdr *h;
 
        t = kzmalloc(sizeof(struct Atable), 0);
-       if(t == NULL)
+       if (t == NULL)
                panic("no memory for more aml tables");
        t->tbl = p;
                panic("no memory for more aml tables");
        t->tbl = p;
-       h = (struct Sdthdr*)t->tbl;
+       h = (struct Sdthdr *)t->tbl;
        t->is64 = h->rev >= 2;
        t->dlen = l32get(h->length) - Sdthdrsz;
        memmove(t->sig, h->sig, sizeof(h->sig));
        t->is64 = h->rev >= 2;
        t->dlen = l32get(h->length) - Sdthdrsz;
        memmove(t->sig, h->sig, sizeof(h->sig));
-       t->sig[sizeof(t->sig)-1] = 0;
+       t->sig[sizeof(t->sig) - 1] = 0;
        memmove(t->oemid, h->oemid, sizeof(h->oemid));
        memmove(t->oemid, h->oemid, sizeof(h->oemid));
-       t->oemtblid[sizeof(t->oemtblid)-1] = 0;
+       t->oemtblid[sizeof(t->oemtblid) - 1] = 0;
        memmove(t->oemtblid, h->oemtblid, sizeof(h->oemtblid));
        memmove(t->oemtblid, h->oemtblid, sizeof(h->oemtblid));
-       t->oemtblid[sizeof(t->oemtblid)-1] = 0;
+       t->oemtblid[sizeof(t->oemtblid) - 1] = 0;
        t->next = NULL;
        t->next = NULL;
-       if(tfirst == NULL)
+       if (tfirst == NULL)
                tfirst = tlast = t;
                tfirst = tlast = t;
-       else{
+       else {
                tlast->next = t;
                tlast = t;
        }
        return t;
 }
 
                tlast->next = t;
                tlast = t;
        }
        return t;
 }
 
-static void*
-sdtchecksum(void* addr, int len)
+static void *sdtchecksum(void *addr, int len)
 {
        uint8_t *p, sum;
 
        sum = 0;
 {
        uint8_t *p, sum;
 
        sum = 0;
-       for(p = addr; len-- > 0; p++)
+       for (p = addr; len-- > 0; p++)
                sum += *p;
                sum += *p;
-       if(sum == 0) {
+       if (sum == 0) {
                return addr;
        }
 
        return NULL;
 }
 
                return addr;
        }
 
        return NULL;
 }
 
-static void *
-sdtmap(uintptr_t pa, int *n, int cksum)
+static void *sdtmap(uintptr_t pa, int *n, int cksum)
 {
 {
-       struct Sdthdrsdt;
+       struct Sdthdr *sdt;
 
 
-       if (! pa){
+       if (!pa) {
                printk("sdtmap: NULL pa\n");
                return NULL;
        }
        sdt = vmap(pa, sizeof(*sdt));
                printk("sdtmap: NULL pa\n");
                return NULL;
        }
        sdt = vmap(pa, sizeof(*sdt));
-       if(sdt == NULL){
+       if (sdt == NULL) {
                printk("acpi: vmap1: NULL\n");
                return NULL;
        }
        *n = l32get(sdt->length);
        vunmap(sdt, sizeof(*sdt));
                printk("acpi: vmap1: NULL\n");
                return NULL;
        }
        *n = l32get(sdt->length);
        vunmap(sdt, sizeof(*sdt));
-       if (! *n) {
+       if (!*n) {
                printk("sdt has zero length!\n");
                return NULL;
        }
                printk("sdt has zero length!\n");
                return NULL;
        }
-       if((sdt = vmap(pa, *n)) == NULL){
+       if ((sdt = vmap(pa, *n)) == NULL) {
                printk("acpi: NULL vmap\n");
                return NULL;
        }
                printk("acpi: NULL vmap\n");
                return NULL;
        }
-       if(cksum != 0 && sdtchecksum(sdt, *n) == NULL){
+       if (cksum != 0 && sdtchecksum(sdt, *n) == NULL) {
                printk("acpi: SDT: bad checksum\n");
                vunmap(sdt, sizeof(*sdt));
                return NULL;
                printk("acpi: SDT: bad checksum\n");
                vunmap(sdt, sizeof(*sdt));
                return NULL;
@@ -474,16 +440,15 @@ sdtmap(uintptr_t pa, int *n, int cksum)
        return sdt;
 }
 
        return sdt;
 }
 
-static int
-loadfacs(uintptr_t pa)
+static int loadfacs(uintptr_t pa)
 {
        int n;
 
        facs = sdtmap(pa, &n, 0);
 {
        int n;
 
        facs = sdtmap(pa, &n, 0);
-       if(facs == NULL) {
+       if (facs == NULL) {
                return -1;
        }
                return -1;
        }
-       if(memcmp(facs, "FACS", 4) != 0){
+       if (memcmp(facs, "FACS", 4) != 0) {
                //vunmap(facs, n);
                facs = NULL;
                return -1;
                //vunmap(facs, n);
                facs = NULL;
                return -1;
@@ -500,34 +465,30 @@ loadfacs(uintptr_t pa)
        return 0;
 }
 
        return 0;
 }
 
-static void
-loaddsdt(uintptr_t pa)
+static void loaddsdt(uintptr_t pa)
 {
        int n;
        uint8_t *dsdtp;
 
        dsdtp = sdtmap(pa, &n, 1);
 {
        int n;
        uint8_t *dsdtp;
 
        dsdtp = sdtmap(pa, &n, 1);
-       if(dsdtp == NULL) {
+       if (dsdtp == NULL) {
                return;
        }
                return;
        }
-       if(acpitable(dsdtp, n) == NULL)
-               ;//vunmap(dsdtp, n);
+       if (acpitable(dsdtp, n) == NULL) ;      //vunmap(dsdtp, n);
 }
 
 }
 
-static void
-gasget(struct Gas *gas, uint8_t *p)
+static void gasget(struct Gas *gas, uint8_t * p)
 {
        gas->spc = p[0];
        gas->len = p[1];
        gas->off = p[2];
        gas->accsz = p[3];
 {
        gas->spc = p[0];
        gas->len = p[1];
        gas->off = p[2];
        gas->accsz = p[3];
-       gas->addr = l64get(p+4);
+       gas->addr = l64get(p + 4);
 }
 
 }
 
-static char *
-dumpfadt(char *start, char *end, struct Fadt *fp)
+static char *dumpfadt(char *start, char *end, struct Fadt *fp)
 {
 {
-       if(2 == 0) {
+       if (2 == 0) {
                return NULL;
        }
 
                return NULL;
        }
 
@@ -536,14 +497,20 @@ dumpfadt(char *start, char *end, struct Fadt *fp)
        start = seprintf(start, end, "acpi: fadt: pmprofile: $%p\n", fp->pmprofile);
        start = seprintf(start, end, "acpi: fadt: sciint: $%p\n", fp->sciint);
        start = seprintf(start, end, "acpi: fadt: smicmd: $%p\n", fp->smicmd);
        start = seprintf(start, end, "acpi: fadt: pmprofile: $%p\n", fp->pmprofile);
        start = seprintf(start, end, "acpi: fadt: sciint: $%p\n", fp->sciint);
        start = seprintf(start, end, "acpi: fadt: smicmd: $%p\n", fp->smicmd);
-       start = seprintf(start, end, "acpi: fadt: acpienable: $%p\n", fp->acpienable);
-       start = seprintf(start, end, "acpi: fadt: acpidisable: $%p\n", fp->acpidisable);
+       start =
+               seprintf(start, end, "acpi: fadt: acpienable: $%p\n", fp->acpienable);
+       start =
+               seprintf(start, end, "acpi: fadt: acpidisable: $%p\n", fp->acpidisable);
        start = seprintf(start, end, "acpi: fadt: s4biosreq: $%p\n", fp->s4biosreq);
        start = seprintf(start, end, "acpi: fadt: pstatecnt: $%p\n", fp->pstatecnt);
        start = seprintf(start, end, "acpi: fadt: s4biosreq: $%p\n", fp->s4biosreq);
        start = seprintf(start, end, "acpi: fadt: pstatecnt: $%p\n", fp->pstatecnt);
-       start = seprintf(start, end, "acpi: fadt: pm1aevtblk: $%p\n", fp->pm1aevtblk);
-       start = seprintf(start, end, "acpi: fadt: pm1bevtblk: $%p\n", fp->pm1bevtblk);
-       start = seprintf(start, end, "acpi: fadt: pm1acntblk: $%p\n", fp->pm1acntblk);
-       start = seprintf(start, end, "acpi: fadt: pm1bcntblk: $%p\n", fp->pm1bcntblk);
+       start =
+               seprintf(start, end, "acpi: fadt: pm1aevtblk: $%p\n", fp->pm1aevtblk);
+       start =
+               seprintf(start, end, "acpi: fadt: pm1bevtblk: $%p\n", fp->pm1bevtblk);
+       start =
+               seprintf(start, end, "acpi: fadt: pm1acntblk: $%p\n", fp->pm1acntblk);
+       start =
+               seprintf(start, end, "acpi: fadt: pm1bcntblk: $%p\n", fp->pm1bcntblk);
        start = seprintf(start, end, "acpi: fadt: pm2cntblk: $%p\n", fp->pm2cntblk);
        start = seprintf(start, end, "acpi: fadt: pmtmrblk: $%p\n", fp->pmtmrblk);
        start = seprintf(start, end, "acpi: fadt: gpe0blk: $%p\n", fp->gpe0blk);
        start = seprintf(start, end, "acpi: fadt: pm2cntblk: $%p\n", fp->pm2cntblk);
        start = seprintf(start, end, "acpi: fadt: pmtmrblk: $%p\n", fp->pmtmrblk);
        start = seprintf(start, end, "acpi: fadt: gpe0blk: $%p\n", fp->gpe0blk);
@@ -552,20 +519,25 @@ dumpfadt(char *start, char *end, struct Fadt *fp)
        start = seprintf(start, end, "acpi: fadt: pm1cntlen: $%p\n", fp->pm1cntlen);
        start = seprintf(start, end, "acpi: fadt: pm2cntlen: $%p\n", fp->pm2cntlen);
        start = seprintf(start, end, "acpi: fadt: pmtmrlen: $%p\n", fp->pmtmrlen);
        start = seprintf(start, end, "acpi: fadt: pm1cntlen: $%p\n", fp->pm1cntlen);
        start = seprintf(start, end, "acpi: fadt: pm2cntlen: $%p\n", fp->pm2cntlen);
        start = seprintf(start, end, "acpi: fadt: pmtmrlen: $%p\n", fp->pmtmrlen);
-       start = seprintf(start, end, "acpi: fadt: gpe0blklen: $%p\n", fp->gpe0blklen);
-       start = seprintf(start, end, "acpi: fadt: gpe1blklen: $%p\n", fp->gpe1blklen);
+       start =
+               seprintf(start, end, "acpi: fadt: gpe0blklen: $%p\n", fp->gpe0blklen);
+       start =
+               seprintf(start, end, "acpi: fadt: gpe1blklen: $%p\n", fp->gpe1blklen);
        start = seprintf(start, end, "acpi: fadt: gp1base: $%p\n", fp->gp1base);
        start = seprintf(start, end, "acpi: fadt: cstcnt: $%p\n", fp->cstcnt);
        start = seprintf(start, end, "acpi: fadt: plvl2lat: $%p\n", fp->plvl2lat);
        start = seprintf(start, end, "acpi: fadt: plvl3lat: $%p\n", fp->plvl3lat);
        start = seprintf(start, end, "acpi: fadt: flushsz: $%p\n", fp->flushsz);
        start = seprintf(start, end, "acpi: fadt: gp1base: $%p\n", fp->gp1base);
        start = seprintf(start, end, "acpi: fadt: cstcnt: $%p\n", fp->cstcnt);
        start = seprintf(start, end, "acpi: fadt: plvl2lat: $%p\n", fp->plvl2lat);
        start = seprintf(start, end, "acpi: fadt: plvl3lat: $%p\n", fp->plvl3lat);
        start = seprintf(start, end, "acpi: fadt: flushsz: $%p\n", fp->flushsz);
-       start = seprintf(start, end, "acpi: fadt: flushstride: $%p\n", fp->flushstride);
+       start =
+               seprintf(start, end, "acpi: fadt: flushstride: $%p\n", fp->flushstride);
        start = seprintf(start, end, "acpi: fadt: dutyoff: $%p\n", fp->dutyoff);
        start = seprintf(start, end, "acpi: fadt: dutywidth: $%p\n", fp->dutywidth);
        start = seprintf(start, end, "acpi: fadt: dayalrm: $%p\n", fp->dayalrm);
        start = seprintf(start, end, "acpi: fadt: monalrm: $%p\n", fp->monalrm);
        start = seprintf(start, end, "acpi: fadt: century: $%p\n", fp->century);
        start = seprintf(start, end, "acpi: fadt: dutyoff: $%p\n", fp->dutyoff);
        start = seprintf(start, end, "acpi: fadt: dutywidth: $%p\n", fp->dutywidth);
        start = seprintf(start, end, "acpi: fadt: dayalrm: $%p\n", fp->dayalrm);
        start = seprintf(start, end, "acpi: fadt: monalrm: $%p\n", fp->monalrm);
        start = seprintf(start, end, "acpi: fadt: century: $%p\n", fp->century);
-       start = seprintf(start, end, "acpi: fadt: iapcbootarch: $%p\n", fp->iapcbootarch);
+       start =
+               seprintf(start, end, "acpi: fadt: iapcbootarch: $%p\n",
+                                fp->iapcbootarch);
        start = seprintf(start, end, "acpi: fadt: flags: $%p\n", fp->flags);
        start = dumpGas(start, end, "acpi: fadt: resetreg: ", &fp->resetreg);
        start = seprintf(start, end, "acpi: fadt: resetval: $%p\n", fp->resetval);
        start = seprintf(start, end, "acpi: fadt: flags: $%p\n", fp->flags);
        start = dumpGas(start, end, "acpi: fadt: resetreg: ", &fp->resetreg);
        start = seprintf(start, end, "acpi: fadt: resetval: $%p\n", fp->resetval);
@@ -582,8 +554,7 @@ dumpfadt(char *start, char *end, struct Fadt *fp)
        return start;
 }
 
        return start;
 }
 
-static struct Atable*
-acpifadt(uint8_t *p, int unused)
+static struct Atable *acpifadt(uint8_t * p, int unused)
 {
        struct Fadt *fp;
 
 {
        struct Fadt *fp;
 
@@ -591,20 +562,20 @@ acpifadt(uint8_t *p, int unused)
        fp->facs = l32get(p + 36);
        fp->dsdt = l32get(p + 40);
        fp->pmprofile = p[45];
        fp->facs = l32get(p + 36);
        fp->dsdt = l32get(p + 40);
        fp->pmprofile = p[45];
-       fp->sciint = l16get(p+46);
-       fp->smicmd = l32get(p+48);
+       fp->sciint = l16get(p + 46);
+       fp->smicmd = l32get(p + 48);
        fp->acpienable = p[52];
        fp->acpidisable = p[53];
        fp->s4biosreq = p[54];
        fp->pstatecnt = p[55];
        fp->acpienable = p[52];
        fp->acpidisable = p[53];
        fp->s4biosreq = p[54];
        fp->pstatecnt = p[55];
-       fp->pm1aevtblk = l32get(p+56);
-       fp->pm1bevtblk = l32get(p+60);
-       fp->pm1acntblk = l32get(p+64);
-       fp->pm1bcntblk = l32get(p+68);
-       fp->pm2cntblk = l32get(p+72);
-       fp->pmtmrblk = l32get(p+76);
-       fp->gpe0blk = l32get(p+80);
-       fp->gpe1blk = l32get(p+84);
+       fp->pm1aevtblk = l32get(p + 56);
+       fp->pm1bevtblk = l32get(p + 60);
+       fp->pm1acntblk = l32get(p + 64);
+       fp->pm1bcntblk = l32get(p + 68);
+       fp->pm2cntblk = l32get(p + 72);
+       fp->pmtmrblk = l32get(p + 76);
+       fp->gpe0blk = l32get(p + 80);
+       fp->gpe1blk = l32get(p + 84);
        fp->pm1evtlen = p[88];
        fp->pm1cntlen = p[89];
        fp->pm2cntlen = p[90];
        fp->pm1evtlen = p[88];
        fp->pm1cntlen = p[89];
        fp->pm2cntlen = p[90];
@@ -613,42 +584,42 @@ acpifadt(uint8_t *p, int unused)
        fp->gpe1blklen = p[93];
        fp->gp1base = p[94];
        fp->cstcnt = p[95];
        fp->gpe1blklen = p[93];
        fp->gp1base = p[94];
        fp->cstcnt = p[95];
-       fp->plvl2lat = l16get(p+96);
-       fp->plvl3lat = l16get(p+98);
-       fp->flushsz = l16get(p+100);
-       fp->flushstride = l16get(p+102);
+       fp->plvl2lat = l16get(p + 96);
+       fp->plvl3lat = l16get(p + 98);
+       fp->flushsz = l16get(p + 100);
+       fp->flushstride = l16get(p + 102);
        fp->dutyoff = p[104];
        fp->dutywidth = p[105];
        fp->dayalrm = p[106];
        fp->monalrm = p[107];
        fp->century = p[108];
        fp->dutyoff = p[104];
        fp->dutywidth = p[105];
        fp->dayalrm = p[106];
        fp->monalrm = p[107];
        fp->century = p[108];
-       fp->iapcbootarch = l16get(p+109);
-       fp->flags = l32get(p+112);
-       gasget(&fp->resetreg, p+116);
+       fp->iapcbootarch = l16get(p + 109);
+       fp->flags = l32get(p + 112);
+       gasget(&fp->resetreg, p + 116);
        fp->resetval = p[128];
        fp->resetval = p[128];
-       fp->xfacs = l64get(p+132);
-       fp->xdsdt = l64get(p+140);
-       gasget(&fp->xpm1aevtblk, p+148);
-       gasget(&fp->xpm1bevtblk, p+160);
-       gasget(&fp->xpm1acntblk, p+172);
-       gasget(&fp->xpm1bcntblk, p+184);
-       gasget(&fp->xpm2cntblk, p+196);
-       gasget(&fp->xpmtmrblk, p+208);
-       gasget(&fp->xgpe0blk, p+220);
-       gasget(&fp->xgpe1blk, p+232);
+       fp->xfacs = l64get(p + 132);
+       fp->xdsdt = l64get(p + 140);
+       gasget(&fp->xpm1aevtblk, p + 148);
+       gasget(&fp->xpm1bevtblk, p + 160);
+       gasget(&fp->xpm1acntblk, p + 172);
+       gasget(&fp->xpm1bcntblk, p + 184);
+       gasget(&fp->xpm2cntblk, p + 196);
+       gasget(&fp->xpmtmrblk, p + 208);
+       gasget(&fp->xgpe0blk, p + 220);
+       gasget(&fp->xgpe1blk, p + 232);
 
 #if 0
 
 #if 0
-       static char buf[8192]; // XXX
+       static char buf[8192];          // XXX
        char *out;
        out = dumpfadt(buf, &buf[8191], fp);
        printk("%s\n", out);
 #endif
        char *out;
        out = dumpfadt(buf, &buf[8191], fp);
        printk("%s\n", out);
 #endif
-       if(fp->xfacs != 0)
+       if (fp->xfacs != 0)
                loadfacs(fp->xfacs);
        else
                loadfacs(fp->facs);
 
                loadfacs(fp->xfacs);
        else
                loadfacs(fp->facs);
 
-       if(fp->xdsdt == ((uint64_t)fp->dsdt)) /* acpica */
+       if (fp->xdsdt == ((uint64_t) fp->dsdt)) /* acpica */
                loaddsdt(fp->xdsdt);
        else
                loaddsdt(fp->dsdt);
                loaddsdt(fp->xdsdt);
        else
                loaddsdt(fp->dsdt);
@@ -656,18 +627,17 @@ acpifadt(uint8_t *p, int unused)
        return NULL;    /* can be unmapped once parsed */
 }
 
        return NULL;    /* can be unmapped once parsed */
 }
 
-static char *
-dumpmsct(char *start, char *end, struct Msct *msct)
+static char *dumpmsct(char *start, char *end, struct Msct *msct)
 {
        struct Mdom *st;
 
 {
        struct Mdom *st;
 
-       if (! msct)
+       if (!msct)
                return start;
        start = seprintf(start, end, "acpi: msct: %d doms %d clkdoms %#p maxpa\n",
                return start;
        start = seprintf(start, end, "acpi: msct: %d doms %d clkdoms %#p maxpa\n",
-               msct->ndoms, msct->nclkdoms, msct->maxpa);
-       for(st = msct->dom; st != NULL; st = st->next)
+                                        msct->ndoms, msct->nclkdoms, msct->maxpa);
+       for (st = msct->dom; st != NULL; st = st->next)
                start = seprintf(start, end, "\t[%d:%d] %d maxproc %#p maxmmem\n",
                start = seprintf(start, end, "\t[%d:%d] %d maxproc %#p maxmmem\n",
-                       st->start, st->end, st->maxproc, st->maxmem);
+                                                st->start, st->end, st->maxproc, st->maxmem);
        start = seprintf(start, end, "\n");
        return start;
 }
        start = seprintf(start, end, "\n");
        return start;
 }
@@ -676,29 +646,27 @@ dumpmsct(char *start, char *end, struct Msct *msct)
  * XXX: should perhaps update our idea of available memory.
  * Else we should remove this code.
  */
  * XXX: should perhaps update our idea of available memory.
  * Else we should remove this code.
  */
-static struct Atable*
-acpimsct(uint8_t *p, int len)
+static struct Atable *acpimsct(uint8_t * p, int len)
 {
        uint8_t *pe;
        struct Mdom **stl, *st;
        int off;
 
 {
        uint8_t *pe;
        struct Mdom **stl, *st;
        int off;
 
-
        msct = kzmalloc(sizeof(struct Msct), KMALLOC_WAIT);
        msct = kzmalloc(sizeof(struct Msct), KMALLOC_WAIT);
-       msct->ndoms = l32get(p+40) + 1;
-       msct->nclkdoms = l32get(p+44) + 1;
-       msct->maxpa = l64get(p+48);
+       msct->ndoms = l32get(p + 40) + 1;
+       msct->nclkdoms = l32get(p + 44) + 1;
+       msct->maxpa = l64get(p + 48);
        msct->dom = NULL;
        stl = &msct->dom;
        pe = p + len;
        msct->dom = NULL;
        stl = &msct->dom;
        pe = p + len;
-       off = l32get(p+36);
-       for(p += off; p < pe; p += 22){
+       off = l32get(p + 36);
+       for (p += off; p < pe; p += 22) {
                st = kzmalloc(sizeof(struct Mdom), KMALLOC_WAIT);
                st->next = NULL;
                st = kzmalloc(sizeof(struct Mdom), KMALLOC_WAIT);
                st->next = NULL;
-               st->start = l32get(p+2);
-               st->end = l32get(p+6);
-               st->maxproc = l32get(p+10);
-               st->maxmem = l64get(p+14);
+               st->start = l32get(p + 2);
+               st->end = l32get(p + 6);
+               st->maxproc = l32get(p + 10);
+               st->maxmem = l64get(p + 14);
                *stl = st;
                stl = &st->next;
        }
                *stl = st;
                stl = &st->next;
        }
@@ -713,94 +681,95 @@ acpimsct(uint8_t *p, int len)
        return NULL;    /* can be unmapped once parsed */
 }
 
        return NULL;    /* can be unmapped once parsed */
 }
 
-static char *
-dumpsrat(char *start, char *end, struct Srat *st)
+static char *dumpsrat(char *start, char *end, struct Srat *st)
 {
        start = seprintf(start, end, "acpi: srat:\n");
 {
        start = seprintf(start, end, "acpi: srat:\n");
-       for(; st != NULL; st = st->next)
-               switch(st->type){
-               case SRlapic:
-                       start = seprintf(start, end, "\tlapic: dom %d apic %d sapic %d clk %d\n",
-                               st->lapic.dom, st->lapic.apic,
-                               st->lapic.sapic, st->lapic.clkdom);
-                       break;
-               case SRmem:
-                       start = seprintf(start, end, "\tmem: dom %d %#p %#p %c%c\n",
-                               st->mem.dom, st->mem.addr, st->mem.len,
-                               st->mem.hplug?'h':'-',
-                               st->mem.nvram?'n':'-');
-                       break;
-               case SRlx2apic:
-                       start = seprintf(start, end, "\tlx2apic: dom %d apic %d clk %d\n",
-                               st->lx2apic.dom, st->lx2apic.apic,
-                               st->lx2apic.clkdom);
-                       break;
-               default:
-                       start = seprintf(start, end, "\t<unknown srat entry>\n");
+       for (; st != NULL; st = st->next)
+               switch (st->type) {
+                       case SRlapic:
+                               start =
+                                       seprintf(start, end,
+                                                        "\tlapic: dom %d apic %d sapic %d clk %d\n",
+                                                        st->lapic.dom, st->lapic.apic, st->lapic.sapic,
+                                                        st->lapic.clkdom);
+                               break;
+                       case SRmem:
+                               start = seprintf(start, end, "\tmem: dom %d %#p %#p %c%c\n",
+                                                                st->mem.dom, st->mem.addr, st->mem.len,
+                                                                st->mem.hplug ? 'h' : '-',
+                                                                st->mem.nvram ? 'n' : '-');
+                               break;
+                       case SRlx2apic:
+                               start =
+                                       seprintf(start, end, "\tlx2apic: dom %d apic %d clk %d\n",
+                                                        st->lx2apic.dom, st->lx2apic.apic,
+                                                        st->lx2apic.clkdom);
+                               break;
+                       default:
+                               start = seprintf(start, end, "\t<unknown srat entry>\n");
                }
        start = seprintf(start, end, "\n");
        return start;
 }
 
                }
        start = seprintf(start, end, "\n");
        return start;
 }
 
-static struct Atable*
-acpisrat(uint8_t *p, int len)
+static struct Atable *acpisrat(uint8_t * p, int len)
 {
 
        struct Srat **stl, *st;
        uint8_t *pe;
        int stlen, flags;
 
 {
 
        struct Srat **stl, *st;
        uint8_t *pe;
        int stlen, flags;
 
-       if(srat != NULL){
+       if (srat != NULL) {
                printd("acpi: two SRATs?\n");
                return NULL;
        }
 
        stl = &srat;
        pe = p + len;
                printd("acpi: two SRATs?\n");
                return NULL;
        }
 
        stl = &srat;
        pe = p + len;
-       for(p += 48; p < pe; p += stlen){
+       for (p += 48; p < pe; p += stlen) {
                st = kzmalloc(sizeof(struct Srat), 1);
                st->type = p[0];
                st->next = NULL;
                stlen = p[1];
                st = kzmalloc(sizeof(struct Srat), 1);
                st->type = p[0];
                st->next = NULL;
                stlen = p[1];
-               switch(st->type){
-               case SRlapic:
-                       st->lapic.dom = p[2] | p[9]<<24| p[10]<<16 | p[11]<<8;
-                       st->lapic.apic = p[3];
-                       st->lapic.sapic = p[8];
-                       st->lapic.clkdom = l32get(p+12);
-                       if(l32get(p+4) == 0){
-                               kfree(st);
-                               st = NULL;
-                       }
-                       break;
-               case SRmem:
-                       st->mem.dom = l32get(p+2);
-                       st->mem.addr = l64get(p+8);
-                       st->mem.len = l64get(p+16);
-                       flags = l32get(p+28);
-                       if((flags&1) == 0){     /* not enabled */
-                               kfree(st);
-                               st = NULL;
-                       }else{
-                               st->mem.hplug = flags & 2;
-                               st->mem.nvram = flags & 4;
-                       }
-                       break;
-               case SRlx2apic:
-                       st->lx2apic.dom = l32get(p+4);
-                       st->lx2apic.apic = l32get(p+8);
-                       st->lx2apic.clkdom = l32get(p+16);
-                       if(l32get(p+12) == 0){
+               switch (st->type) {
+                       case SRlapic:
+                               st->lapic.dom = p[2] | p[9] << 24 | p[10] << 16 | p[11] << 8;
+                               st->lapic.apic = p[3];
+                               st->lapic.sapic = p[8];
+                               st->lapic.clkdom = l32get(p + 12);
+                               if (l32get(p + 4) == 0) {
+                                       kfree(st);
+                                       st = NULL;
+                               }
+                               break;
+                       case SRmem:
+                               st->mem.dom = l32get(p + 2);
+                               st->mem.addr = l64get(p + 8);
+                               st->mem.len = l64get(p + 16);
+                               flags = l32get(p + 28);
+                               if ((flags & 1) == 0) { /* not enabled */
+                                       kfree(st);
+                                       st = NULL;
+                               } else {
+                                       st->mem.hplug = flags & 2;
+                                       st->mem.nvram = flags & 4;
+                               }
+                               break;
+                       case SRlx2apic:
+                               st->lx2apic.dom = l32get(p + 4);
+                               st->lx2apic.apic = l32get(p + 8);
+                               st->lx2apic.clkdom = l32get(p + 16);
+                               if (l32get(p + 12) == 0) {
+                                       kfree(st);
+                                       st = NULL;
+                               }
+                               break;
+                       default:
+                               printd("unknown SRAT structure\n");
                                kfree(st);
                                st = NULL;
                                kfree(st);
                                st = NULL;
-                       }
-                       break;
-               default:
-                       printd("unknown SRAT structure\n");
-                       kfree(st);
-                       st = NULL;
                }
                }
-               if(st != NULL){
+               if (st != NULL) {
                        *stl = st;
                        stl = &st->next;
                }
                        *stl = st;
                        stl = &st->next;
                }
@@ -816,24 +785,23 @@ acpisrat(uint8_t *p, int len)
        return NULL;    /* can be unmapped once parsed */
 }
 
        return NULL;    /* can be unmapped once parsed */
 }
 
-static char *
-dumpslit(char *start, char *end, struct Slit *sl)
+static char *dumpslit(char *start, char *end, struct Slit *sl)
 {
        int i;
 {
        int i;
-       
-       if (! sl)
+
+       if (!sl)
                return start;
        start = seprintf(start, end, "acpi slit:\n");
                return start;
        start = seprintf(start, end, "acpi slit:\n");
-       for(i = 0; i < sl->rowlen*sl->rowlen; i++){
+       for (i = 0; i < sl->rowlen * sl->rowlen; i++) {
                start = seprintf(start, end,
                start = seprintf(start, end,
-                               "slit: %ux\n", sl->e[i/sl->rowlen][i%sl->rowlen].dist);
+                                                "slit: %ux\n",
+                                                sl->e[i / sl->rowlen][i % sl->rowlen].dist);
        }
        start = seprintf(start, end, "\n");
        return start;
 }
 
        }
        start = seprintf(start, end, "\n");
        return start;
 }
 
-static int
-cmpslitent(void* v1, void* v2)
+static int cmpslitent(void *v1, void *v2)
 {
        struct SlEntry *se1, *se2;
 
 {
        struct SlEntry *se1, *se2;
 
@@ -842,8 +810,7 @@ cmpslitent(void* v1, void* v2)
        return se1->dist - se2->dist;
 }
 
        return se1->dist - se2->dist;
 }
 
-static struct Atable*
-acpislit(uint8_t *p, int len)
+static struct Atable *acpislit(uint8_t * p, int len)
 {
 
        uint8_t *pe;
 {
 
        uint8_t *pe;
@@ -852,15 +819,15 @@ acpislit(uint8_t *p, int len)
 
        pe = p + len;
        slit = kzmalloc(sizeof(*slit), 0);
 
        pe = p + len;
        slit = kzmalloc(sizeof(*slit), 0);
-       slit->rowlen = l64get(p+36);
+       slit->rowlen = l64get(p + 36);
        slit->e = kzmalloc(slit->rowlen * sizeof(struct SlEntry *), 0);
        slit->e = kzmalloc(slit->rowlen * sizeof(struct SlEntry *), 0);
-       for(i = 0; i < slit->rowlen; i++)
+       for (i = 0; i < slit->rowlen; i++)
                slit->e[i] = kzmalloc(sizeof(struct SlEntry) * slit->rowlen, 0);
 
        i = 0;
                slit->e[i] = kzmalloc(sizeof(struct SlEntry) * slit->rowlen, 0);
 
        i = 0;
-       for(p += 44; p < pe; p++, i++){
-               j = i/slit->rowlen;
-               k = i%slit->rowlen;
+       for (p += 44; p < pe; p++, i++) {
+               j = i / slit->rowlen;
+               k = i % slit->rowlen;
                se = &slit->e[j][k];
                se->dom = k;
                se->dist = *p;
                se = &slit->e[j][k];
                se->dom = k;
                se->dist = *p;
@@ -873,54 +840,51 @@ acpislit(uint8_t *p, int len)
        dumpslit(dump, &dump[8191], slit);
        printk("%s", dump);
        kfree(dump);
        dumpslit(dump, &dump[8191], slit);
        printk("%s", dump);
        kfree(dump);
-       for(i = 0; i < slit->rowlen; i++)
+       for (i = 0; i < slit->rowlen; i++)
                qsort(slit->e[i], slit->rowlen, sizeof(slit->e[0][0]), cmpslitent);
                qsort(slit->e[i], slit->rowlen, sizeof(slit->e[0][0]), cmpslitent);
-       
+
        dumpslit(slit);
 #endif
        return NULL;    /* can be unmapped once parsed */
 }
 
        dumpslit(slit);
 #endif
        return NULL;    /* can be unmapped once parsed */
 }
 
-uintptr_t
-acpimblocksize(uintptr_t addr, int *dom)
+uintptr_t acpimblocksize(uintptr_t addr, int *dom)
 {
        struct Srat *sl;
 
 {
        struct Srat *sl;
 
-       for(sl = srat; sl != NULL; sl = sl->next)
-               if(sl->type == SRmem)
-               if(sl->mem.addr <= addr && sl->mem.addr + sl->mem.len > addr){
-                       *dom = sl->mem.dom;
-                       return sl->mem.len - (addr - sl->mem.addr);
-               }
+       for (sl = srat; sl != NULL; sl = sl->next)
+               if (sl->type == SRmem)
+                       if (sl->mem.addr <= addr && sl->mem.addr + sl->mem.len > addr) {
+                               *dom = sl->mem.dom;
+                               return sl->mem.len - (addr - sl->mem.addr);
+                       }
        return 0;
 }
 
        return 0;
 }
 
-
 /*
  * we use mp->machno (or index in Mach array) as the identifier,
  * but ACPI relies on the apic identifier.
  */
 /*
  * we use mp->machno (or index in Mach array) as the identifier,
  * but ACPI relies on the apic identifier.
  */
-int
-corecolor(int core)
+int corecolor(int core)
 {
 #warning "can't do core colors yet"
 {
 #warning "can't do core colors yet"
-return -1;
+       return -1;
 #if 0
        struct Srat *sl;
        static int colors[32];
 
 #if 0
        struct Srat *sl;
        static int colors[32];
 
-       if(core < 0 || core >= num_cpus)
+       if (core < 0 || core >= num_cpus)
                return -1;
        m = sys->machptr[core];
                return -1;
        m = sys->machptr[core];
-       if(m == NULL)
+       if (m == NULL)
                return -1;
 
                return -1;
 
-       if(core >= 0 && core < ARRAY_SIZE(colors) && colors[core] != 0)
+       if (core >= 0 && core < ARRAY_SIZE(colors) && colors[core] != 0)
                return colors[core] - 1;
 
                return colors[core] - 1;
 
-       for(sl = srat; sl != NULL; sl = sl->next)
-               if(sl->type == SRlapic && sl->lapic.apic == m->apicno){
-                       if(core >= 0 && core < ARRAY_SIZE(colors))
+       for (sl = srat; sl != NULL; sl = sl->next)
+               if (sl->type == SRlapic && sl->lapic.apic == m->apicno) {
+                       if (core >= 0 && core < ARRAY_SIZE(colors))
                                colors[core] = 1 + sl->lapic.dom;
                        return sl->lapic.dom;
                }
                                colors[core] = 1 + sl->lapic.dom;
                        return sl->lapic.dom;
                }