BNX2X: uint*_t spatch
authorBarret Rhoden <brho@cs.berkeley.edu>
Tue, 3 Feb 2015 23:06:44 +0000 (18:06 -0500)
committerBarret Rhoden <brho@cs.berkeley.edu>
Mon, 2 Mar 2015 16:59:07 +0000 (11:59 -0500)
24 files changed:
kern/drivers/net/bnx2x/bnx2x.h
kern/drivers/net/bnx2x/bnx2x_cmn.c
kern/drivers/net/bnx2x/bnx2x_cmn.h
kern/drivers/net/bnx2x/bnx2x_dcb.c
kern/drivers/net/bnx2x/bnx2x_dcb.h
kern/drivers/net/bnx2x/bnx2x_dump.h
kern/drivers/net/bnx2x/bnx2x_ethtool.c
kern/drivers/net/bnx2x/bnx2x_hsi.h
kern/drivers/net/bnx2x/bnx2x_init.h
kern/drivers/net/bnx2x/bnx2x_init_ops.h
kern/drivers/net/bnx2x/bnx2x_link.c
kern/drivers/net/bnx2x/bnx2x_link.h
kern/drivers/net/bnx2x/bnx2x_main.c
kern/drivers/net/bnx2x/bnx2x_mfw_req.h
kern/drivers/net/bnx2x/bnx2x_reg.h
kern/drivers/net/bnx2x/bnx2x_sp.c
kern/drivers/net/bnx2x/bnx2x_sp.h
kern/drivers/net/bnx2x/bnx2x_sriov.c
kern/drivers/net/bnx2x/bnx2x_sriov.h
kern/drivers/net/bnx2x/bnx2x_stats.c
kern/drivers/net/bnx2x/bnx2x_stats.h
kern/drivers/net/bnx2x/bnx2x_vfpf.c
kern/drivers/net/bnx2x/bnx2x_vfpf.h
scripts/spatch/linux/scalar.cocci [new file with mode: 0644]

index 152bc65..b55c879 100644 (file)
@@ -152,9 +152,12 @@ do {                                               \
 #define REG_RD8(bp, offset)            readb(REG_ADDR(bp, offset))
 #define REG_RD16(bp, offset)           readw(REG_ADDR(bp, offset))
 
-#define REG_WR(bp, offset, val)                writel((u32)val, REG_ADDR(bp, offset))
-#define REG_WR8(bp, offset, val)       writeb((u8)val, REG_ADDR(bp, offset))
-#define REG_WR16(bp, offset, val)      writew((u16)val, REG_ADDR(bp, offset))
+#define REG_WR(bp, offset, val)                writel((uint32_t)val,
+                                                     REG_ADDR(bp, offset))
+#define REG_WR8(bp, offset, val)       writeb((uint8_t)val,
+                                              REG_ADDR(bp, offset))
+#define REG_WR16(bp, offset, val)      writew((uint16_t)val,
+                                               REG_ADDR(bp, offset))
 
 #define REG_RD_IND(bp, offset)         bnx2x_reg_rd_ind(bp, offset)
 #define REG_WR_IND(bp, offset, val)    bnx2x_reg_wr_ind(bp, offset, val)
@@ -329,14 +332,14 @@ enum {
  * skb are built only after Hardware filled the frame.
  */
 struct sw_rx_bd {
-       u8              *data;
+       uint8_t         *data;
        DEFINE_DMA_UNMAP_ADDR(mapping);
 };
 
 struct sw_tx_bd {
        struct sk_buff  *skb;
-       u16             first_bd;
-       u8              flags;
+       uint16_t                first_bd;
+       uint8_t         flags;
 /* Set on the first BD descriptor when there is a split BD */
 #define BNX2X_TSO_SPLIT_BD             (1<<0)
 #define BNX2X_HAS_SECOND_PBD           (1<<1)
@@ -349,7 +352,7 @@ struct sw_rx_page {
 
 union db_prod {
        struct doorbell_set_prod data;
-       u32             raw;
+       uint32_t                raw;
 };
 
 /* dropless fc FW/HW related params */
@@ -373,7 +376,7 @@ union db_prod {
 #define SGE_PAGE_SHIFT         PAGE_SHIFT
 #define SGE_PAGE_ALIGN(addr)   PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
 #define SGE_PAGES              (SGE_PAGE_SIZE * PAGES_PER_SGE)
-#define TPA_AGG_SIZE           min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
+#define TPA_AGG_SIZE           min_t(uint32_t, (min_t(uint32_t, 8, MAX_SKB_FRAGS) * \
                                            SGE_PAGES), 0xffff)
 
 /* SGE ring related macros */
@@ -413,16 +416,16 @@ union db_prod {
 /* Number of bits in one sge_mask array element */
 #define BIT_VEC64_ELEM_SZ              64
 #define BIT_VEC64_ELEM_SHIFT           6
-#define BIT_VEC64_ELEM_MASK            ((u64)BIT_VEC64_ELEM_SZ - 1)
+#define BIT_VEC64_ELEM_MASK            ((uint64_t)BIT_VEC64_ELEM_SZ - 1)
 
 #define __BIT_VEC64_SET_BIT(el, bit) \
        do { \
-               el = ((el) | ((u64)0x1 << (bit))); \
+               el = ((el) | ((uint64_t)0x1 << (bit))); \
        } while (0)
 
 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
        do { \
-               el = ((el) & (~((u64)0x1 << (bit)))); \
+               el = ((el) & (~((uint64_t)0x1 << (bit)))); \
        } while (0)
 
 #define BIT_VEC64_SET_BIT(vec64, idx) \
@@ -440,8 +443,8 @@ union db_prod {
 /* Creates a bitmask of all ones in less significant bits.
    idx - index of the most significant bit in the created mask */
 #define BIT_VEC64_ONES_MASK(idx) \
-               (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
-#define BIT_VEC64_ELEM_ONE_MASK        ((u64)(~0))
+               (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
+#define BIT_VEC64_ELEM_ONE_MASK        ((uint64_t)(~0))
 
 /*******************************************************/
 
@@ -466,18 +469,18 @@ struct bnx2x_agg_info {
         * keep the Rx BD ring consistent.
         */
        struct sw_rx_bd         first_buf;
-       u8                      tpa_state;
+       uint8_t                 tpa_state;
 #define BNX2X_TPA_START                        1
 #define BNX2X_TPA_STOP                 2
 #define BNX2X_TPA_ERROR                        3
-       u8                      placement_offset;
-       u16                     parsing_flags;
-       u16                     vlan_tag;
-       u16                     len_on_bd;
-       u32                     rxhash;
+       uint8_t                 placement_offset;
+       uint16_t                        parsing_flags;
+       uint16_t                        vlan_tag;
+       uint16_t                        len_on_bd;
+       uint32_t                        rxhash;
        enum pkt_hash_types     rxhash_type;
-       u16                     gro_size;
-       u16                     full_page;
+       uint16_t                        gro_size;
+       uint16_t                        full_page;
 };
 
 #define Q_STATS_OFFSET32(stat_name) \
@@ -490,14 +493,14 @@ struct bnx2x_fp_txdata {
        union eth_tx_bd_types   *tx_desc_ring;
        dma_addr_t              tx_desc_mapping;
 
-       u32                     cid;
+       uint32_t                        cid;
 
        union db_prod           tx_db;
 
-       u16                     tx_pkt_prod;
-       u16                     tx_pkt_cons;
-       u16                     tx_bd_prod;
-       u16                     tx_bd_cons;
+       uint16_t                        tx_pkt_prod;
+       uint16_t                        tx_pkt_cons;
+       uint16_t                        tx_bd_prod;
+       uint16_t                        tx_bd_cons;
 
        unsigned long           tx_pkt;
 
@@ -539,15 +542,15 @@ struct bnx2x_fastpath {
        __le16                  *sb_index_values;
        __le16                  *sb_running_index;
        /* chip independent shortcut into rx_prods_offset memory */
-       u32                     ustorm_rx_prods_offset;
+       uint32_t                        ustorm_rx_prods_offset;
 
-       u32                     rx_buf_size;
-       u32                     rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
+       uint32_t                        rx_buf_size;
+       uint32_t                        rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
        dma_addr_t              status_blk_mapping;
 
        enum bnx2x_tpa_mode_t   mode;
 
-       u8                      max_cos; /* actual number of active tx coses */
+       uint8_t                 max_cos; /* actual number of active tx coses */
        struct bnx2x_fp_txdata  *txdata_ptr[BNX2X_MULTI_TX_COS];
 
        struct sw_rx_bd         *rx_buf_ring;   /* BDs mappings ring */
@@ -563,35 +566,35 @@ struct bnx2x_fastpath {
        struct eth_rx_sge       *rx_sge_ring;
        dma_addr_t              rx_sge_mapping;
 
-       u64                     sge_mask[RX_SGE_MASK_LEN];
+       uint64_t                        sge_mask[RX_SGE_MASK_LEN];
 
-       u32                     cid;
+       uint32_t                        cid;
 
        __le16                  fp_hc_idx;
 
-       u8                      index;          /* number in fp array */
-       u8                      rx_queue;       /* index for skb_record */
-       u8                      cl_id;          /* eth client id */
-       u8                      cl_qzone_id;
-       u8                      fw_sb_id;       /* status block number in FW */
-       u8                      igu_sb_id;      /* status block number in HW */
-
-       u16                     rx_bd_prod;
-       u16                     rx_bd_cons;
-       u16                     rx_comp_prod;
-       u16                     rx_comp_cons;
-       u16                     rx_sge_prod;
+       uint8_t                 index;          /* number in fp array */
+       uint8_t                 rx_queue;       /* index for skb_record */
+       uint8_t                 cl_id;          /* eth client id */
+       uint8_t                 cl_qzone_id;
+       uint8_t                 fw_sb_id;       /* status block number in FW */
+       uint8_t                 igu_sb_id;      /* status block number in HW */
+
+       uint16_t                        rx_bd_prod;
+       uint16_t                        rx_bd_cons;
+       uint16_t                        rx_comp_prod;
+       uint16_t                        rx_comp_cons;
+       uint16_t                        rx_sge_prod;
        /* The last maximal completed SGE */
-       u16                     last_max_sge;
+       uint16_t                        last_max_sge;
        __le16                  *rx_cons_sb;
        unsigned long           rx_pkt,
                                rx_calls;
 
        /* TPA related */
        struct bnx2x_agg_info   *tpa_info;
-       u8                      disable_tpa;
+       uint8_t                 disable_tpa;
 #ifdef BNX2X_STOP_ON_ERROR
-       u64                     tpa_queue_used;
+       uint64_t                        tpa_queue_used;
 #endif
        /* The size is calculated using the following:
             sizeof name field from netdev structure +
@@ -822,8 +825,8 @@ static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp)
                                        ETH_MIN_RX_CQES_WITH_TPA_E1 : \
                                        ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
 #define MIN_RX_SIZE_NONTPA_HW   ETH_MIN_RX_CQES_WITHOUT_TPA
-#define MIN_RX_SIZE_TPA                (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
-#define MIN_RX_SIZE_NONTPA     (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
+#define MIN_RX_SIZE_TPA                (max_t(uint32_t, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
+#define MIN_RX_SIZE_NONTPA     (max_t(uint32_t, MIN_RX_SIZE_NONTPA_HW,\
                                                                MIN_RX_AVAIL))
 
 #define NEXT_RX_IDX(x)         ((((x) & RX_DESC_MASK) == \
@@ -887,13 +890,13 @@ static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp)
 #endif
 #define DOORBELL(bp, cid, val) \
        do { \
-               writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \
+               writel((uint32_t)(val), bp->doorbells + (bp->db_size * (cid))); \
        } while (0)
 
 /* TX CSUM helpers */
 #define SKB_CS_OFF(skb)                (offsetof(struct tcphdr, check) - \
                                 skb->csum_offset)
-#define SKB_CS(skb)            (*(u16 *)(skb_transport_header(skb) + \
+#define SKB_CS(skb)            (*(uint16_t *)(skb_transport_header(skb) + \
                                          skb->csum_offset))
 
 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
@@ -963,7 +966,7 @@ static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp)
 
 struct bnx2x_common {
 
-       u32                     chip_id;
+       uint32_t                        chip_id;
 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
 #define CHIP_ID(bp)                    (bp->common.chip_id & 0xfffffff0)
 
@@ -1082,16 +1085,16 @@ struct bnx2x_common {
 #define BNX2X_NVRAM_TIMEOUT_COUNT              30000
 #define BNX2X_NVRAM_PAGE_SIZE                  256
 
-       u32                     shmem_base;
-       u32                     shmem2_base;
-       u32                     mf_cfg_base;
-       u32                     mf2_cfg_base;
+       uint32_t                        shmem_base;
+       uint32_t                        shmem2_base;
+       uint32_t                        mf_cfg_base;
+       uint32_t                        mf2_cfg_base;
 
-       u32                     hw_config;
+       uint32_t                        hw_config;
 
-       u32                     bc_ver;
+       uint32_t                        bc_ver;
 
-       u8                      int_block;
+       uint8_t                 int_block;
 #define INT_BLOCK_HC                   0
 #define INT_BLOCK_IGU                  1
 #define INT_BLOCK_MODE_NORMAL          0
@@ -1101,14 +1104,14 @@ struct bnx2x_common {
                        !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
 
-       u8                      chip_port_mode;
+       uint8_t                 chip_port_mode;
 #define CHIP_4_PORT_MODE                       0x0
 #define CHIP_2_PORT_MODE                       0x1
 #define CHIP_PORT_MODE_NONE                    0x2
 #define CHIP_MODE(bp)                  (bp->common.chip_port_mode)
 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
 
-       u32                     boot_mode;
+       uint32_t                        boot_mode;
 };
 
 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
@@ -1121,24 +1124,24 @@ struct bnx2x_common {
 /* port */
 
 struct bnx2x_port {
-       u32                     pmf;
+       uint32_t                        pmf;
 
-       u32                     link_config[LINK_CONFIG_SIZE];
+       uint32_t                        link_config[LINK_CONFIG_SIZE];
 
-       u32                     supported[LINK_CONFIG_SIZE];
+       uint32_t                        supported[LINK_CONFIG_SIZE];
 /* link settings - missing defines */
 #define SUPPORTED_2500baseX_Full       (1 << 15)
 
-       u32                     advertising[LINK_CONFIG_SIZE];
+       uint32_t                        advertising[LINK_CONFIG_SIZE];
 /* link settings - missing defines */
 #define ADVERTISED_2500baseX_Full      (1 << 15)
 
-       u32                     phy_addr;
+       uint32_t                        phy_addr;
 
        /* used to synchronize phy accesses */
        struct mutex            phy_mutex;
 
-       u32                     port_stx;
+       uint32_t                        port_stx;
 
        struct nig_stats        old_nig_stats;
 };
@@ -1282,14 +1285,14 @@ struct bnx2x_slowpath {
        /* used by dmae command executer */
        struct dmae_command             dmae[MAX_DMAE_C];
 
-       u32                             stats_comp;
+       uint32_t                                stats_comp;
        union mac_stats                 mac_stats;
        struct nig_stats                nig_stats;
        struct host_port_stats          port_stats;
        struct host_func_stats          func_stats;
 
-       u32                             wb_comp;
-       u32                             wb_data[4];
+       uint32_t                                wb_comp;
+       uint32_t                                wb_data[4];
 
        union drv_info_to_mcp           drv_info_to_mcp;
 };
@@ -1302,15 +1305,15 @@ struct bnx2x_slowpath {
 #define MAX_DYNAMIC_ATTN_GRPS          8
 
 struct attn_route {
-       u32 sig[5];
+       uint32_t sig[5];
 };
 
 struct iro {
-       u32 base;
-       u16 m1;
-       u16 m2;
-       u16 m3;
-       u16 size;
+       uint32_t base;
+       uint16_t m1;
+       uint16_t m2;
+       uint16_t m3;
+       uint16_t size;
 };
 
 struct hw_context {
@@ -1359,7 +1362,7 @@ enum bnx2x_recovery_state {
  * to prevent reporting the same link parameters twice.
  */
 struct bnx2x_link_report_data {
-       u16 line_speed;                 /* Effective line speed */
+       uint16_t line_speed;                    /* Effective line speed */
        unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
 };
 
@@ -1413,11 +1416,11 @@ enum bnx2x_iov_flag {
 
 struct bnx2x_prev_path_list {
        struct list_head list;
-       u8 bus;
-       u8 slot;
-       u8 path;
-       u8 aer;
-       u8 undi;
+       uint8_t bus;
+       uint8_t slot;
+       uint8_t path;
+       uint8_t aer;
+       uint8_t undi;
 };
 
 struct bnx2x_sp_objs {
@@ -1986,10 +1989,10 @@ struct bnx2x_func_init_params {
        dma_addr_t      fw_stat_map;    /* valid iff FUNC_FLG_STATS */
        dma_addr_t      spq_map;        /* valid iff FUNC_FLG_SPQ */
 
-       u16             func_flgs;
-       u16             func_id;        /* abs fid */
-       u16             pf_id;
-       u16             spq_prod;       /* valid iff FUNC_FLG_SPQ */
+       uint16_t                func_flgs;
+       uint16_t                func_id;        /* abs fid */
+       uint16_t                pf_id;
+       uint16_t                spq_prod;       /* valid iff FUNC_FLG_SPQ */
 };
 
 #define for_each_cnic_queue(bp, var) \
@@ -2096,7 +2099,7 @@ struct bnx2x_func_init_params {
  * operation has been successfully scheduled and a negative - if a requested
  * operations has failed.
  */
-int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
+int bnx2x_set_mac_one(struct bnx2x *bp, uint8_t *mac,
                      struct bnx2x_vlan_mac_obj *obj, bool set,
                      int mac_type, unsigned long *ramrod_flags);
 /**
@@ -2120,50 +2123,55 @@ int bnx2x_del_all_macs(struct bnx2x *bp,
 /* Init Function API  */
 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
-                   u8 vf_valid, int fw_sb_id, int igu_sb_id);
-int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
-int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
-int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
-int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
+                   uint8_t vf_valid, int fw_sb_id, int igu_sb_id);
+int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, uint8_t port);
+int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, uint32_t mode,
+                  uint8_t port);
+int bnx2x_set_mult_gpio(struct bnx2x *bp, uint8_t pins, uint32_t mode);
+int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, uint32_t mode,
+                      uint8_t port);
 void bnx2x_read_mf_cfg(struct bnx2x *bp);
 
-int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
+int bnx2x_pretend_func(struct bnx2x *bp, uint16_t pretend_func_val);
 
 /* dmae */
-void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
-void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
-                     u32 len32);
+void bnx2x_read_dmae(struct bnx2x *bp, uint32_t src_addr, uint32_t len32);
+void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
+                     uint32_t dst_addr,
+                     uint32_t len32);
 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
-u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
-u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
-u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
-                     bool with_comp, u8 comp_type);
+uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
+uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode);
+uint32_t bnx2x_dmae_opcode(struct bnx2x *bp, uint8_t src_type, uint8_t dst_type,
+                     bool with_comp, uint8_t comp_type);
 
 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
-                              u8 src_type, u8 dst_type);
+                              uint8_t src_type, uint8_t dst_type);
 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
-                              u32 *comp);
+                              uint32_t *comp);
 
 /* FLR related routines */
-u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
-void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
-int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
-u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
-int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
-                                   char *msg, u32 poll_cnt);
+uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
+void bnx2x_tx_hw_flushed(struct bnx2x *bp, uint32_t poll_count);
+int bnx2x_send_final_clnup(struct bnx2x *bp, uint8_t clnup_func,
+                          uint32_t poll_cnt);
+uint8_t bnx2x_is_pcie_pending(struct pci_dev *dev);
+int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, uint32_t reg,
+                                   char *msg, uint32_t poll_cnt);
 
 void bnx2x_calc_fc_adv(struct bnx2x *bp);
 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
-                 u32 data_hi, u32 data_lo, int cmd_type);
+                 uint32_t data_hi, uint32_t data_lo, int cmd_type);
 void bnx2x_update_coalesce(struct bnx2x *bp);
 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
 
 bool bnx2x_port_after_undi(struct bnx2x *bp);
 
-static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
+static inline uint32_t reg_poll(struct bnx2x *bp, uint32_t reg,
+                               uint32_t expected, int ms,
                           int wait)
 {
-       u32 val;
+       uint32_t val;
 
        do {
                val = REG_RD(bp, reg);
@@ -2177,7 +2185,8 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
        return val;
 }
 
-void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
+void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, uint8_t func,
+                           uint8_t idu_sb_id,
                            bool is_pf);
 
 #define BNX2X_ILT_ZALLOC(x, y, size)                                   \
@@ -2208,8 +2217,8 @@ void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
  * then since this is a wide register(TM)
  * we split it into two 32 bit writes
  */
-#define ONCHIP_ADDR1(x)                ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
-#define ONCHIP_ADDR2(x)                ((u32)((1 << 20) | ((u64)x >> 44)))
+#define ONCHIP_ADDR1(x)                ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
+#define ONCHIP_ADDR2(x)                ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
 
 /* load/unload mode */
 #define LOAD_NORMAL                    0
@@ -2503,7 +2512,8 @@ void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
 
 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
                            (!((me_reg) & ME_REG_VF_ERR)))
-int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err);
+int bnx2x_compare_fw_ver(struct bnx2x *bp, uint32_t load_code,
+                        bool print_err);
 
 /* Congestion management fairness mode */
 #define CMNG_FNS_NONE                  0
@@ -2513,7 +2523,7 @@ int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err);
 #define HC_SEG_ACCESS_ATTN             4
 #define HC_SEG_ACCESS_NORM             0   /*Driver decision 0-1*/
 
-static const u32 dmae_reg_go_c[] = {
+static const uint32_t dmae_reg_go_c[] = {
        DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
        DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
        DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
index 78e5df0..136f80c 100644 (file)
@@ -135,7 +135,7 @@ static inline void bnx2x_move_fp(struct bnx2x *bp, int from, int to)
 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len)
 {
        if (IS_PF(bp)) {
-               u8 phy_fw_ver[PHY_FW_VER_LEN];
+               uint8_t phy_fw_ver[PHY_FW_VER_LEN];
 
                phy_fw_ver[0] = '\0';
                bnx2x_get_ext_phy_fw_version(&bp->link_params,
@@ -182,17 +182,17 @@ int bnx2x_load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
 /* free skb in the packet ring at pos idx
  * return idx of last bd freed
  */
-static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
-                            u16 idx, unsigned int *pkts_compl,
+static uint16_t bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
+                            uint16_t idx, unsigned int *pkts_compl,
                             unsigned int *bytes_compl)
 {
        struct sw_tx_bd *tx_buf = &txdata->tx_buf_ring[idx];
        struct eth_tx_start_bd *tx_start_bd;
        struct eth_tx_bd *tx_data_bd;
        struct sk_buff *skb = tx_buf->skb;
-       u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
+       uint16_t bd_idx = TX_BD(tx_buf->first_bd), new_cons;
        int nbd;
-       u16 split_bd_len = 0;
+       uint16_t split_bd_len = 0;
 
        /* prefetch skb end pointer to speedup dev_kfree_skb() */
        prefetch(&skb->end);
@@ -264,7 +264,7 @@ static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
 {
        struct netdev_queue *txq;
-       u16 hw_cons, sw_cons, bd_cons = txdata->tx_bd_cons;
+       uint16_t hw_cons, sw_cons, bd_cons = txdata->tx_bd_cons;
        unsigned int pkts_compl = 0, bytes_compl = 0;
 
 #ifdef BNX2X_STOP_ON_ERROR
@@ -277,7 +277,7 @@ int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
        sw_cons = txdata->tx_pkt_cons;
 
        while (sw_cons != hw_cons) {
-               u16 pkt_cons;
+               uint16_t pkt_cons;
 
                pkt_cons = TX_BD(sw_cons);
 
@@ -331,22 +331,22 @@ int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
 }
 
 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
-                                            u16 idx)
+                                            uint16_t idx)
 {
-       u16 last_max = fp->last_max_sge;
+       uint16_t last_max = fp->last_max_sge;
 
        if (SUB_S16(idx, last_max) > 0)
                fp->last_max_sge = idx;
 }
 
 static inline void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
-                                        u16 sge_len,
+                                        uint16_t sge_len,
                                         struct eth_end_agg_rx_cqe *cqe)
 {
        struct bnx2x *bp = fp->bp;
-       u16 last_max, last_elem, first_elem;
-       u16 delta = 0;
-       u16 i;
+       uint16_t last_max, last_elem, first_elem;
+       uint16_t delta = 0;
+       uint16_t i;
 
        if (!sge_len)
                return;
@@ -395,7 +395,7 @@ static inline void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
 /* Get Toeplitz hash value in the skb using the value from the
  * CQE (calculated by HW).
  */
-static u32 bnx2x_get_rxhash(const struct bnx2x *bp,
+static uint32_t bnx2x_get_rxhash(const struct bnx2x *bp,
                            const struct eth_fast_path_rx_cqe *cqe,
                            enum pkt_hash_types *rxhash_type)
 {
@@ -415,8 +415,8 @@ static u32 bnx2x_get_rxhash(const struct bnx2x *bp,
        return 0;
 }
 
-static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
-                           u16 cons, u16 prod,
+static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, uint16_t queue,
+                           uint16_t cons, uint16_t prod,
                            struct eth_fast_path_rx_cqe *cqe)
 {
        struct bnx2x *bp = fp->bp;
@@ -467,7 +467,7 @@ static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
        tpa_info->placement_offset = cqe->placement_offset;
        tpa_info->rxhash = bnx2x_get_rxhash(bp, cqe, &tpa_info->rxhash_type);
        if (fp->mode == TPA_MODE_GRO) {
-               u16 gro_size = le16_to_cpu(cqe->pkt_len_or_gro_seg_len);
+               uint16_t gro_size = le16_to_cpu(cqe->pkt_len_or_gro_seg_len);
                tpa_info->full_page = SGE_PAGES / gro_size * gro_size;
                tpa_info->gro_size = gro_size;
        }
@@ -497,14 +497,14 @@ static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
  * the first packet of it.
  * Compute number of aggregated segments, and gso_type.
  */
-static void bnx2x_set_gro_params(struct sk_buff *skb, u16 parsing_flags,
-                                u16 len_on_bd, unsigned int pkt_len,
-                                u16 num_of_coalesced_segs)
+static void bnx2x_set_gro_params(struct sk_buff *skb, uint16_t parsing_flags,
+                                uint16_t len_on_bd, unsigned int pkt_len,
+                                uint16_t num_of_coalesced_segs)
 {
        /* TPA aggregation won't have either IP options or TCP options
         * other than timestamp or IPv6 extension headers.
         */
-       u16 hdrs_len = ETH_HLEN + sizeof(struct tcphdr);
+       uint16_t hdrs_len = ETH_HLEN + sizeof(struct tcphdr);
 
        if (GET_FLAG(parsing_flags, PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) ==
            PRS_FLAG_OVERETH_IPV6) {
@@ -532,7 +532,7 @@ static void bnx2x_set_gro_params(struct sk_buff *skb, u16 parsing_flags,
 }
 
 static int bnx2x_alloc_rx_sge(struct bnx2x *bp, struct bnx2x_fastpath *fp,
-                             u16 index, gfp_t gfp_mask)
+                             uint16_t index, gfp_t gfp_mask)
 {
        struct page *page = alloc_pages(gfp_mask, PAGES_PER_SGE_SHIFT);
        struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
@@ -563,16 +563,16 @@ static int bnx2x_alloc_rx_sge(struct bnx2x *bp, struct bnx2x_fastpath *fp,
 
 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
                               struct bnx2x_agg_info *tpa_info,
-                              u16 pages,
+                              uint16_t pages,
                               struct sk_buff *skb,
                               struct eth_end_agg_rx_cqe *cqe,
-                              u16 cqe_idx)
+                              uint16_t cqe_idx)
 {
        struct sw_rx_page *rx_pg, old_rx_pg;
-       u32 i, frag_len, frag_size;
+       uint32_t i, frag_len, frag_size;
        int err, j, frag_id = 0;
-       u16 len_on_bd = tpa_info->len_on_bd;
-       u16 full_page = 0, gro_size = 0;
+       uint16_t len_on_bd = tpa_info->len_on_bd;
+       uint16_t full_page = 0, gro_size = 0;
 
        frag_size = le16_to_cpu(cqe->pkt_len) - len_on_bd;
 
@@ -588,7 +588,7 @@ static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
                                     le16_to_cpu(cqe->num_of_coalesced_segs));
 
 #ifdef BNX2X_STOP_ON_ERROR
-       if (pages > min_t(u32, 8, MAX_SKB_FRAGS) * SGE_PAGES) {
+       if (pages > min_t(uint32_t, 8, MAX_SKB_FRAGS) * SGE_PAGES) {
                BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
                          pages, cqe_idx);
                BNX2X_ERR("cqe->pkt_len = %d\n", cqe->pkt_len);
@@ -599,14 +599,16 @@ static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
 
        /* Run through the SGL and compose the fragmented skb */
        for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
-               u16 sge_idx = RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[j]));
+               uint16_t sge_idx = RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[j]));
 
                /* FW gives the indices of the SGE as if the ring is an array
                   (meaning that "next" element will consume 2 indices) */
                if (fp->mode == TPA_MODE_GRO)
-                       frag_len = min_t(u32, frag_size, (u32)full_page);
+                       frag_len = min_t(uint32_t, frag_size,
+                                        (uint32_t)full_page);
                else /* LRO */
-                       frag_len = min_t(u32, frag_size, (u32)SGE_PAGES);
+                       frag_len = min_t(uint32_t, frag_size,
+                                        (uint32_t)SGE_PAGES);
 
                rx_pg = &fp->rx_page_ring[sge_idx];
                old_rx_pg = *rx_pg;
@@ -728,16 +730,16 @@ static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp,
 
 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
                           struct bnx2x_agg_info *tpa_info,
-                          u16 pages,
+                          uint16_t pages,
                           struct eth_end_agg_rx_cqe *cqe,
-                          u16 cqe_idx)
+                          uint16_t cqe_idx)
 {
        struct sw_rx_bd *rx_buf = &tpa_info->first_buf;
-       u8 pad = tpa_info->placement_offset;
-       u16 len = tpa_info->len_on_bd;
+       uint8_t pad = tpa_info->placement_offset;
+       uint16_t len = tpa_info->len_on_bd;
        struct sk_buff *skb = NULL;
-       u8 *new_data, *data = rx_buf->data;
-       u8 old_tpa_state = tpa_info->tpa_state;
+       uint8_t *new_data, *data = rx_buf->data;
+       uint8_t old_tpa_state = tpa_info->tpa_state;
 
        tpa_info->tpa_state = BNX2X_TPA_STOP;
 
@@ -800,9 +802,9 @@ drop:
 }
 
 static int bnx2x_alloc_rx_data(struct bnx2x *bp, struct bnx2x_fastpath *fp,
-                              u16 index, gfp_t gfp_mask)
+                              uint16_t index, gfp_t gfp_mask)
 {
-       u8 *data;
+       uint8_t *data;
        struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
        struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
        dma_addr_t mapping;
@@ -856,8 +858,8 @@ void bnx2x_csum_validate(struct sk_buff *skb, union eth_rx_cqe *cqe,
 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
 {
        struct bnx2x *bp = fp->bp;
-       u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
-       u16 sw_comp_cons, sw_comp_prod;
+       uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
+       uint16_t sw_comp_cons, sw_comp_prod;
        int rx_pkt = 0;
        union eth_rx_cqe *cqe;
        struct eth_fast_path_rx_cqe *cqe_fp;
@@ -885,11 +887,11 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
        while (BNX2X_IS_CQE_COMPLETED(cqe_fp)) {
                struct sw_rx_bd *rx_buf = NULL;
                struct sk_buff *skb;
-               u8 cqe_fp_flags;
+               uint8_t cqe_fp_flags;
                enum eth_rx_cqe_type cqe_fp_type;
-               u16 len, pad, queue;
-               u8 *data;
-               u32 rxhash;
+               uint16_t len, pad, queue;
+               uint8_t *data;
+               uint32_t rxhash;
                enum pkt_hash_types rxhash_type;
 
 #ifdef BNX2X_STOP_ON_ERROR
@@ -934,7 +936,7 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
 
                if (!CQE_TYPE_FAST(cqe_fp_type)) {
                        struct bnx2x_agg_info *tpa_info;
-                       u16 frag_size, pages;
+                       uint16_t frag_size, pages;
 #ifdef BNX2X_STOP_ON_ERROR
                        /* sanity check */
                        if (fp->disable_tpa &&
@@ -945,7 +947,7 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
 #endif
 
                        if (CQE_TYPE_START(cqe_fp_type)) {
-                               u16 queue = cqe_fp->queue_index;
+                               uint16_t queue = cqe_fp->queue_index;
                                DP(NETIF_MSG_RX_STATUS,
                                   "calling tpa_start on queue %d\n",
                                   queue);
@@ -1111,7 +1113,7 @@ static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
 {
        struct bnx2x_fastpath *fp = fp_cookie;
        struct bnx2x *bp = fp->bp;
-       u8 cos;
+       uint8_t cos;
 
        DP(NETIF_MSG_INTR,
           "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n",
@@ -1150,11 +1152,11 @@ void bnx2x_release_phy_lock(struct bnx2x *bp)
 }
 
 /* calculates MF speed according to current linespeed and MF configuration */
-u16 bnx2x_get_mf_speed(struct bnx2x *bp)
+uint16_t bnx2x_get_mf_speed(struct bnx2x *bp)
 {
-       u16 line_speed = bp->link_vars.line_speed;
+       uint16_t line_speed = bp->link_vars.line_speed;
        if (IS_MF(bp)) {
-               u16 maxCfg = bnx2x_extract_max_cfg(bp,
+               uint16_t maxCfg = bnx2x_extract_max_cfg(bp,
                                                   bp->mf_config[BP_VN(bp)]);
 
                /* Calculate the current MAX line speed limit for the MF
@@ -1163,7 +1165,7 @@ u16 bnx2x_get_mf_speed(struct bnx2x *bp)
                if (IS_MF_SI(bp))
                        line_speed = (line_speed * maxCfg) / 100;
                else { /* SD mode */
-                       u16 vn_max_rate = maxCfg * 100;
+                       uint16_t vn_max_rate = maxCfg * 100;
 
                        if (vn_max_rate < line_speed)
                                line_speed = vn_max_rate;
@@ -1339,7 +1341,7 @@ static void bnx2x_free_tpa_pool(struct bnx2x *bp,
        for (i = 0; i < last; i++) {
                struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i];
                struct sw_rx_bd *first_buf = &tpa_info->first_buf;
-               u8 *data = first_buf->data;
+               uint8_t *data = first_buf->data;
 
                if (data == NULL) {
                        DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
@@ -1376,7 +1378,7 @@ void bnx2x_init_rx_rings_cnic(struct bnx2x *bp)
 void bnx2x_init_rx_rings(struct bnx2x *bp)
 {
        int func = BP_FUNC(bp);
-       u16 ring_prod;
+       uint16_t ring_prod;
        int i, j;
 
        /* Allocate TPA resources */
@@ -1468,15 +1470,15 @@ void bnx2x_init_rx_rings(struct bnx2x *bp)
 
 static void bnx2x_free_tx_skbs_queue(struct bnx2x_fastpath *fp)
 {
-       u8 cos;
+       uint8_t cos;
        struct bnx2x *bp = fp->bp;
 
        for_each_cos_in_tx_queue(fp, cos) {
                struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
                unsigned pkts_compl = 0, bytes_compl = 0;
 
-               u16 sw_prod = txdata->tx_pkt_prod;
-               u16 sw_cons = txdata->tx_pkt_cons;
+               uint16_t sw_prod = txdata->tx_pkt_prod;
+               uint16_t sw_cons = txdata->tx_pkt_cons;
 
                while (sw_cons != sw_prod) {
                        bnx2x_free_tx_pkt(bp, txdata, TX_BD(sw_cons),
@@ -1519,7 +1521,7 @@ static void bnx2x_free_rx_bds(struct bnx2x_fastpath *fp)
 
        for (i = 0; i < NUM_RX_BD; i++) {
                struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
-               u8 *data = rx_buf->data;
+               uint8_t *data = rx_buf->data;
 
                if (data == NULL)
                        continue;
@@ -1567,10 +1569,10 @@ void bnx2x_free_skbs(struct bnx2x *bp)
        bnx2x_free_rx_skbs(bp);
 }
 
-void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value)
+void bnx2x_update_max_mf_config(struct bnx2x *bp, uint32_t value)
 {
        /* load old values */
-       u32 mf_cfg = bp->mf_config[BP_VN(bp)];
+       uint32_t mf_cfg = bp->mf_config[BP_VN(bp)];
 
        if (value != bnx2x_extract_max_cfg(bp, mf_cfg)) {
                /* leave all but MAX value */
@@ -1896,14 +1898,14 @@ void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
                bnx2x_napi_disable_cnic(bp);
 }
 
-u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb,
+uint16_t bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb,
                       void *accel_priv, select_queue_fallback_t fallback)
 {
        struct bnx2x *bp = netdev_priv(dev);
 
        if (CNIC_LOADED(bp) && !NO_FCOE(bp)) {
                struct ethhdr *hdr = (struct ethhdr *)skb->data;
-               u16 ether_type = ntohs(hdr->h_proto);
+               uint16_t ether_type = ntohs(hdr->h_proto);
 
                /* Skip VLAN tag if present */
                if (ether_type == ETH_P_8021Q) {
@@ -1996,7 +1998,7 @@ static void bnx2x_set_rx_buf_size(struct bnx2x *bp)
 
        for_each_queue(bp, i) {
                struct bnx2x_fastpath *fp = &bp->fp[i];
-               u32 mtu;
+               uint32_t mtu;
 
                /* Always use a mini-jumbo MTU for the FCoE L2 ring */
                if (IS_FCOE_IDX(i))
@@ -2025,7 +2027,7 @@ static void bnx2x_set_rx_buf_size(struct bnx2x *bp)
 static int bnx2x_init_rss(struct bnx2x *bp)
 {
        int i;
-       u8 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
+       uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
 
        /* Prepare the initial contents for the indirection table if RSS is
         * enabled
@@ -2099,7 +2101,7 @@ int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
                return bnx2x_vfpf_config_rss(bp, &params);
 }
 
-static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
+static int bnx2x_init_hw(struct bnx2x *bp, uint32_t load_code)
 {
        struct bnx2x_func_state_params func_params = {NULL};
 
@@ -2216,7 +2218,7 @@ static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
        int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
 
        /* number of queues for statistics is number of eth queues + FCoE */
-       u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
+       uint8_t num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
 
        /* Total number of FW statistics requests =
         * 1 for port stats + 1 for PF stats + potential 2 for FCoE (fcoe proper
@@ -2271,7 +2273,7 @@ static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
        bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
        bp->fw_stats_req_mapping = bp->fw_stats_mapping;
        bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
-               ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
+               ((uint8_t *)bp->fw_stats + bp->fw_stats_req_sz);
        bp->fw_stats_data_mapping = bp->fw_stats_mapping +
                bp->fw_stats_req_sz;
 
@@ -2290,9 +2292,9 @@ alloc_mem_err:
 }
 
 /* send load request to mcp and analyze response */
-static int bnx2x_nic_load_request(struct bnx2x *bp, u32 *load_code)
+static int bnx2x_nic_load_request(struct bnx2x *bp, uint32_t *load_code)
 {
-       u32 param;
+       uint32_t param;
 
        /* init fw_seq */
        bp->fw_seq =
@@ -2334,19 +2336,20 @@ static int bnx2x_nic_load_request(struct bnx2x *bp, u32 *load_code)
  * virtualized environments a pf from another VM may have already
  * initialized the device including loading FW
  */
-int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err)
+int bnx2x_compare_fw_ver(struct bnx2x *bp, uint32_t load_code,
+                        bool print_err)
 {
        /* is another pf loaded on this engine? */
        if (load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP &&
            load_code != FW_MSG_CODE_DRV_LOAD_COMMON) {
                /* build my FW version dword */
-               u32 my_fw = (BCM_5710_FW_MAJOR_VERSION) +
+               uint32_t my_fw = (BCM_5710_FW_MAJOR_VERSION) +
                        (BCM_5710_FW_MINOR_VERSION << 8) +
                        (BCM_5710_FW_REVISION_VERSION << 16) +
                        (BCM_5710_FW_ENGINEERING_VERSION << 24);
 
                /* read loaded FW from chip */
-               u32 loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
+               uint32_t loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
 
                DP(BNX2X_MSG_SP, "loaded fw %x, my fw %x\n",
                   loaded_fw, my_fw);
@@ -2387,7 +2390,7 @@ static int bnx2x_nic_load_no_mcp(struct bnx2x *bp, int port)
 }
 
 /* mark PMF if applicable */
-static void bnx2x_nic_load_pmf(struct bnx2x *bp, u32 load_code)
+static void bnx2x_nic_load_pmf(struct bnx2x *bp, uint32_t load_code)
 {
        if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
            (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
@@ -2841,7 +2844,7 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
 
        if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
                /* mark driver is loaded in shmem2 */
-               u32 val;
+               uint32_t val;
                val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
                SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
                          val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
@@ -2904,7 +2907,7 @@ load_error0:
 
 int bnx2x_drain_tx_queues(struct bnx2x *bp)
 {
-       u8 rc = 0, cos, i;
+       uint8_t rc = 0, cos, i;
 
        /* Wait until tx fastpath tasks complete */
        for_each_tx_queue(bp, i) {
@@ -2928,7 +2931,7 @@ int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
 
        /* mark driver is unloaded in shmem2 */
        if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
-               u32 val;
+               uint32_t val;
                val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
                SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
                          val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
@@ -3095,7 +3098,7 @@ int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
 
 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
 {
-       u16 pmcsr;
+       uint16_t pmcsr;
 
        /* If there is no power capability, silently succeed */
        if (!bp->pdev->pm_cap) {
@@ -3152,7 +3155,7 @@ int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
 static int bnx2x_poll(struct napi_struct *napi, int budget)
 {
        int work_done = 0;
-       u8 cos;
+       uint8_t cos;
        struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
                                                 napi);
        struct bnx2x *bp = fp->bp;
@@ -3255,11 +3258,11 @@ int bnx2x_low_latency_recv(struct napi_struct *napi)
  * to ease the pain of our fellow microcode engineers
  * we use one mapping for both BDs
  */
-static u16 bnx2x_tx_split(struct bnx2x *bp,
+static uint16_t bnx2x_tx_split(struct bnx2x *bp,
                          struct bnx2x_fp_txdata *txdata,
                          struct sw_tx_bd *tx_buf,
-                         struct eth_tx_start_bd **tx_bd, u16 hlen,
-                         u16 bd_prod)
+                         struct eth_tx_start_bd **tx_bd, uint16_t hlen,
+                         uint16_t bd_prod)
 {
        struct eth_tx_start_bd *h_tx_bd = *tx_bd;
        struct eth_tx_bd *d_tx_bd;
@@ -3299,7 +3302,7 @@ static u16 bnx2x_tx_split(struct bnx2x *bp,
 
 #define bswab32(b32) ((__force __le32) swab32((__force __u32) (b32)))
 #define bswab16(b16) ((__force __le16) swab16((__force __u16) (b16)))
-static __le16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
+static __le16 bnx2x_csum_fix(unsigned char *t_header, uint16_t csum, s8 fix)
 {
        __sum16 tsum = (__force __sum16) csum;
 
@@ -3314,9 +3317,9 @@ static __le16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
        return bswab16(tsum);
 }
 
-static u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
+static uint32_t bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
 {
-       u32 rc;
+       uint32_t rc;
        __u8 prot = 0;
        __be16 protocol;
 
@@ -3366,7 +3369,7 @@ static u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
    no need to check fragmentation if page size > 8K (there will be no
    violation to FW restrictions) */
 static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
-                            u32 xmit_type)
+                            uint32_t xmit_type)
 {
        int to_copy = 0;
        int hlen = 0;
@@ -3384,7 +3387,7 @@ static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
                        int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
                        int wnd_idx = 0;
                        int frag_idx = 0;
-                       u32 wnd_sum = 0;
+                       uint32_t wnd_sum = 0;
 
                        /* Headers length */
                        hlen = (int)(skb_transport_header(skb) - skb->data) +
@@ -3450,7 +3453,7 @@ exit_lbl:
  */
 static void bnx2x_set_pbd_gso(struct sk_buff *skb,
                              struct eth_tx_parse_bd_e1x *pbd,
-                             u32 xmit_type)
+                             uint32_t xmit_type)
 {
        pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
        pbd->tcp_send_seq = bswab32(tcp_hdr(skb)->seq);
@@ -3483,11 +3486,11 @@ static void bnx2x_set_pbd_gso(struct sk_buff *skb,
  *
  * 57712/578xx related, when skb has encapsulation
  */
-static u8 bnx2x_set_pbd_csum_enc(struct bnx2x *bp, struct sk_buff *skb,
-                                u32 *parsing_data, u32 xmit_type)
+static uint8_t bnx2x_set_pbd_csum_enc(struct bnx2x *bp, struct sk_buff *skb,
+                                uint32_t *parsing_data, uint32_t xmit_type)
 {
        *parsing_data |=
-               ((((u8 *)skb_inner_transport_header(skb) - skb->data) >> 1) <<
+               ((((uint8_t *)skb_inner_transport_header(skb) - skb->data) >> 1) <<
                ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) &
                ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W;
 
@@ -3517,11 +3520,11 @@ static u8 bnx2x_set_pbd_csum_enc(struct bnx2x *bp, struct sk_buff *skb,
  *
  * 57712/578xx related
  */
-static u8 bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb,
-                               u32 *parsing_data, u32 xmit_type)
+static uint8_t bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb,
+                               uint32_t *parsing_data, uint32_t xmit_type)
 {
        *parsing_data |=
-               ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) <<
+               ((((uint8_t *)skb_transport_header(skb) - skb->data) >> 1) <<
                ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) &
                ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W;
 
@@ -3541,7 +3544,7 @@ static u8 bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb,
 /* set FW indication according to inner or outer protocols if tunneled */
 static void bnx2x_set_sbd_csum(struct bnx2x *bp, struct sk_buff *skb,
                               struct eth_tx_start_bd *tx_start_bd,
-                              u32 xmit_type)
+                              uint32_t xmit_type)
 {
        tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
 
@@ -3560,11 +3563,11 @@ static void bnx2x_set_sbd_csum(struct bnx2x *bp, struct sk_buff *skb,
  * @pbd:       parse BD to be updated
  * @xmit_type: xmit flags
  */
-static u8 bnx2x_set_pbd_csum(struct bnx2x *bp, struct sk_buff *skb,
+static uint8_t bnx2x_set_pbd_csum(struct bnx2x *bp, struct sk_buff *skb,
                             struct eth_tx_parse_bd_e1x *pbd,
-                            u32 xmit_type)
+                            uint32_t xmit_type)
 {
-       u8 hlen = (skb_network_header(skb) - skb->data) >> 1;
+       uint8_t hlen = (skb_network_header(skb) - skb->data) >> 1;
 
        /* for now NS flag is not used in Linux */
        pbd->global_data =
@@ -3611,11 +3614,11 @@ static u8 bnx2x_set_pbd_csum(struct bnx2x *bp, struct sk_buff *skb,
 static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
                                      struct eth_tx_parse_bd_e2 *pbd_e2,
                                      struct eth_tx_parse_2nd_bd *pbd2,
-                                     u16 *global_data,
-                                     u32 xmit_type)
+                                     uint16_t *global_data,
+                                     uint32_t xmit_type)
 {
-       u16 hlen_w = 0;
-       u8 outerip_off, outerip_len = 0;
+       uint16_t hlen_w = 0;
+       uint8_t outerip_off, outerip_len = 0;
 
        /* from outer IP to transport */
        hlen_w = (skb_inner_transport_header(skb) -
@@ -3629,9 +3632,9 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
        /* outer IP header info */
        if (xmit_type & XMIT_CSUM_V4) {
                struct iphdr *iph = ip_hdr(skb);
-               u32 csum = (__force u32)(~iph->check) -
-                          (__force u32)iph->tot_len -
-                          (__force u32)iph->frag_off;
+               uint32_t csum = (__force uint32_t)(~iph->check) -
+                          (__force uint32_t)iph->tot_len -
+                          (__force uint32_t)iph->frag_off;
 
                outerip_len = iph->ihl << 1;
 
@@ -3680,8 +3683,9 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
        }
 }
 
-static inline void bnx2x_set_ipv6_ext_e2(struct sk_buff *skb, u32 *parsing_data,
-                                        u32 xmit_type)
+static inline void bnx2x_set_ipv6_ext_e2(struct sk_buff *skb,
+                                        uint32_t *parsing_data,
+                                        uint32_t xmit_type)
 {
        struct ipv6hdr *ipv6;
 
@@ -3713,16 +3717,16 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
        struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
        struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
        struct eth_tx_parse_2nd_bd *pbd2 = NULL;
-       u32 pbd_e2_parsing_data = 0;
-       u16 pkt_prod, bd_prod;
+       uint32_t pbd_e2_parsing_data = 0;
+       uint16_t pkt_prod, bd_prod;
        int nbd, txq_index;
        dma_addr_t mapping;
-       u32 xmit_type = bnx2x_xmit_type(bp, skb);
+       uint32_t xmit_type = bnx2x_xmit_type(bp, skb);
        int i;
-       u8 hlen = 0;
+       uint8_t hlen = 0;
        __le16 pkt_size = 0;
        struct ethhdr *eth;
-       u8 mac_type = UNICAST_ADDRESS;
+       uint8_t mac_type = UNICAST_ADDRESS;
 
 #ifdef BNX2X_STOP_ON_ERROR
        if (unlikely(bp->panic))
@@ -3889,7 +3893,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
                memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
 
                if (xmit_type & XMIT_CSUM_ENC) {
-                       u16 global_data = 0;
+                       uint16_t global_data = 0;
 
                        /* Set PBD in enc checksum offload case */
                        hlen = bnx2x_set_pbd_csum_enc(bp, skb,
@@ -3967,7 +3971,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
                SET_FLAG(pbd_e2_parsing_data,
                         ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, mac_type);
        } else {
-               u16 global_data = 0;
+               uint16_t global_data = 0;
                pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
                memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
                /* Set PBD in checksum offload case */
@@ -4156,7 +4160,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
  *
  * callback connected to the ndo_setup_tc function pointer
  */
-int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)
+int bnx2x_setup_tc(struct net_device *dev, uint8_t num_tc)
 {
        int cos, prio, count, offset;
        struct bnx2x *bp = netdev_priv(dev);
@@ -4249,7 +4253,7 @@ static void bnx2x_free_fp_mem_at(struct bnx2x *bp, int fp_index)
 {
        union host_hc_status_block *sb = &bnx2x_fp(bp, fp_index, status_blk);
        struct bnx2x_fastpath *fp = &bp->fp[fp_index];
-       u8 cos;
+       uint8_t cos;
 
        /* Common */
 
@@ -4346,7 +4350,7 @@ static int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp,
                              int rx_ring_size)
 {
        struct bnx2x *bp = fp->bp;
-       u16 ring_prod, cqe_ring_prod;
+       uint16_t ring_prod, cqe_ring_prod;
        int i, failure_cnt = 0;
 
        fp->rx_comp_cons = 0;
@@ -4371,7 +4375,7 @@ static int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp,
 
        fp->rx_bd_prod = ring_prod;
        /* Limit the CQE producer by the CQE ring size */
-       fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT,
+       fp->rx_comp_prod = min_t(uint16_t, NUM_RCQ_RINGS*RCQ_DESC_CNT,
                               cqe_ring_prod);
        fp->rx_pkt = fp->rx_calls = 0;
 
@@ -4403,7 +4407,7 @@ static int bnx2x_alloc_fp_mem_at(struct bnx2x *bp, int index)
        union host_hc_status_block *sb;
        struct bnx2x_fastpath *fp = &bp->fp[index];
        int ring_size = 0;
-       u8 cos;
+       uint8_t cos;
        int rx_ring_size = 0;
 
        if (!bp->rx_ring_size && IS_MF_STORAGE_ONLY(bp)) {
@@ -4413,7 +4417,7 @@ static int bnx2x_alloc_fp_mem_at(struct bnx2x *bp, int index)
                rx_ring_size = MAX_RX_AVAIL/BNX2X_NUM_RX_QUEUES(bp);
 
                if (CHIP_IS_E3(bp)) {
-                       u32 cfg = SHMEM_RD(bp,
+                       uint32_t cfg = SHMEM_RD(bp,
                                           dev_info.port_hw_config[BP_PORT(bp)].
                                           default_cfg);
 
@@ -4698,7 +4702,7 @@ int bnx2x_reload_if_running(struct net_device *dev)
 
 int bnx2x_get_cur_phy_idx(struct bnx2x *bp)
 {
-       u32 sel_phy_idx = 0;
+       uint32_t sel_phy_idx = 0;
        if (bp->link_params.num_phys <= 1)
                return INT_PHY;
 
@@ -4727,7 +4731,7 @@ int bnx2x_get_cur_phy_idx(struct bnx2x *bp)
 }
 int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
 {
-       u32 sel_phy_idx = bnx2x_get_cur_phy_idx(bp);
+       uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(bp);
        /*
         * The selected activated PHY is always after swapping (in case PHY
         * swapping is enabled). So when swapping is enabled, we need to reverse
@@ -4745,7 +4749,7 @@ int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
 }
 
 #ifdef NETDEV_FCOE_WWNN
-int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type)
+int bnx2x_fcoe_get_wwn(struct net_device *dev, uint64_t *wwn, int type)
 {
        struct bnx2x *bp = netdev_priv(dev);
        struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
@@ -4814,8 +4818,8 @@ netdev_features_t bnx2x_fix_features(struct net_device *dev,
 int bnx2x_set_features(struct net_device *dev, netdev_features_t features)
 {
        struct bnx2x *bp = netdev_priv(dev);
-       u32 flags = bp->flags;
-       u32 changes;
+       uint32_t flags = bp->flags;
+       uint32_t changes;
        bool bnx2x_reload = false;
 
        if (features & NETIF_F_LRO)
@@ -4945,7 +4949,7 @@ int bnx2x_resume(struct pci_dev *pdev)
 }
 
 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
-                             u32 cid)
+                             uint32_t cid)
 {
        if (!cxt) {
                BNX2X_ERR("bad context pointer %p\n", cxt);
@@ -4962,11 +4966,11 @@ void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
                        CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
 }
 
-static void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
-                                   u8 fw_sb_id, u8 sb_index,
-                                   u8 ticks)
+static void storm_memset_hc_timeout(struct bnx2x *bp, uint8_t port,
+                                   uint8_t fw_sb_id, uint8_t sb_index,
+                                   uint8_t ticks)
 {
-       u32 addr = BAR_CSTRORM_INTMEM +
+       uint32_t addr = BAR_CSTRORM_INTMEM +
                   CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index);
        REG_WR8(bp, addr, ticks);
        DP(NETIF_MSG_IFUP,
@@ -4974,14 +4978,14 @@ static void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
           port, fw_sb_id, sb_index, ticks);
 }
 
-static void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
-                                   u16 fw_sb_id, u8 sb_index,
-                                   u8 disable)
+static void storm_memset_hc_disable(struct bnx2x *bp, uint8_t port,
+                                   uint16_t fw_sb_id, uint8_t sb_index,
+                                   uint8_t disable)
 {
-       u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
-       u32 addr = BAR_CSTRORM_INTMEM +
+       uint32_t enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
+       uint32_t addr = BAR_CSTRORM_INTMEM +
                   CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index);
-       u8 flags = REG_RD8(bp, addr);
+       uint8_t flags = REG_RD8(bp, addr);
        /* clear and set */
        flags &= ~HC_INDEX_DATA_HC_ENABLED;
        flags |= enable_flag;
@@ -4991,11 +4995,12 @@ static void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
           port, fw_sb_id, sb_index, disable);
 }
 
-void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
-                                   u8 sb_index, u8 disable, u16 usec)
+void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, uint8_t fw_sb_id,
+                                   uint8_t sb_index, uint8_t disable,
+                                   uint16_t usec)
 {
        int port = BP_PORT(bp);
-       u8 ticks = usec / BNX2X_BTR;
+       uint8_t ticks = usec / BNX2X_BTR;
 
        storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
 
@@ -5004,7 +5009,7 @@ void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
 }
 
 void bnx2x_schedule_sp_rtnl(struct bnx2x *bp, enum sp_rtnl_flag flag,
-                           u32 verbose)
+                           uint32_t verbose)
 {
        smp_mb__before_atomic();
        set_bit(flag, &bp->sp_rtnl_state);
index 0603e56..f6a0048 100644 (file)
@@ -78,7 +78,7 @@ extern int bnx2x_num_queues;
  *
  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
  */
-u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
+uint32_t bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
 
 /**
  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
@@ -138,7 +138,7 @@ int bnx2x_setup_leading(struct bnx2x *bp);
  *
  * block until there is a reply
  */
-u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
+uint32_t bnx2x_fw_command(struct bnx2x *bp, uint32_t command, uint32_t param);
 
 /**
  * bnx2x_initial_phy_init - initialize link parameters structure variables.
@@ -171,7 +171,7 @@ void bnx2x_force_link_reset(struct bnx2x *bp);
  *
  * Returns 0 if link is UP.
  */
-u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
+uint8_t bnx2x_link_test(struct bnx2x *bp, uint8_t is_serdes);
 
 /**
  * bnx2x_drv_pulse - write driver pulse to shmem
@@ -193,12 +193,12 @@ void bnx2x_drv_pulse(struct bnx2x *bp);
  * @op:                SB operation
  * @update:    is HW update required
  */
-void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
-                     u16 index, u8 op, u8 update);
+void bnx2x_igu_ack_sb(struct bnx2x *bp, uint8_t igu_sb_id, uint8_t segment,
+                     uint16_t index, uint8_t op, uint8_t update);
 
 /* Disable transactions from chip to host */
 void bnx2x_pf_disable(struct bnx2x *bp);
-int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
+int bnx2x_pretend_func(struct bnx2x *bp, uint16_t pretend_func_val);
 
 /**
  * bnx2x__link_status_update - handles link status change.
@@ -224,7 +224,7 @@ void __bnx2x_link_report(struct bnx2x *bp);
  *
  * Takes into account current linespeed and MF configuration.
  */
-u16 bnx2x_get_mf_speed(struct bnx2x *bp);
+uint16_t bnx2x_get_mf_speed(struct bnx2x *bp);
 
 /**
  * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler
@@ -318,7 +318,7 @@ void bnx2x_pre_irq_nic_init(struct bnx2x *bp);
  *  - slowpath rings
  *  - etc.
  */
-void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code);
+void bnx2x_post_irq_nic_init(struct bnx2x *bp, uint32_t load_code);
 /**
  * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic.
  *
@@ -371,7 +371,7 @@ void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link);
  * @bp:                driver handle
  * @resource:  resource bit which was locked
  */
-int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
+int bnx2x_acquire_hw_lock(struct bnx2x *bp, uint32_t resource);
 
 /**
  * bnx2x_release_hw_lock - release HW lock.
@@ -379,7 +379,7 @@ int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
  * @bp:                driver handle
  * @resource:  resource bit which was locked
  */
-int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
+int bnx2x_release_hw_lock(struct bnx2x *bp, uint32_t resource);
 
 /**
  * bnx2x_release_leader_lock - release recovery leader lock
@@ -465,7 +465,7 @@ int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
  * @bp:                driver handle
  * @value:     new value
  */
-void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
+void bnx2x_update_max_mf_config(struct bnx2x *bp, uint32_t value);
 /* Error handling */
 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl);
 
@@ -479,24 +479,26 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
 
 /* setup_tc callback */
-int bnx2x_setup_tc(struct net_device *dev, u8 num_tc);
+int bnx2x_setup_tc(struct net_device *dev, uint8_t num_tc);
 
 int bnx2x_get_vf_config(struct net_device *dev, int vf,
                        struct ifla_vf_info *ivi);
-int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac);
-int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos);
+int bnx2x_set_vf_mac(struct net_device *dev, int queue, uint8_t *mac);
+int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, uint16_t vlan,
+                     uint8_t qos);
 
 /* select_queue callback */
-u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb,
+uint16_t bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb,
                       void *accel_priv, select_queue_fallback_t fallback);
 
 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
                                        struct bnx2x_fastpath *fp,
-                                       u16 bd_prod, u16 rx_comp_prod,
-                                       u16 rx_sge_prod)
+                                       uint16_t bd_prod,
+                                       uint16_t rx_comp_prod,
+                                       uint16_t rx_sge_prod)
 {
        struct ustorm_eth_rx_producers rx_prods = {0};
-       u32 i;
+       uint32_t i;
 
        /* Update producers */
        rx_prods.bd_prod = bd_prod;
@@ -514,7 +516,7 @@ static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
 
        for (i = 0; i < sizeof(rx_prods)/4; i++)
                REG_WR(bp, fp->ustorm_rx_prods_offset + i*4,
-                      ((u32 *)&rx_prods)[i]);
+                      ((uint32_t *)&rx_prods)[i]);
 
        mmiowb(); /* keep prod updates ordered */
 
@@ -602,7 +604,7 @@ int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
  * @type:      WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port)
  *
  */
-int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type);
+int bnx2x_fcoe_get_wwn(struct net_device *dev, uint64_t *wwn, int type);
 #endif
 
 netdev_features_t bnx2x_fix_features(struct net_device *dev,
@@ -624,9 +626,10 @@ static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
        fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
 }
 
-static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
-                                       u8 segment, u16 index, u8 op,
-                                       u8 update, u32 igu_addr)
+static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, uint8_t igu_sb_id,
+                                       uint8_t segment, uint16_t index,
+                                       uint8_t op,
+                                       uint8_t update, uint32_t igu_addr)
 {
        struct igu_regular cmd_data = {0};
 
@@ -645,10 +648,11 @@ static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
        barrier();
 }
 
-static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
-                                  u8 storm, u16 index, u8 op, u8 update)
+static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, uint8_t sb_id,
+                                  uint8_t storm, uint16_t index, uint8_t op,
+                                  uint8_t update)
 {
-       u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
+       uint32_t hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
                       COMMAND_REG_INT_ACK);
        struct igu_ack_register igu_ack;
 
@@ -659,20 +663,21 @@ static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
                         (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
                         (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
 
-       REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
+       REG_WR(bp, hc_addr, (*(uint32_t *)&igu_ack));
 
        /* Make sure that ACK is written */
        mmiowb();
        barrier();
 }
 
-static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
-                               u16 index, u8 op, u8 update)
+static inline void bnx2x_ack_sb(struct bnx2x *bp, uint8_t igu_sb_id,
+                               uint8_t storm,
+                               uint16_t index, uint8_t op, uint8_t update)
 {
        if (bp->common.int_block == INT_BLOCK_HC)
                bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
        else {
-               u8 segment;
+               uint8_t segment;
 
                if (CHIP_INT_MODE_IS_BC(bp))
                        segment = storm;
@@ -686,20 +691,20 @@ static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
        }
 }
 
-static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
+static inline uint16_t bnx2x_hc_ack_int(struct bnx2x *bp)
 {
-       u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
+       uint32_t hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
                       COMMAND_REG_SIMD_MASK);
-       u32 result = REG_RD(bp, hc_addr);
+       uint32_t result = REG_RD(bp, hc_addr);
 
        barrier();
        return result;
 }
 
-static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
+static inline uint16_t bnx2x_igu_ack_int(struct bnx2x *bp)
 {
-       u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
-       u32 result = REG_RD(bp, igu_addr);
+       uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
+       uint32_t result = REG_RD(bp, igu_addr);
 
        DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
           result, igu_addr);
@@ -708,7 +713,7 @@ static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
        return result;
 }
 
-static inline u16 bnx2x_ack_int(struct bnx2x *bp)
+static inline uint16_t bnx2x_ack_int(struct bnx2x *bp)
 {
        barrier();
        if (bp->common.int_block == INT_BLOCK_HC)
@@ -724,12 +729,12 @@ static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata)
        return txdata->tx_pkt_prod != txdata->tx_pkt_cons;
 }
 
-static inline u16 bnx2x_tx_avail(struct bnx2x *bp,
+static inline uint16_t bnx2x_tx_avail(struct bnx2x *bp,
                                 struct bnx2x_fp_txdata *txdata)
 {
        s16 used;
-       u16 prod;
-       u16 cons;
+       uint16_t prod;
+       uint16_t cons;
 
        prod = txdata->tx_bd_prod;
        cons = txdata->tx_bd_cons;
@@ -747,7 +752,7 @@ static inline u16 bnx2x_tx_avail(struct bnx2x *bp,
 
 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata)
 {
-       u16 hw_cons;
+       uint16_t hw_cons;
 
        /* Tell compiler that status block fields can change */
        barrier();
@@ -757,7 +762,7 @@ static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata)
 
 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
 {
-       u8 cos;
+       uint8_t cos;
        for_each_cos_in_tx_queue(fp, cos)
                if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
                        return true;
@@ -768,7 +773,7 @@ static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
 #define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF)
 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
 {
-       u16 cons;
+       uint16_t cons;
        union eth_rx_cqe *cqe;
        struct eth_fast_path_rx_cqe *cqe_fp;
 
@@ -790,7 +795,8 @@ static inline void bnx2x_tx_disable(struct bnx2x *bp)
 }
 
 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
-                                    struct bnx2x_fastpath *fp, u16 index)
+                                    struct bnx2x_fastpath *fp,
+                                    uint16_t index)
 {
        struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
        struct page *page = sw_buf->page;
@@ -874,7 +880,7 @@ static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
  * so there is no need to check for dma_mapping_error().
  */
 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp,
-                                     u16 cons, u16 prod)
+                                     uint16_t cons, uint16_t prod)
 {
        struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
        struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
@@ -950,14 +956,14 @@ static inline int bnx2x_func_start(struct bnx2x *bp)
  * @mac:       pointer to MAC address
  */
 static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid,
-                                        __le16 *fw_lo, u8 *mac)
+                                        __le16 *fw_lo, uint8_t *mac)
 {
-       ((u8 *)fw_hi)[0]  = mac[1];
-       ((u8 *)fw_hi)[1]  = mac[0];
-       ((u8 *)fw_mid)[0] = mac[3];
-       ((u8 *)fw_mid)[1] = mac[2];
-       ((u8 *)fw_lo)[0]  = mac[5];
-       ((u8 *)fw_lo)[1]  = mac[4];
+       ((uint8_t *)fw_hi)[0]  = mac[1];
+       ((uint8_t *)fw_hi)[1]  = mac[0];
+       ((uint8_t *)fw_mid)[0] = mac[3];
+       ((uint8_t *)fw_mid)[1] = mac[2];
+       ((uint8_t *)fw_lo)[0]  = mac[5];
+       ((uint8_t *)fw_lo)[1]  = mac[4];
 }
 
 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
@@ -992,7 +998,7 @@ static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
 /* Statistics ID are global per chip/path, while Client IDs for E1x are per
  * port.
  */
-static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp)
+static inline uint8_t bnx2x_stats_id(struct bnx2x_fastpath *fp)
 {
        struct bnx2x *bp = fp->bp;
        if (!CHIP_IS_E1x(bp)) {
@@ -1026,9 +1032,9 @@ static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp,
  * Calculates the number of active (not hidden) functions on the
  * current path.
  */
-static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp)
+static inline uint8_t bnx2x_get_path_func_num(struct bnx2x *bp)
 {
-       u8 func_num = 0, i;
+       uint8_t func_num = 0, i;
 
        /* 57710 has only one function per-port */
        if (CHIP_IS_E1(bp))
@@ -1044,7 +1050,7 @@ static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp)
                        func_num = 2;
        } else {
                for (i = 0; i < E1H_FUNC_MAX / 2; i++) {
-                       u32 func_config =
+                       uint32_t func_config =
                                MF_CFG_RD(bp,
                                          func_mf_config[BP_PORT(bp) + 2 * i].
                                          config);
@@ -1087,7 +1093,7 @@ static inline void bnx2x_init_bp_objs(struct bnx2x *bp)
                                  BNX2X_OBJ_TYPE_RX);
 }
 
-static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
+static inline uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
 {
        if (CHIP_IS_E1x(fp->bp))
                return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H;
@@ -1096,7 +1102,8 @@ static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
 }
 
 static inline void bnx2x_init_txdata(struct bnx2x *bp,
-                                    struct bnx2x_fp_txdata *txdata, u32 cid,
+                                    struct bnx2x_fp_txdata *txdata,
+                                    uint32_t cid,
                                     int txq_index, __le16 *tx_cons_sb,
                                     struct bnx2x_fastpath *fp)
 {
@@ -1110,19 +1117,19 @@ static inline void bnx2x_init_txdata(struct bnx2x *bp,
           txdata->cid, txdata->txq_index);
 }
 
-static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx)
+static inline uint8_t bnx2x_cnic_eth_cl_id(struct bnx2x *bp, uint8_t cl_idx)
 {
        return bp->cnic_base_cl_id + cl_idx +
                (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX;
 }
 
-static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
+static inline uint8_t bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
 {
        /* the 'first' id is allocated for the cnic */
        return bp->base_fw_ndsb;
 }
 
-static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp)
+static inline uint8_t bnx2x_cnic_igu_sb_id(struct bnx2x *bp)
 {
        return bp->igu_base_sb;
 }
@@ -1154,7 +1161,8 @@ static inline int bnx2x_clean_tx_queue(struct bnx2x *bp,
 int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
 
 static inline void __storm_memset_struct(struct bnx2x *bp,
-                                        u32 addr, size_t size, u32 *data)
+                                        uint32_t addr, size_t size,
+                                        uint32_t *data)
 {
        int i;
        for (i = 0; i < size/4; i++)
@@ -1205,10 +1213,11 @@ static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask)
  * @cid:       SW CID of the connection to be configured
  */
 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
-                             u32 cid);
+                             uint32_t cid);
 
-void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
-                                   u8 sb_index, u8 disable, u16 usec);
+void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, uint8_t fw_sb_id,
+                                   uint8_t sb_index, uint8_t disable,
+                                   uint16_t usec);
 void bnx2x_acquire_phy_lock(struct bnx2x *bp);
 void bnx2x_release_phy_lock(struct bnx2x *bp);
 
@@ -1219,9 +1228,10 @@ void bnx2x_release_phy_lock(struct bnx2x *bp);
  * @mf_cfg:    MF configuration
  *
  */
-static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
+static inline uint16_t bnx2x_extract_max_cfg(struct bnx2x *bp,
+                                            uint32_t mf_cfg)
 {
-       u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
+       uint16_t max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
                              FUNC_MF_CFG_MAX_BW_SHIFT;
        if (!max_cfg) {
                DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL,
@@ -1282,10 +1292,11 @@ static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
  * @set:       set or clear
  *
  */
-static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set)
+static inline void bnx2x_update_drv_flags(struct bnx2x *bp, uint32_t flags,
+                                         uint32_t set)
 {
        if (SHMEM2_HAS(bp, drv_flags)) {
-               u32 drv_flags;
+               uint32_t drv_flags;
                bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
                drv_flags = SHMEM2_RD(bp, drv_flags);
 
@@ -1316,6 +1327,6 @@ int bnx2x_drain_tx_queues(struct bnx2x *bp);
 void bnx2x_squeeze_objects(struct bnx2x *bp);
 
 void bnx2x_schedule_sp_rtnl(struct bnx2x*, enum sp_rtnl_flag,
-                           u32 verbose);
+                           uint32_t verbose);
 
 #endif /* BNX2X_CMN_H */
index beb61b4..423d3e2 100644 (file)
 static void bnx2x_pfc_set_pfc(struct bnx2x *bp);
 static void bnx2x_dcbx_update_ets_params(struct bnx2x *bp);
 static void bnx2x_dcbx_get_ets_pri_pg_tbl(struct bnx2x *bp,
-                                         u32 *set_configuration_ets_pg,
-                                         u32 *pri_pg_tbl);
+                                         uint32_t *set_configuration_ets_pg,
+                                         uint32_t *pri_pg_tbl);
 static void bnx2x_dcbx_get_num_pg_traf_type(struct bnx2x *bp,
-                                           u32 *pg_pri_orginal_spread,
+                                           uint32_t *pg_pri_orginal_spread,
                                            struct pg_help_data *help_data);
 static void bnx2x_dcbx_fill_cos_params(struct bnx2x *bp,
                                       struct pg_help_data *help_data,
                                       struct dcbx_ets_feature *ets,
-                                      u32 *pg_pri_orginal_spread);
+                                      uint32_t *pg_pri_orginal_spread);
 static void bnx2x_dcbx_separate_pauseable_from_non(struct bnx2x *bp,
                                struct cos_help_data *cos_data,
-                               u32 *pg_pri_orginal_spread,
+                               uint32_t *pg_pri_orginal_spread,
                                struct dcbx_ets_feature *ets);
 static void bnx2x_dcbx_fw_struct(struct bnx2x *bp,
                                 struct bnx2x_func_tx_start_params*);
 
 /* helpers: read/write len bytes from addr into buff by REG_RD/REG_WR */
-static void bnx2x_read_data(struct bnx2x *bp, u32 *buff,
-                                  u32 addr, u32 len)
+static void bnx2x_read_data(struct bnx2x *bp, uint32_t *buff,
+                                  uint32_t addr, uint32_t len)
 {
        int i;
        for (i = 0; i < len; i += 4, buff++)
                *buff = REG_RD(bp, addr + i);
 }
 
-static void bnx2x_write_data(struct bnx2x *bp, u32 *buff,
-                                   u32 addr, u32 len)
+static void bnx2x_write_data(struct bnx2x *bp, uint32_t *buff,
+                                   uint32_t addr, uint32_t len)
 {
        int i;
        for (i = 0; i < len; i += 4, buff++)
@@ -63,7 +63,7 @@ static void bnx2x_write_data(struct bnx2x *bp, u32 *buff,
 static void bnx2x_pfc_set(struct bnx2x *bp)
 {
        struct bnx2x_nig_brb_pfc_port_params pfc_params = {0};
-       u32 pri_bit, val = 0;
+       uint32_t pri_bit, val = 0;
        int i;
 
        pfc_params.num_of_rx_cos_priority_mask =
@@ -117,9 +117,9 @@ static void bnx2x_pfc_clear(struct bnx2x *bp)
 
 static void  bnx2x_dump_dcbx_drv_param(struct bnx2x *bp,
                                       struct dcbx_features *features,
-                                      u32 error)
+                                      uint32_t error)
 {
-       u8 i = 0;
+       uint8_t i = 0;
        DP(NETIF_MSG_LINK, "local_mib.error %x\n", error);
 
        /* PG */
@@ -162,13 +162,13 @@ static void  bnx2x_dump_dcbx_drv_param(struct bnx2x *bp,
 }
 
 static void bnx2x_dcbx_get_ap_priority(struct bnx2x *bp,
-                                      u8 pri_bitmap,
-                                      u8 llfc_traf_type)
+                                      uint8_t pri_bitmap,
+                                      uint8_t llfc_traf_type)
 {
-       u32 pri = MAX_PFC_PRIORITIES;
-       u32 index = MAX_PFC_PRIORITIES - 1;
-       u32 pri_mask;
-       u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
+       uint32_t pri = MAX_PFC_PRIORITIES;
+       uint32_t index = MAX_PFC_PRIORITIES - 1;
+       uint32_t pri_mask;
+       uint32_t *ttp = bp->dcbx_port_params.app.traffic_type_priority;
 
        /* Choose the highest priority */
        while ((MAX_PFC_PRIORITIES == pri) && (0 != index)) {
@@ -179,14 +179,15 @@ static void bnx2x_dcbx_get_ap_priority(struct bnx2x *bp,
        }
 
        if (pri < MAX_PFC_PRIORITIES)
-               ttp[llfc_traf_type] = max_t(u32, ttp[llfc_traf_type], pri);
+               ttp[llfc_traf_type] = max_t(uint32_t, ttp[llfc_traf_type],
+                                           pri);
 }
 
 static void bnx2x_dcbx_get_ap_feature(struct bnx2x *bp,
                                   struct dcbx_app_priority_feature *app,
-                                  u32 error) {
-       u8 index;
-       u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
+                                  uint32_t error) {
+       uint8_t index;
+       uint32_t *ttp = bp->dcbx_port_params.app.traffic_type_priority;
 
        if (GET_FLAGS(error, DCBX_LOCAL_APP_ERROR))
                DP(BNX2X_MSG_DCB, "DCBX_LOCAL_APP_ERROR\n");
@@ -236,9 +237,9 @@ static void bnx2x_dcbx_get_ap_feature(struct bnx2x *bp,
 
 static void bnx2x_dcbx_get_ets_feature(struct bnx2x *bp,
                                       struct dcbx_ets_feature *ets,
-                                      u32 error) {
+                                      uint32_t error) {
        int i = 0;
-       u32 pg_pri_orginal_spread[DCBX_MAX_NUM_PG_BW_ENTRIES] = {0};
+       uint32_t pg_pri_orginal_spread[DCBX_MAX_NUM_PG_BW_ENTRIES] = {0};
        struct pg_help_data pg_help_data;
        struct bnx2x_dcbx_cos_params *cos_params =
                        bp->dcbx_port_params.ets.cos_params;
@@ -287,7 +288,8 @@ static void bnx2x_dcbx_get_ets_feature(struct bnx2x *bp,
 }
 
 static void  bnx2x_dcbx_get_pfc_feature(struct bnx2x *bp,
-                                       struct dcbx_pfc_feature *pfc, u32 error)
+                                       struct dcbx_pfc_feature *pfc,
+                                       uint32_t error)
 {
        if (GET_FLAGS(error, DCBX_LOCAL_PFC_ERROR))
                DP(BNX2X_MSG_DCB, "DCBX_LOCAL_PFC_ERROR\n");
@@ -311,9 +313,9 @@ static void  bnx2x_dcbx_get_pfc_feature(struct bnx2x *bp,
 static void bnx2x_dcbx_map_nw(struct bnx2x *bp)
 {
        int i;
-       u32 unmapped = (1 << MAX_PFC_PRIORITIES) - 1; /* all ones */
-       u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
-       u32 nw_prio = 1 << ttp[LLFC_TRAFFIC_TYPE_NW];
+       uint32_t unmapped = (1 << MAX_PFC_PRIORITIES) - 1; /* all ones */
+       uint32_t *ttp = bp->dcbx_port_params.app.traffic_type_priority;
+       uint32_t nw_prio = 1 << ttp[LLFC_TRAFFIC_TYPE_NW];
        struct bnx2x_dcbx_cos_params *cos_params =
                        bp->dcbx_port_params.ets.cos_params;
 
@@ -335,7 +337,7 @@ static void bnx2x_dcbx_map_nw(struct bnx2x *bp)
 
 static void bnx2x_get_dcbx_drv_param(struct bnx2x *bp,
                                     struct dcbx_features *features,
-                                    u32 error)
+                                    uint32_t error)
 {
        bnx2x_dcbx_get_ap_feature(bp, &features->app, error);
 
@@ -348,12 +350,12 @@ static void bnx2x_get_dcbx_drv_param(struct bnx2x *bp,
 
 #define DCBX_LOCAL_MIB_MAX_TRY_READ            (100)
 static int bnx2x_dcbx_read_mib(struct bnx2x *bp,
-                              u32 *base_mib_addr,
-                              u32 offset,
+                              uint32_t *base_mib_addr,
+                              uint32_t offset,
                               int read_mib_type)
 {
        int max_try_read = 0;
-       u32 mib_size, prefix_seq_num, suffix_seq_num;
+       uint32_t mib_size, prefix_seq_num, suffix_seq_num;
        struct lldp_remote_mib *remote_mib ;
        struct lldp_local_mib  *local_mib;
 
@@ -498,8 +500,8 @@ static void bnx2x_dcbx_2cos_limit_update_ets_config(struct bnx2x *bp)
        /* If we join a group and there is bw_tbl and strict then bw rules */
        if ((DCBX_INVALID_COS_BW != ets->cos_params[0].bw_tbl) &&
            (DCBX_INVALID_COS_BW != ets->cos_params[1].bw_tbl)) {
-               u32 bw_tbl_0 = ets->cos_params[0].bw_tbl;
-               u32 bw_tbl_1 = ets->cos_params[1].bw_tbl;
+               uint32_t bw_tbl_0 = ets->cos_params[0].bw_tbl;
+               uint32_t bw_tbl_1 = ets->cos_params[1].bw_tbl;
                /* Do not allow 0-100 configuration
                 * since PBF does not support it
                 * force 1-99 instead
@@ -531,7 +533,7 @@ static void bnx2x_dcbx_update_ets_config(struct bnx2x *bp)
 {
        struct bnx2x_dcbx_pg_params *ets = &(bp->dcbx_port_params.ets);
        struct bnx2x_ets_params ets_params = { 0 };
-       u8 i;
+       uint8_t i;
 
        ets_params.num_of_cos = ets->num_of_cos;
 
@@ -553,7 +555,7 @@ static void bnx2x_dcbx_update_ets_config(struct bnx2x *bp)
                        }
                        ets_params.cos[i].state = bnx2x_cos_state_bw;
                        ets_params.cos[i].params.bw_params.bw =
-                                               (u8)ets->cos_params[i].bw_tbl;
+                                               (uint8_t)ets->cos_params[i].bw_tbl;
                }
        }
 
@@ -587,7 +589,7 @@ static void bnx2x_dcbx_update_ets_params(struct bnx2x *bp)
 static int bnx2x_dcbx_read_shmem_remote_mib(struct bnx2x *bp)
 {
        struct lldp_remote_mib remote_mib = {0};
-       u32 dcbx_remote_mib_offset = SHMEM2_RD(bp, dcbx_remote_mib_offset);
+       uint32_t dcbx_remote_mib_offset = SHMEM2_RD(bp, dcbx_remote_mib_offset);
        int rc;
 
        DP(BNX2X_MSG_DCB, "dcbx_remote_mib_offset 0x%x\n",
@@ -598,7 +600,8 @@ static int bnx2x_dcbx_read_shmem_remote_mib(struct bnx2x *bp)
                return -EINVAL;
        }
 
-       rc = bnx2x_dcbx_read_mib(bp, (u32 *)&remote_mib, dcbx_remote_mib_offset,
+       rc = bnx2x_dcbx_read_mib(bp, (uint32_t *)&remote_mib,
+                                dcbx_remote_mib_offset,
                                 DCBX_READ_REMOTE_MIB);
 
        if (rc) {
@@ -616,7 +619,7 @@ static int bnx2x_dcbx_read_shmem_remote_mib(struct bnx2x *bp)
 static int bnx2x_dcbx_read_shmem_neg_results(struct bnx2x *bp)
 {
        struct lldp_local_mib local_mib = {0};
-       u32 dcbx_neg_res_offset = SHMEM2_RD(bp, dcbx_neg_res_offset);
+       uint32_t dcbx_neg_res_offset = SHMEM2_RD(bp, dcbx_neg_res_offset);
        int rc;
 
        DP(BNX2X_MSG_DCB, "dcbx_neg_res_offset 0x%x\n", dcbx_neg_res_offset);
@@ -626,7 +629,8 @@ static int bnx2x_dcbx_read_shmem_neg_results(struct bnx2x *bp)
                return -EINVAL;
        }
 
-       rc = bnx2x_dcbx_read_mib(bp, (u32 *)&local_mib, dcbx_neg_res_offset,
+       rc = bnx2x_dcbx_read_mib(bp, (uint32_t *)&local_mib,
+                                dcbx_neg_res_offset,
                                 DCBX_READ_LOCAL_MIB);
 
        if (rc) {
@@ -642,9 +646,9 @@ static int bnx2x_dcbx_read_shmem_neg_results(struct bnx2x *bp)
 
 #ifdef BCM_DCBNL
 static inline
-u8 bnx2x_dcbx_dcbnl_app_up(struct dcbx_app_priority_entry *ent)
+uint8_t bnx2x_dcbx_dcbnl_app_up(struct dcbx_app_priority_entry *ent)
 {
-       u8 pri;
+       uint8_t pri;
 
        /* Choose the highest priority */
        for (pri = MAX_PFC_PRIORITIES - 1; pri > 0; pri--)
@@ -654,7 +658,7 @@ u8 bnx2x_dcbx_dcbnl_app_up(struct dcbx_app_priority_entry *ent)
 }
 
 static inline
-u8 bnx2x_dcbx_dcbnl_app_idtype(struct dcbx_app_priority_entry *ent)
+uint8_t bnx2x_dcbx_dcbnl_app_idtype(struct dcbx_app_priority_entry *ent)
 {
        return ((ent->appBitfield & DCBX_APP_ENTRY_SF_MASK) ==
                DCBX_APP_SF_PORT) ? DCB_APP_IDTYPE_PORTNUM :
@@ -670,7 +674,7 @@ int bnx2x_dcbnl_update_applist(struct bnx2x *bp, bool delall)
                        &bp->dcbx_local_feat.app.app_pri_tbl[i];
 
                if (ent->appBitfield & DCBX_APP_ENTRY_VALID) {
-                       u8 up = bnx2x_dcbx_dcbnl_app_up(ent);
+                       uint8_t up = bnx2x_dcbx_dcbnl_app_up(ent);
 
                        /* avoid invalid user-priority */
                        if (up) {
@@ -688,7 +692,7 @@ int bnx2x_dcbnl_update_applist(struct bnx2x *bp, bool delall)
 
 static inline void bnx2x_dcbx_update_tc_mapping(struct bnx2x *bp)
 {
-       u8 prio, cos;
+       uint8_t prio, cos;
        for (cos = 0; cos < bp->dcbx_port_params.ets.num_of_cos; cos++) {
                for (prio = 0; prio < BNX2X_MAX_PRIORITY; prio++) {
                        if (bp->dcbx_port_params.ets.cos_params[cos].pri_bitmask
@@ -707,7 +711,7 @@ static inline void bnx2x_dcbx_update_tc_mapping(struct bnx2x *bp)
        bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_SETUP_TC, 0);
 }
 
-void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state)
+void bnx2x_dcbx_set_params(struct bnx2x *bp, uint32_t state)
 {
        switch (state) {
        case BNX2X_DCBX_STATE_NEG_RECEIVED:
@@ -788,11 +792,11 @@ void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state)
                                      BP_PORT(bp)*sizeof(struct lldp_admin_mib))
 
 static void bnx2x_dcbx_admin_mib_updated_params(struct bnx2x *bp,
-                               u32 dcbx_lldp_params_offset)
+                               uint32_t dcbx_lldp_params_offset)
 {
        struct lldp_admin_mib admin_mib;
-       u32 i, other_traf_type = PREDEFINED_APP_IDX_MAX, traf_type = 0;
-       u32 offset = dcbx_lldp_params_offset + LLDP_ADMIN_MIB_OFFSET(bp);
+       uint32_t i, other_traf_type = PREDEFINED_APP_IDX_MAX, traf_type = 0;
+       uint32_t offset = dcbx_lldp_params_offset + LLDP_ADMIN_MIB_OFFSET(bp);
 
        /*shortcuts*/
        struct dcbx_features *af = &admin_mib.features;
@@ -801,7 +805,7 @@ static void bnx2x_dcbx_admin_mib_updated_params(struct bnx2x *bp,
        memset(&admin_mib, 0, sizeof(struct lldp_admin_mib));
 
        /* Read the data first */
-       bnx2x_read_data(bp, (u32 *)&admin_mib, offset,
+       bnx2x_read_data(bp, (uint32_t *)&admin_mib, offset,
                        sizeof(struct lldp_admin_mib));
 
        if (bp->dcbx_enabled == BNX2X_DCBX_ENABLED_ON_NEG_ON)
@@ -816,9 +820,9 @@ static void bnx2x_dcbx_admin_mib_updated_params(struct bnx2x *bp,
                        (dp->admin_dcbx_version << DCBX_CEE_VERSION_SHIFT) &
                         DCBX_CEE_VERSION_MASK;
 
-               af->ets.enabled = (u8)dp->admin_ets_enable;
+               af->ets.enabled = (uint8_t)dp->admin_ets_enable;
 
-               af->pfc.enabled = (u8)dp->admin_pfc_enable;
+               af->pfc.enabled = (uint8_t)dp->admin_pfc_enable;
 
                /* FOR IEEE dp->admin_tc_supported_tx_enable */
                if (dp->admin_ets_configuration_tx_enable)
@@ -859,7 +863,7 @@ static void bnx2x_dcbx_admin_mib_updated_params(struct bnx2x *bp,
 
                for (i = 0 ; i < DCBX_MAX_NUM_PG_BW_ENTRIES; i++) {
                        DCBX_PG_BW_SET(af->ets.pg_bw_tbl, i,
-                               (u8)dp->admin_configuration_bw_precentage[i]);
+                               (uint8_t)dp->admin_configuration_bw_precentage[i]);
 
                        DP(BNX2X_MSG_DCB, "pg_bw_tbl[%d] = %02x\n",
                           i, DCBX_PG_BW_GET(af->ets.pg_bw_tbl, i));
@@ -867,7 +871,7 @@ static void bnx2x_dcbx_admin_mib_updated_params(struct bnx2x *bp,
 
                for (i = 0; i < DCBX_MAX_NUM_PRI_PG_ENTRIES; i++) {
                        DCBX_PRI_PG_SET(af->ets.pri_pg_tbl, i,
-                                       (u8)dp->admin_configuration_ets_pg[i]);
+                                       (uint8_t)dp->admin_configuration_ets_pg[i]);
 
                        DP(BNX2X_MSG_DCB, "pri_pg_tbl[%d] = %02x\n",
                           i, DCBX_PRI_PG_GET(af->ets.pri_pg_tbl, i));
@@ -875,7 +879,7 @@ static void bnx2x_dcbx_admin_mib_updated_params(struct bnx2x *bp,
 
                /*For IEEE admin_recommendation_bw_percentage
                 *For IEEE admin_recommendation_ets_pg */
-               af->pfc.pri_en_bitmap = (u8)dp->admin_pfc_bitmap;
+               af->pfc.pri_en_bitmap = (uint8_t)dp->admin_pfc_bitmap;
                for (i = 0; i < DCBX_CONFIG_MAX_APP_PROTOCOL; i++) {
                        if (dp->admin_priority_app_table[i].valid) {
                                struct bnx2x_admin_priority_app_table *table =
@@ -893,7 +897,7 @@ static void bnx2x_dcbx_admin_mib_updated_params(struct bnx2x *bp,
                                        table[i].app_id;
 
                                af->app.app_pri_tbl[traf_type].pri_bitmap =
-                                       (u8)(1 << table[i].priority);
+                                       (uint8_t)(1 << table[i].priority);
 
                                af->app.app_pri_tbl[traf_type].appBitfield =
                                    (DCBX_APP_ENTRY_VALID);
@@ -904,15 +908,16 @@ static void bnx2x_dcbx_admin_mib_updated_params(struct bnx2x *bp,
                        }
                }
 
-               af->app.default_pri = (u8)dp->admin_default_priority;
+               af->app.default_pri = (uint8_t)dp->admin_default_priority;
        }
 
        /* Write the data. */
-       bnx2x_write_data(bp, (u32 *)&admin_mib, offset,
+       bnx2x_write_data(bp, (uint32_t *)&admin_mib, offset,
                         sizeof(struct lldp_admin_mib));
 }
 
-void bnx2x_dcbx_set_state(struct bnx2x *bp, bool dcb_on, u32 dcbx_enabled)
+void bnx2x_dcbx_set_state(struct bnx2x *bp, bool dcb_on,
+                         uint32_t dcbx_enabled)
 {
        if (!CHIP_IS_E1x(bp)) {
                bp->dcb_state = dcb_on;
@@ -985,7 +990,7 @@ void bnx2x_dcbx_init_params(struct bnx2x *bp)
 
 void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem)
 {
-       u32 dcbx_lldp_params_offset = SHMEM_LLDP_DCBX_PARAMS_NONE;
+       uint32_t dcbx_lldp_params_offset = SHMEM_LLDP_DCBX_PARAMS_NONE;
 
        /* only PMF can send ADMIN msg to MFW in old MFW versions */
        if ((!bp->port.pmf) && (!(bp->flags & BC_SUPPORTS_DCBX_MSG_NON_PMF)))
@@ -1037,8 +1042,8 @@ static void
 bnx2x_dcbx_print_cos_params(struct bnx2x *bp,
                            struct bnx2x_func_tx_start_params *pfc_fw_cfg)
 {
-       u8 pri = 0;
-       u8 cos = 0;
+       uint8_t pri = 0;
+       uint8_t cos = 0;
 
        DP(BNX2X_MSG_DCB,
           "pfc_fw_cfg->dcb_version %x\n", pfc_fw_cfg->dcb_version);
@@ -1077,12 +1082,12 @@ bnx2x_dcbx_print_cos_params(struct bnx2x *bp,
 
 /* fills help_data according to pg_info */
 static void bnx2x_dcbx_get_num_pg_traf_type(struct bnx2x *bp,
-                                           u32 *pg_pri_orginal_spread,
+                                           uint32_t *pg_pri_orginal_spread,
                                            struct pg_help_data *help_data)
 {
        bool pg_found  = false;
-       u32 i, traf_type, add_traf_type, add_pg;
-       u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
+       uint32_t i, traf_type, add_traf_type, add_pg;
+       uint32_t *ttp = bp->dcbx_port_params.app.traffic_type_priority;
        struct pg_entry_help_data *data = help_data->data; /*shortcut*/
 
        /* Set to invalid */
@@ -1093,7 +1098,7 @@ static void bnx2x_dcbx_get_num_pg_traf_type(struct bnx2x *bp,
             add_traf_type < LLFC_DRIVER_TRAFFIC_TYPE_MAX; add_traf_type++) {
                pg_found = false;
                if (ttp[add_traf_type] < MAX_PFC_PRIORITIES) {
-                       add_pg = (u8)pg_pri_orginal_spread[ttp[add_traf_type]];
+                       add_pg = (uint8_t)pg_pri_orginal_spread[ttp[add_traf_type]];
                        for (traf_type = 0;
                             traf_type < LLFC_DRIVER_TRAFFIC_TYPE_MAX;
                             traf_type++) {
@@ -1125,7 +1130,7 @@ static void bnx2x_dcbx_get_num_pg_traf_type(struct bnx2x *bp,
 
 static void bnx2x_dcbx_ets_disabled_entry_data(struct bnx2x *bp,
                                               struct cos_help_data *cos_data,
-                                              u32 pri_join_mask)
+                                              uint32_t pri_join_mask)
 {
        /* Only one priority than only one COS */
        cos_data->data[0].pausable =
@@ -1137,7 +1142,7 @@ static void bnx2x_dcbx_ets_disabled_entry_data(struct bnx2x *bp,
 
 static inline void bnx2x_dcbx_add_to_cos_bw(struct bnx2x *bp,
                                            struct cos_entry_help_data *data,
-                                           u8 pg_bw)
+                                           uint8_t pg_bw)
 {
        if (data->cos_bw == DCBX_INVALID_COS_BW)
                data->cos_bw = pg_bw;
@@ -1147,14 +1152,14 @@ static inline void bnx2x_dcbx_add_to_cos_bw(struct bnx2x *bp,
 
 static void bnx2x_dcbx_separate_pauseable_from_non(struct bnx2x *bp,
                        struct cos_help_data *cos_data,
-                       u32 *pg_pri_orginal_spread,
+                       uint32_t *pg_pri_orginal_spread,
                        struct dcbx_ets_feature *ets)
 {
-       u32     pri_tested      = 0;
-       u8      i               = 0;
-       u8      entry           = 0;
-       u8      pg_entry        = 0;
-       u8      num_of_pri      = LLFC_DRIVER_TRAFFIC_TYPE_MAX;
+       uint32_t        pri_tested      = 0;
+       uint8_t i               = 0;
+       uint8_t entry           = 0;
+       uint8_t pg_entry        = 0;
+       uint8_t num_of_pri      = LLFC_DRIVER_TRAFFIC_TYPE_MAX;
 
        cos_data->data[0].pausable = true;
        cos_data->data[1].pausable = false;
@@ -1171,7 +1176,7 @@ static void bnx2x_dcbx_separate_pauseable_from_non(struct bnx2x *bp,
                        cos_data->data[0].pri_join_mask |= pri_tested;
                        entry = 0;
                }
-               pg_entry = (u8)pg_pri_orginal_spread[bp->dcbx_port_params.
+               pg_entry = (uint8_t)pg_pri_orginal_spread[bp->dcbx_port_params.
                                                app.traffic_type_priority[i]];
                /* There can be only one strict pg */
                if (pg_entry < DCBX_MAX_NUM_PG_BW_ENTRIES)
@@ -1196,13 +1201,13 @@ static void bnx2x_dcbx_separate_pauseable_from_non(struct bnx2x *bp,
 static void bnx2x_dcbx_2cos_limit_cee_single_pg_to_cos_params(struct bnx2x *bp,
                                              struct pg_help_data *pg_help_data,
                                              struct cos_help_data *cos_data,
-                                             u32 pri_join_mask,
-                                             u8 num_of_dif_pri)
+                                             uint32_t pri_join_mask,
+                                             uint8_t num_of_dif_pri)
 {
-       u8 i = 0;
-       u32 pri_tested = 0;
-       u32 pri_mask_without_pri = 0;
-       u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
+       uint8_t i = 0;
+       uint32_t pri_tested = 0;
+       uint32_t pri_mask_without_pri = 0;
+       uint32_t *ttp = bp->dcbx_port_params.app.traffic_type_priority;
        /*debug*/
        if (num_of_dif_pri == 1) {
                bnx2x_dcbx_ets_disabled_entry_data(bp, cos_data, pri_join_mask);
@@ -1252,7 +1257,7 @@ static void bnx2x_dcbx_2cos_limit_cee_single_pg_to_cos_params(struct bnx2x *bp,
                        cos_data->data[0].pausable = true;
                        /* All priorities except FCOE */
                        cos_data->data[0].pri_join_mask = (pri_join_mask &
-                               ((u8)~(1 << ttp[LLFC_TRAFFIC_TYPE_FCOE])));
+                               ((uint8_t)~(1 << ttp[LLFC_TRAFFIC_TYPE_FCOE])));
                        /* Only FCOE priority.*/
                        cos_data->data[1].pri_join_mask =
                                (1 << ttp[LLFC_TRAFFIC_TYPE_FCOE]);
@@ -1303,7 +1308,7 @@ static void bnx2x_dcbx_2cos_limit_cee_single_pg_to_cos_params(struct bnx2x *bp,
                                        app.traffic_type_priority[i];
                                /* Remove priority tested */
                                pri_mask_without_pri =
-                                       (pri_join_mask & ((u8)(~pri_tested)));
+                                       (pri_join_mask & ((uint8_t)(~pri_tested)));
                                if (pri_mask_without_pri < pri_tested)
                                        break;
                        }
@@ -1331,12 +1336,12 @@ static void bnx2x_dcbx_2cos_limit_cee_two_pg_to_cos_params(
                            struct  pg_help_data        *pg_help_data,
                            struct dcbx_ets_feature     *ets,
                            struct cos_help_data        *cos_data,
-                           u32                 *pg_pri_orginal_spread,
-                           u32                         pri_join_mask,
-                           u8                          num_of_dif_pri)
+                           uint32_t                    *pg_pri_orginal_spread,
+                           uint32_t                            pri_join_mask,
+                           uint8_t                             num_of_dif_pri)
 {
-       u8 i = 0;
-       u8 pg[DCBX_COS_MAX_NUM_E2] = { 0 };
+       uint8_t i = 0;
+       uint8_t pg[DCBX_COS_MAX_NUM_E2] = { 0 };
 
        /* If there are both pauseable and non-pauseable priorities,
         * the pauseable priorities go to the first queue and
@@ -1406,11 +1411,11 @@ static int bnx2x_dcbx_join_pgs(
                              struct bnx2x            *bp,
                              struct dcbx_ets_feature *ets,
                              struct pg_help_data     *pg_help_data,
-                             u8                      required_num_of_pg)
+                             uint8_t                      required_num_of_pg)
 {
-       u8 entry_joined    = pg_help_data->num_of_pg - 1;
-       u8 entry_removed   = entry_joined + 1;
-       u8 pg_joined       = 0;
+       uint8_t entry_joined    = pg_help_data->num_of_pg - 1;
+       uint8_t entry_removed   = entry_joined + 1;
+       uint8_t pg_joined       = 0;
 
        if (required_num_of_pg == 0 || ARRAY_SIZE(pg_help_data->data)
                                                <= pg_help_data->num_of_pg) {
@@ -1458,16 +1463,16 @@ static void bnx2x_dcbx_2cos_limit_cee_three_pg_to_cos_params(
                              struct pg_help_data       *pg_help_data,
                              struct dcbx_ets_feature   *ets,
                              struct cos_help_data      *cos_data,
-                             u32                       *pg_pri_orginal_spread,
-                             u32                       pri_join_mask,
-                             u8                        num_of_dif_pri)
-{
-       u8 i = 0;
-       u32 pri_tested = 0;
-       u8 entry = 0;
-       u8 pg_entry = 0;
+                             uint32_t                  *pg_pri_orginal_spread,
+                             uint32_t                  pri_join_mask,
+                             uint8_t                   num_of_dif_pri)
+{
+       uint8_t i = 0;
+       uint32_t pri_tested = 0;
+       uint8_t entry = 0;
+       uint8_t pg_entry = 0;
        bool b_found_strict = false;
-       u8 num_of_pri = LLFC_DRIVER_TRAFFIC_TYPE_MAX;
+       uint8_t num_of_pri = LLFC_DRIVER_TRAFFIC_TYPE_MAX;
 
        cos_data->data[0].pri_join_mask = cos_data->data[1].pri_join_mask = 0;
        /* If there are both pauseable and non-pauseable priorities,
@@ -1501,7 +1506,7 @@ static void bnx2x_dcbx_2cos_limit_cee_three_pg_to_cos_params(
                for (i = 0 ; i < num_of_pri; i++) {
                        pri_tested = 1 << bp->dcbx_port_params.
                                app.traffic_type_priority[i];
-                       pg_entry = (u8)pg_pri_orginal_spread[bp->
+                       pg_entry = (uint8_t)pg_pri_orginal_spread[bp->
                                dcbx_port_params.app.traffic_type_priority[i]];
 
                        if (pg_entry < DCBX_MAX_NUM_PG_BW_ENTRIES) {
@@ -1537,9 +1542,9 @@ static void bnx2x_dcbx_2cos_limit_cee_fill_cos_params(struct bnx2x *bp,
                                       struct pg_help_data *help_data,
                                       struct dcbx_ets_feature *ets,
                                       struct cos_help_data *cos_data,
-                                      u32 *pg_pri_orginal_spread,
-                                      u32 pri_join_mask,
-                                      u8 num_of_dif_pri)
+                                      uint32_t *pg_pri_orginal_spread,
+                                      uint32_t pri_join_mask,
+                                      uint8_t num_of_dif_pri)
 {
        /* default E2 settings */
        cos_data->num_of_cos = DCBX_COS_MAX_NUM_E2;
@@ -1583,13 +1588,13 @@ static void bnx2x_dcbx_2cos_limit_cee_fill_cos_params(struct bnx2x *bp,
 
 static int bnx2x_dcbx_spread_strict_pri(struct bnx2x *bp,
                                        struct cos_help_data *cos_data,
-                                       u8 entry,
-                                       u8 num_spread_of_entries,
-                                       u8 strict_app_pris)
+                                       uint8_t entry,
+                                       uint8_t num_spread_of_entries,
+                                       uint8_t strict_app_pris)
 {
-       u8 strict_pri = BNX2X_DCBX_STRICT_COS_HIGHEST;
-       u8 num_of_app_pri = MAX_PFC_PRIORITIES;
-       u8 app_pri_bit = 0;
+       uint8_t strict_pri = BNX2X_DCBX_STRICT_COS_HIGHEST;
+       uint8_t num_of_app_pri = MAX_PFC_PRIORITIES;
+       uint8_t app_pri_bit = 0;
 
        while (num_spread_of_entries && num_of_app_pri > 0) {
                app_pri_bit = 1 << (num_of_app_pri - 1);
@@ -1630,11 +1635,11 @@ static int bnx2x_dcbx_spread_strict_pri(struct bnx2x *bp,
        return 0;
 }
 
-static u8 bnx2x_dcbx_cee_fill_strict_pri(struct bnx2x *bp,
+static uint8_t bnx2x_dcbx_cee_fill_strict_pri(struct bnx2x *bp,
                                         struct cos_help_data *cos_data,
-                                        u8 entry,
-                                        u8 num_spread_of_entries,
-                                        u8 strict_app_pris)
+                                        uint8_t entry,
+                                        uint8_t num_spread_of_entries,
+                                        uint8_t strict_app_pris)
 {
        if (bnx2x_dcbx_spread_strict_pri(bp, cos_data, entry,
                                         num_spread_of_entries,
@@ -1657,12 +1662,12 @@ static void bnx2x_dcbx_cee_fill_cos_params(struct bnx2x *bp,
                                           struct pg_help_data *help_data,
                                           struct dcbx_ets_feature *ets,
                                           struct cos_help_data *cos_data,
-                                          u32 pri_join_mask)
+                                          uint32_t pri_join_mask)
 
 {
-       u8 need_num_of_entries = 0;
-       u8 i = 0;
-       u8 entry = 0;
+       uint8_t need_num_of_entries = 0;
+       uint8_t i = 0;
+       uint8_t entry = 0;
 
        /*
         * if the number of requested PG-s in CEE is greater than 3
@@ -1693,9 +1698,9 @@ static void bnx2x_dcbx_cee_fill_cos_params(struct bnx2x *bp,
 
                        entry++;
                } else {
-                       need_num_of_entries =  min_t(u8,
-                               (u8)pg->num_of_dif_pri,
-                               (u8)DCBX_COS_MAX_NUM_E3B0 -
+                       need_num_of_entries =  min_t(uint8_t,
+                               (uint8_t)pg->num_of_dif_pri,
+                               (uint8_t)DCBX_COS_MAX_NUM_E3B0 -
                                                 help_data->num_of_pg + 1);
                        /*
                         * If there are still VOQ-s which have no associated PG,
@@ -1713,12 +1718,12 @@ static void bnx2x_dcbx_cee_fill_cos_params(struct bnx2x *bp,
 static void bnx2x_dcbx_fill_cos_params(struct bnx2x *bp,
                                       struct pg_help_data *help_data,
                                       struct dcbx_ets_feature *ets,
-                                      u32 *pg_pri_orginal_spread)
+                                      uint32_t *pg_pri_orginal_spread)
 {
        struct cos_help_data         cos_data;
-       u8                    i                           = 0;
-       u32                   pri_join_mask               = 0;
-       u8                    num_of_dif_pri              = 0;
+       uint8_t                    i                           = 0;
+       uint32_t                   pri_join_mask               = 0;
+       uint8_t                    num_of_dif_pri              = 0;
 
        memset(&cos_data, 0, sizeof(cos_data));
 
@@ -1796,8 +1801,8 @@ static void bnx2x_dcbx_fill_cos_params(struct bnx2x *bp,
 }
 
 static void bnx2x_dcbx_get_ets_pri_pg_tbl(struct bnx2x *bp,
-                               u32 *set_configuration_ets_pg,
-                               u32 *pri_pg_tbl)
+                               uint32_t *set_configuration_ets_pg,
+                               uint32_t *pri_pg_tbl)
 {
        int i;
 
@@ -1812,10 +1817,10 @@ static void bnx2x_dcbx_get_ets_pri_pg_tbl(struct bnx2x *bp,
 static void bnx2x_dcbx_fw_struct(struct bnx2x *bp,
                                 struct bnx2x_func_tx_start_params *pfc_fw_cfg)
 {
-       u16 pri_bit = 0;
-       u8 cos = 0, pri = 0;
+       uint16_t pri_bit = 0;
+       uint8_t cos = 0, pri = 0;
        struct priority_cos *tt2cos;
-       u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
+       uint32_t *ttp = bp->dcbx_port_params.app.traffic_type_priority;
        int mfw_configured = SHMEM2_HAS(bp, drv_flags) &&
                             GET_FLAGS(SHMEM2_RD(bp, drv_flags),
                                       1 << DRV_FLAGS_DCB_MFW_CONFIGURED);
@@ -1899,14 +1904,14 @@ static inline bool bnx2x_dcbnl_set_valid(struct bnx2x *bp)
        return bp->dcb_state && bp->dcbx_mode_uset;
 }
 
-static u8 bnx2x_dcbnl_get_state(struct net_device *netdev)
+static uint8_t bnx2x_dcbnl_get_state(struct net_device *netdev)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "state = %d\n", bp->dcb_state);
        return bp->dcb_state;
 }
 
-static u8 bnx2x_dcbnl_set_state(struct net_device *netdev, u8 state)
+static uint8_t bnx2x_dcbnl_set_state(struct net_device *netdev, uint8_t state)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "state = %s\n", state ? "on" : "off");
@@ -1923,7 +1928,7 @@ static u8 bnx2x_dcbnl_set_state(struct net_device *netdev, u8 state)
 }
 
 static void bnx2x_dcbnl_get_perm_hw_addr(struct net_device *netdev,
-                                        u8 *perm_addr)
+                                        uint8_t *perm_addr)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "GET-PERM-ADDR\n");
@@ -1938,8 +1943,9 @@ static void bnx2x_dcbnl_get_perm_hw_addr(struct net_device *netdev,
 }
 
 static void bnx2x_dcbnl_set_pg_tccfg_tx(struct net_device *netdev, int prio,
-                                       u8 prio_type, u8 pgid, u8 bw_pct,
-                                       u8 up_map)
+                                       uint8_t prio_type, uint8_t pgid,
+                                       uint8_t bw_pct,
+                                       uint8_t up_map)
 {
        struct bnx2x *bp = netdev_priv(netdev);
 
@@ -1965,7 +1971,7 @@ static void bnx2x_dcbnl_set_pg_tccfg_tx(struct net_device *netdev, int prio,
 }
 
 static void bnx2x_dcbnl_set_pg_bwgcfg_tx(struct net_device *netdev,
-                                        int pgid, u8 bw_pct)
+                                        int pgid, uint8_t bw_pct)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "pgid[%d] = %d\n", pgid, bw_pct);
@@ -1978,23 +1984,25 @@ static void bnx2x_dcbnl_set_pg_bwgcfg_tx(struct net_device *netdev,
 }
 
 static void bnx2x_dcbnl_set_pg_tccfg_rx(struct net_device *netdev, int prio,
-                                       u8 prio_type, u8 pgid, u8 bw_pct,
-                                       u8 up_map)
+                                       uint8_t prio_type, uint8_t pgid,
+                                       uint8_t bw_pct,
+                                       uint8_t up_map)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "Nothing to set; No RX support\n");
 }
 
 static void bnx2x_dcbnl_set_pg_bwgcfg_rx(struct net_device *netdev,
-                                        int pgid, u8 bw_pct)
+                                        int pgid, uint8_t bw_pct)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "Nothing to set; No RX support\n");
 }
 
 static void bnx2x_dcbnl_get_pg_tccfg_tx(struct net_device *netdev, int prio,
-                                       u8 *prio_type, u8 *pgid, u8 *bw_pct,
-                                       u8 *up_map)
+                                       uint8_t *prio_type, uint8_t *pgid,
+                                       uint8_t *bw_pct,
+                                       uint8_t *up_map)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "prio = %d\n", prio);
@@ -2020,7 +2028,7 @@ static void bnx2x_dcbnl_get_pg_tccfg_tx(struct net_device *netdev, int prio,
 }
 
 static void bnx2x_dcbnl_get_pg_bwgcfg_tx(struct net_device *netdev,
-                                        int pgid, u8 *bw_pct)
+                                        int pgid, uint8_t *bw_pct)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "pgid = %d\n", pgid);
@@ -2034,8 +2042,9 @@ static void bnx2x_dcbnl_get_pg_bwgcfg_tx(struct net_device *netdev,
 }
 
 static void bnx2x_dcbnl_get_pg_tccfg_rx(struct net_device *netdev, int prio,
-                                       u8 *prio_type, u8 *pgid, u8 *bw_pct,
-                                       u8 *up_map)
+                                       uint8_t *prio_type, uint8_t *pgid,
+                                       uint8_t *bw_pct,
+                                       uint8_t *up_map)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "Nothing to get; No RX support\n");
@@ -2044,7 +2053,7 @@ static void bnx2x_dcbnl_get_pg_tccfg_rx(struct net_device *netdev, int prio,
 }
 
 static void bnx2x_dcbnl_get_pg_bwgcfg_rx(struct net_device *netdev,
-                                        int pgid, u8 *bw_pct)
+                                        int pgid, uint8_t *bw_pct)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "Nothing to get; No RX support\n");
@@ -2053,7 +2062,7 @@ static void bnx2x_dcbnl_get_pg_bwgcfg_rx(struct net_device *netdev,
 }
 
 static void bnx2x_dcbnl_set_pfc_cfg(struct net_device *netdev, int prio,
-                                   u8 setting)
+                                   uint8_t setting)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "prio[%d] = %d\n", prio, setting);
@@ -2070,7 +2079,7 @@ static void bnx2x_dcbnl_set_pfc_cfg(struct net_device *netdev, int prio,
 }
 
 static void bnx2x_dcbnl_get_pfc_cfg(struct net_device *netdev, int prio,
-                                   u8 *setting)
+                                   uint8_t *setting)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "prio = %d\n", prio);
@@ -2083,7 +2092,7 @@ static void bnx2x_dcbnl_get_pfc_cfg(struct net_device *netdev, int prio,
        *setting = (bp->dcbx_local_feat.pfc.pri_en_bitmap >> prio) & 0x1;
 }
 
-static u8 bnx2x_dcbnl_set_all(struct net_device *netdev)
+static uint8_t bnx2x_dcbnl_set_all(struct net_device *netdev)
 {
        struct bnx2x *bp = netdev_priv(netdev);
 
@@ -2108,10 +2117,11 @@ static u8 bnx2x_dcbnl_set_all(struct net_device *netdev)
        return 0;
 }
 
-static u8 bnx2x_dcbnl_get_cap(struct net_device *netdev, int capid, u8 *cap)
+static uint8_t bnx2x_dcbnl_get_cap(struct net_device *netdev, int capid,
+                                  uint8_t *cap)
 {
        struct bnx2x *bp = netdev_priv(netdev);
-       u8 rval = 0;
+       uint8_t rval = 0;
 
        if (bp->dcb_state) {
                switch (capid) {
@@ -2153,10 +2163,11 @@ static u8 bnx2x_dcbnl_get_cap(struct net_device *netdev, int capid, u8 *cap)
        return rval;
 }
 
-static int bnx2x_dcbnl_get_numtcs(struct net_device *netdev, int tcid, u8 *num)
+static int bnx2x_dcbnl_get_numtcs(struct net_device *netdev, int tcid,
+                                 uint8_t *num)
 {
        struct bnx2x *bp = netdev_priv(netdev);
-       u8 rval = 0;
+       uint8_t rval = 0;
 
        DP(BNX2X_MSG_DCB, "tcid %d\n", tcid);
 
@@ -2183,14 +2194,15 @@ static int bnx2x_dcbnl_get_numtcs(struct net_device *netdev, int tcid, u8 *num)
        return rval;
 }
 
-static int bnx2x_dcbnl_set_numtcs(struct net_device *netdev, int tcid, u8 num)
+static int bnx2x_dcbnl_set_numtcs(struct net_device *netdev, int tcid,
+                                 uint8_t num)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "num tcs = %d; Not supported\n", num);
        return -EINVAL;
 }
 
-static u8 bnx2x_dcbnl_get_pfc_state(struct net_device *netdev)
+static uint8_t bnx2x_dcbnl_get_pfc_state(struct net_device *netdev)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "state = %d\n", bp->dcbx_local_feat.pfc.enabled);
@@ -2201,7 +2213,8 @@ static u8 bnx2x_dcbnl_get_pfc_state(struct net_device *netdev)
        return bp->dcbx_local_feat.pfc.enabled;
 }
 
-static void bnx2x_dcbnl_set_pfc_state(struct net_device *netdev, u8 state)
+static void bnx2x_dcbnl_set_pfc_state(struct net_device *netdev,
+                                     uint8_t state)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "state = %s\n", state ? "on" : "off");
@@ -2215,7 +2228,7 @@ static void bnx2x_dcbnl_set_pfc_state(struct net_device *netdev, u8 state)
 
 static void bnx2x_admin_app_set_ent(
        struct bnx2x_admin_priority_app_table *app_ent,
-       u8 idtype, u16 idval, u8 up)
+       uint8_t idtype, uint16_t idval, uint8_t up)
 {
        app_ent->valid = 1;
 
@@ -2235,7 +2248,7 @@ static void bnx2x_admin_app_set_ent(
 
 static bool bnx2x_admin_app_is_equal(
        struct bnx2x_admin_priority_app_table *app_ent,
-       u8 idtype, u16 idval)
+       uint8_t idtype, uint16_t idval)
 {
        if (!app_ent->valid)
                return false;
@@ -2258,7 +2271,8 @@ static bool bnx2x_admin_app_is_equal(
        return true;
 }
 
-static int bnx2x_set_admin_app_up(struct bnx2x *bp, u8 idtype, u16 idval, u8 up)
+static int bnx2x_set_admin_app_up(struct bnx2x *bp, uint8_t idtype,
+                                 uint16_t idval, uint8_t up)
 {
        int i, ff;
 
@@ -2294,8 +2308,8 @@ static int bnx2x_set_admin_app_up(struct bnx2x *bp, u8 idtype, u16 idval, u8 up)
        return 0;
 }
 
-static int bnx2x_dcbnl_set_app_up(struct net_device *netdev, u8 idtype,
-                                 u16 idval, u8 up)
+static int bnx2x_dcbnl_set_app_up(struct net_device *netdev, uint8_t idtype,
+                                 uint16_t idval, uint8_t up)
 {
        struct bnx2x *bp = netdev_priv(netdev);
 
@@ -2319,10 +2333,10 @@ static int bnx2x_dcbnl_set_app_up(struct net_device *netdev, u8 idtype,
        return bnx2x_set_admin_app_up(bp, idtype, idval, up);
 }
 
-static u8 bnx2x_dcbnl_get_dcbx(struct net_device *netdev)
+static uint8_t bnx2x_dcbnl_get_dcbx(struct net_device *netdev)
 {
        struct bnx2x *bp = netdev_priv(netdev);
-       u8 state;
+       uint8_t state;
 
        state = DCB_CAP_DCBX_LLD_MANAGED | DCB_CAP_DCBX_VER_CEE;
 
@@ -2332,7 +2346,7 @@ static u8 bnx2x_dcbnl_get_dcbx(struct net_device *netdev)
        return state;
 }
 
-static u8 bnx2x_dcbnl_set_dcbx(struct net_device *netdev, u8 state)
+static uint8_t bnx2x_dcbnl_set_dcbx(struct net_device *netdev, uint8_t state)
 {
        struct bnx2x *bp = netdev_priv(netdev);
        DP(BNX2X_MSG_DCB, "state = %02x\n", state);
@@ -2359,11 +2373,11 @@ static u8 bnx2x_dcbnl_set_dcbx(struct net_device *netdev, u8 state)
        return 0;
 }
 
-static u8 bnx2x_dcbnl_get_featcfg(struct net_device *netdev, int featid,
-                                 u8 *flags)
+static uint8_t bnx2x_dcbnl_get_featcfg(struct net_device *netdev, int featid,
+                                 uint8_t *flags)
 {
        struct bnx2x *bp = netdev_priv(netdev);
-       u8 rval = 0;
+       uint8_t rval = 0;
 
        DP(BNX2X_MSG_DCB, "featid %d\n", featid);
 
@@ -2406,11 +2420,11 @@ static u8 bnx2x_dcbnl_get_featcfg(struct net_device *netdev, int featid,
        return rval;
 }
 
-static u8 bnx2x_dcbnl_set_featcfg(struct net_device *netdev, int featid,
-                                 u8 flags)
+static uint8_t bnx2x_dcbnl_set_featcfg(struct net_device *netdev, int featid,
+                                 uint8_t flags)
 {
        struct bnx2x *bp = netdev_priv(netdev);
-       u8 rval = 0;
+       uint8_t rval = 0;
 
        DP(BNX2X_MSG_DCB, "featid = %d flags = %02x\n", featid, flags);
 
@@ -2448,7 +2462,8 @@ static u8 bnx2x_dcbnl_set_featcfg(struct net_device *netdev, int featid,
 }
 
 static int bnx2x_peer_appinfo(struct net_device *netdev,
-                             struct dcb_peer_app_info *info, u16* app_count)
+                             struct dcb_peer_app_info *info,
+                             uint16_t* app_count)
 {
        int i;
        struct bnx2x *bp = netdev_priv(netdev);
index c6939ec..b1b08c5 100644 (file)
@@ -23,8 +23,8 @@
 
 #define LLFC_DRIVER_TRAFFIC_TYPE_MAX 3 /* NW, iSCSI, FCoE */
 struct bnx2x_dcbx_app_params {
-       u32 enabled;
-       u32 traffic_type_priority[LLFC_DRIVER_TRAFFIC_TYPE_MAX];
+       uint32_t enabled;
+       uint32_t traffic_type_priority[LLFC_DRIVER_TRAFFIC_TYPE_MAX];
 };
 
 #define DCBX_COS_MAX_NUM_E2    DCBX_E2E3_MAX_NUM_COS
@@ -34,28 +34,28 @@ struct bnx2x_dcbx_app_params {
 #define DCBX_COS_MAX_NUM       BNX2X_MAX_COS_SUPPORT
 
 struct bnx2x_dcbx_cos_params {
-       u32     bw_tbl;
-       u32     pri_bitmask;
+       uint32_t        bw_tbl;
+       uint32_t        pri_bitmask;
        /*
         * strict priority: valid values are 0..5; 0 is highest priority.
         * There can't be two COSes with the same priority.
         */
-       u8      strict;
+       uint8_t strict;
 #define BNX2X_DCBX_STRICT_INVALID                      DCBX_COS_MAX_NUM
 #define BNX2X_DCBX_STRICT_COS_HIGHEST                  0
 #define BNX2X_DCBX_STRICT_COS_NEXT_LOWER_PRI(sp)       ((sp) + 1)
-       u8      pauseable;
+       uint8_t pauseable;
 };
 
 struct bnx2x_dcbx_pg_params {
-       u32 enabled;
-       u8 num_of_cos; /* valid COS entries */
+       uint32_t enabled;
+       uint8_t num_of_cos; /* valid COS entries */
        struct bnx2x_dcbx_cos_params    cos_params[DCBX_COS_MAX_NUM];
 };
 
 struct bnx2x_dcbx_pfc_params {
-       u32 enabled;
-       u32 priority_non_pauseable_mask;
+       uint32_t enabled;
+       uint32_t priority_non_pauseable_mask;
 };
 
 struct bnx2x_dcbx_port_params {
@@ -72,47 +72,47 @@ struct bnx2x_dcbx_port_params {
                                  (bp)->dcbx_port_params.ets.enabled)
 
 struct bnx2x_config_lldp_params {
-       u32 overwrite_settings;
-       u32 msg_tx_hold;
-       u32 msg_fast_tx;
-       u32 tx_credit_max;
-       u32 msg_tx_interval;
-       u32 tx_fast;
+       uint32_t overwrite_settings;
+       uint32_t msg_tx_hold;
+       uint32_t msg_fast_tx;
+       uint32_t tx_credit_max;
+       uint32_t msg_tx_interval;
+       uint32_t tx_fast;
 };
 
 struct bnx2x_admin_priority_app_table {
-               u32 valid;
-               u32 priority;
+               uint32_t valid;
+               uint32_t priority;
 #define INVALID_TRAFFIC_TYPE_PRIORITY  (0xFFFFFFFF)
-               u32 traffic_type;
+               uint32_t traffic_type;
 #define TRAFFIC_TYPE_ETH               0
 #define TRAFFIC_TYPE_PORT              1
-               u32 app_id;
+               uint32_t app_id;
 };
 
 #define DCBX_CONFIG_MAX_APP_PROTOCOL 4
 struct bnx2x_config_dcbx_params {
-       u32 overwrite_settings;
-       u32 admin_dcbx_version;
-       u32 admin_ets_enable;
-       u32 admin_pfc_enable;
-       u32 admin_tc_supported_tx_enable;
-       u32 admin_ets_configuration_tx_enable;
-       u32 admin_ets_recommendation_tx_enable;
-       u32 admin_pfc_tx_enable;
-       u32 admin_application_priority_tx_enable;
-       u32 admin_ets_willing;
-       u32 admin_ets_reco_valid;
-       u32 admin_pfc_willing;
-       u32 admin_app_priority_willing;
-       u32 admin_configuration_bw_precentage[8];
-       u32 admin_configuration_ets_pg[8];
-       u32 admin_recommendation_bw_precentage[8];
-       u32 admin_recommendation_ets_pg[8];
-       u32 admin_pfc_bitmap;
+       uint32_t overwrite_settings;
+       uint32_t admin_dcbx_version;
+       uint32_t admin_ets_enable;
+       uint32_t admin_pfc_enable;
+       uint32_t admin_tc_supported_tx_enable;
+       uint32_t admin_ets_configuration_tx_enable;
+       uint32_t admin_ets_recommendation_tx_enable;
+       uint32_t admin_pfc_tx_enable;
+       uint32_t admin_application_priority_tx_enable;
+       uint32_t admin_ets_willing;
+       uint32_t admin_ets_reco_valid;
+       uint32_t admin_pfc_willing;
+       uint32_t admin_app_priority_willing;
+       uint32_t admin_configuration_bw_precentage[8];
+       uint32_t admin_configuration_ets_pg[8];
+       uint32_t admin_recommendation_bw_precentage[8];
+       uint32_t admin_recommendation_ets_pg[8];
+       uint32_t admin_pfc_bitmap;
        struct bnx2x_admin_priority_app_table
                admin_priority_app_table[DCBX_CONFIG_MAX_APP_PROTOCOL];
-       u32 admin_default_priority;
+       uint32_t admin_default_priority;
 };
 
 #define GET_FLAGS(flags, bits)         ((flags) & (bits))
@@ -135,15 +135,15 @@ enum {
 #define PFC_BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD                  170
 
 struct cos_entry_help_data {
-       u32                     pri_join_mask;
-       u32                     cos_bw;
-       u8                      strict;
+       uint32_t                        pri_join_mask;
+       uint32_t                        cos_bw;
+       uint8_t                 strict;
        bool                    pausable;
 };
 
 struct cos_help_data {
        struct cos_entry_help_data      data[DCBX_COS_MAX_NUM];
-       u8                              num_of_cos;
+       uint8_t                         num_of_cos;
 };
 
 #define DCBX_ILLEGAL_PG                                (0xFF)
@@ -153,7 +153,7 @@ struct cos_help_data {
 #define DCBX_PFC_PRI_NON_PAUSE_MASK(bp)                \
                        ((bp)->dcbx_port_params.pfc.priority_non_pauseable_mask)
 #define DCBX_PFC_PRI_PAUSE_MASK(bp)            \
-                                       ((u8)~DCBX_PFC_PRI_NON_PAUSE_MASK(bp))
+                                       ((uint8_t)~DCBX_PFC_PRI_NON_PAUSE_MASK(bp))
 #define DCBX_PFC_PRI_GET_PAUSE(bp, pg_pri)     \
                                ((pg_pri) & (DCBX_PFC_PRI_PAUSE_MASK(bp)))
 #define DCBX_PFC_PRI_GET_NON_PAUSE(bp, pg_pri) \
@@ -169,21 +169,22 @@ struct cos_help_data {
                         IS_DCBX_PFC_PRI_ONLY_PAUSE((bp), (pg_pri))))
 
 struct pg_entry_help_data {
-       u8      num_of_dif_pri;
-       u8      pg;
-       u32     pg_priority;
+       uint8_t num_of_dif_pri;
+       uint8_t pg;
+       uint32_t        pg_priority;
 };
 
 struct pg_help_data {
        struct pg_entry_help_data       data[LLFC_DRIVER_TRAFFIC_TYPE_MAX];
-       u8                              num_of_pg;
+       uint8_t                         num_of_pg;
 };
 
 /* forward DCB/PFC related declarations */
 struct bnx2x;
 void bnx2x_dcbx_update(struct work_struct *work);
 void bnx2x_dcbx_init_params(struct bnx2x *bp);
-void bnx2x_dcbx_set_state(struct bnx2x *bp, bool dcb_on, u32 dcbx_enabled);
+void bnx2x_dcbx_set_state(struct bnx2x *bp, bool dcb_on,
+                         uint32_t dcbx_enabled);
 
 enum {
        BNX2X_DCBX_STATE_NEG_RECEIVED = 0x1,
@@ -191,7 +192,7 @@ enum {
        BNX2X_DCBX_STATE_TX_RELEASED
 };
 
-void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state);
+void bnx2x_dcbx_set_params(struct bnx2x *bp, uint32_t state);
 void bnx2x_dcbx_pmf_update(struct bnx2x *bp);
 /* DCB netlink */
 #ifdef BCM_DCBNL
index 741aa13..33f3fec 100644 (file)
 #define NUM_CHIPS 5
 
 struct dump_header {
-       u32 header_size; /* Size in DWORDs excluding this field */
-       u32 version;
-       u32 preset;
-       u32 dump_meta_data; /* OR of CHIP and PATH. */
+       uint32_t header_size; /* Size in DWORDs excluding this field */
+       uint32_t version;
+       uint32_t preset;
+       uint32_t dump_meta_data; /* OR of CHIP and PATH. */
 };
 
 #define  BNX2X_DUMP_VERSION 0x61111111
 struct reg_addr {
-       u32 addr;
-       u32 size;
-       u32 chips;
-       u32 presets;
+       uint32_t addr;
+       uint32_t size;
+       uint32_t chips;
+       uint32_t presets;
 };
 
 struct wreg_addr {
-       u32 addr;
-       u32 size;
-       u32 read_regs_count;
-       const u32 *read_regs;
-       u32 chips;
-       u32 presets;
+       uint32_t addr;
+       uint32_t size;
+       uint32_t read_regs_count;
+       const uint32_t *read_regs;
+       uint32_t chips;
+       uint32_t presets;
 };
 
 #define PAGE_MODE_VALUES_E2 2
 #define PAGE_READ_REGS_E2 1
 #define PAGE_WRITE_REGS_E2 1
-static const u32 page_vals_e2[] = {0, 128};
-static const u32 page_write_regs_e2[] = {328476};
+static const uint32_t page_vals_e2[] = {0, 128};
+static const uint32_t page_write_regs_e2[] = {328476};
 static const struct reg_addr page_read_regs_e2[] = {
        {0x58000, 4608, DUMP_CHIP_E2, 0x30}
 };
@@ -69,8 +69,8 @@ static const struct reg_addr page_read_regs_e2[] = {
 #define PAGE_MODE_VALUES_E3 2
 #define PAGE_READ_REGS_E3 1
 #define PAGE_WRITE_REGS_E3 1
-static const u32 page_vals_e3[] = {0, 128};
-static const u32 page_write_regs_e3[] = {328476};
+static const uint32_t page_vals_e3[] = {0, 128};
+static const uint32_t page_write_regs_e3[] = {328476};
 static const struct reg_addr page_read_regs_e3[] = {
        {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
 };
@@ -2171,31 +2171,31 @@ static const struct reg_addr idle_reg_addrs[] = {
 
 #define IDLE_REGS_COUNT ARRAY_SIZE(idle_reg_addrs)
 
-static const u32 read_reg_e1[] = {
+static const uint32_t read_reg_e1[] = {
        0x1b1000};
 
 static const struct wreg_addr wreg_addr_e1 = {
        0x1b0c00, 192, 1, read_reg_e1, 0x1f, 0x1fff};
 
-static const u32 read_reg_e1h[] = {
+static const uint32_t read_reg_e1h[] = {
        0x1b1040, 0x1b1000};
 
 static const struct wreg_addr wreg_addr_e1h = {
        0x1b0c00, 256, 2, read_reg_e1h, 0x1f, 0x1fff};
 
-static const u32 read_reg_e2[] = {
+static const uint32_t read_reg_e2[] = {
        0x1b1040, 0x1b1000};
 
 static const struct wreg_addr wreg_addr_e2 = {
        0x1b0c00, 128, 2, read_reg_e2, 0x1f, 0x1fff};
 
-static const u32 read_reg_e3[] = {
+static const uint32_t read_reg_e3[] = {
        0x1b1040, 0x1b1000};
 
 static const struct wreg_addr wreg_addr_e3 = {
        0x1b0c00, 128, 2, read_reg_e3, 0x1f, 0x1fff};
 
-static const u32 read_reg_e3b0[] = {
+static const uint32_t read_reg_e3b0[] = {
        0x1b1040, 0x1b1000};
 
 static const struct wreg_addr wreg_addr_e3b0 = {
index 0e293b1..58752f8 100644 (file)
@@ -67,7 +67,7 @@ static const struct {
 static const struct {
        long offset;
        int size;
-       u32 flags;
+       uint32_t flags;
 #define STATS_FLAGS_PORT               1
 #define STATS_FLAGS_FUNC               2
 #define STATS_FLAGS_BOTH               (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
@@ -185,7 +185,7 @@ static const struct {
 static int bnx2x_get_port_type(struct bnx2x *bp)
 {
        int port_type;
-       u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
+       uint32_t phy_idx = bnx2x_get_cur_phy_idx(bp);
        switch (bp->link_params.phy[phy_idx].media_type) {
        case ETH_PHY_SFPP_10G_FIBER:
        case ETH_PHY_SFP_1G_FIBER:
@@ -289,7 +289,7 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 
        /* Publish LP advertised speeds and FC */
        if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
-               u32 status = bp->link_vars.link_status;
+               uint32_t status = bp->link_vars.link_status;
 
                cmd->lp_advertising |= ADVERTISED_Autoneg;
                if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
@@ -335,8 +335,8 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
        struct bnx2x *bp = netdev_priv(dev);
-       u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
-       u32 speed, phy_idx;
+       uint32_t advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
+       uint32_t speed, phy_idx;
 
        if (IS_MF_SD(bp))
                return 0;
@@ -357,8 +357,8 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
                cmd->duplex = DUPLEX_FULL;
 
        if (IS_MF_SI(bp)) {
-               u32 part;
-               u32 line_speed = bp->link_vars.line_speed;
+               uint32_t part;
+               uint32_t line_speed = bp->link_vars.line_speed;
 
                /* use 10G if no link detected */
                if (!line_speed)
@@ -442,7 +442,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
        DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
 
        if (cmd->autoneg == AUTONEG_ENABLE) {
-               u32 an_supported_speed = bp->port.supported[cfg_idx];
+               uint32_t an_supported_speed = bp->port.supported[cfg_idx];
                if (bp->link_params.phy[EXT_PHY1].type ==
                    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
                        an_supported_speed |= (SUPPORTED_100baseT_Half |
@@ -637,7 +637,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 #define DUMP_ALL_PRESETS               0x1FFF
 #define DUMP_MAX_PRESETS               13
 
-static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
+static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, uint32_t preset)
 {
        if (CHIP_IS_E1(bp))
                return dump_num_registers[0][preset-1];
@@ -655,7 +655,7 @@ static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
 
 static int __bnx2x_get_regs_len(struct bnx2x *bp)
 {
-       u32 preset_idx;
+       uint32_t preset_idx;
        int regdump_len = 0;
 
        /* Calculate the total preset regs length */
@@ -690,7 +690,7 @@ static int bnx2x_get_regs_len(struct net_device *dev)
                ((presets & (1 << (idx-1))) == (1 << (idx-1)))
 
 /******* Paged registers info selectors ********/
-static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
+static const uint32_t *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 {
        if (CHIP_IS_E2(bp))
                return page_vals_e2;
@@ -700,7 +700,7 @@ static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
                return NULL;
 }
 
-static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
+static uint32_t __bnx2x_get_page_reg_num(struct bnx2x *bp)
 {
        if (CHIP_IS_E2(bp))
                return PAGE_MODE_VALUES_E2;
@@ -710,7 +710,7 @@ static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
                return 0;
 }
 
-static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
+static const uint32_t *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 {
        if (CHIP_IS_E2(bp))
                return page_write_regs_e2;
@@ -720,7 +720,7 @@ static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
                return NULL;
 }
 
-static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
+static uint32_t __bnx2x_get_page_write_num(struct bnx2x *bp)
 {
        if (CHIP_IS_E2(bp))
                return PAGE_WRITE_REGS_E2;
@@ -740,7 +740,7 @@ static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
                return NULL;
 }
 
-static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
+static uint32_t __bnx2x_get_page_read_num(struct bnx2x *bp)
 {
        if (CHIP_IS_E2(bp))
                return PAGE_READ_REGS_E2;
@@ -795,23 +795,24 @@ static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
  * ("read address"). There may be more than one write address per "page" and
  * more than one read address per write address.
  */
-static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
+static void bnx2x_read_pages_regs(struct bnx2x *bp, uint32_t *p,
+                                 uint32_t preset)
 {
-       u32 i, j, k, n;
+       uint32_t i, j, k, n;
 
        /* addresses of the paged registers */
-       const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
+       const uint32_t *page_addr = __bnx2x_get_page_addr_ar(bp);
        /* number of paged registers */
        int num_pages = __bnx2x_get_page_reg_num(bp);
        /* write addresses */
-       const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
+       const uint32_t *write_addr = __bnx2x_get_page_write_ar(bp);
        /* number of write addresses */
        int write_num = __bnx2x_get_page_write_num(bp);
        /* read addresses info */
        const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
        /* number of read addresses */
        int read_num = __bnx2x_get_page_read_num(bp);
-       u32 addr, size;
+       uint32_t addr, size;
 
        for (i = 0; i < num_pages; i++) {
                for (j = 0; j < write_num; j++) {
@@ -831,9 +832,10 @@ static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
        }
 }
 
-static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
+static int __bnx2x_get_preset_regs(struct bnx2x *bp, uint32_t *p,
+                                  uint32_t preset)
 {
-       u32 i, j, addr;
+       uint32_t i, j, addr;
        const struct wreg_addr *wreg_addr_p = NULL;
 
        if (CHIP_IS_E1(bp))
@@ -890,9 +892,9 @@ static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
        return 0;
 }
 
-static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
+static void __bnx2x_get_regs(struct bnx2x *bp, uint32_t *p)
 {
-       u32 preset_idx;
+       uint32_t preset_idx;
 
        /* Read all registers, by reading all preset registers */
        for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
@@ -910,7 +912,7 @@ static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 static void bnx2x_get_regs(struct net_device *dev,
                           struct ethtool_regs *regs, void *_p)
 {
-       u32 *p = _p;
+       uint32_t *p = _p;
        struct bnx2x *bp = netdev_priv(dev);
        struct dump_header dump_hdr = {0};
 
@@ -958,7 +960,7 @@ static void bnx2x_get_regs(struct net_device *dev,
        bnx2x_enable_blocks_parity(bp);
 }
 
-static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
+static int bnx2x_get_preset_regs_len(struct net_device *dev, uint32_t preset)
 {
        struct bnx2x *bp = netdev_priv(dev);
        int regdump_len = 0;
@@ -1000,7 +1002,7 @@ static int bnx2x_get_dump_data(struct net_device *dev,
                               struct ethtool_dump *dump,
                               void *buffer)
 {
-       u32 *p = buffer;
+       uint32_t *p = buffer;
        struct bnx2x *bp = netdev_priv(dev);
        struct dump_header dump_hdr = {0};
 
@@ -1101,14 +1103,14 @@ static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
        return 0;
 }
 
-static u32 bnx2x_get_msglevel(struct net_device *dev)
+static uint32_t bnx2x_get_msglevel(struct net_device *dev)
 {
        struct bnx2x *bp = netdev_priv(dev);
 
        return bp->msg_enable;
 }
 
-static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
+static void bnx2x_set_msglevel(struct net_device *dev, uint32_t level)
 {
        struct bnx2x *bp = netdev_priv(dev);
 
@@ -1136,7 +1138,7 @@ static int bnx2x_nway_reset(struct net_device *dev)
        return 0;
 }
 
-static u32 bnx2x_get_link(struct net_device *dev)
+static uint32_t bnx2x_get_link(struct net_device *dev)
 {
        struct bnx2x *bp = netdev_priv(dev);
 
@@ -1174,7 +1176,7 @@ static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
 {
        int port = BP_PORT(bp);
        int count, i;
-       u32 val;
+       uint32_t val;
 
        /* acquire HW lock: protect against other PFs in PF Direct Assignment */
        bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
@@ -1209,7 +1211,7 @@ static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 {
        int port = BP_PORT(bp);
        int count, i;
-       u32 val;
+       uint32_t val;
 
        /* adjust timeout for emulation/FPGA */
        count = BNX2X_NVRAM_TIMEOUT_COUNT;
@@ -1241,7 +1243,7 @@ static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 
 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
 {
-       u32 val;
+       uint32_t val;
 
        val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 
@@ -1253,7 +1255,7 @@ static void bnx2x_enable_nvram_access(struct bnx2x *bp)
 
 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
 {
-       u32 val;
+       uint32_t val;
 
        val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 
@@ -1263,11 +1265,12 @@ static void bnx2x_disable_nvram_access(struct bnx2x *bp)
                        MCPR_NVM_ACCESS_ENABLE_WR_EN)));
 }
 
-static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
-                                 u32 cmd_flags)
+static int bnx2x_nvram_read_dword(struct bnx2x *bp, uint32_t offset,
+                                 __be32 *ret_val,
+                                 uint32_t cmd_flags)
 {
        int count, i, rc;
-       u32 val;
+       uint32_t val;
 
        /* build the command word */
        cmd_flags |= MCPR_NVM_COMMAND_DOIT;
@@ -1311,11 +1314,12 @@ static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
        return rc;
 }
 
-static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
+static int bnx2x_nvram_read(struct bnx2x *bp, uint32_t offset,
+                           uint8_t *ret_buf,
                            int buf_size)
 {
        int rc;
-       u32 cmd_flags;
+       uint32_t cmd_flags;
        __be32 val;
 
        if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
@@ -1342,14 +1346,14 @@ static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
 
        /* read the first word(s) */
        cmd_flags = MCPR_NVM_COMMAND_FIRST;
-       while ((buf_size > sizeof(u32)) && (rc == 0)) {
+       while ((buf_size > sizeof(uint32_t)) && (rc == 0)) {
                rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
                memcpy(ret_buf, &val, 4);
 
                /* advance to the next dword */
-               offset += sizeof(u32);
-               ret_buf += sizeof(u32);
-               buf_size -= sizeof(u32);
+               offset += sizeof(uint32_t);
+               ret_buf += sizeof(uint32_t);
+               buf_size -= sizeof(uint32_t);
                cmd_flags = 0;
        }
 
@@ -1366,12 +1370,13 @@ static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
        return rc;
 }
 
-static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
+static int bnx2x_nvram_read32(struct bnx2x *bp, uint32_t offset,
+                             uint32_t *buf,
                              int buf_size)
 {
        int rc;
 
-       rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
+       rc = bnx2x_nvram_read(bp, offset, (uint8_t *)buf, buf_size);
 
        if (!rc) {
                __be32 *be = (__be32 *)buf;
@@ -1386,7 +1391,7 @@ static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
 {
        int rc = 1;
-       u16 pm = 0;
+       uint16_t pm = 0;
        struct net_device *dev = pci_get_drvdata(bp->pdev);
 
        if (bp->pdev->pm_cap)
@@ -1394,14 +1399,14 @@ static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
                                          bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
 
        if ((rc && !netif_running(dev)) ||
-           (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
+           (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force uint16_t)PCI_D0)))
                return false;
 
        return true;
 }
 
 static int bnx2x_get_eeprom(struct net_device *dev,
-                           struct ethtool_eeprom *eeprom, u8 *eebuf)
+                           struct ethtool_eeprom *eeprom, uint8_t *eebuf)
 {
        struct bnx2x *bp = netdev_priv(dev);
 
@@ -1423,11 +1428,11 @@ static int bnx2x_get_eeprom(struct net_device *dev,
 
 static int bnx2x_get_module_eeprom(struct net_device *dev,
                                   struct ethtool_eeprom *ee,
-                                  u8 *data)
+                                  uint8_t *data)
 {
        struct bnx2x *bp = netdev_priv(dev);
        int rc = -EINVAL, phy_idx;
-       u8 *user_data = data;
+       uint8_t *user_data = data;
        unsigned int start_addr = ee->offset, xfer_size = 0;
 
        if (!bnx2x_is_nvm_accessible(bp)) {
@@ -1491,7 +1496,7 @@ static int bnx2x_get_module_info(struct net_device *dev,
 {
        struct bnx2x *bp = netdev_priv(dev);
        int phy_idx, rc;
-       u8 sff8472_comp, diag_type;
+       uint8_t sff8472_comp, diag_type;
 
        if (!bnx2x_is_nvm_accessible(bp)) {
                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
@@ -1536,8 +1541,9 @@ static int bnx2x_get_module_info(struct net_device *dev,
        return 0;
 }
 
-static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
-                                  u32 cmd_flags)
+static int bnx2x_nvram_write_dword(struct bnx2x *bp, uint32_t offset,
+                                  uint32_t val,
+                                  uint32_t cmd_flags)
 {
        int count, i, rc;
 
@@ -1581,11 +1587,12 @@ static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
 
 #define BYTE_OFFSET(offset)            (8 * (offset & 0x03))
 
-static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
+static int bnx2x_nvram_write1(struct bnx2x *bp, uint32_t offset,
+                             uint8_t *data_buf,
                              int buf_size)
 {
        int rc;
-       u32 cmd_flags, align_offset, val;
+       uint32_t cmd_flags, align_offset, val;
        __be32 val_be;
 
        if (offset + buf_size > bp->common.flash_size) {
@@ -1629,13 +1636,14 @@ static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
        return rc;
 }
 
-static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
+static int bnx2x_nvram_write(struct bnx2x *bp, uint32_t offset,
+                            uint8_t *data_buf,
                             int buf_size)
 {
        int rc;
-       u32 cmd_flags;
-       u32 val;
-       u32 written_so_far;
+       uint32_t cmd_flags;
+       uint32_t val;
+       uint32_t written_so_far;
 
        if (buf_size == 1)      /* ethtool */
                return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
@@ -1665,7 +1673,7 @@ static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
        written_so_far = 0;
        cmd_flags = MCPR_NVM_COMMAND_FIRST;
        while ((written_so_far < buf_size) && (rc == 0)) {
-               if (written_so_far == (buf_size - sizeof(u32)))
+               if (written_so_far == (buf_size - sizeof(uint32_t)))
                        cmd_flags |= MCPR_NVM_COMMAND_LAST;
                else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
                        cmd_flags |= MCPR_NVM_COMMAND_LAST;
@@ -1683,9 +1691,9 @@ static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
                rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
 
                /* advance to the next dword */
-               offset += sizeof(u32);
-               data_buf += sizeof(u32);
-               written_so_far += sizeof(u32);
+               offset += sizeof(uint32_t);
+               data_buf += sizeof(uint32_t);
+               written_so_far += sizeof(uint32_t);
                cmd_flags = 0;
        }
 
@@ -1697,12 +1705,12 @@ static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
 }
 
 static int bnx2x_set_eeprom(struct net_device *dev,
-                           struct ethtool_eeprom *eeprom, u8 *eebuf)
+                           struct ethtool_eeprom *eeprom, uint8_t *eebuf)
 {
        struct bnx2x *bp = netdev_priv(dev);
        int port = BP_PORT(bp);
        int rc = 0;
-       u32 ext_phy_config;
+       uint32_t ext_phy_config;
 
        if (!bnx2x_is_nvm_accessible(bp)) {
                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
@@ -1799,11 +1807,11 @@ static int bnx2x_set_coalesce(struct net_device *dev,
 {
        struct bnx2x *bp = netdev_priv(dev);
 
-       bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
+       bp->rx_ticks = (uint16_t)coal->rx_coalesce_usecs;
        if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
                bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
 
-       bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
+       bp->tx_ticks = (uint16_t)coal->tx_coalesce_usecs;
        if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
                bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
 
@@ -1888,7 +1896,7 @@ static int bnx2x_set_pauseparam(struct net_device *dev,
                                struct ethtool_pauseparam *epause)
 {
        struct bnx2x *bp = netdev_priv(dev);
-       u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
+       uint32_t cfg_idx = bnx2x_get_link_cfg_idx(bp);
        if (IS_MF(bp))
                return 0;
 
@@ -1962,9 +1970,9 @@ static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
        "Storage only interface"
 };
 
-static u32 bnx2x_eee_to_adv(u32 eee_adv)
+static uint32_t bnx2x_eee_to_adv(uint32_t eee_adv)
 {
-       u32 modes = 0;
+       uint32_t modes = 0;
 
        if (eee_adv & SHMEM_EEE_100M_ADV)
                modes |= ADVERTISED_100baseT_Full;
@@ -1976,9 +1984,9 @@ static u32 bnx2x_eee_to_adv(u32 eee_adv)
        return modes;
 }
 
-static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
+static uint32_t bnx2x_adv_to_eee(uint32_t modes, uint32_t shift)
 {
-       u32 eee_adv = 0;
+       uint32_t eee_adv = 0;
        if (modes & ADVERTISED_100baseT_Full)
                eee_adv |= SHMEM_EEE_100M_ADV;
        if (modes & ADVERTISED_1000baseT_Full)
@@ -1992,7 +2000,7 @@ static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
 {
        struct bnx2x *bp = netdev_priv(dev);
-       u32 eee_cfg;
+       uint32_t eee_cfg;
 
        if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
                DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
@@ -2025,8 +2033,8 @@ static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
 {
        struct bnx2x *bp = netdev_priv(dev);
-       u32 eee_cfg;
-       u32 advertised;
+       uint32_t eee_cfg;
+       uint32_t advertised;
 
        if (IS_MF(bp))
                return 0;
@@ -2113,13 +2121,13 @@ enum {
 static int bnx2x_test_registers(struct bnx2x *bp)
 {
        int idx, i, rc = -ENODEV;
-       u32 wr_val = 0, hw;
+       uint32_t wr_val = 0, hw;
        int port = BP_PORT(bp);
        static const struct {
-               u32 hw;
-               u32 offset0;
-               u32 offset1;
-               u32 mask;
+               uint32_t hw;
+               uint32_t offset0;
+               uint32_t offset1;
+               uint32_t mask;
        } reg_tbl[] = {
 /* 0 */                { BNX2X_CHIP_MASK_ALL,
                        BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
@@ -2233,7 +2241,7 @@ static int bnx2x_test_registers(struct bnx2x *bp)
                }
 
                for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
-                       u32 offset, mask, save_val, val;
+                       uint32_t offset, mask, save_val, val;
                        if (!(hw & reg_tbl[i].hw))
                                continue;
 
@@ -2268,9 +2276,9 @@ test_reg_exit:
 static int bnx2x_test_memory(struct bnx2x *bp)
 {
        int i, j, rc = -ENODEV;
-       u32 val, index;
+       uint32_t val, index;
        static const struct {
-               u32 offset;
+               uint32_t offset;
                int size;
        } mem_tbl[] = {
                { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
@@ -2286,8 +2294,8 @@ static int bnx2x_test_memory(struct bnx2x *bp)
 
        static const struct {
                char *name;
-               u32 offset;
-               u32 hw_mask[BNX2X_CHIP_MAX_OFST];
+               uint32_t offset;
+               uint32_t hw_mask[BNX2X_CHIP_MAX_OFST];
        } prty_tbl[] = {
                { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
                        {0x3ffc0, 0,   0, 0} },
@@ -2351,7 +2359,8 @@ test_mem_exit:
        return rc;
 }
 
-static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
+static void bnx2x_wait_for_link(struct bnx2x *bp, uint8_t link_up,
+                               uint8_t is_serdes)
 {
        int cnt = 1400;
 
@@ -2380,18 +2389,18 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
        struct bnx2x_fastpath *fp_rx = &bp->fp[0];
        struct bnx2x_fastpath *fp_tx = &bp->fp[0];
        struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
-       u16 tx_start_idx, tx_idx;
-       u16 rx_start_idx, rx_idx;
-       u16 pkt_prod, bd_prod;
+       uint16_t tx_start_idx, tx_idx;
+       uint16_t rx_start_idx, rx_idx;
+       uint16_t pkt_prod, bd_prod;
        struct sw_tx_bd *tx_buf;
        struct eth_tx_start_bd *tx_start_bd;
        dma_addr_t mapping;
        union eth_rx_cqe *cqe;
-       u8 cqe_fp_flags, cqe_fp_type;
+       uint8_t cqe_fp_flags, cqe_fp_type;
        struct sw_rx_bd *rx_buf;
-       u16 len;
+       uint16_t len;
        int rc = -ENODEV;
-       u8 *data;
+       uint8_t *data;
        struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
                                                       txdata->txq_index);
 
@@ -2486,7 +2495,7 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
        bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
 
        if (CHIP_IS_E1x(bp)) {
-               u16 global_data = 0;
+               uint16_t global_data = 0;
                struct eth_tx_parse_bd_e1x  *pbd_e1x =
                        &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
                memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
@@ -2494,7 +2503,7 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
                         ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
                pbd_e1x->global_data = cpu_to_le16(global_data);
        } else {
-               u32 parsing_data = 0;
+               uint32_t parsing_data = 0;
                struct eth_tx_parse_bd_e2  *pbd_e2 =
                        &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
                memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
@@ -2610,7 +2619,7 @@ static int bnx2x_test_loopback(struct bnx2x *bp)
 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
 {
        int rc;
-       u8 is_serdes =
+       uint8_t is_serdes =
                (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
 
        if (BP_NOMCP(bp))
@@ -2640,13 +2649,13 @@ static int bnx2x_test_ext_loopback(struct bnx2x *bp)
 }
 
 struct code_entry {
-       u32 sram_start_addr;
-       u32 code_attribute;
+       uint32_t sram_start_addr;
+       uint32_t code_attribute;
 #define CODE_IMAGE_TYPE_MASK                   0xf0800003
 #define CODE_IMAGE_VNTAG_PROFILES_DATA         0xd0000003
 #define CODE_IMAGE_LENGTH_MASK                 0x007ffffc
 #define CODE_IMAGE_TYPE_EXTENDED_DIR           0xe0000000
-       u32 nvm_start_addr;
+       uint32_t nvm_start_addr;
 };
 
 #define CODE_ENTRY_MAX                 16
@@ -2664,9 +2673,9 @@ struct code_entry {
 static int bnx2x_nvram_crc(struct bnx2x *bp,
                           int offset,
                           int size,
-                          u8 *buff)
+                          uint8_t *buff)
 {
-       u32 crc = ~0;
+       uint32_t crc = ~0;
        int rc = 0, done = 0;
 
        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
@@ -2692,10 +2701,10 @@ static int bnx2x_nvram_crc(struct bnx2x *bp,
 
 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
                                struct code_entry *entry,
-                               u8 *buff)
+                               uint8_t *buff)
 {
        size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
-       u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
+       uint32_t type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
        int rc;
 
        /* Zero-length images and AFEX profiles do not have CRC */
@@ -2710,28 +2719,29 @@ static int bnx2x_test_nvram_dir(struct bnx2x *bp,
        return rc;
 }
 
-static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
+static int bnx2x_test_dir_entry(struct bnx2x *bp, uint32_t addr,
+                               uint8_t *buff)
 {
        int rc;
        struct code_entry entry;
 
-       rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
+       rc = bnx2x_nvram_read32(bp, addr, (uint32_t *)&entry, sizeof(entry));
        if (rc)
                return rc;
 
        return bnx2x_test_nvram_dir(bp, &entry, buff);
 }
 
-static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
+static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, uint8_t *buff)
 {
-       u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
+       uint32_t rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
        struct code_entry entry;
        int i;
 
        rc = bnx2x_nvram_read32(bp,
                                dir_offset +
                                sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
-                               (u32 *)&entry, sizeof(entry));
+                               (uint32_t *)&entry, sizeof(entry));
        if (rc)
                return rc;
 
@@ -2739,7 +2749,7 @@ static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
                return 0;
 
        rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
-                               &cnt, sizeof(u32));
+                               &cnt, sizeof(uint32_t));
        if (rc)
                return rc;
 
@@ -2756,9 +2766,9 @@ static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
        return 0;
 }
 
-static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
+static int bnx2x_test_nvram_dirs(struct bnx2x *bp, uint8_t *buff)
 {
-       u32 rc, dir_offset = NVRAM_DIR_OFFSET;
+       uint32_t rc, dir_offset = NVRAM_DIR_OFFSET;
        int i;
 
        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
@@ -2780,7 +2790,8 @@ struct crc_pair {
 };
 
 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
-                               const struct crc_pair *nvram_tbl, u8 *buf)
+                               const struct crc_pair *nvram_tbl,
+                               uint8_t *buf)
 {
        int i;
 
@@ -2815,9 +2826,9 @@ static int bnx2x_test_nvram(struct bnx2x *bp)
                {     0,     0 }
        };
 
-       u8 *buf;
+       uint8_t *buf;
        int rc;
-       u32 magic;
+       uint32_t magic;
 
        if (BP_NOMCP(bp))
                return 0;
@@ -2849,7 +2860,7 @@ static int bnx2x_test_nvram(struct bnx2x *bp)
                goto test_nvram_exit;
 
        if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
-               u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
+               uint32_t hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
                           SHARED_HW_CFG_HIDE_PORT1;
 
                if (!hide) {
@@ -2888,10 +2899,10 @@ static int bnx2x_test_intr(struct bnx2x *bp)
 }
 
 static void bnx2x_self_test(struct net_device *dev,
-                           struct ethtool_test *etest, u64 *buf)
+                           struct ethtool_test *etest, uint64_t *buf)
 {
        struct bnx2x *bp = netdev_priv(dev);
-       u8 is_serdes, link_up;
+       uint8_t is_serdes, link_up;
        int rc, cnt = 0;
 
        if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
@@ -2906,7 +2917,7 @@ static void bnx2x_self_test(struct net_device *dev,
           (etest->flags & ETH_TEST_FL_OFFLINE),
           (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
 
-       memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
+       memset(buf, 0, sizeof(uint64_t) * BNX2X_NUM_TESTS(bp));
 
        if (bnx2x_test_nvram(bp) != 0) {
                if (!IS_MF(bp))
@@ -2926,7 +2937,7 @@ static void bnx2x_self_test(struct net_device *dev,
        /* offline tests are not supported in MF mode */
        if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
                int port = BP_PORT(bp);
-               u32 val;
+               uint32_t val;
 
                /* save current value of input enable for TX port IF */
                val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
@@ -3050,10 +3061,10 @@ static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
        }
 }
 
-static u32 bnx2x_get_private_flags(struct net_device *dev)
+static uint32_t bnx2x_get_private_flags(struct net_device *dev)
 {
        struct bnx2x *bp = netdev_priv(dev);
-       u32 flags = 0;
+       uint32_t flags = 0;
 
        flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
        flags |= (!(bp->flags & NO_FCOE_FLAG)  ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
@@ -3062,7 +3073,8 @@ static u32 bnx2x_get_private_flags(struct net_device *dev)
        return flags;
 }
 
-static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
+static void bnx2x_get_strings(struct net_device *dev, uint32_t stringset,
+                             uint8_t *buf)
 {
        struct bnx2x *bp = netdev_priv(dev);
        int i, j, k, start;
@@ -3112,15 +3124,16 @@ static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
 }
 
 static void bnx2x_get_ethtool_stats(struct net_device *dev,
-                                   struct ethtool_stats *stats, u64 *buf)
+                                   struct ethtool_stats *stats,
+                                   uint64_t *buf)
 {
        struct bnx2x *bp = netdev_priv(dev);
-       u32 *hw_stats, *offset;
+       uint32_t *hw_stats, *offset;
        int i, j, k = 0;
 
        if (is_multi(bp)) {
                for_each_eth_queue(bp, i) {
-                       hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
+                       hw_stats = (uint32_t *)&bp->fp_stats[i].eth_q_stats;
                        for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
                                if (bnx2x_q_stats_arr[j].size == 0) {
                                        /* skip this counter */
@@ -3131,7 +3144,7 @@ static void bnx2x_get_ethtool_stats(struct net_device *dev,
                                          bnx2x_q_stats_arr[j].offset);
                                if (bnx2x_q_stats_arr[j].size == 4) {
                                        /* 4-byte counter */
-                                       buf[k + j] = (u64) *offset;
+                                       buf[k + j] = (uint64_t) *offset;
                                        continue;
                                }
                                /* 8-byte counter */
@@ -3141,7 +3154,7 @@ static void bnx2x_get_ethtool_stats(struct net_device *dev,
                }
        }
 
-       hw_stats = (u32 *)&bp->eth_stats;
+       hw_stats = (uint32_t *)&bp->eth_stats;
        for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
                if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
                        continue;
@@ -3154,7 +3167,7 @@ static void bnx2x_get_ethtool_stats(struct net_device *dev,
                offset = (hw_stats + bnx2x_stats_arr[i].offset);
                if (bnx2x_stats_arr[i].size == 4) {
                        /* 4-byte counter */
-                       buf[k + j] = (u64) *offset;
+                       buf[k + j] = (uint64_t) *offset;
                        j++;
                        continue;
                }
@@ -3239,7 +3252,7 @@ static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
 }
 
 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
-                          u32 *rules __always_unused)
+                          uint32_t *rules __always_unused)
 {
        struct bnx2x *bp = netdev_priv(dev);
 
@@ -3348,16 +3361,17 @@ static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
        }
 }
 
-static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
+static uint32_t bnx2x_get_rxfh_indir_size(struct net_device *dev)
 {
        return T_ETH_INDIRECTION_TABLE_SIZE;
 }
 
-static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
-                         u8 *hfunc)
+static int bnx2x_get_rxfh(struct net_device *dev, uint32_t *indir,
+                         uint8_t *key,
+                         uint8_t *hfunc)
 {
        struct bnx2x *bp = netdev_priv(dev);
-       u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
+       uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
        size_t i;
 
        if (hfunc)
@@ -3383,8 +3397,8 @@ static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
        return 0;
 }
 
-static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
-                         const u8 *key, const u8 hfunc)
+static int bnx2x_set_rxfh(struct net_device *dev, const uint32_t *indir,
+                         const uint8_t *key, const uint8_t hfunc)
 {
        struct bnx2x *bp = netdev_priv(dev);
        size_t i;
index 583591d..24808e1 100644 (file)
 #define FW_ENCODE_32BIT_PATTERN         0x1e1e1e1e
 
 struct license_key {
-       u32 reserved[6];
+       uint32_t reserved[6];
 
-       u32 max_iscsi_conn;
+       uint32_t max_iscsi_conn;
 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT        0
 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT        16
 
-       u32 reserved_a;
+       uint32_t reserved_a;
 
-       u32 max_fcoe_conn;
+       uint32_t max_fcoe_conn;
 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK  0xFFFF
 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
 #define BNX2X_MAX_FCOE_INIT_CONN_MASK  0xFFFF0000
 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
 
-       u32 reserved_b[4];
+       uint32_t reserved_b[4];
 };
 
 /****************************************************************************
@@ -115,15 +115,15 @@ struct license_key {
 #define EPIO_CFG_EPIO31                     0x00000020
 
 struct mac_addr {
-       u32 upper;
-       u32 lower;
+       uint32_t upper;
+       uint32_t lower;
 };
 
 struct shared_hw_cfg {                  /* NVRAM Offset */
        /* Up to 16 bytes of NULL-terminated string */
-       u8  part_num[16];                   /* 0x104 */
+       uint8_t  part_num[16];              /* 0x104 */
 
-       u32 config;                     /* 0x114 */
+       uint32_t config;                        /* 0x114 */
        #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
                #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT             0
                #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V              0x00000000
@@ -192,7 +192,7 @@ struct shared_hw_cfg {                       /* NVRAM Offset */
                #define SHARED_HW_CFG_ATC_DISABLED                   0x00000000
                #define SHARED_HW_CFG_ATC_ENABLED                    0x80000000
 
-       u32 config2;                        /* 0x118 */
+       uint32_t config2;                           /* 0x118 */
        /* one time auto detect grace period (in sec) */
        #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
        #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT                     0
@@ -280,13 +280,13 @@ struct shared_hw_cfg {                     /* NVRAM Offset */
                #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH          0x60000000
                #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED       0x80000000
 
-       u32 config_3;                           /* 0x11C */
+       uint32_t config_3;                              /* 0x11C */
        #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK         0x00000F00
                #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT              8
                #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5        0x00000000
                #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0        0x00000100
 
-       u32 ump_nc_si_config;                   /* 0x120 */
+       uint32_t ump_nc_si_config;                      /* 0x120 */
        #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
                #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT       0
                #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC         0x00000000
@@ -302,7 +302,7 @@ struct shared_hw_cfg {                       /* NVRAM Offset */
                #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE    0x00000000
                #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
 
-       u32 board;                      /* 0x124 */
+       uint32_t board;                 /* 0x124 */
        #define SHARED_HW_CFG_E3_I2C_MUX0_MASK              0x0000003F
        #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT                      0
        #define SHARED_HW_CFG_E3_I2C_MUX1_MASK              0x00000FC0
@@ -317,7 +317,7 @@ struct shared_hw_cfg {                       /* NVRAM Offset */
        #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xf0000000
        #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT                  28
 
-       u32 wc_lane_config;                                 /* 0x128 */
+       uint32_t wc_lane_config;                                    /* 0x128 */
        #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK            0x0000FFFF
                #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT            0
                #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210         0x00001b1b
@@ -357,15 +357,15 @@ struct shared_hw_cfg {                     /* NVRAM Offset */
  ****************************************************************************/
 struct port_hw_cfg {               /* port 0: 0x12c  port 1: 0x2bc */
 
-       u32 pci_id;
+       uint32_t pci_id;
        #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
        #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
 
-       u32 pci_sub_id;
+       uint32_t pci_sub_id;
        #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
        #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
 
-       u32 power_dissipated;
+       uint32_t power_dissipated;
        #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
        #define PORT_HW_CFG_POWER_DIS_D0_SHIFT                       0
        #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
@@ -375,7 +375,7 @@ struct port_hw_cfg {                    /* port 0: 0x12c  port 1: 0x2bc */
        #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
        #define PORT_HW_CFG_POWER_DIS_D3_SHIFT                       24
 
-       u32 power_consumed;
+       uint32_t power_consumed;
        #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
        #define PORT_HW_CFG_POWER_CONS_D0_SHIFT                      0
        #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
@@ -385,18 +385,18 @@ struct port_hw_cfg {                  /* port 0: 0x12c  port 1: 0x2bc */
        #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
        #define PORT_HW_CFG_POWER_CONS_D3_SHIFT                      24
 
-       u32 mac_upper;
+       uint32_t mac_upper;
        #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
        #define PORT_HW_CFG_UPPERMAC_SHIFT                           0
-       u32 mac_lower;
+       uint32_t mac_lower;
 
-       u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
-       u32 iscsi_mac_lower;
+       uint32_t iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
+       uint32_t iscsi_mac_lower;
 
-       u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
-       u32 rdma_mac_lower;
+       uint32_t rdma_mac_upper;   /* Upper 16 bits are always zeroes */
+       uint32_t rdma_mac_lower;
 
-       u32 serdes_config;
+       uint32_t serdes_config;
        #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
        #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT         0
 
@@ -405,7 +405,7 @@ struct port_hw_cfg {                    /* port 0: 0x12c  port 1: 0x2bc */
 
 
        /*  Default values: 2P-64, 4P-32 */
-       u32 pf_config;                                      /* 0x158 */
+       uint32_t pf_config;                                         /* 0x158 */
        #define PORT_HW_CFG_PF_NUM_VF_MASK                  0x0000007F
        #define PORT_HW_CFG_PF_NUM_VF_SHIFT                          0
 
@@ -416,19 +416,19 @@ struct port_hw_cfg {                  /* port 0: 0x12c  port 1: 0x2bc */
        #define PORT_HW_CFG_ENABLE_FLR_MASK                 0x00010000
        #define PORT_HW_CFG_FLR_ENABLED                     0x00010000
 
-       u32 vf_config;                                      /* 0x15C */
+       uint32_t vf_config;                                         /* 0x15C */
        #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK        0x0000007F
        #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT                0
 
        #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK           0xFFFF0000
        #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT                   16
 
-       u32 mf_pci_id;                                      /* 0x160 */
+       uint32_t mf_pci_id;                                         /* 0x160 */
        #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK           0x0000FFFF
        #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT                   0
 
        /*  Controls the TX laser of the SFP+ module */
-       u32 sfp_ctrl;                                       /* 0x164 */
+       uint32_t sfp_ctrl;                                          /* 0x164 */
        #define PORT_HW_CFG_TX_LASER_MASK                   0x000000FF
                #define PORT_HW_CFG_TX_LASER_SHIFT                   0
                #define PORT_HW_CFG_TX_LASER_MDIO                    0x00000000
@@ -448,7 +448,7 @@ struct port_hw_cfg {                    /* port 0: 0x12c  port 1: 0x2bc */
 
        /*  The output pin TX_DIS that controls the TX laser of the SFP+
          module. Use the PIN_CFG_XXX defines on top */
-       u32 e3_sfp_ctrl;                                    /* 0x168 */
+       uint32_t e3_sfp_ctrl;                               /* 0x168 */
        #define PORT_HW_CFG_E3_TX_LASER_MASK                0x000000FF
        #define PORT_HW_CFG_E3_TX_LASER_SHIFT                        0
 
@@ -470,7 +470,7 @@ struct port_hw_cfg {                    /* port 0: 0x12c  port 1: 0x2bc */
         * The input pin which signals module transmit fault. Use the
         * PIN_CFG_XXX defines on top
         */
-       u32 e3_cmn_pin_cfg;                                 /* 0x16C */
+       uint32_t e3_cmn_pin_cfg;                                    /* 0x16C */
        #define PORT_HW_CFG_E3_TX_FAULT_MASK                0x000000FF
        #define PORT_HW_CFG_E3_TX_FAULT_SHIFT                        0
 
@@ -496,12 +496,12 @@ struct port_hw_cfg {                  /* port 0: 0x12c  port 1: 0x2bc */
         * The input pin I_FAULT which indicate over-current has occurred.
         * Use the PIN_CFG_XXX defines on top
         */
-       u32 e3_cmn_pin_cfg1;                                /* 0x170 */
+       uint32_t e3_cmn_pin_cfg1;                                   /* 0x170 */
        #define PORT_HW_CFG_E3_OVER_CURRENT_MASK            0x000000FF
        #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT                    0
 
        /*  pause on host ring */
-       u32 generic_features;                               /* 0x174 */
+       uint32_t generic_features;                               /* 0x174 */
        #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK                   0x00000001
        #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT                  0
        #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED               0x00000000
@@ -511,7 +511,7 @@ struct port_hw_cfg {                    /* port 0: 0x12c  port 1: 0x2bc */
         * LOM recommended and tested value is 0xBEB2. Using a different
         * value means using a value not tested by BRCM
         */
-       u32 sfi_tap_values;                                 /* 0x178 */
+       uint32_t sfi_tap_values;                                 /* 0x178 */
        #define PORT_HW_CFG_TX_EQUALIZATION_MASK                      0x0000FFFF
        #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT                     0
 
@@ -522,11 +522,11 @@ struct port_hw_cfg {                  /* port 0: 0x12c  port 1: 0x2bc */
        #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK                     0x000F0000
        #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT                    16
 
-       u32 reserved0[5];                                   /* 0x17c */
+       uint32_t reserved0[5];                              /* 0x17c */
 
-       u32 aeu_int_mask;                                   /* 0x190 */
+       uint32_t aeu_int_mask;                              /* 0x190 */
 
-       u32 media_type;                                     /* 0x194 */
+       uint32_t media_type;                                        /* 0x194 */
        #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK            0x000000FF
        #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT                    0
 
@@ -541,30 +541,30 @@ struct port_hw_cfg {                  /* port 0: 0x12c  port 1: 0x2bc */
              lanes. For some external PHYs (such as 8706 and 8726) the values
              will be used to configure the external PHY  in those cases, not
              all 4 values are needed. */
-       u16 xgxs_config_rx[4];                  /* 0x198 */
-       u16 xgxs_config_tx[4];                  /* 0x1A0 */
+       uint16_t xgxs_config_rx[4];                     /* 0x198 */
+       uint16_t xgxs_config_tx[4];                     /* 0x1A0 */
 
        /* For storing FCOE mac on shared memory */
-       u32 fcoe_fip_mac_upper;
+       uint32_t fcoe_fip_mac_upper;
        #define PORT_HW_CFG_FCOE_UPPERMAC_MASK              0x0000ffff
        #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT                      0
-       u32 fcoe_fip_mac_lower;
+       uint32_t fcoe_fip_mac_lower;
 
-       u32 fcoe_wwn_port_name_upper;
-       u32 fcoe_wwn_port_name_lower;
+       uint32_t fcoe_wwn_port_name_upper;
+       uint32_t fcoe_wwn_port_name_lower;
 
-       u32 fcoe_wwn_node_name_upper;
-       u32 fcoe_wwn_node_name_lower;
+       uint32_t fcoe_wwn_node_name_upper;
+       uint32_t fcoe_wwn_node_name_lower;
 
-       u32 Reserved1[49];                                  /* 0x1C0 */
+       uint32_t Reserved1[49];                             /* 0x1C0 */
 
        /*  Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
              84833 only */
-       u32 xgbt_phy_cfg;                                   /* 0x284 */
+       uint32_t xgbt_phy_cfg;                              /* 0x284 */
        #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK             0x000000FF
        #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT                     0
 
-               u32 default_cfg;                            /* 0x288 */
+               uint32_t default_cfg;                       /* 0x288 */
        #define PORT_HW_CFG_GPIO0_CONFIG_MASK               0x00000003
                #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT               0
                #define PORT_HW_CFG_GPIO0_CONFIG_NA                  0x00000000
@@ -647,7 +647,7 @@ struct port_hw_cfg {                    /* port 0: 0x12c  port 1: 0x2bc */
        #define PORT_HW_CFG_NET_SERDES_IF_KR2                        0x05000000
 
 
-       u32 speed_capability_mask2;                         /* 0x28C */
+       uint32_t speed_capability_mask2;                            /* 0x28C */
        #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK       0x0000FFFF
                #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT       0
                #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL    0x00000001
@@ -675,7 +675,7 @@ struct port_hw_cfg {                    /* port 0: 0x12c  port 1: 0x2bc */
              present and electrically active at the same time, PHY Selection
              will determine which of the two PHYs will be designated as the
              Active PHY and used for a connection to the network.  */
-       u32 multi_phy_config;                               /* 0x290 */
+       uint32_t multi_phy_config;                                  /* 0x290 */
        #define PORT_HW_CFG_PHY_SELECTION_MASK              0x00000007
                #define PORT_HW_CFG_PHY_SELECTION_SHIFT              0
                #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT   0x00000000
@@ -693,7 +693,7 @@ struct port_hw_cfg {                    /* port 0: 0x12c  port 1: 0x2bc */
 
 
        /*  Address of the second external phy */
-       u32 external_phy_config2;                           /* 0x294 */
+       uint32_t external_phy_config2;                      /* 0x294 */
        #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK         0x000000FF
        #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT                 0
 
@@ -724,10 +724,10 @@ struct port_hw_cfg {                  /* port 0: 0x12c  port 1: 0x2bc */
 
        /*  4 times 16 bits for all 4 lanes. For some external PHYs (such as
              8706, 8726 and 8727) not all 4 values are needed. */
-       u16 xgxs_config2_rx[4];                             /* 0x296 */
-       u16 xgxs_config2_tx[4];                             /* 0x2A0 */
+       uint16_t xgxs_config2_rx[4];                                /* 0x296 */
+       uint16_t xgxs_config2_tx[4];                                /* 0x2A0 */
 
-       u32 lane_config;
+       uint32_t lane_config;
        #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
                #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT              0
                /* AN and forced */
@@ -751,7 +751,7 @@ struct port_hw_cfg {                    /* port 0: 0x12c  port 1: 0x2bc */
                #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED        0x00010000
 
 
-       u32 external_phy_config;
+       uint32_t external_phy_config;
        #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
        #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT                  0
 
@@ -789,7 +789,7 @@ struct port_hw_cfg {                    /* port 0: 0x12c  port 1: 0x2bc */
                #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD    0x02000000
                #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN     0xff000000
 
-       u32 speed_capability_mask;
+       uint32_t speed_capability_mask;
        #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
                #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT        0
                #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL     0x00000001
@@ -815,8 +815,8 @@ struct port_hw_cfg {                    /* port 0: 0x12c  port 1: 0x2bc */
                #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED     0xf0000000
 
        /*  A place to hold the original MAC address as a backup */
-       u32 backup_mac_upper;                   /* 0x2B4 */
-       u32 backup_mac_lower;                   /* 0x2B8 */
+       uint32_t backup_mac_upper;                      /* 0x2B4 */
+       uint32_t backup_mac_lower;                      /* 0x2B8 */
 
 };
 
@@ -826,7 +826,7 @@ struct port_hw_cfg {                    /* port 0: 0x12c  port 1: 0x2bc */
  ****************************************************************************/
 struct shared_feat_cfg {                /* NVRAM Offset */
 
-       u32 config;                     /* 0x450 */
+       uint32_t config;                        /* 0x450 */
        #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
 
        /* Use NVRAM values instead of HW default values */
@@ -873,7 +873,7 @@ struct shared_feat_cfg {             /* NVRAM Offset */
  ****************************************************************************/
 struct port_feat_cfg {             /* port 0: 0x454  port 1: 0x4c8 */
 
-       u32 config;
+       uint32_t config;
        #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
                #define PORT_FEATURE_BAR1_SIZE_SHIFT                 0
                #define PORT_FEATURE_BAR1_SIZE_DISABLED              0x00000000
@@ -941,7 +941,7 @@ struct port_feat_cfg {                  /* port 0: 0x454  port 1: 0x4c8 */
                #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG   0x40000000
                #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN    0x60000000
 
-       u32 wol_config;
+       uint32_t wol_config;
        /* Default is used when driver sets to "auto" mode */
        #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
                #define PORT_FEATURE_WOL_DEFAULT_SHIFT               0
@@ -953,7 +953,7 @@ struct port_feat_cfg {                  /* port 0: 0x454  port 1: 0x4c8 */
        #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
        #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
 
-       u32 mba_config;
+       uint32_t mba_config;
        #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000007
                #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT       0
                #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE         0x00000000
@@ -1009,28 +1009,28 @@ struct port_feat_cfg {              /* port 0: 0x454  port 1: 0x4c8 */
                #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS          0x18000000
                #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4       0x1c000000
                #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS           0x20000000
-       u32 bmc_config;
+       uint32_t bmc_config;
        #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK         0x00000001
                #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT       0x00000000
                #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN            0x00000001
 
-       u32 mba_vlan_cfg;
+       uint32_t mba_vlan_cfg;
        #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
        #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT                      0
        #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
 
-       u32 resource_cfg;
+       uint32_t resource_cfg;
        #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
        #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
        #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
        #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
        #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
 
-       u32 smbus_config;
+       uint32_t smbus_config;
        #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
        #define PORT_FEATURE_SMBUS_ADDR_SHIFT                        1
 
-       u32 vf_config;
+       uint32_t vf_config;
        #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK             0x0000000f
                #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT             0
                #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED          0x00000000
@@ -1050,7 +1050,7 @@ struct port_feat_cfg {                /* port 0: 0x454  port 1: 0x4c8 */
                #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M               0x0000000e
                #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M               0x0000000f
 
-       u32 link_config;    /* Used as HW defaults for the driver */
+       uint32_t link_config;    /* Used as HW defaults for the driver */
        #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
                #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT          24
                /* (forced) low speed switch (< 10G) */
@@ -1082,19 +1082,19 @@ struct port_feat_cfg {              /* port 0: 0x454  port 1: 0x4c8 */
 
        /* The default for MCP link configuration,
           uses the same defines as link_config */
-       u32 mfw_wol_link_cfg;
+       uint32_t mfw_wol_link_cfg;
 
        /* The default for the driver of the second external phy,
           uses the same defines as link_config */
-       u32 link_config2;                                   /* 0x47C */
+       uint32_t link_config2;                              /* 0x47C */
 
        /* The default for MCP of the second external phy,
           uses the same defines as link_config */
-       u32 mfw_wol_link_cfg2;                              /* 0x480 */
+       uint32_t mfw_wol_link_cfg2;                                 /* 0x480 */
 
 
        /*  EEE power saving mode */
-       u32 eee_power_mode;                                 /* 0x484 */
+       uint32_t eee_power_mode;                                 /* 0x484 */
        #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK                     0x000000FF
        #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT                    0
        #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED                 0x00000000
@@ -1103,7 +1103,7 @@ struct port_feat_cfg {                /* port 0: 0x454  port 1: 0x4c8 */
        #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY              0x00000003
 
 
-       u32 Reserved2[16];                                  /* 0x488 */
+       uint32_t Reserved2[16];                                  /* 0x488 */
 };
 
 
@@ -1112,7 +1112,7 @@ struct port_feat_cfg {                /* port 0: 0x454  port 1: 0x4c8 */
  ****************************************************************************/
 struct shm_dev_info {                          /* size */
 
-       u32    bc_rev; /* 8 bits each: major, minor, build */          /* 4 */
+       uint32_t    bc_rev; /* 8 bits each: major, minor, build */             /* 4 */
 
        struct shared_hw_cfg     shared_hw_config;            /* 40 */
 
@@ -1172,7 +1172,7 @@ struct shm_dev_info {                             /* size */
  ****************************************************************************/
 struct drv_port_mb {
 
-       u32 link_status;
+       uint32_t link_status;
        /* Driver should update this field on any link change event */
 
        #define LINK_STATUS_NONE                                (0<<0)
@@ -1235,19 +1235,19 @@ struct drv_port_mb {
        #define LINK_STATUS_PHYSICAL_LINK_FLAG                  0x40000000
        #define LINK_STATUS_SFP_TX_FAULT                        0x80000000
 
-       u32 port_stx;
+       uint32_t port_stx;
 
-       u32 stat_nig_timer;
+       uint32_t stat_nig_timer;
 
        /* MCP firmware does not use this field */
-       u32 ext_phy_fw_version;
+       uint32_t ext_phy_fw_version;
 
 };
 
 
 struct drv_func_mb {
 
-       u32 drv_mb_header;
+       uint32_t drv_mb_header;
        #define DRV_MSG_CODE_MASK                       0xffff0000
        #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
        #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
@@ -1320,7 +1320,7 @@ struct drv_func_mb {
 
        #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
 
-       u32 drv_mb_param;
+       uint32_t drv_mb_param;
        #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK         0x00ff0000
        #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK         0xff000000
 
@@ -1329,7 +1329,7 @@ struct drv_func_mb {
        #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA          0x0000100a
        #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA         0x00002000
 
-       u32 fw_mb_header;
+       uint32_t fw_mb_header;
        #define FW_MSG_CODE_MASK                        0xffff0000
        #define FW_MSG_CODE_DRV_LOAD_COMMON             0x10100000
        #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
@@ -1390,9 +1390,9 @@ struct drv_func_mb {
 
        #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
 
-       u32 fw_mb_param;
+       uint32_t fw_mb_param;
 
-       u32 drv_pulse_mb;
+       uint32_t drv_pulse_mb;
        #define DRV_PULSE_SEQ_MASK                      0x00007fff
        #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
        /*
@@ -1406,7 +1406,7 @@ struct drv_func_mb {
         * This is used for debugging as well for PXE(MBA).
         */
 
-       u32 mcp_pulse_mb;
+       uint32_t mcp_pulse_mb;
        #define MCP_PULSE_SEQ_MASK                      0x00007fff
        #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
        /* Indicates to the driver not to assert due to lack
@@ -1414,10 +1414,10 @@ struct drv_func_mb {
        #define MCP_EVENT_MASK                          0xffff0000
        #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
 
-       u32 iscsi_boot_signature;
-       u32 iscsi_boot_block_offset;
+       uint32_t iscsi_boot_signature;
+       uint32_t iscsi_boot_block_offset;
 
-       u32 drv_status;
+       uint32_t drv_status;
        #define DRV_STATUS_PMF                          0x00000001
        #define DRV_STATUS_VF_DISABLED                  0x00000002
        #define DRV_STATUS_SET_MF_BW                    0x00000004
@@ -1449,10 +1449,10 @@ struct drv_func_mb {
 
        #define DRV_STATUS_EEE_NEGOTIATION_RESULTS      0x08000000
 
-       u32 virt_mac_upper;
+       uint32_t virt_mac_upper;
        #define VIRT_MAC_SIGN_MASK                      0xffff0000
        #define VIRT_MAC_SIGNATURE                      0x564d0000
-       u32 virt_mac_lower;
+       uint32_t virt_mac_lower;
 
 };
 
@@ -1464,7 +1464,7 @@ struct drv_func_mb {
 #define MGMTFW_STATE_WORD_SIZE                          110
 
 struct mgmtfw_state {
-       u32 opaque[MGMTFW_STATE_WORD_SIZE];
+       uint32_t opaque[MGMTFW_STATE_WORD_SIZE];
 };
 
 
@@ -1473,7 +1473,7 @@ struct mgmtfw_state {
  ****************************************************************************/
 struct shared_mf_cfg {
 
-       u32 clp_mb;
+       uint32_t clp_mb;
        #define SHARED_MF_CLP_SET_DEFAULT               0x00000000
        /* set by CLP */
        #define SHARED_MF_CLP_EXIT                      0x00000001
@@ -1484,18 +1484,18 @@ struct shared_mf_cfg {
 
 struct port_mf_cfg {
 
-       u32 dynamic_cfg;    /* device control channel */
+       uint32_t dynamic_cfg;    /* device control channel */
        #define PORT_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
        #define PORT_MF_CFG_E1HOV_TAG_SHIFT             0
        #define PORT_MF_CFG_E1HOV_TAG_DEFAULT         PORT_MF_CFG_E1HOV_TAG_MASK
 
-       u32 reserved[1];
+       uint32_t reserved[1];
 
 };
 
 struct func_mf_cfg {
 
-       u32 config;
+       uint32_t config;
        /* E/R/I/D */
        /* function 0 of each port cannot be hidden */
        #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
@@ -1526,14 +1526,14 @@ struct func_mf_cfg {
        #define FUNC_MF_CFG_MAX_BW_SHIFT                24
        #define FUNC_MF_CFG_MAX_BW_DEFAULT              0x64000000
 
-       u32 mac_upper;      /* MAC */
+       uint32_t mac_upper;         /* MAC */
        #define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
        #define FUNC_MF_CFG_UPPERMAC_SHIFT              0
        #define FUNC_MF_CFG_UPPERMAC_DEFAULT           FUNC_MF_CFG_UPPERMAC_MASK
-       u32 mac_lower;
+       uint32_t mac_lower;
        #define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
 
-       u32 e1hov_tag;  /* VNI */
+       uint32_t e1hov_tag;     /* VNI */
        #define FUNC_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
        #define FUNC_MF_CFG_E1HOV_TAG_SHIFT             0
        #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT         FUNC_MF_CFG_E1HOV_TAG_MASK
@@ -1542,7 +1542,7 @@ struct func_mf_cfg {
        #define FUNC_MF_CFG_AFEX_VLAN_MASK              0x0fff0000
        #define FUNC_MF_CFG_AFEX_VLAN_SHIFT             16
 
-       u32 afex_config;
+       uint32_t afex_config;
        #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK                     0x000000ff
        #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT                    0
        #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK                    0x0000ff00
@@ -1551,7 +1551,7 @@ struct func_mf_cfg {
        #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK                      0x000f0000
        #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT                     16
 
-       u32 reserved;
+       uint32_t reserved;
 };
 
 enum mf_cfg_afex_vlan_mode {
@@ -1562,7 +1562,7 @@ enum mf_cfg_afex_vlan_mode {
 
 /* This structure is not applicable and should not be accessed on 57711 */
 struct func_ext_cfg {
-       u32 func_cfg;
+       uint32_t func_cfg;
        #define MACP_FUNC_CFG_FLAGS_MASK                0x0000007F
        #define MACP_FUNC_CFG_FLAGS_SHIFT               0
        #define MACP_FUNC_CFG_FLAGS_ENABLED             0x00000001
@@ -1571,19 +1571,19 @@ struct func_ext_cfg {
        #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD        0x00000008
        #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING        0x00000080
 
-       u32 iscsi_mac_addr_upper;
-       u32 iscsi_mac_addr_lower;
+       uint32_t iscsi_mac_addr_upper;
+       uint32_t iscsi_mac_addr_lower;
 
-       u32 fcoe_mac_addr_upper;
-       u32 fcoe_mac_addr_lower;
+       uint32_t fcoe_mac_addr_upper;
+       uint32_t fcoe_mac_addr_lower;
 
-       u32 fcoe_wwn_port_name_upper;
-       u32 fcoe_wwn_port_name_lower;
+       uint32_t fcoe_wwn_port_name_upper;
+       uint32_t fcoe_wwn_port_name_lower;
 
-       u32 fcoe_wwn_node_name_upper;
-       u32 fcoe_wwn_node_name_lower;
+       uint32_t fcoe_wwn_node_name_upper;
+       uint32_t fcoe_wwn_node_name_lower;
 
-       u32 preserve_data;
+       uint32_t preserve_data;
        #define MF_FUNC_CFG_PRESERVE_L2_MAC             (1<<0)
        #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC          (1<<1)
        #define MF_FUNC_CFG_PRESERVE_FCOE_MAC           (1<<2)
@@ -1611,7 +1611,7 @@ struct mf_cfg {
  ****************************************************************************/
 struct shmem_region {                 /*   SharedMem Offset (size) */
 
-       u32         validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
+       uint32_t         validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
        #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
        #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
        /* validity bits */
@@ -1637,7 +1637,7 @@ struct shmem_region {                    /*   SharedMem Offset (size) */
        struct license_key       drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
 
        /* FW information (for internal FW use) */
-       u32         fw_info_fio_offset;         /* 0x4a8       (0x4) */
+       uint32_t         fw_info_fio_offset;            /* 0x4a8       (0x4) */
        struct mgmtfw_state mgmtfw_state;       /* 0x4ac     (0x1b8) */
 
        struct drv_port_mb  port_mb[PORT_MAX];  /* 0x664 (16*2=0x20) */
@@ -1669,20 +1669,20 @@ struct shmem_region {                  /*   SharedMem Offset (size) */
 /* above                                                                    */
 /****************************************************************************/
 struct fw_flr_ack {
-       u32         pf_ack;
-       u32         vf_ack[1];
-       u32         iov_dis_ack;
+       uint32_t         pf_ack;
+       uint32_t         vf_ack[1];
+       uint32_t         iov_dis_ack;
 };
 
 struct fw_flr_mb {
-       u32         aggint;
-       u32         opgen_addr;
+       uint32_t         aggint;
+       uint32_t         opgen_addr;
        struct fw_flr_ack ack;
 };
 
 struct eee_remote_vals {
-       u32         tx_tw;
-       u32         rx_tw;
+       uint32_t         tx_tw;
+       uint32_t         rx_tw;
 };
 
 /**** SUPPORT FOR SHMEM ARRRAYS ***
@@ -1766,15 +1766,15 @@ struct dcbx_ets_feature {
         * For Admin MIB - is this feature supported by the
         * driver | For Local MIB - should this feature be enabled.
         */
-       u32 enabled;
-       u32  pg_bw_tbl[2];
-       u32  pri_pg_tbl[1];
+       uint32_t enabled;
+       uint32_t  pg_bw_tbl[2];
+       uint32_t  pri_pg_tbl[1];
 };
 
 /* Driver structure in LE */
 struct dcbx_pfc_feature {
 #ifdef __BIG_ENDIAN
-       u8 pri_en_bitmap;
+       uint8_t pri_en_bitmap;
        #define DCBX_PFC_PRI_0 0x01
        #define DCBX_PFC_PRI_1 0x02
        #define DCBX_PFC_PRI_2 0x04
@@ -1783,14 +1783,14 @@ struct dcbx_pfc_feature {
        #define DCBX_PFC_PRI_5 0x20
        #define DCBX_PFC_PRI_6 0x40
        #define DCBX_PFC_PRI_7 0x80
-       u8 pfc_caps;
-       u8 reserved;
-       u8 enabled;
+       uint8_t pfc_caps;
+       uint8_t reserved;
+       uint8_t enabled;
 #elif defined(__LITTLE_ENDIAN)
-       u8 enabled;
-       u8 reserved;
-       u8 pfc_caps;
-       u8 pri_en_bitmap;
+       uint8_t enabled;
+       uint8_t reserved;
+       uint8_t pfc_caps;
+       uint8_t pri_en_bitmap;
        #define DCBX_PFC_PRI_0 0x01
        #define DCBX_PFC_PRI_1 0x02
        #define DCBX_PFC_PRI_2 0x04
@@ -1804,23 +1804,23 @@ struct dcbx_pfc_feature {
 
 struct dcbx_app_priority_entry {
 #ifdef __BIG_ENDIAN
-       u16  app_id;
-       u8  pri_bitmap;
-       u8  appBitfield;
+       uint16_t  app_id;
+       uint8_t  pri_bitmap;
+       uint8_t  appBitfield;
        #define DCBX_APP_ENTRY_VALID         0x01
        #define DCBX_APP_ENTRY_SF_MASK       0x30
        #define DCBX_APP_ENTRY_SF_SHIFT      4
        #define DCBX_APP_SF_ETH_TYPE         0x10
        #define DCBX_APP_SF_PORT             0x20
 #elif defined(__LITTLE_ENDIAN)
-       u8 appBitfield;
+       uint8_t appBitfield;
        #define DCBX_APP_ENTRY_VALID         0x01
        #define DCBX_APP_ENTRY_SF_MASK       0x30
        #define DCBX_APP_ENTRY_SF_SHIFT      4
        #define DCBX_APP_SF_ETH_TYPE         0x10
        #define DCBX_APP_SF_PORT             0x20
-       u8  pri_bitmap;
-       u16  app_id;
+       uint8_t  pri_bitmap;
+       uint16_t  app_id;
 #endif
 };
 
@@ -1828,15 +1828,15 @@ struct dcbx_app_priority_entry {
 /* FW structure in BE */
 struct dcbx_app_priority_feature {
 #ifdef __BIG_ENDIAN
-       u8 reserved;
-       u8 default_pri;
-       u8 tc_supported;
-       u8 enabled;
+       uint8_t reserved;
+       uint8_t default_pri;
+       uint8_t tc_supported;
+       uint8_t enabled;
 #elif defined(__LITTLE_ENDIAN)
-       u8 enabled;
-       u8 tc_supported;
-       u8 default_pri;
-       u8 reserved;
+       uint8_t enabled;
+       uint8_t tc_supported;
+       uint8_t default_pri;
+       uint8_t reserved;
 #endif
        struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
 };
@@ -1855,56 +1855,56 @@ struct dcbx_features {
 /* FW structure in BE */
 struct lldp_params {
 #ifdef __BIG_ENDIAN
-       u8  msg_fast_tx_interval;
-       u8  msg_tx_hold;
-       u8  msg_tx_interval;
-       u8  admin_status;
+       uint8_t  msg_fast_tx_interval;
+       uint8_t  msg_tx_hold;
+       uint8_t  msg_tx_interval;
+       uint8_t  admin_status;
        #define LLDP_TX_ONLY  0x01
        #define LLDP_RX_ONLY  0x02
        #define LLDP_TX_RX    0x03
        #define LLDP_DISABLED 0x04
-       u8  reserved1;
-       u8  tx_fast;
-       u8  tx_crd_max;
-       u8  tx_crd;
+       uint8_t  reserved1;
+       uint8_t  tx_fast;
+       uint8_t  tx_crd_max;
+       uint8_t  tx_crd;
 #elif defined(__LITTLE_ENDIAN)
-       u8  admin_status;
+       uint8_t  admin_status;
        #define LLDP_TX_ONLY  0x01
        #define LLDP_RX_ONLY  0x02
        #define LLDP_TX_RX    0x03
        #define LLDP_DISABLED 0x04
-       u8  msg_tx_interval;
-       u8  msg_tx_hold;
-       u8  msg_fast_tx_interval;
-       u8  tx_crd;
-       u8  tx_crd_max;
-       u8  tx_fast;
-       u8  reserved1;
+       uint8_t  msg_tx_interval;
+       uint8_t  msg_tx_hold;
+       uint8_t  msg_fast_tx_interval;
+       uint8_t  tx_crd;
+       uint8_t  tx_crd_max;
+       uint8_t  tx_fast;
+       uint8_t  reserved1;
 #endif
        #define REM_CHASSIS_ID_STAT_LEN 4
        #define REM_PORT_ID_STAT_LEN 4
        /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
-       u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
+       uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
        /* Holds remote Port ID TLV header, subtype and 9B of payload. */
-       u32 peer_port_id[REM_PORT_ID_STAT_LEN];
+       uint32_t peer_port_id[REM_PORT_ID_STAT_LEN];
 };
 
 struct lldp_dcbx_stat {
        #define LOCAL_CHASSIS_ID_STAT_LEN 2
        #define LOCAL_PORT_ID_STAT_LEN 2
        /* Holds local Chassis ID 8B payload of constant subtype 4. */
-       u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
+       uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
        /* Holds local Port ID 8B payload of constant subtype 3. */
-       u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
+       uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN];
        /* Number of DCBX frames transmitted. */
-       u32 num_tx_dcbx_pkts;
+       uint32_t num_tx_dcbx_pkts;
        /* Number of DCBX frames received. */
-       u32 num_rx_dcbx_pkts;
+       uint32_t num_rx_dcbx_pkts;
 };
 
 /* ADMIN MIB - DCBX local machine default configuration. */
 struct lldp_admin_mib {
-       u32     ver_cfg_flags;
+       uint32_t     ver_cfg_flags;
        #define DCBX_ETS_CONFIG_TX_ENABLED       0x00000001
        #define DCBX_PFC_CONFIG_TX_ENABLED       0x00000002
        #define DCBX_APP_CONFIG_TX_ENABLED       0x00000004
@@ -1925,8 +1925,8 @@ struct lldp_admin_mib {
 
 /* REMOTE MIB - remote machine DCBX configuration. */
 struct lldp_remote_mib {
-       u32 prefix_seq_num;
-       u32 flags;
+       uint32_t prefix_seq_num;
+       uint32_t flags;
        #define DCBX_ETS_TLV_RX                  0x00000001
        #define DCBX_PFC_TLV_RX                  0x00000002
        #define DCBX_APP_TLV_RX                  0x00000004
@@ -1939,14 +1939,14 @@ struct lldp_remote_mib {
        #define DCBX_REMOTE_ETS_RECO_VALID       0x00001000
        #define DCBX_REMOTE_MIB_VALID            0x00002000
        struct dcbx_features features;
-       u32 suffix_seq_num;
+       uint32_t suffix_seq_num;
 };
 
 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
 struct lldp_local_mib {
-       u32 prefix_seq_num;
+       uint32_t prefix_seq_num;
        /* Indicates if there is mismatch with negotiation results. */
-       u32 error;
+       uint32_t error;
        #define DCBX_LOCAL_ETS_ERROR             0x00000001
        #define DCBX_LOCAL_PFC_ERROR             0x00000002
        #define DCBX_LOCAL_APP_ERROR             0x00000004
@@ -1957,7 +1957,7 @@ struct lldp_local_mib {
        #define DCBX_REMOTE_PFC_TLV_NOT_FOUND    0x00000100
        #define DCBX_REMOTE_APP_TLV_NOT_FOUND    0x00000200
        struct dcbx_features   features;
-       u32 suffix_seq_num;
+       uint32_t suffix_seq_num;
 };
 /***END OF DCBX STRUCTURES DECLARATIONS***/
 
@@ -1966,27 +1966,27 @@ struct lldp_local_mib {
 /***********************************************************/
 #define SHMEM_LINK_CONFIG_SIZE 2
 struct shmem_lfa {
-       u32 req_duplex;
+       uint32_t req_duplex;
        #define REQ_DUPLEX_PHY0_MASK        0x0000ffff
        #define REQ_DUPLEX_PHY0_SHIFT       0
        #define REQ_DUPLEX_PHY1_MASK        0xffff0000
        #define REQ_DUPLEX_PHY1_SHIFT       16
-       u32 req_flow_ctrl;
+       uint32_t req_flow_ctrl;
        #define REQ_FLOW_CTRL_PHY0_MASK     0x0000ffff
        #define REQ_FLOW_CTRL_PHY0_SHIFT    0
        #define REQ_FLOW_CTRL_PHY1_MASK     0xffff0000
        #define REQ_FLOW_CTRL_PHY1_SHIFT    16
-       u32 req_line_speed; /* Also determine AutoNeg */
+       uint32_t req_line_speed; /* Also determine AutoNeg */
        #define REQ_LINE_SPD_PHY0_MASK      0x0000ffff
        #define REQ_LINE_SPD_PHY0_SHIFT     0
        #define REQ_LINE_SPD_PHY1_MASK      0xffff0000
        #define REQ_LINE_SPD_PHY1_SHIFT     16
-       u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
-       u32 additional_config;
+       uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
+       uint32_t additional_config;
        #define REQ_FC_AUTO_ADV_MASK        0x0000ffff
        #define REQ_FC_AUTO_ADV0_SHIFT      0
        #define NO_LFA_DUE_TO_DCC_MASK      0x00010000
-       u32 lfa_sts;
+       uint32_t lfa_sts;
        #define LFA_LINK_FLAP_REASON_OFFSET             0
        #define LFA_LINK_FLAP_REASON_MASK               0x000000ff
                #define LFA_LINK_DOWN                       0x1
@@ -2023,46 +2023,46 @@ struct os_drv_ver {
 
        /* shmem2 struct is constant can't add more personalties here */
 #define MAX_DRV_PERS                           3
-       u32 versions[MAX_DRV_PERS];
+       uint32_t versions[MAX_DRV_PERS];
 };
 
 struct ncsi_oem_fcoe_features {
-       u32 fcoe_features1;
+       uint32_t fcoe_features1;
        #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK          0x0000FFFF
        #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET        0
 
        #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK             0xFFFF0000
        #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET           16
 
-       u32 fcoe_features2;
+       uint32_t fcoe_features2;
        #define FCOE_FEATURES2_EXCHANGES_MASK                   0x0000FFFF
        #define FCOE_FEATURES2_EXCHANGES_OFFSET                 0
 
        #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK           0xFFFF0000
        #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET         16
 
-       u32 fcoe_features3;
+       uint32_t fcoe_features3;
        #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK           0x0000FFFF
        #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET         0
 
        #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK        0xFFFF0000
        #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET      16
 
-       u32 fcoe_features4;
+       uint32_t fcoe_features4;
        #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK            0x0000000F
        #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET          0
 };
 
 struct ncsi_oem_data {
-       u32 driver_version[4];
+       uint32_t driver_version[4];
        struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
 };
 
 struct shmem2_region {
 
-       u32 size;                                       /* 0x0000 */
+       uint32_t size;                                  /* 0x0000 */
 
-       u32 dcc_support;                                /* 0x0004 */
+       uint32_t dcc_support;                           /* 0x0004 */
        #define SHMEM_DCC_SUPPORT_NONE                      0x00000000
        #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
        #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
@@ -2070,21 +2070,21 @@ struct shmem2_region {
        #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
        #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080
 
-       u32 ext_phy_fw_version2[PORT_MAX];              /* 0x0008 */
+       uint32_t ext_phy_fw_version2[PORT_MAX];         /* 0x0008 */
        /*
         * For backwards compatibility, if the mf_cfg_addr does not exist
         * (the size filed is smaller than 0xc) the mf_cfg resides at the
         * end of struct shmem_region
         */
-       u32 mf_cfg_addr;                                /* 0x0010 */
+       uint32_t mf_cfg_addr;                           /* 0x0010 */
        #define SHMEM_MF_CFG_ADDR_NONE                  0x00000000
 
        struct fw_flr_mb flr_mb;                        /* 0x0014 */
-       u32 dcbx_lldp_params_offset;                    /* 0x0028 */
+       uint32_t dcbx_lldp_params_offset;                       /* 0x0028 */
        #define SHMEM_LLDP_DCBX_PARAMS_NONE             0x00000000
-       u32 dcbx_neg_res_offset;                        /* 0x002c */
+       uint32_t dcbx_neg_res_offset;                   /* 0x002c */
        #define SHMEM_DCBX_NEG_RES_NONE                 0x00000000
-       u32 dcbx_remote_mib_offset;                     /* 0x0030 */
+       uint32_t dcbx_remote_mib_offset;                        /* 0x0030 */
        #define SHMEM_DCBX_REMOTE_MIB_NONE              0x00000000
        /*
         * The other shmemX_base_addr holds the other path's shmem address
@@ -2092,21 +2092,21 @@ struct shmem2_region {
         * the address of mcp debug trace which is located in offset from shmem
         * of path0
         */
-       u32 other_shmem_base_addr;                      /* 0x0034 */
-       u32 other_shmem2_base_addr;                     /* 0x0038 */
+       uint32_t other_shmem_base_addr;                 /* 0x0034 */
+       uint32_t other_shmem2_base_addr;                        /* 0x0038 */
        /*
         * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
         * which were disabled/flred
         */
-       u32 mcp_vf_disabled[E2_VF_MAX / 32];            /* 0x003c */
+       uint32_t mcp_vf_disabled[E2_VF_MAX / 32];               /* 0x003c */
 
        /*
         * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
         * VFs
         */
-       u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
+       uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
 
-       u32 dcbx_lldp_dcbx_stat_offset;                 /* 0x0064 */
+       uint32_t dcbx_lldp_dcbx_stat_offset;                    /* 0x0064 */
        #define SHMEM_LLDP_DCBX_STAT_NONE               0x00000000
 
        /*
@@ -2118,39 +2118,39 @@ struct shmem2_region {
         * bits 3-5 -  op code / is_ack?
         * bits 6-63 - data
         */
-       u32 edebug_driver_if[2];                        /* 0x0068 */
+       uint32_t edebug_driver_if[2];                   /* 0x0068 */
        #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR  1
        #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR   2
        #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT   3
 
-       u32 nvm_retain_bitmap_addr;                     /* 0x0070 */
+       uint32_t nvm_retain_bitmap_addr;                        /* 0x0070 */
 
        /* afex support of that driver */
-       u32 afex_driver_support;                        /* 0x0074 */
+       uint32_t afex_driver_support;                   /* 0x0074 */
        #define SHMEM_AFEX_VERSION_MASK                  0x100f
        #define SHMEM_AFEX_SUPPORTED_VERSION_ONE         0x1001
        #define SHMEM_AFEX_REDUCED_DRV_LOADED            0x8000
 
        /* driver receives addr in scratchpad to which it should respond */
-       u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX];
+       uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX];
 
        /* generic params from MCP to driver (value depends on the msg sent
         * to driver
         */
-       u32 afex_param1_to_driver[E2_FUNC_MAX];         /* 0x0088 */
-       u32 afex_param2_to_driver[E2_FUNC_MAX];         /* 0x0098 */
+       uint32_t afex_param1_to_driver[E2_FUNC_MAX];            /* 0x0088 */
+       uint32_t afex_param2_to_driver[E2_FUNC_MAX];            /* 0x0098 */
 
-       u32 swim_base_addr;                             /* 0x0108 */
-       u32 swim_funcs;
-       u32 swim_main_cb;
+       uint32_t swim_base_addr;                                /* 0x0108 */
+       uint32_t swim_funcs;
+       uint32_t swim_main_cb;
 
        /* bitmap notifying which VIF profiles stored in nvram are enabled by
         * switch
         */
-       u32 afex_profiles_enabled[2];
+       uint32_t afex_profiles_enabled[2];
 
        /* generic flags controlled by the driver */
-       u32 drv_flags;
+       uint32_t drv_flags;
        #define DRV_FLAGS_DCB_CONFIGURED                0x0
        #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED     0x1
        #define DRV_FLAGS_DCB_MFW_CONFIGURED    0x2
@@ -2159,44 +2159,44 @@ struct shmem2_region {
                        (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
                        (1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
        /* pointer to extended dev_info shared data copied from nvm image */
-       u32 extended_dev_info_shared_addr;
-       u32 ncsi_oem_data_addr;
+       uint32_t extended_dev_info_shared_addr;
+       uint32_t ncsi_oem_data_addr;
 
-       u32 ocsd_host_addr; /* initialized by option ROM */
-       u32 ocbb_host_addr; /* initialized by option ROM */
-       u32 ocsd_req_update_interval; /* initialized by option ROM */
-       u32 temperature_in_half_celsius;
-       u32 glob_struct_in_host;
+       uint32_t ocsd_host_addr; /* initialized by option ROM */
+       uint32_t ocbb_host_addr; /* initialized by option ROM */
+       uint32_t ocsd_req_update_interval; /* initialized by option ROM */
+       uint32_t temperature_in_half_celsius;
+       uint32_t glob_struct_in_host;
 
-       u32 dcbx_neg_res_ext_offset;
+       uint32_t dcbx_neg_res_ext_offset;
 #define SHMEM_DCBX_NEG_RES_EXT_NONE                    0x00000000
 
-       u32 drv_capabilities_flag[E2_FUNC_MAX];
+       uint32_t drv_capabilities_flag[E2_FUNC_MAX];
 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
 #define DRV_FLAGS_CAPABILITIES_LOADED_L2        0x00000002
 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE      0x00000004
 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI     0x00000008
 
-       u32 extended_dev_info_shared_cfg_size;
+       uint32_t extended_dev_info_shared_cfg_size;
 
-       u32 dcbx_en[PORT_MAX];
+       uint32_t dcbx_en[PORT_MAX];
 
        /* The offset points to the multi threaded meta structure */
-       u32 multi_thread_data_offset;
+       uint32_t multi_thread_data_offset;
 
        /* address of DMAable host address holding values from the drivers */
-       u32 drv_info_host_addr_lo;
-       u32 drv_info_host_addr_hi;
+       uint32_t drv_info_host_addr_lo;
+       uint32_t drv_info_host_addr_hi;
 
        /* general values written by the MFW (such as current version) */
-       u32 drv_info_control;
+       uint32_t drv_info_control;
 #define DRV_INFO_CONTROL_VER_MASK          0x000000ff
 #define DRV_INFO_CONTROL_VER_SHIFT         0
 #define DRV_INFO_CONTROL_OP_CODE_MASK      0x0000ff00
 #define DRV_INFO_CONTROL_OP_CODE_SHIFT     8
-       u32 ibft_host_addr; /* initialized by option ROM */
+       uint32_t ibft_host_addr; /* initialized by option ROM */
        struct eee_remote_vals eee_remote_vals[PORT_MAX];
-       u32 reserved[E2_FUNC_MAX];
+       uint32_t reserved[E2_FUNC_MAX];
 
 
        /* the status of EEE auto-negotiation
@@ -2213,7 +2213,7 @@ struct shmem2_region {
         * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
         * value. When 1'b1 those bits contains a value times 16 microseconds.
         */
-       u32 eee_status[PORT_MAX];
+       uint32_t eee_status[PORT_MAX];
        #define SHMEM_EEE_TIMER_MASK               0x0000ffff
        #define SHMEM_EEE_SUPPORTED_MASK           0x000f0000
        #define SHMEM_EEE_SUPPORTED_SHIFT          16
@@ -2229,16 +2229,16 @@ struct shmem2_region {
        #define SHMEM_EEE_ACTIVE_BIT               0x40000000
        #define SHMEM_EEE_TIME_OUTPUT_BIT          0x80000000
 
-       u32 sizeof_port_stats;
+       uint32_t sizeof_port_stats;
 
        /* Link Flap Avoidance */
-       u32 lfa_host_addr[PORT_MAX];
-       u32 reserved1;
+       uint32_t lfa_host_addr[PORT_MAX];
+       uint32_t reserved1;
 
-       u32 reserved2;                          /* Offset 0x148 */
-       u32 reserved3;                          /* Offset 0x14C */
-       u32 reserved4;                          /* Offset 0x150 */
-       u32 link_attr_sync[PORT_MAX];           /* Offset 0x154 */
+       uint32_t reserved2;                             /* Offset 0x148 */
+       uint32_t reserved3;                             /* Offset 0x14C */
+       uint32_t reserved4;                             /* Offset 0x150 */
+       uint32_t link_attr_sync[PORT_MAX];              /* Offset 0x154 */
        #define LINK_ATTR_SYNC_KR2_ENABLE       0x00000001
        #define LINK_SFP_EEPROM_COMP_CODE_MASK  0x0000ff00
        #define LINK_SFP_EEPROM_COMP_CODE_SHIFT          8
@@ -2246,14 +2246,14 @@ struct shmem2_region {
        #define LINK_SFP_EEPROM_COMP_CODE_LR    0x00002000
        #define LINK_SFP_EEPROM_COMP_CODE_LRM   0x00004000
 
-       u32 reserved5[2];
-       u32 reserved6[PORT_MAX];
+       uint32_t reserved5[2];
+       uint32_t reserved6[PORT_MAX];
 
        /* driver version for each personality */
        struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */
 
        /* Flag to the driver that PF's drv_info_host_addr buffer was read  */
-       u32 mfw_drv_indication;
+       uint32_t mfw_drv_indication;
 
        /* We use indication for each PF (0..3) */
 #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))
@@ -2261,275 +2261,275 @@ struct shmem2_region {
 
 
 struct emac_stats {
-       u32     rx_stat_ifhcinoctets;
-       u32     rx_stat_ifhcinbadoctets;
-       u32     rx_stat_etherstatsfragments;
-       u32     rx_stat_ifhcinucastpkts;
-       u32     rx_stat_ifhcinmulticastpkts;
-       u32     rx_stat_ifhcinbroadcastpkts;
-       u32     rx_stat_dot3statsfcserrors;
-       u32     rx_stat_dot3statsalignmenterrors;
-       u32     rx_stat_dot3statscarriersenseerrors;
-       u32     rx_stat_xonpauseframesreceived;
-       u32     rx_stat_xoffpauseframesreceived;
-       u32     rx_stat_maccontrolframesreceived;
-       u32     rx_stat_xoffstateentered;
-       u32     rx_stat_dot3statsframestoolong;
-       u32     rx_stat_etherstatsjabbers;
-       u32     rx_stat_etherstatsundersizepkts;
-       u32     rx_stat_etherstatspkts64octets;
-       u32     rx_stat_etherstatspkts65octetsto127octets;
-       u32     rx_stat_etherstatspkts128octetsto255octets;
-       u32     rx_stat_etherstatspkts256octetsto511octets;
-       u32     rx_stat_etherstatspkts512octetsto1023octets;
-       u32     rx_stat_etherstatspkts1024octetsto1522octets;
-       u32     rx_stat_etherstatspktsover1522octets;
-
-       u32     rx_stat_falsecarriererrors;
-
-       u32     tx_stat_ifhcoutoctets;
-       u32     tx_stat_ifhcoutbadoctets;
-       u32     tx_stat_etherstatscollisions;
-       u32     tx_stat_outxonsent;
-       u32     tx_stat_outxoffsent;
-       u32     tx_stat_flowcontroldone;
-       u32     tx_stat_dot3statssinglecollisionframes;
-       u32     tx_stat_dot3statsmultiplecollisionframes;
-       u32     tx_stat_dot3statsdeferredtransmissions;
-       u32     tx_stat_dot3statsexcessivecollisions;
-       u32     tx_stat_dot3statslatecollisions;
-       u32     tx_stat_ifhcoutucastpkts;
-       u32     tx_stat_ifhcoutmulticastpkts;
-       u32     tx_stat_ifhcoutbroadcastpkts;
-       u32     tx_stat_etherstatspkts64octets;
-       u32     tx_stat_etherstatspkts65octetsto127octets;
-       u32     tx_stat_etherstatspkts128octetsto255octets;
-       u32     tx_stat_etherstatspkts256octetsto511octets;
-       u32     tx_stat_etherstatspkts512octetsto1023octets;
-       u32     tx_stat_etherstatspkts1024octetsto1522octets;
-       u32     tx_stat_etherstatspktsover1522octets;
-       u32     tx_stat_dot3statsinternalmactransmiterrors;
+       uint32_t     rx_stat_ifhcinoctets;
+       uint32_t     rx_stat_ifhcinbadoctets;
+       uint32_t     rx_stat_etherstatsfragments;
+       uint32_t     rx_stat_ifhcinucastpkts;
+       uint32_t     rx_stat_ifhcinmulticastpkts;
+       uint32_t     rx_stat_ifhcinbroadcastpkts;
+       uint32_t     rx_stat_dot3statsfcserrors;
+       uint32_t     rx_stat_dot3statsalignmenterrors;
+       uint32_t     rx_stat_dot3statscarriersenseerrors;
+       uint32_t     rx_stat_xonpauseframesreceived;
+       uint32_t     rx_stat_xoffpauseframesreceived;
+       uint32_t     rx_stat_maccontrolframesreceived;
+       uint32_t     rx_stat_xoffstateentered;
+       uint32_t     rx_stat_dot3statsframestoolong;
+       uint32_t     rx_stat_etherstatsjabbers;
+       uint32_t     rx_stat_etherstatsundersizepkts;
+       uint32_t     rx_stat_etherstatspkts64octets;
+       uint32_t     rx_stat_etherstatspkts65octetsto127octets;
+       uint32_t     rx_stat_etherstatspkts128octetsto255octets;
+       uint32_t     rx_stat_etherstatspkts256octetsto511octets;
+       uint32_t     rx_stat_etherstatspkts512octetsto1023octets;
+       uint32_t     rx_stat_etherstatspkts1024octetsto1522octets;
+       uint32_t     rx_stat_etherstatspktsover1522octets;
+
+       uint32_t     rx_stat_falsecarriererrors;
+
+       uint32_t     tx_stat_ifhcoutoctets;
+       uint32_t     tx_stat_ifhcoutbadoctets;
+       uint32_t     tx_stat_etherstatscollisions;
+       uint32_t     tx_stat_outxonsent;
+       uint32_t     tx_stat_outxoffsent;
+       uint32_t     tx_stat_flowcontroldone;
+       uint32_t     tx_stat_dot3statssinglecollisionframes;
+       uint32_t     tx_stat_dot3statsmultiplecollisionframes;
+       uint32_t     tx_stat_dot3statsdeferredtransmissions;
+       uint32_t     tx_stat_dot3statsexcessivecollisions;
+       uint32_t     tx_stat_dot3statslatecollisions;
+       uint32_t     tx_stat_ifhcoutucastpkts;
+       uint32_t     tx_stat_ifhcoutmulticastpkts;
+       uint32_t     tx_stat_ifhcoutbroadcastpkts;
+       uint32_t     tx_stat_etherstatspkts64octets;
+       uint32_t     tx_stat_etherstatspkts65octetsto127octets;
+       uint32_t     tx_stat_etherstatspkts128octetsto255octets;
+       uint32_t     tx_stat_etherstatspkts256octetsto511octets;
+       uint32_t     tx_stat_etherstatspkts512octetsto1023octets;
+       uint32_t     tx_stat_etherstatspkts1024octetsto1522octets;
+       uint32_t     tx_stat_etherstatspktsover1522octets;
+       uint32_t     tx_stat_dot3statsinternalmactransmiterrors;
 };
 
 
 struct bmac1_stats {
-       u32     tx_stat_gtpkt_lo;
-       u32     tx_stat_gtpkt_hi;
-       u32     tx_stat_gtxpf_lo;
-       u32     tx_stat_gtxpf_hi;
-       u32     tx_stat_gtfcs_lo;
-       u32     tx_stat_gtfcs_hi;
-       u32     tx_stat_gtmca_lo;
-       u32     tx_stat_gtmca_hi;
-       u32     tx_stat_gtbca_lo;
-       u32     tx_stat_gtbca_hi;
-       u32     tx_stat_gtfrg_lo;
-       u32     tx_stat_gtfrg_hi;
-       u32     tx_stat_gtovr_lo;
-       u32     tx_stat_gtovr_hi;
-       u32     tx_stat_gt64_lo;
-       u32     tx_stat_gt64_hi;
-       u32     tx_stat_gt127_lo;
-       u32     tx_stat_gt127_hi;
-       u32     tx_stat_gt255_lo;
-       u32     tx_stat_gt255_hi;
-       u32     tx_stat_gt511_lo;
-       u32     tx_stat_gt511_hi;
-       u32     tx_stat_gt1023_lo;
-       u32     tx_stat_gt1023_hi;
-       u32     tx_stat_gt1518_lo;
-       u32     tx_stat_gt1518_hi;
-       u32     tx_stat_gt2047_lo;
-       u32     tx_stat_gt2047_hi;
-       u32     tx_stat_gt4095_lo;
-       u32     tx_stat_gt4095_hi;
-       u32     tx_stat_gt9216_lo;
-       u32     tx_stat_gt9216_hi;
-       u32     tx_stat_gt16383_lo;
-       u32     tx_stat_gt16383_hi;
-       u32     tx_stat_gtmax_lo;
-       u32     tx_stat_gtmax_hi;
-       u32     tx_stat_gtufl_lo;
-       u32     tx_stat_gtufl_hi;
-       u32     tx_stat_gterr_lo;
-       u32     tx_stat_gterr_hi;
-       u32     tx_stat_gtbyt_lo;
-       u32     tx_stat_gtbyt_hi;
-
-       u32     rx_stat_gr64_lo;
-       u32     rx_stat_gr64_hi;
-       u32     rx_stat_gr127_lo;
-       u32     rx_stat_gr127_hi;
-       u32     rx_stat_gr255_lo;
-       u32     rx_stat_gr255_hi;
-       u32     rx_stat_gr511_lo;
-       u32     rx_stat_gr511_hi;
-       u32     rx_stat_gr1023_lo;
-       u32     rx_stat_gr1023_hi;
-       u32     rx_stat_gr1518_lo;
-       u32     rx_stat_gr1518_hi;
-       u32     rx_stat_gr2047_lo;
-       u32     rx_stat_gr2047_hi;
-       u32     rx_stat_gr4095_lo;
-       u32     rx_stat_gr4095_hi;
-       u32     rx_stat_gr9216_lo;
-       u32     rx_stat_gr9216_hi;
-       u32     rx_stat_gr16383_lo;
-       u32     rx_stat_gr16383_hi;
-       u32     rx_stat_grmax_lo;
-       u32     rx_stat_grmax_hi;
-       u32     rx_stat_grpkt_lo;
-       u32     rx_stat_grpkt_hi;
-       u32     rx_stat_grfcs_lo;
-       u32     rx_stat_grfcs_hi;
-       u32     rx_stat_grmca_lo;
-       u32     rx_stat_grmca_hi;
-       u32     rx_stat_grbca_lo;
-       u32     rx_stat_grbca_hi;
-       u32     rx_stat_grxcf_lo;
-       u32     rx_stat_grxcf_hi;
-       u32     rx_stat_grxpf_lo;
-       u32     rx_stat_grxpf_hi;
-       u32     rx_stat_grxuo_lo;
-       u32     rx_stat_grxuo_hi;
-       u32     rx_stat_grjbr_lo;
-       u32     rx_stat_grjbr_hi;
-       u32     rx_stat_grovr_lo;
-       u32     rx_stat_grovr_hi;
-       u32     rx_stat_grflr_lo;
-       u32     rx_stat_grflr_hi;
-       u32     rx_stat_grmeg_lo;
-       u32     rx_stat_grmeg_hi;
-       u32     rx_stat_grmeb_lo;
-       u32     rx_stat_grmeb_hi;
-       u32     rx_stat_grbyt_lo;
-       u32     rx_stat_grbyt_hi;
-       u32     rx_stat_grund_lo;
-       u32     rx_stat_grund_hi;
-       u32     rx_stat_grfrg_lo;
-       u32     rx_stat_grfrg_hi;
-       u32     rx_stat_grerb_lo;
-       u32     rx_stat_grerb_hi;
-       u32     rx_stat_grfre_lo;
-       u32     rx_stat_grfre_hi;
-       u32     rx_stat_gripj_lo;
-       u32     rx_stat_gripj_hi;
+       uint32_t        tx_stat_gtpkt_lo;
+       uint32_t        tx_stat_gtpkt_hi;
+       uint32_t        tx_stat_gtxpf_lo;
+       uint32_t        tx_stat_gtxpf_hi;
+       uint32_t        tx_stat_gtfcs_lo;
+       uint32_t        tx_stat_gtfcs_hi;
+       uint32_t        tx_stat_gtmca_lo;
+       uint32_t        tx_stat_gtmca_hi;
+       uint32_t        tx_stat_gtbca_lo;
+       uint32_t        tx_stat_gtbca_hi;
+       uint32_t        tx_stat_gtfrg_lo;
+       uint32_t        tx_stat_gtfrg_hi;
+       uint32_t        tx_stat_gtovr_lo;
+       uint32_t        tx_stat_gtovr_hi;
+       uint32_t        tx_stat_gt64_lo;
+       uint32_t        tx_stat_gt64_hi;
+       uint32_t        tx_stat_gt127_lo;
+       uint32_t        tx_stat_gt127_hi;
+       uint32_t        tx_stat_gt255_lo;
+       uint32_t        tx_stat_gt255_hi;
+       uint32_t        tx_stat_gt511_lo;
+       uint32_t        tx_stat_gt511_hi;
+       uint32_t        tx_stat_gt1023_lo;
+       uint32_t        tx_stat_gt1023_hi;
+       uint32_t        tx_stat_gt1518_lo;
+       uint32_t        tx_stat_gt1518_hi;
+       uint32_t        tx_stat_gt2047_lo;
+       uint32_t        tx_stat_gt2047_hi;
+       uint32_t        tx_stat_gt4095_lo;
+       uint32_t        tx_stat_gt4095_hi;
+       uint32_t        tx_stat_gt9216_lo;
+       uint32_t        tx_stat_gt9216_hi;
+       uint32_t        tx_stat_gt16383_lo;
+       uint32_t        tx_stat_gt16383_hi;
+       uint32_t        tx_stat_gtmax_lo;
+       uint32_t        tx_stat_gtmax_hi;
+       uint32_t        tx_stat_gtufl_lo;
+       uint32_t        tx_stat_gtufl_hi;
+       uint32_t        tx_stat_gterr_lo;
+       uint32_t        tx_stat_gterr_hi;
+       uint32_t        tx_stat_gtbyt_lo;
+       uint32_t        tx_stat_gtbyt_hi;
+
+       uint32_t        rx_stat_gr64_lo;
+       uint32_t        rx_stat_gr64_hi;
+       uint32_t        rx_stat_gr127_lo;
+       uint32_t        rx_stat_gr127_hi;
+       uint32_t        rx_stat_gr255_lo;
+       uint32_t        rx_stat_gr255_hi;
+       uint32_t        rx_stat_gr511_lo;
+       uint32_t        rx_stat_gr511_hi;
+       uint32_t        rx_stat_gr1023_lo;
+       uint32_t        rx_stat_gr1023_hi;
+       uint32_t        rx_stat_gr1518_lo;
+       uint32_t        rx_stat_gr1518_hi;
+       uint32_t        rx_stat_gr2047_lo;
+       uint32_t        rx_stat_gr2047_hi;
+       uint32_t        rx_stat_gr4095_lo;
+       uint32_t        rx_stat_gr4095_hi;
+       uint32_t        rx_stat_gr9216_lo;
+       uint32_t        rx_stat_gr9216_hi;
+       uint32_t        rx_stat_gr16383_lo;
+       uint32_t        rx_stat_gr16383_hi;
+       uint32_t        rx_stat_grmax_lo;
+       uint32_t        rx_stat_grmax_hi;
+       uint32_t        rx_stat_grpkt_lo;
+       uint32_t        rx_stat_grpkt_hi;
+       uint32_t        rx_stat_grfcs_lo;
+       uint32_t        rx_stat_grfcs_hi;
+       uint32_t        rx_stat_grmca_lo;
+       uint32_t        rx_stat_grmca_hi;
+       uint32_t        rx_stat_grbca_lo;
+       uint32_t        rx_stat_grbca_hi;
+       uint32_t        rx_stat_grxcf_lo;
+       uint32_t        rx_stat_grxcf_hi;
+       uint32_t        rx_stat_grxpf_lo;
+       uint32_t        rx_stat_grxpf_hi;
+       uint32_t        rx_stat_grxuo_lo;
+       uint32_t        rx_stat_grxuo_hi;
+       uint32_t        rx_stat_grjbr_lo;
+       uint32_t        rx_stat_grjbr_hi;
+       uint32_t        rx_stat_grovr_lo;
+       uint32_t        rx_stat_grovr_hi;
+       uint32_t        rx_stat_grflr_lo;
+       uint32_t        rx_stat_grflr_hi;
+       uint32_t        rx_stat_grmeg_lo;
+       uint32_t        rx_stat_grmeg_hi;
+       uint32_t        rx_stat_grmeb_lo;
+       uint32_t        rx_stat_grmeb_hi;
+       uint32_t        rx_stat_grbyt_lo;
+       uint32_t        rx_stat_grbyt_hi;
+       uint32_t        rx_stat_grund_lo;
+       uint32_t        rx_stat_grund_hi;
+       uint32_t        rx_stat_grfrg_lo;
+       uint32_t        rx_stat_grfrg_hi;
+       uint32_t        rx_stat_grerb_lo;
+       uint32_t        rx_stat_grerb_hi;
+       uint32_t        rx_stat_grfre_lo;
+       uint32_t        rx_stat_grfre_hi;
+       uint32_t        rx_stat_gripj_lo;
+       uint32_t        rx_stat_gripj_hi;
 };
 
 struct bmac2_stats {
-       u32     tx_stat_gtpk_lo; /* gtpok */
-       u32     tx_stat_gtpk_hi; /* gtpok */
-       u32     tx_stat_gtxpf_lo; /* gtpf */
-       u32     tx_stat_gtxpf_hi; /* gtpf */
-       u32     tx_stat_gtpp_lo; /* NEW BMAC2 */
-       u32     tx_stat_gtpp_hi; /* NEW BMAC2 */
-       u32     tx_stat_gtfcs_lo;
-       u32     tx_stat_gtfcs_hi;
-       u32     tx_stat_gtuca_lo; /* NEW BMAC2 */
-       u32     tx_stat_gtuca_hi; /* NEW BMAC2 */
-       u32     tx_stat_gtmca_lo;
-       u32     tx_stat_gtmca_hi;
-       u32     tx_stat_gtbca_lo;
-       u32     tx_stat_gtbca_hi;
-       u32     tx_stat_gtovr_lo;
-       u32     tx_stat_gtovr_hi;
-       u32     tx_stat_gtfrg_lo;
-       u32     tx_stat_gtfrg_hi;
-       u32     tx_stat_gtpkt1_lo; /* gtpkt */
-       u32     tx_stat_gtpkt1_hi; /* gtpkt */
-       u32     tx_stat_gt64_lo;
-       u32     tx_stat_gt64_hi;
-       u32     tx_stat_gt127_lo;
-       u32     tx_stat_gt127_hi;
-       u32     tx_stat_gt255_lo;
-       u32     tx_stat_gt255_hi;
-       u32     tx_stat_gt511_lo;
-       u32     tx_stat_gt511_hi;
-       u32     tx_stat_gt1023_lo;
-       u32     tx_stat_gt1023_hi;
-       u32     tx_stat_gt1518_lo;
-       u32     tx_stat_gt1518_hi;
-       u32     tx_stat_gt2047_lo;
-       u32     tx_stat_gt2047_hi;
-       u32     tx_stat_gt4095_lo;
-       u32     tx_stat_gt4095_hi;
-       u32     tx_stat_gt9216_lo;
-       u32     tx_stat_gt9216_hi;
-       u32     tx_stat_gt16383_lo;
-       u32     tx_stat_gt16383_hi;
-       u32     tx_stat_gtmax_lo;
-       u32     tx_stat_gtmax_hi;
-       u32     tx_stat_gtufl_lo;
-       u32     tx_stat_gtufl_hi;
-       u32     tx_stat_gterr_lo;
-       u32     tx_stat_gterr_hi;
-       u32     tx_stat_gtbyt_lo;
-       u32     tx_stat_gtbyt_hi;
-
-       u32     rx_stat_gr64_lo;
-       u32     rx_stat_gr64_hi;
-       u32     rx_stat_gr127_lo;
-       u32     rx_stat_gr127_hi;
-       u32     rx_stat_gr255_lo;
-       u32     rx_stat_gr255_hi;
-       u32     rx_stat_gr511_lo;
-       u32     rx_stat_gr511_hi;
-       u32     rx_stat_gr1023_lo;
-       u32     rx_stat_gr1023_hi;
-       u32     rx_stat_gr1518_lo;
-       u32     rx_stat_gr1518_hi;
-       u32     rx_stat_gr2047_lo;
-       u32     rx_stat_gr2047_hi;
-       u32     rx_stat_gr4095_lo;
-       u32     rx_stat_gr4095_hi;
-       u32     rx_stat_gr9216_lo;
-       u32     rx_stat_gr9216_hi;
-       u32     rx_stat_gr16383_lo;
-       u32     rx_stat_gr16383_hi;
-       u32     rx_stat_grmax_lo;
-       u32     rx_stat_grmax_hi;
-       u32     rx_stat_grpkt_lo;
-       u32     rx_stat_grpkt_hi;
-       u32     rx_stat_grfcs_lo;
-       u32     rx_stat_grfcs_hi;
-       u32     rx_stat_gruca_lo;
-       u32     rx_stat_gruca_hi;
-       u32     rx_stat_grmca_lo;
-       u32     rx_stat_grmca_hi;
-       u32     rx_stat_grbca_lo;
-       u32     rx_stat_grbca_hi;
-       u32     rx_stat_grxpf_lo; /* grpf */
-       u32     rx_stat_grxpf_hi; /* grpf */
-       u32     rx_stat_grpp_lo;
-       u32     rx_stat_grpp_hi;
-       u32     rx_stat_grxuo_lo; /* gruo */
-       u32     rx_stat_grxuo_hi; /* gruo */
-       u32     rx_stat_grjbr_lo;
-       u32     rx_stat_grjbr_hi;
-       u32     rx_stat_grovr_lo;
-       u32     rx_stat_grovr_hi;
-       u32     rx_stat_grxcf_lo; /* grcf */
-       u32     rx_stat_grxcf_hi; /* grcf */
-       u32     rx_stat_grflr_lo;
-       u32     rx_stat_grflr_hi;
-       u32     rx_stat_grpok_lo;
-       u32     rx_stat_grpok_hi;
-       u32     rx_stat_grmeg_lo;
-       u32     rx_stat_grmeg_hi;
-       u32     rx_stat_grmeb_lo;
-       u32     rx_stat_grmeb_hi;
-       u32     rx_stat_grbyt_lo;
-       u32     rx_stat_grbyt_hi;
-       u32     rx_stat_grund_lo;
-       u32     rx_stat_grund_hi;
-       u32     rx_stat_grfrg_lo;
-       u32     rx_stat_grfrg_hi;
-       u32     rx_stat_grerb_lo; /* grerrbyt */
-       u32     rx_stat_grerb_hi; /* grerrbyt */
-       u32     rx_stat_grfre_lo; /* grfrerr */
-       u32     rx_stat_grfre_hi; /* grfrerr */
-       u32     rx_stat_gripj_lo;
-       u32     rx_stat_gripj_hi;
+       uint32_t        tx_stat_gtpk_lo; /* gtpok */
+       uint32_t        tx_stat_gtpk_hi; /* gtpok */
+       uint32_t        tx_stat_gtxpf_lo; /* gtpf */
+       uint32_t        tx_stat_gtxpf_hi; /* gtpf */
+       uint32_t        tx_stat_gtpp_lo; /* NEW BMAC2 */
+       uint32_t        tx_stat_gtpp_hi; /* NEW BMAC2 */
+       uint32_t        tx_stat_gtfcs_lo;
+       uint32_t        tx_stat_gtfcs_hi;
+       uint32_t        tx_stat_gtuca_lo; /* NEW BMAC2 */
+       uint32_t        tx_stat_gtuca_hi; /* NEW BMAC2 */
+       uint32_t        tx_stat_gtmca_lo;
+       uint32_t        tx_stat_gtmca_hi;
+       uint32_t        tx_stat_gtbca_lo;
+       uint32_t        tx_stat_gtbca_hi;
+       uint32_t        tx_stat_gtovr_lo;
+       uint32_t        tx_stat_gtovr_hi;
+       uint32_t        tx_stat_gtfrg_lo;
+       uint32_t        tx_stat_gtfrg_hi;
+       uint32_t        tx_stat_gtpkt1_lo; /* gtpkt */
+       uint32_t        tx_stat_gtpkt1_hi; /* gtpkt */
+       uint32_t        tx_stat_gt64_lo;
+       uint32_t        tx_stat_gt64_hi;
+       uint32_t        tx_stat_gt127_lo;
+       uint32_t        tx_stat_gt127_hi;
+       uint32_t        tx_stat_gt255_lo;
+       uint32_t        tx_stat_gt255_hi;
+       uint32_t        tx_stat_gt511_lo;
+       uint32_t        tx_stat_gt511_hi;
+       uint32_t        tx_stat_gt1023_lo;
+       uint32_t        tx_stat_gt1023_hi;
+       uint32_t        tx_stat_gt1518_lo;
+       uint32_t        tx_stat_gt1518_hi;
+       uint32_t        tx_stat_gt2047_lo;
+       uint32_t        tx_stat_gt2047_hi;
+       uint32_t        tx_stat_gt4095_lo;
+       uint32_t        tx_stat_gt4095_hi;
+       uint32_t        tx_stat_gt9216_lo;
+       uint32_t        tx_stat_gt9216_hi;
+       uint32_t        tx_stat_gt16383_lo;
+       uint32_t        tx_stat_gt16383_hi;
+       uint32_t        tx_stat_gtmax_lo;
+       uint32_t        tx_stat_gtmax_hi;
+       uint32_t        tx_stat_gtufl_lo;
+       uint32_t        tx_stat_gtufl_hi;
+       uint32_t        tx_stat_gterr_lo;
+       uint32_t        tx_stat_gterr_hi;
+       uint32_t        tx_stat_gtbyt_lo;
+       uint32_t        tx_stat_gtbyt_hi;
+
+       uint32_t        rx_stat_gr64_lo;
+       uint32_t        rx_stat_gr64_hi;
+       uint32_t        rx_stat_gr127_lo;
+       uint32_t        rx_stat_gr127_hi;
+       uint32_t        rx_stat_gr255_lo;
+       uint32_t        rx_stat_gr255_hi;
+       uint32_t        rx_stat_gr511_lo;
+       uint32_t        rx_stat_gr511_hi;
+       uint32_t        rx_stat_gr1023_lo;
+       uint32_t        rx_stat_gr1023_hi;
+       uint32_t        rx_stat_gr1518_lo;
+       uint32_t        rx_stat_gr1518_hi;
+       uint32_t        rx_stat_gr2047_lo;
+       uint32_t        rx_stat_gr2047_hi;
+       uint32_t        rx_stat_gr4095_lo;
+       uint32_t        rx_stat_gr4095_hi;
+       uint32_t        rx_stat_gr9216_lo;
+       uint32_t        rx_stat_gr9216_hi;
+       uint32_t        rx_stat_gr16383_lo;
+       uint32_t        rx_stat_gr16383_hi;
+       uint32_t        rx_stat_grmax_lo;
+       uint32_t        rx_stat_grmax_hi;
+       uint32_t        rx_stat_grpkt_lo;
+       uint32_t        rx_stat_grpkt_hi;
+       uint32_t        rx_stat_grfcs_lo;
+       uint32_t        rx_stat_grfcs_hi;
+       uint32_t        rx_stat_gruca_lo;
+       uint32_t        rx_stat_gruca_hi;
+       uint32_t        rx_stat_grmca_lo;
+       uint32_t        rx_stat_grmca_hi;
+       uint32_t        rx_stat_grbca_lo;
+       uint32_t        rx_stat_grbca_hi;
+       uint32_t        rx_stat_grxpf_lo; /* grpf */
+       uint32_t        rx_stat_grxpf_hi; /* grpf */
+       uint32_t        rx_stat_grpp_lo;
+       uint32_t        rx_stat_grpp_hi;
+       uint32_t        rx_stat_grxuo_lo; /* gruo */
+       uint32_t        rx_stat_grxuo_hi; /* gruo */
+       uint32_t        rx_stat_grjbr_lo;
+       uint32_t        rx_stat_grjbr_hi;
+       uint32_t        rx_stat_grovr_lo;
+       uint32_t        rx_stat_grovr_hi;
+       uint32_t        rx_stat_grxcf_lo; /* grcf */
+       uint32_t        rx_stat_grxcf_hi; /* grcf */
+       uint32_t        rx_stat_grflr_lo;
+       uint32_t        rx_stat_grflr_hi;
+       uint32_t        rx_stat_grpok_lo;
+       uint32_t        rx_stat_grpok_hi;
+       uint32_t        rx_stat_grmeg_lo;
+       uint32_t        rx_stat_grmeg_hi;
+       uint32_t        rx_stat_grmeb_lo;
+       uint32_t        rx_stat_grmeb_hi;
+       uint32_t        rx_stat_grbyt_lo;
+       uint32_t        rx_stat_grbyt_hi;
+       uint32_t        rx_stat_grund_lo;
+       uint32_t        rx_stat_grund_hi;
+       uint32_t        rx_stat_grfrg_lo;
+       uint32_t        rx_stat_grfrg_hi;
+       uint32_t        rx_stat_grerb_lo; /* grerrbyt */
+       uint32_t        rx_stat_grerb_hi; /* grerrbyt */
+       uint32_t        rx_stat_grfre_lo; /* grfrerr */
+       uint32_t        rx_stat_grfre_hi; /* grfrerr */
+       uint32_t        rx_stat_gripj_lo;
+       uint32_t        rx_stat_gripj_hi;
 };
 
 struct mstat_stats {
@@ -2537,124 +2537,124 @@ struct mstat_stats {
                /* OTE MSTAT on E3 has a bug where this register's contents are
                 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
                 */
-               u32 tx_gtxpok_lo;
-               u32 tx_gtxpok_hi;
-               u32 tx_gtxpf_lo;
-               u32 tx_gtxpf_hi;
-               u32 tx_gtxpp_lo;
-               u32 tx_gtxpp_hi;
-               u32 tx_gtfcs_lo;
-               u32 tx_gtfcs_hi;
-               u32 tx_gtuca_lo;
-               u32 tx_gtuca_hi;
-               u32 tx_gtmca_lo;
-               u32 tx_gtmca_hi;
-               u32 tx_gtgca_lo;
-               u32 tx_gtgca_hi;
-               u32 tx_gtpkt_lo;
-               u32 tx_gtpkt_hi;
-               u32 tx_gt64_lo;
-               u32 tx_gt64_hi;
-               u32 tx_gt127_lo;
-               u32 tx_gt127_hi;
-               u32 tx_gt255_lo;
-               u32 tx_gt255_hi;
-               u32 tx_gt511_lo;
-               u32 tx_gt511_hi;
-               u32 tx_gt1023_lo;
-               u32 tx_gt1023_hi;
-               u32 tx_gt1518_lo;
-               u32 tx_gt1518_hi;
-               u32 tx_gt2047_lo;
-               u32 tx_gt2047_hi;
-               u32 tx_gt4095_lo;
-               u32 tx_gt4095_hi;
-               u32 tx_gt9216_lo;
-               u32 tx_gt9216_hi;
-               u32 tx_gt16383_lo;
-               u32 tx_gt16383_hi;
-               u32 tx_gtufl_lo;
-               u32 tx_gtufl_hi;
-               u32 tx_gterr_lo;
-               u32 tx_gterr_hi;
-               u32 tx_gtbyt_lo;
-               u32 tx_gtbyt_hi;
-               u32 tx_collisions_lo;
-               u32 tx_collisions_hi;
-               u32 tx_singlecollision_lo;
-               u32 tx_singlecollision_hi;
-               u32 tx_multiplecollisions_lo;
-               u32 tx_multiplecollisions_hi;
-               u32 tx_deferred_lo;
-               u32 tx_deferred_hi;
-               u32 tx_excessivecollisions_lo;
-               u32 tx_excessivecollisions_hi;
-               u32 tx_latecollisions_lo;
-               u32 tx_latecollisions_hi;
+               uint32_t tx_gtxpok_lo;
+               uint32_t tx_gtxpok_hi;
+               uint32_t tx_gtxpf_lo;
+               uint32_t tx_gtxpf_hi;
+               uint32_t tx_gtxpp_lo;
+               uint32_t tx_gtxpp_hi;
+               uint32_t tx_gtfcs_lo;
+               uint32_t tx_gtfcs_hi;
+               uint32_t tx_gtuca_lo;
+               uint32_t tx_gtuca_hi;
+               uint32_t tx_gtmca_lo;
+               uint32_t tx_gtmca_hi;
+               uint32_t tx_gtgca_lo;
+               uint32_t tx_gtgca_hi;
+               uint32_t tx_gtpkt_lo;
+               uint32_t tx_gtpkt_hi;
+               uint32_t tx_gt64_lo;
+               uint32_t tx_gt64_hi;
+               uint32_t tx_gt127_lo;
+               uint32_t tx_gt127_hi;
+               uint32_t tx_gt255_lo;
+               uint32_t tx_gt255_hi;
+               uint32_t tx_gt511_lo;
+               uint32_t tx_gt511_hi;
+               uint32_t tx_gt1023_lo;
+               uint32_t tx_gt1023_hi;
+               uint32_t tx_gt1518_lo;
+               uint32_t tx_gt1518_hi;
+               uint32_t tx_gt2047_lo;
+               uint32_t tx_gt2047_hi;
+               uint32_t tx_gt4095_lo;
+               uint32_t tx_gt4095_hi;
+               uint32_t tx_gt9216_lo;
+               uint32_t tx_gt9216_hi;
+               uint32_t tx_gt16383_lo;
+               uint32_t tx_gt16383_hi;
+               uint32_t tx_gtufl_lo;
+               uint32_t tx_gtufl_hi;
+               uint32_t tx_gterr_lo;
+               uint32_t tx_gterr_hi;
+               uint32_t tx_gtbyt_lo;
+               uint32_t tx_gtbyt_hi;
+