Port over linux 4.1.15 mlx4 kernel bypass driver
authorKanoj Sarcar' via Akaros <akaros@googlegroups.com>
Wed, 10 Feb 2016 23:54:30 +0000 (15:54 -0800)
committerBarret Rhoden <brho@cs.berkeley.edu>
Wed, 17 Feb 2016 22:23:14 +0000 (17:23 -0500)
Port over linux 4.1.15 drivers/infiniband/hw/mlx4 logic essential for
kernel bypass NIC access. Slight edits to adapt to Akaros environment
(#if exclusion of non essential code blocks, panic stubs etc), described
in README file.

Signed-off-by: Kanoj Sarcar <kanoj@google.com>
Signed-off-by: Barret Rhoden <brho@cs.berkeley.edu>
kern/drivers/net/mlx4u/Kconfig [new file with mode: 0644]
kern/drivers/net/mlx4u/Makefile [new file with mode: 0644]
kern/drivers/net/mlx4u/README [new file with mode: 0644]
kern/drivers/net/mlx4u/cq.c [new file with mode: 0644]
kern/drivers/net/mlx4u/doorbell.c [new file with mode: 0644]
kern/drivers/net/mlx4u/main.c [new file with mode: 0644]
kern/drivers/net/mlx4u/mlx4_ib.h [new file with mode: 0644]
kern/drivers/net/mlx4u/mr.c [new file with mode: 0644]
kern/drivers/net/mlx4u/qp.c [new file with mode: 0644]
kern/drivers/net/mlx4u/srq.c [new file with mode: 0644]
kern/drivers/net/mlx4u/user.h [new file with mode: 0644]

diff --git a/kern/drivers/net/mlx4u/Kconfig b/kern/drivers/net/mlx4u/Kconfig
new file mode 100644 (file)
index 0000000..fc01dea
--- /dev/null
@@ -0,0 +1,10 @@
+config MLX4_INFINIBAND
+       tristate "Mellanox ConnectX HCA support"
+       depends on NETDEVICES && ETHERNET && PCI && INET
+       select NET_VENDOR_MELLANOX
+       select MLX4_CORE
+       ---help---
+         This driver provides low-level InfiniBand support for
+         Mellanox ConnectX PCI Express host channel adapters (HCAs).
+         This is required to use InfiniBand protocols such as
+         IP-over-IB or SRP with these devices.
diff --git a/kern/drivers/net/mlx4u/Makefile b/kern/drivers/net/mlx4u/Makefile
new file mode 100644 (file)
index 0000000..62b4719
--- /dev/null
@@ -0,0 +1,6 @@
+obj-$(CONFIG_MLX4_INFINIBAND)  += mlx4_ib.o
+
+CFLAGS_KERNEL += -include kern/drivers/net/udrvr/compat.h -Wno-pointer-sign
+
+#mlx4_ib-y :=  ah.o cq.o doorbell.o mad.o main.o mr.o qp.o srq.o mcg.o cm.o alias_GUID.o sysfs.o
+mlx4_ib-y :=   cq.o doorbell.o main.o mr.o qp.o srq.o
diff --git a/kern/drivers/net/mlx4u/README b/kern/drivers/net/mlx4u/README
new file mode 100644 (file)
index 0000000..a113e94
--- /dev/null
@@ -0,0 +1,41 @@
+This directory contains logic for priviledged verbs aka user mode control
+path to support libibverbs. It is based off linux-4.1.15 snapshot of
+drivers/infiniband/hw/mlx4/. Changes on top of baseline are described
+here.
+
+Some common reasons for changes to baseline source:
+
+HF1:   Linux source code that #includes standard linux header files eg
+       linux/list.h, linux/idr.h had to be modified since these headers
+       are absent in akaros.
+
+HF2:   Headers copied from Linux eg rdma/ib_verbs.h were placed in akaros
+       in linux/rdma/ib_verbs.h.
+
+HF3:   Some changes were done to pull in lesser header files from Linux.
+
+Per file listing of changes:
+
+user.h, cq.c, doorbell.c, mr.c, srq.c, qp.c, mlx4_ib.h, main.c:        HF1
+main.c: HF2
+mlx4_ib.h: HF3 (ib_sa.h)
+
+qp.c:  Avoid compiling/linking big chunk of code, while providing
+       panic-stub mandatory function vectors (checked by
+       ib_device_check_mandatory()).
+
+main.c:        Stubs to reduce including other mlx4/ source files.
+       Akaros version of mlx4_ib_mmap()
+       Akaros does not have dev->dev->persist->pdev->device
+       Akaros does not have dev->persist->pdev->bus->name
+       Sysfs elimination
+       Reduced uverbs_cmd_mask and mlx4 function vector for minimal support
+       No register_netdevice_notifier() and register_inetaddr_notifier()
+       No netdev/inet events ... generally no netdev hook up
+       Panic-stub eth_link_query_port() because dependencies on netdev
+
+Makefile: Compilation of this directory depends on CONFIG_MLX4_INFINIBAND,
+       which must be selected in build config. Use -Wno-pointer-sign (for
+       main.c mlx4_ib_add() mlx4_counter_alloc() call) and -include local
+       compatibility header file (sometimes overriding akaros compatibility
+       definitions).
diff --git a/kern/drivers/net/mlx4u/cq.c b/kern/drivers/net/mlx4u/cq.c
new file mode 100644 (file)
index 0000000..9ce6bf8
--- /dev/null
@@ -0,0 +1,983 @@
+/*
+ * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
+ * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <linux/mlx4/cq.h>
+#include <linux/mlx4/qp.h>
+#include <linux/mlx4/srq.h>
+//#include <linux/slab.h>      /* AKAROS */
+
+#include "mlx4_ib.h"
+#include "user.h"
+
+static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
+{
+       struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
+       ibcq->comp_handler(ibcq, ibcq->cq_context);
+}
+
+static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
+{
+       struct ib_event event;
+       struct ib_cq *ibcq;
+
+       if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
+               pr_warn("Unexpected event type %d "
+                      "on CQ %06x\n", type, cq->cqn);
+               return;
+       }
+
+       ibcq = &to_mibcq(cq)->ibcq;
+       if (ibcq->event_handler) {
+               event.device     = ibcq->device;
+               event.event      = IB_EVENT_CQ_ERR;
+               event.element.cq = ibcq;
+               ibcq->event_handler(&event, ibcq->cq_context);
+       }
+}
+
+static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
+{
+       return mlx4_buf_offset(&buf->buf, n * buf->entry_size);
+}
+
+static void *get_cqe(struct mlx4_ib_cq *cq, int n)
+{
+       return get_cqe_from_buf(&cq->buf, n);
+}
+
+static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
+{
+       struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
+       struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe);
+
+       return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
+               !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
+}
+
+static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
+{
+       return get_sw_cqe(cq, cq->mcq.cons_index);
+}
+
+int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
+{
+       struct mlx4_ib_cq *mcq = to_mcq(cq);
+       struct mlx4_ib_dev *dev = to_mdev(cq->device);
+
+       return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
+}
+
+static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
+{
+       int err;
+
+       err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size,
+                            PAGE_SIZE * 2, &buf->buf, GFP_KERNEL);
+
+       if (err)
+               goto out;
+
+       buf->entry_size = dev->dev->caps.cqe_size;
+       err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
+                                   &buf->mtt);
+       if (err)
+               goto err_buf;
+
+       err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf, GFP_KERNEL);
+       if (err)
+               goto err_mtt;
+
+       return 0;
+
+err_mtt:
+       mlx4_mtt_cleanup(dev->dev, &buf->mtt);
+
+err_buf:
+       mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf);
+
+out:
+       return err;
+}
+
+static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
+{
+       mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf);
+}
+
+static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context,
+                              struct mlx4_ib_cq_buf *buf, struct ib_umem **umem,
+                              u64 buf_addr, int cqe)
+{
+       int err;
+       int cqe_size = dev->dev->caps.cqe_size;
+
+       *umem = ib_umem_get(context, buf_addr, cqe * cqe_size,
+                           IB_ACCESS_LOCAL_WRITE, 1);
+       if (IS_ERR(*umem))
+               return PTR_ERR(*umem);
+
+       err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem),
+                           ilog2((*umem)->page_size), &buf->mtt);
+       if (err)
+               goto err_buf;
+
+       err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
+       if (err)
+               goto err_mtt;
+
+       return 0;
+
+err_mtt:
+       mlx4_mtt_cleanup(dev->dev, &buf->mtt);
+
+err_buf:
+       ib_umem_release(*umem);
+
+       return err;
+}
+
+struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector,
+                               struct ib_ucontext *context,
+                               struct ib_udata *udata)
+{
+       struct mlx4_ib_dev *dev = to_mdev(ibdev);
+       struct mlx4_ib_cq *cq;
+       struct mlx4_uar *uar;
+       int err;
+
+       if (entries < 1 || entries > dev->dev->caps.max_cqes)
+               return ERR_PTR(-EINVAL);
+
+       cq = kmalloc(sizeof *cq, GFP_KERNEL);
+       if (!cq)
+               return ERR_PTR(-ENOMEM);
+
+       entries      = roundup_pow_of_two(entries + 1);
+       cq->ibcq.cqe = entries - 1;
+       mutex_init(&cq->resize_mutex);
+       spin_lock_init(&cq->lock);
+       cq->resize_buf = NULL;
+       cq->resize_umem = NULL;
+       INIT_LIST_HEAD(&cq->send_qp_list);
+       INIT_LIST_HEAD(&cq->recv_qp_list);
+
+       if (context) {
+               struct mlx4_ib_create_cq ucmd;
+
+               if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
+                       err = -EFAULT;
+                       goto err_cq;
+               }
+
+               err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem,
+                                         ucmd.buf_addr, entries);
+               if (err)
+                       goto err_cq;
+
+               err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
+                                         &cq->db);
+               if (err)
+                       goto err_mtt;
+
+               uar = &to_mucontext(context)->uar;
+       } else {
+               err = mlx4_db_alloc(dev->dev, &cq->db, 1, GFP_KERNEL);
+               if (err)
+                       goto err_cq;
+
+               cq->mcq.set_ci_db  = cq->db.db;
+               cq->mcq.arm_db     = cq->db.db + 1;
+               *cq->mcq.set_ci_db = 0;
+               *cq->mcq.arm_db    = 0;
+
+               err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
+               if (err)
+                       goto err_db;
+
+               uar = &dev->priv_uar;
+       }
+
+       if (dev->eq_table)
+               vector = dev->eq_table[vector % ibdev->num_comp_vectors];
+
+       err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar,
+                           cq->db.dma, &cq->mcq, vector, 0, 0);
+       if (err)
+               goto err_dbmap;
+
+       if (context)
+               cq->mcq.tasklet_ctx.comp = mlx4_ib_cq_comp;
+       else
+               cq->mcq.comp = mlx4_ib_cq_comp;
+       cq->mcq.event = mlx4_ib_cq_event;
+
+       if (context)
+               if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
+                       err = -EFAULT;
+                       goto err_dbmap;
+               }
+
+       return &cq->ibcq;
+
+err_dbmap:
+       if (context)
+               mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);
+
+err_mtt:
+       mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
+
+       if (context)
+               ib_umem_release(cq->umem);
+       else
+               mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
+
+err_db:
+       if (!context)
+               mlx4_db_free(dev->dev, &cq->db);
+
+err_cq:
+       kfree(cq);
+
+       return ERR_PTR(err);
+}
+
+static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
+                                 int entries)
+{
+       int err;
+
+       if (cq->resize_buf)
+               return -EBUSY;
+
+       cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
+       if (!cq->resize_buf)
+               return -ENOMEM;
+
+       err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
+       if (err) {
+               kfree(cq->resize_buf);
+               cq->resize_buf = NULL;
+               return err;
+       }
+
+       cq->resize_buf->cqe = entries - 1;
+
+       return 0;
+}
+
+static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
+                                  int entries, struct ib_udata *udata)
+{
+       struct mlx4_ib_resize_cq ucmd;
+       int err;
+
+       if (cq->resize_umem)
+               return -EBUSY;
+
+       if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
+               return -EFAULT;
+
+       cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
+       if (!cq->resize_buf)
+               return -ENOMEM;
+
+       err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf,
+                                 &cq->resize_umem, ucmd.buf_addr, entries);
+       if (err) {
+               kfree(cq->resize_buf);
+               cq->resize_buf = NULL;
+               return err;
+       }
+
+       cq->resize_buf->cqe = entries - 1;
+
+       return 0;
+}
+
+static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
+{
+       u32 i;
+
+       i = cq->mcq.cons_index;
+       while (get_sw_cqe(cq, i))
+               ++i;
+
+       return i - cq->mcq.cons_index;
+}
+
+static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
+{
+       struct mlx4_cqe *cqe, *new_cqe;
+       int i;
+       int cqe_size = cq->buf.entry_size;
+       int cqe_inc = cqe_size == 64 ? 1 : 0;
+
+       i = cq->mcq.cons_index;
+       cqe = get_cqe(cq, i & cq->ibcq.cqe);
+       cqe += cqe_inc;
+
+       while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
+               new_cqe = get_cqe_from_buf(&cq->resize_buf->buf,
+                                          (i + 1) & cq->resize_buf->cqe);
+               memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size);
+               new_cqe += cqe_inc;
+
+               new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |
+                       (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0);
+               cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
+               cqe += cqe_inc;
+       }
+       ++cq->mcq.cons_index;
+}
+
+int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
+{
+       struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
+       struct mlx4_ib_cq *cq = to_mcq(ibcq);
+       struct mlx4_mtt mtt;
+       int outst_cqe;
+       int err;
+
+       mutex_lock(&cq->resize_mutex);
+       if (entries < 1 || entries > dev->dev->caps.max_cqes) {
+               err = -EINVAL;
+               goto out;
+       }
+
+       entries = roundup_pow_of_two(entries + 1);
+       if (entries == ibcq->cqe + 1) {
+               err = 0;
+               goto out;
+       }
+
+       if (entries > dev->dev->caps.max_cqes + 1) {
+               err = -EINVAL;
+               goto out;
+       }
+
+       if (ibcq->uobject) {
+               err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
+               if (err)
+                       goto out;
+       } else {
+               /* Can't be smaller than the number of outstanding CQEs */
+               outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
+               if (entries < outst_cqe + 1) {
+                       err = -EINVAL;
+                       goto out;
+               }
+
+               err = mlx4_alloc_resize_buf(dev, cq, entries);
+               if (err)
+                       goto out;
+       }
+
+       mtt = cq->buf.mtt;
+
+       err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
+       if (err)
+               goto err_buf;
+
+       mlx4_mtt_cleanup(dev->dev, &mtt);
+       if (ibcq->uobject) {
+               cq->buf      = cq->resize_buf->buf;
+               cq->ibcq.cqe = cq->resize_buf->cqe;
+               ib_umem_release(cq->umem);
+               cq->umem     = cq->resize_umem;
+
+               kfree(cq->resize_buf);
+               cq->resize_buf = NULL;
+               cq->resize_umem = NULL;
+       } else {
+               struct mlx4_ib_cq_buf tmp_buf;
+               int tmp_cqe = 0;
+
+               spin_lock_irq(&cq->lock);
+               if (cq->resize_buf) {
+                       mlx4_ib_cq_resize_copy_cqes(cq);
+                       tmp_buf = cq->buf;
+                       tmp_cqe = cq->ibcq.cqe;
+                       cq->buf      = cq->resize_buf->buf;
+                       cq->ibcq.cqe = cq->resize_buf->cqe;
+
+                       kfree(cq->resize_buf);
+                       cq->resize_buf = NULL;
+               }
+               spin_unlock_irq(&cq->lock);
+
+               if (tmp_cqe)
+                       mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe);
+       }
+
+       goto out;
+
+err_buf:
+       mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt);
+       if (!ibcq->uobject)
+               mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
+                                   cq->resize_buf->cqe);
+
+       kfree(cq->resize_buf);
+       cq->resize_buf = NULL;
+
+       if (cq->resize_umem) {
+               ib_umem_release(cq->resize_umem);
+               cq->resize_umem = NULL;
+       }
+
+out:
+       mutex_unlock(&cq->resize_mutex);
+
+       return err;
+}
+
+int mlx4_ib_destroy_cq(struct ib_cq *cq)
+{
+       struct mlx4_ib_dev *dev = to_mdev(cq->device);
+       struct mlx4_ib_cq *mcq = to_mcq(cq);
+
+       mlx4_cq_free(dev->dev, &mcq->mcq);
+       mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
+
+       if (cq->uobject) {
+               mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db);
+               ib_umem_release(mcq->umem);
+       } else {
+               mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
+               mlx4_db_free(dev->dev, &mcq->db);
+       }
+
+       kfree(mcq);
+
+       return 0;
+}
+
+static void dump_cqe(void *cqe)
+{
+       __be32 *buf = cqe;
+
+       pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
+              be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
+              be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
+              be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
+}
+
+static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
+                                    struct ib_wc *wc)
+{
+       if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
+               pr_debug("local QP operation err "
+                      "(QPN %06x, WQE index %x, vendor syndrome %02x, "
+                      "opcode = %02x)\n",
+                      be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
+                      cqe->vendor_err_syndrome,
+                      cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
+               dump_cqe(cqe);
+       }
+
+       switch (cqe->syndrome) {
+       case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
+               wc->status = IB_WC_LOC_LEN_ERR;
+               break;
+       case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
+               wc->status = IB_WC_LOC_QP_OP_ERR;
+               break;
+       case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
+               wc->status = IB_WC_LOC_PROT_ERR;
+               break;
+       case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
+               wc->status = IB_WC_WR_FLUSH_ERR;
+               break;
+       case MLX4_CQE_SYNDROME_MW_BIND_ERR:
+               wc->status = IB_WC_MW_BIND_ERR;
+               break;
+       case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
+               wc->status = IB_WC_BAD_RESP_ERR;
+               break;
+       case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
+               wc->status = IB_WC_LOC_ACCESS_ERR;
+               break;
+       case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
+               wc->status = IB_WC_REM_INV_REQ_ERR;
+               break;
+       case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
+               wc->status = IB_WC_REM_ACCESS_ERR;
+               break;
+       case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
+               wc->status = IB_WC_REM_OP_ERR;
+               break;
+       case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
+               wc->status = IB_WC_RETRY_EXC_ERR;
+               break;
+       case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
+               wc->status = IB_WC_RNR_RETRY_EXC_ERR;
+               break;
+       case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
+               wc->status = IB_WC_REM_ABORT_ERR;
+               break;
+       default:
+               wc->status = IB_WC_GENERAL_ERR;
+               break;
+       }
+
+       wc->vendor_err = cqe->vendor_err_syndrome;
+}
+
+static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
+{
+       return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4      |
+                                     MLX4_CQE_STATUS_IPV4F     |
+                                     MLX4_CQE_STATUS_IPV4OPT   |
+                                     MLX4_CQE_STATUS_IPV6      |
+                                     MLX4_CQE_STATUS_IPOK)) ==
+               cpu_to_be16(MLX4_CQE_STATUS_IPV4        |
+                           MLX4_CQE_STATUS_IPOK))              &&
+               (status & cpu_to_be16(MLX4_CQE_STATUS_UDP       |
+                                     MLX4_CQE_STATUS_TCP))     &&
+               checksum == cpu_to_be16(0xffff);
+}
+
+static int use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc,
+                          unsigned tail, struct mlx4_cqe *cqe, int is_eth)
+{
+       struct mlx4_ib_proxy_sqp_hdr *hdr;
+
+       ib_dma_sync_single_for_cpu(qp->ibqp.device,
+                                  qp->sqp_proxy_rcv[tail].map,
+                                  sizeof (struct mlx4_ib_proxy_sqp_hdr),
+                                  DMA_FROM_DEVICE);
+       hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr);
+       wc->pkey_index  = be16_to_cpu(hdr->tun.pkey_index);
+       wc->src_qp      = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF;
+       wc->wc_flags   |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0;
+       wc->dlid_path_bits = 0;
+
+       if (is_eth) {
+               wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid);
+               memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4);
+               memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2);
+               wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
+       } else {
+               wc->slid        = be16_to_cpu(hdr->tun.slid_mac_47_32);
+               wc->sl          = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12);
+       }
+
+       return 0;
+}
+
+static void mlx4_ib_qp_sw_comp(struct mlx4_ib_qp *qp, int num_entries,
+                              struct ib_wc *wc, int *npolled, int is_send)
+{
+       struct mlx4_ib_wq *wq;
+       unsigned cur;
+       int i;
+
+       wq = is_send ? &qp->sq : &qp->rq;
+       cur = wq->head - wq->tail;
+
+       if (cur == 0)
+               return;
+
+       for (i = 0;  i < cur && *npolled < num_entries; i++) {
+               wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
+               wc->status = IB_WC_WR_FLUSH_ERR;
+               wc->vendor_err = MLX4_CQE_SYNDROME_WR_FLUSH_ERR;
+               wq->tail++;
+               (*npolled)++;
+               wc->qp = &qp->ibqp;
+               wc++;
+       }
+}
+
+static void mlx4_ib_poll_sw_comp(struct mlx4_ib_cq *cq, int num_entries,
+                                struct ib_wc *wc, int *npolled)
+{
+       struct mlx4_ib_qp *qp;
+
+       *npolled = 0;
+       /* Find uncompleted WQEs belonging to that cq and retrun
+        * simulated FLUSH_ERR completions
+        */
+       list_for_each_entry(qp, &cq->send_qp_list, cq_send_list) {
+               mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 1);
+               if (*npolled >= num_entries)
+                       goto out;
+       }
+
+       list_for_each_entry(qp, &cq->recv_qp_list, cq_recv_list) {
+               mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 0);
+               if (*npolled >= num_entries)
+                       goto out;
+       }
+
+out:
+       return;
+}
+
+static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
+                           struct mlx4_ib_qp **cur_qp,
+                           struct ib_wc *wc)
+{
+       struct mlx4_cqe *cqe;
+       struct mlx4_qp *mqp;
+       struct mlx4_ib_wq *wq;
+       struct mlx4_ib_srq *srq;
+       struct mlx4_srq *msrq = NULL;
+       int is_send;
+       int is_error;
+       int is_eth;
+       u32 g_mlpath_rqpn;
+       u16 wqe_ctr;
+       unsigned tail = 0;
+
+repoll:
+       cqe = next_cqe_sw(cq);
+       if (!cqe)
+               return -EAGAIN;
+
+       if (cq->buf.entry_size == 64)
+               cqe++;
+
+       ++cq->mcq.cons_index;
+
+       /*
+        * Make sure we read CQ entry contents after we've checked the
+        * ownership bit.
+        */
+       rmb();
+
+       is_send  = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
+       is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
+               MLX4_CQE_OPCODE_ERROR;
+
+       if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP &&
+                    is_send)) {
+               pr_warn("Completion for NOP opcode detected!\n");
+               return -EINVAL;
+       }
+
+       /* Resize CQ in progress */
+       if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
+               if (cq->resize_buf) {
+                       struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
+
+                       mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
+                       cq->buf      = cq->resize_buf->buf;
+                       cq->ibcq.cqe = cq->resize_buf->cqe;
+
+                       kfree(cq->resize_buf);
+                       cq->resize_buf = NULL;
+               }
+
+               goto repoll;
+       }
+
+       if (!*cur_qp ||
+           (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
+               /*
+                * We do not have to take the QP table lock here,
+                * because CQs will be locked while QPs are removed
+                * from the table.
+                */
+               mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
+                                      be32_to_cpu(cqe->vlan_my_qpn));
+               if (unlikely(!mqp)) {
+                       pr_warn("CQ %06x with entry for unknown QPN %06x\n",
+                              cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK);
+                       return -EINVAL;
+               }
+
+               *cur_qp = to_mibqp(mqp);
+       }
+
+       wc->qp = &(*cur_qp)->ibqp;
+
+       if (wc->qp->qp_type == IB_QPT_XRC_TGT) {
+               u32 srq_num;
+               g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
+               srq_num       = g_mlpath_rqpn & 0xffffff;
+               /* SRQ is also in the radix tree */
+               msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev,
+                                      srq_num);
+               if (unlikely(!msrq)) {
+                       pr_warn("CQ %06x with entry for unknown SRQN %06x\n",
+                               cq->mcq.cqn, srq_num);
+                       return -EINVAL;
+               }
+       }
+
+       if (is_send) {
+               wq = &(*cur_qp)->sq;
+               if (!(*cur_qp)->sq_signal_bits) {
+                       wqe_ctr = be16_to_cpu(cqe->wqe_index);
+                       wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
+               }
+               wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
+               ++wq->tail;
+       } else if ((*cur_qp)->ibqp.srq) {
+               srq = to_msrq((*cur_qp)->ibqp.srq);
+               wqe_ctr = be16_to_cpu(cqe->wqe_index);
+               wc->wr_id = srq->wrid[wqe_ctr];
+               mlx4_ib_free_srq_wqe(srq, wqe_ctr);
+       } else if (msrq) {
+               srq = to_mibsrq(msrq);
+               wqe_ctr = be16_to_cpu(cqe->wqe_index);
+               wc->wr_id = srq->wrid[wqe_ctr];
+               mlx4_ib_free_srq_wqe(srq, wqe_ctr);
+       } else {
+               wq        = &(*cur_qp)->rq;
+               tail      = wq->tail & (wq->wqe_cnt - 1);
+               wc->wr_id = wq->wrid[tail];
+               ++wq->tail;
+       }
+
+       if (unlikely(is_error)) {
+               mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
+               return 0;
+       }
+
+       wc->status = IB_WC_SUCCESS;
+
+       if (is_send) {
+               wc->wc_flags = 0;
+               switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
+               case MLX4_OPCODE_RDMA_WRITE_IMM:
+                       wc->wc_flags |= IB_WC_WITH_IMM;
+               case MLX4_OPCODE_RDMA_WRITE:
+                       wc->opcode    = IB_WC_RDMA_WRITE;
+                       break;
+               case MLX4_OPCODE_SEND_IMM:
+                       wc->wc_flags |= IB_WC_WITH_IMM;
+               case MLX4_OPCODE_SEND:
+               case MLX4_OPCODE_SEND_INVAL:
+                       wc->opcode    = IB_WC_SEND;
+                       break;
+               case MLX4_OPCODE_RDMA_READ:
+                       wc->opcode    = IB_WC_RDMA_READ;
+                       wc->byte_len  = be32_to_cpu(cqe->byte_cnt);
+                       break;
+               case MLX4_OPCODE_ATOMIC_CS:
+                       wc->opcode    = IB_WC_COMP_SWAP;
+                       wc->byte_len  = 8;
+                       break;
+               case MLX4_OPCODE_ATOMIC_FA:
+                       wc->opcode    = IB_WC_FETCH_ADD;
+                       wc->byte_len  = 8;
+                       break;
+               case MLX4_OPCODE_MASKED_ATOMIC_CS:
+                       wc->opcode    = IB_WC_MASKED_COMP_SWAP;
+                       wc->byte_len  = 8;
+                       break;
+               case MLX4_OPCODE_MASKED_ATOMIC_FA:
+                       wc->opcode    = IB_WC_MASKED_FETCH_ADD;
+                       wc->byte_len  = 8;
+                       break;
+               case MLX4_OPCODE_BIND_MW:
+                       wc->opcode    = IB_WC_BIND_MW;
+                       break;
+               case MLX4_OPCODE_LSO:
+                       wc->opcode    = IB_WC_LSO;
+                       break;
+               case MLX4_OPCODE_FMR:
+                       wc->opcode    = IB_WC_FAST_REG_MR;
+                       break;
+               case MLX4_OPCODE_LOCAL_INVAL:
+                       wc->opcode    = IB_WC_LOCAL_INV;
+                       break;
+               }
+       } else {
+               wc->byte_len = be32_to_cpu(cqe->byte_cnt);
+
+               switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
+               case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
+                       wc->opcode      = IB_WC_RECV_RDMA_WITH_IMM;
+                       wc->wc_flags    = IB_WC_WITH_IMM;
+                       wc->ex.imm_data = cqe->immed_rss_invalid;
+                       break;
+               case MLX4_RECV_OPCODE_SEND_INVAL:
+                       wc->opcode      = IB_WC_RECV;
+                       wc->wc_flags    = IB_WC_WITH_INVALIDATE;
+                       wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid);
+                       break;
+               case MLX4_RECV_OPCODE_SEND:
+                       wc->opcode   = IB_WC_RECV;
+                       wc->wc_flags = 0;
+                       break;
+               case MLX4_RECV_OPCODE_SEND_IMM:
+                       wc->opcode      = IB_WC_RECV;
+                       wc->wc_flags    = IB_WC_WITH_IMM;
+                       wc->ex.imm_data = cqe->immed_rss_invalid;
+                       break;
+               }
+
+               is_eth = (rdma_port_get_link_layer(wc->qp->device,
+                                                 (*cur_qp)->port) ==
+                         IB_LINK_LAYER_ETHERNET);
+               if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) {
+                       if ((*cur_qp)->mlx4_ib_qp_type &
+                           (MLX4_IB_QPT_PROXY_SMI_OWNER |
+                            MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
+                               return use_tunnel_data(*cur_qp, cq, wc, tail,
+                                                      cqe, is_eth);
+               }
+
+               wc->slid           = be16_to_cpu(cqe->rlid);
+               g_mlpath_rqpn      = be32_to_cpu(cqe->g_mlpath_rqpn);
+               wc->src_qp         = g_mlpath_rqpn & 0xffffff;
+               wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
+               wc->wc_flags      |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
+               wc->pkey_index     = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
+               wc->wc_flags      |= mlx4_ib_ipoib_csum_ok(cqe->status,
+                                       cqe->checksum) ? IB_WC_IP_CSUM_OK : 0;
+               if (is_eth) {
+                       wc->sl  = be16_to_cpu(cqe->sl_vid) >> 13;
+                       if (be32_to_cpu(cqe->vlan_my_qpn) &
+                                       MLX4_CQE_VLAN_PRESENT_MASK) {
+                               wc->vlan_id = be16_to_cpu(cqe->sl_vid) &
+                                       MLX4_CQE_VID_MASK;
+                       } else {
+                               wc->vlan_id = 0xffff;
+                       }
+                       memcpy(wc->smac, cqe->smac, ETH_ALEN);
+                       wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
+               } else {
+                       wc->sl  = be16_to_cpu(cqe->sl_vid) >> 12;
+                       wc->vlan_id = 0xffff;
+               }
+       }
+
+       return 0;
+}
+
+int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
+{
+       struct mlx4_ib_cq *cq = to_mcq(ibcq);
+       struct mlx4_ib_qp *cur_qp = NULL;
+       unsigned long flags;
+       int npolled;
+       int err = 0;
+       struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device);
+
+       spin_lock_irqsave(&cq->lock, flags);
+       if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
+               mlx4_ib_poll_sw_comp(cq, num_entries, wc, &npolled);
+               goto out;
+       }
+
+       for (npolled = 0; npolled < num_entries; ++npolled) {
+               err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled);
+               if (err)
+                       break;
+       }
+
+       mlx4_cq_set_ci(&cq->mcq);
+
+out:
+       spin_unlock_irqrestore(&cq->lock, flags);
+
+       if (err == 0 || err == -EAGAIN)
+               return npolled;
+       else
+               return err;
+}
+
+int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
+{
+       mlx4_cq_arm(&to_mcq(ibcq)->mcq,
+                   (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
+                   MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
+                   to_mdev(ibcq->device)->uar_map,
+                   MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
+
+       return 0;
+}
+
+void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
+{
+       u32 prod_index;
+       int nfreed = 0;
+       struct mlx4_cqe *cqe, *dest;
+       u8 owner_bit;
+       int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0;
+
+       /*
+        * First we need to find the current producer index, so we
+        * know where to start cleaning from.  It doesn't matter if HW
+        * adds new entries after this loop -- the QP we're worried
+        * about is already in RESET, so the new entries won't come
+        * from our QP and therefore don't need to be checked.
+        */
+       for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
+               if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
+                       break;
+
+       /*
+        * Now sweep backwards through the CQ, removing CQ entries
+        * that match our QP by copying older entries on top of them.
+        */
+       while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
+               cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
+               cqe += cqe_inc;
+
+               if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
+                       if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
+                               mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
+                       ++nfreed;
+               } else if (nfreed) {
+                       dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
+                       dest += cqe_inc;
+
+                       owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
+                       memcpy(dest, cqe, sizeof *cqe);
+                       dest->owner_sr_opcode = owner_bit |
+                               (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
+               }
+       }
+
+       if (nfreed) {
+               cq->mcq.cons_index += nfreed;
+               /*
+                * Make sure update of buffer contents is done before
+                * updating consumer index.
+                */
+               wmb();
+               mlx4_cq_set_ci(&cq->mcq);
+       }
+}
+
+void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
+{
+       spin_lock_irq(&cq->lock);
+       __mlx4_ib_cq_clean(cq, qpn, srq);
+       spin_unlock_irq(&cq->lock);
+}
diff --git a/kern/drivers/net/mlx4u/doorbell.c b/kern/drivers/net/mlx4u/doorbell.c
new file mode 100644 (file)
index 0000000..e54c1e6
--- /dev/null
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+//#include <linux/slab.h>      /* AKAROS */
+
+#include "mlx4_ib.h"
+
+struct mlx4_ib_user_db_page {
+       struct list_head        list;
+       struct ib_umem         *umem;
+       unsigned long           user_virt;
+       int                     refcnt;
+};
+
+int mlx4_ib_db_map_user(struct mlx4_ib_ucontext *context, unsigned long virt,
+                       struct mlx4_db *db)
+{
+       struct mlx4_ib_user_db_page *page;
+       int err = 0;
+
+       mutex_lock(&context->db_page_mutex);
+
+       list_for_each_entry(page, &context->db_page_list, list)
+               if (page->user_virt == (virt & PAGE_MASK))
+                       goto found;
+
+       page = kmalloc(sizeof *page, GFP_KERNEL);
+       if (!page) {
+               err = -ENOMEM;
+               goto out;
+       }
+
+       page->user_virt = (virt & PAGE_MASK);
+       page->refcnt    = 0;
+       page->umem      = ib_umem_get(&context->ibucontext, virt & PAGE_MASK,
+                                     PAGE_SIZE, 0, 0);
+       if (IS_ERR(page->umem)) {
+               err = PTR_ERR(page->umem);
+               kfree(page);
+               goto out;
+       }
+
+       list_add(&page->list, &context->db_page_list);
+
+found:
+       db->dma = sg_dma_address(page->umem->sg_head.sgl) + (virt & ~PAGE_MASK);
+       db->u.user_page = page;
+       ++page->refcnt;
+
+out:
+       mutex_unlock(&context->db_page_mutex);
+
+       return err;
+}
+
+void mlx4_ib_db_unmap_user(struct mlx4_ib_ucontext *context, struct mlx4_db *db)
+{
+       mutex_lock(&context->db_page_mutex);
+
+       if (!--db->u.user_page->refcnt) {
+               list_del(&db->u.user_page->list);
+               ib_umem_release(db->u.user_page->umem);
+               kfree(db->u.user_page);
+       }
+
+       mutex_unlock(&context->db_page_mutex);
+}
diff --git a/kern/drivers/net/mlx4u/main.c b/kern/drivers/net/mlx4u/main.c
new file mode 100644 (file)
index 0000000..b662f81
--- /dev/null
@@ -0,0 +1,3010 @@
+/*
+ * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
+ * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#if 1  /* AKAROS */
+#include <linux/rdma/ib_smi.h>
+#include <linux/rdma/ib_verbs.h>
+#include <linux/rdma/ib_user_verbs.h>
+#else  /* AKAROS */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/inetdevice.h>
+#include <linux/rtnetlink.h>
+#include <linux/if_vlan.h>
+#include <net/ipv6.h>
+#include <net/addrconf.h>
+
+#include <rdma/ib_smi.h>
+#include <rdma/ib_user_verbs.h>
+#include <rdma/ib_addr.h>
+#endif /* AKAROS */
+
+#include <linux/mlx4/driver.h>
+#include <linux/mlx4/cmd.h>
+#include <linux/mlx4/qp.h>
+
+#include "mlx4_ib.h"
+#include "user.h"
+
+#if 1  /* AKAROS */
+
+#define        netdev_master_upper_dev_get(p)  p
+#define        iboe_get_mtu(v)                 IB_MTU_1024     /* TODO */
+
+/* STUB START */
+int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev) { return 0; }
+int mlx4_ib_mad_init(struct mlx4_ib_dev *dev) { return 0; }
+void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev) {}
+void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev) {}
+void mlx4_ib_mcg_destroy() { }
+int mlx4_ib_mcg_init(void) { return 0; }
+void mlx4_ib_invalidate_all_guid_record(struct mlx4_ib_dev *dev, int port) {}
+void mlx4_ib_slave_alias_guid_event(struct mlx4_ib_dev *dev, int slave,
+    int port, int slave_init) {}
+void handle_port_mgmt_change_event(struct work_struct *work){}
+void mlx4_ib_tunnels_update_work(struct work_struct *work) {}
+int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags, int port,
+    struct ib_wc *in_wc, struct ib_grh *in_grh, void *in_mad,
+    void *response_mad) { return 0; }
+/* STUB END */
+
+#endif /* AKAROS */
+
+#define DRV_NAME       MLX4_IB_DRV_NAME
+#define DRV_VERSION    "2.2-1"
+#define DRV_RELDATE    "Feb 2014"
+
+#define MLX4_IB_FLOW_MAX_PRIO 0xFFF
+#define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
+#define MLX4_IB_CARD_REV_A0   0xA0
+
+MODULE_AUTHOR("Roland Dreier");
+MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_VERSION(DRV_VERSION);
+
+int mlx4_ib_sm_guid_assign = 0;
+module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
+MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
+
+static const char mlx4_ib_version[] =
+       DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
+       DRV_VERSION " (" DRV_RELDATE ")\n";
+
+struct update_gid_work {
+       struct work_struct      work;
+       union ib_gid            gids[128];
+       struct mlx4_ib_dev     *dev;
+       int                     port;
+};
+
+static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
+
+static struct workqueue_struct *wq;
+
+static void init_query_mad(struct ib_smp *mad)
+{
+       mad->base_version  = 1;
+       mad->mgmt_class    = IB_MGMT_CLASS_SUBN_LID_ROUTED;
+       mad->class_version = 1;
+       mad->method        = IB_MGMT_METHOD_GET;
+}
+
+static union ib_gid zgid;
+
+static int check_flow_steering_support(struct mlx4_dev *dev)
+{
+       int eth_num_ports = 0;
+       int ib_num_ports = 0;
+
+       int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
+
+       if (dmfs) {
+               int i;
+               mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
+                       eth_num_ports++;
+               mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
+                       ib_num_ports++;
+               dmfs &= (!ib_num_ports ||
+                        (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
+                       (!eth_num_ports ||
+                        (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
+               if (ib_num_ports && mlx4_is_mfunc(dev)) {
+                       pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
+                       dmfs = 0;
+               }
+       }
+       return dmfs;
+}
+
+static int num_ib_ports(struct mlx4_dev *dev)
+{
+       int ib_ports = 0;
+       int i;
+
+       mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
+               ib_ports++;
+
+       return ib_ports;
+}
+
+static int mlx4_ib_query_device(struct ib_device *ibdev,
+                               struct ib_device_attr *props)
+{
+       struct mlx4_ib_dev *dev = to_mdev(ibdev);
+       struct ib_smp *in_mad  = NULL;
+       struct ib_smp *out_mad = NULL;
+       int err = -ENOMEM;
+       int have_ib_ports;
+
+       in_mad  = kzalloc(sizeof *in_mad, GFP_KERNEL);
+       out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
+       if (!in_mad || !out_mad)
+               goto out;
+
+       init_query_mad(in_mad);
+       in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
+
+       err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
+                          1, NULL, NULL, in_mad, out_mad);
+       if (err)
+               goto out;
+
+       memset(props, 0, sizeof *props);
+
+       have_ib_ports = num_ib_ports(dev->dev);
+
+       props->fw_ver = dev->dev->caps.fw_ver;
+       props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
+               IB_DEVICE_PORT_ACTIVE_EVENT             |
+               IB_DEVICE_SYS_IMAGE_GUID                |
+               IB_DEVICE_RC_RNR_NAK_GEN                |
+               IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
+       if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
+               props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
+       if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
+               props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
+       if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
+               props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
+       if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
+               props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
+       if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
+               props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
+       if (dev->dev->caps.max_gso_sz &&
+           (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
+           (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
+               props->device_cap_flags |= IB_DEVICE_UD_TSO;
+       if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
+               props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
+       if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
+           (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
+           (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
+               props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
+       if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
+               props->device_cap_flags |= IB_DEVICE_XRC;
+       if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
+               props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
+       if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
+               if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
+                       props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
+               else
+                       props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
+       if (dev->steering_support ==  MLX4_STEERING_MODE_DEVICE_MANAGED)
+               props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
+       }
+
+       props->vendor_id           = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
+               0xffffff;
+#if 0  /* AKAROS */
+       props->vendor_part_id      = dev->dev->persist->pdev->device;
+#endif /* AKAROS */
+       props->hw_ver              = be32_to_cpup((__be32 *) (out_mad->data + 32));
+       memcpy(&props->sys_image_guid, out_mad->data +  4, 8);
+
+       props->max_mr_size         = ~0ull;
+       props->page_size_cap       = dev->dev->caps.page_size_cap;
+       props->max_qp              = dev->dev->quotas.qp;
+       props->max_qp_wr           = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
+       props->max_sge             = min(dev->dev->caps.max_sq_sg,
+                                        dev->dev->caps.max_rq_sg);
+       props->max_cq              = dev->dev->quotas.cq;
+       props->max_cqe             = dev->dev->caps.max_cqes;
+       props->max_mr              = dev->dev->quotas.mpt;
+       props->max_pd              = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
+       props->max_qp_rd_atom      = dev->dev->caps.max_qp_dest_rdma;
+       props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
+       props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
+       props->max_srq             = dev->dev->quotas.srq;
+       props->max_srq_wr          = dev->dev->caps.max_srq_wqes - 1;
+       props->max_srq_sge         = dev->dev->caps.max_srq_sge;
+       props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
+       props->local_ca_ack_delay  = dev->dev->caps.local_ca_ack_delay;
+       props->atomic_cap          = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
+               IB_ATOMIC_HCA : IB_ATOMIC_NONE;
+       props->masked_atomic_cap   = props->atomic_cap;
+       props->max_pkeys           = dev->dev->caps.pkey_table_len[1];
+       props->max_mcast_grp       = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
+       props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
+       props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
+                                          props->max_mcast_grp;
+       props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
+
+out:
+       kfree(in_mad);
+       kfree(out_mad);
+
+       return err;
+}
+
+static enum rdma_link_layer
+mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
+{
+       struct mlx4_dev *dev = to_mdev(device)->dev;
+
+       return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
+               IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
+}
+
+static int ib_link_query_port(struct ib_device *ibdev, u8 port,
+                             struct ib_port_attr *props, int netw_view)
+{
+       struct ib_smp *in_mad  = NULL;
+       struct ib_smp *out_mad = NULL;
+       int ext_active_speed;
+       int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
+       int err = -ENOMEM;
+
+       in_mad  = kzalloc(sizeof *in_mad, GFP_KERNEL);
+       out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
+       if (!in_mad || !out_mad)
+               goto out;
+
+       init_query_mad(in_mad);
+       in_mad->attr_id  = IB_SMP_ATTR_PORT_INFO;
+       in_mad->attr_mod = cpu_to_be32(port);
+
+       if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
+               mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
+
+       err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
+                               in_mad, out_mad);
+       if (err)
+               goto out;
+
+
+       props->lid              = be16_to_cpup((__be16 *) (out_mad->data + 16));
+       props->lmc              = out_mad->data[34] & 0x7;
+       props->sm_lid           = be16_to_cpup((__be16 *) (out_mad->data + 18));
+       props->sm_sl            = out_mad->data[36] & 0xf;
+       props->state            = out_mad->data[32] & 0xf;
+       props->phys_state       = out_mad->data[33] >> 4;
+       props->port_cap_flags   = be32_to_cpup((__be32 *) (out_mad->data + 20));
+       if (netw_view)
+               props->gid_tbl_len = out_mad->data[50];
+       else
+               props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
+       props->max_msg_sz       = to_mdev(ibdev)->dev->caps.max_msg_sz;
+       props->pkey_tbl_len     = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
+       props->bad_pkey_cntr    = be16_to_cpup((__be16 *) (out_mad->data + 46));
+       props->qkey_viol_cntr   = be16_to_cpup((__be16 *) (out_mad->data + 48));
+       props->active_width     = out_mad->data[31] & 0xf;
+       props->active_speed     = out_mad->data[35] >> 4;
+       props->max_mtu          = out_mad->data[41] & 0xf;
+       props->active_mtu       = out_mad->data[36] >> 4;
+       props->subnet_timeout   = out_mad->data[51] & 0x1f;
+       props->max_vl_num       = out_mad->data[37] >> 4;
+       props->init_type_reply  = out_mad->data[41] >> 4;
+
+       /* Check if extended speeds (EDR/FDR/...) are supported */
+       if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
+               ext_active_speed = out_mad->data[62] >> 4;
+
+               switch (ext_active_speed) {
+               case 1:
+                       props->active_speed = IB_SPEED_FDR;
+                       break;
+               case 2:
+                       props->active_speed = IB_SPEED_EDR;
+                       break;
+               }
+       }
+
+       /* If reported active speed is QDR, check if is FDR-10 */
+       if (props->active_speed == IB_SPEED_QDR) {
+               init_query_mad(in_mad);
+               in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
+               in_mad->attr_mod = cpu_to_be32(port);
+
+               err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
+                                  NULL, NULL, in_mad, out_mad);
+               if (err)
+                       goto out;
+
+               /* Checking LinkSpeedActive for FDR-10 */
+               if (out_mad->data[15] & 0x1)
+                       props->active_speed = IB_SPEED_FDR10;
+       }
+
+       /* Avoid wrong speed value returned by FW if the IB link is down. */
+       if (props->state == IB_PORT_DOWN)
+                props->active_speed = IB_SPEED_SDR;
+
+out:
+       kfree(in_mad);
+       kfree(out_mad);
+       return err;
+}
+
+static u8 state_to_phys_state(enum ib_port_state state)
+{
+       return state == IB_PORT_ACTIVE ? 5 : 3;
+}
+
+static int eth_link_query_port(struct ib_device *ibdev, u8 port,
+                              struct ib_port_attr *props, int netw_view)
+{
+
+       struct mlx4_ib_dev *mdev = to_mdev(ibdev);
+       struct mlx4_ib_iboe *iboe = &mdev->iboe;
+       struct net_device *ndev;
+       enum ib_mtu tmp;
+       struct mlx4_cmd_mailbox *mailbox;
+       int err = 0;
+       int is_bonded = mlx4_is_bonded(mdev->dev);
+
+       mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
+       if (IS_ERR(mailbox))
+               return PTR_ERR(mailbox);
+
+       err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
+                          MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
+                          MLX4_CMD_WRAPPED);
+       if (err)
+               goto out;
+
+       props->active_width     =  (((u8 *)mailbox->buf)[5] == 0x40) ?
+                                               IB_WIDTH_4X : IB_WIDTH_1X;
+       props->active_speed     = IB_SPEED_QDR;
+       props->port_cap_flags   = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
+       props->gid_tbl_len      = mdev->dev->caps.gid_table_len[port];
+       props->max_msg_sz       = mdev->dev->caps.max_msg_sz;
+       props->pkey_tbl_len     = 1;
+       props->max_mtu          = IB_MTU_4096;
+       props->max_vl_num       = 2;
+       props->state            = IB_PORT_DOWN;
+       props->phys_state       = state_to_phys_state(props->state);
+       props->active_mtu       = IB_MTU_256;
+       if (is_bonded)
+               rtnl_lock(); /* required to get upper dev */
+       spin_lock_bh(&iboe->lock);
+       ndev = iboe->netdevs[port - 1];
+       if (ndev && is_bonded)
+               ndev = netdev_master_upper_dev_get(ndev);
+       if (!ndev)
+               goto out_unlock;
+
+       tmp = iboe_get_mtu(ndev->mtu);
+       props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
+
+       props->state            = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
+                                       IB_PORT_ACTIVE : IB_PORT_DOWN;
+       props->phys_state       = state_to_phys_state(props->state);
+out_unlock:
+       spin_unlock_bh(&iboe->lock);
+       if (is_bonded)
+               rtnl_unlock();
+out:
+       mlx4_free_cmd_mailbox(mdev->dev, mailbox);
+       return err;
+}
+
+int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
+                        struct ib_port_attr *props, int netw_view)
+{
+       int err;
+
+       memset(props, 0, sizeof *props);
+
+       err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
+               ib_link_query_port(ibdev, port, props, netw_view) :
+                               eth_link_query_port(ibdev, port, props, netw_view);
+
+       return err;
+}
+
+static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
+                             struct ib_port_attr *props)
+{
+       /* returns host view */
+       return __mlx4_ib_query_port(ibdev, port, props, 0);
+}
+
+int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
+                       union ib_gid *gid, int netw_view)
+{
+       struct ib_smp *in_mad  = NULL;
+       struct ib_smp *out_mad = NULL;
+       int err = -ENOMEM;
+       struct mlx4_ib_dev *dev = to_mdev(ibdev);
+       int clear = 0;
+       int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
+
+       in_mad  = kzalloc(sizeof *in_mad, GFP_KERNEL);
+       out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
+       if (!in_mad || !out_mad)
+               goto out;
+
+       init_query_mad(in_mad);
+       in_mad->attr_id  = IB_SMP_ATTR_PORT_INFO;
+       in_mad->attr_mod = cpu_to_be32(port);
+
+       if (mlx4_is_mfunc(dev->dev) && netw_view)
+               mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
+
+       err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
+       if (err)
+               goto out;
+
+       memcpy(gid->raw, out_mad->data + 8, 8);
+
+       if (mlx4_is_mfunc(dev->dev) && !netw_view) {
+               if (index) {
+                       /* For any index > 0, return the null guid */
+                       err = 0;
+                       clear = 1;
+                       goto out;
+               }
+       }
+
+       init_query_mad(in_mad);
+       in_mad->attr_id  = IB_SMP_ATTR_GUID_INFO;
+       in_mad->attr_mod = cpu_to_be32(index / 8);
+
+       err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
+                          NULL, NULL, in_mad, out_mad);
+       if (err)
+               goto out;
+
+       memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
+
+out:
+       if (clear)
+               memset(gid->raw + 8, 0, 8);
+       kfree(in_mad);
+       kfree(out_mad);
+       return err;
+}
+
+static int iboe_query_gid(struct ib_device *ibdev, u8 port, int index,
+                         union ib_gid *gid)
+{
+       struct mlx4_ib_dev *dev = to_mdev(ibdev);
+
+       *gid = dev->iboe.gid_table[port - 1][index];
+
+       return 0;
+}
+
+static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
+                            union ib_gid *gid)
+{
+       if (rdma_port_get_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND)
+               return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
+       else
+               return iboe_query_gid(ibdev, port, index, gid);
+}
+
+int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
+                        u16 *pkey, int netw_view)
+{
+       struct ib_smp *in_mad  = NULL;
+       struct ib_smp *out_mad = NULL;
+       int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
+       int err = -ENOMEM;
+
+       in_mad  = kzalloc(sizeof *in_mad, GFP_KERNEL);
+       out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
+       if (!in_mad || !out_mad)
+               goto out;
+
+       init_query_mad(in_mad);
+       in_mad->attr_id  = IB_SMP_ATTR_PKEY_TABLE;
+       in_mad->attr_mod = cpu_to_be32(index / 32);
+
+       if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
+               mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
+
+       err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
+                          in_mad, out_mad);
+       if (err)
+               goto out;
+
+       *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
+
+out:
+       kfree(in_mad);
+       kfree(out_mad);
+       return err;
+}
+
+static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
+{
+       return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
+}
+
+static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
+                                struct ib_device_modify *props)
+{
+       struct mlx4_cmd_mailbox *mailbox;
+       unsigned long flags;
+
+       if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
+               return -EOPNOTSUPP;
+
+       if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
+               return 0;
+
+       if (mlx4_is_slave(to_mdev(ibdev)->dev))
+               return -EOPNOTSUPP;
+
+       spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
+       memcpy(ibdev->node_desc, props->node_desc, 64);
+       spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
+
+       /*
+        * If possible, pass node desc to FW, so it can generate
+        * a 144 trap.  If cmd fails, just ignore.
+        */
+       mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
+       if (IS_ERR(mailbox))
+               return 0;
+
+       memcpy(mailbox->buf, props->node_desc, 64);
+       mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
+                MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
+
+       mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
+
+       return 0;
+}
+
+static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
+                           u32 cap_mask)
+{
+       struct mlx4_cmd_mailbox *mailbox;
+       int err;
+
+       mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
+       if (IS_ERR(mailbox))
+               return PTR_ERR(mailbox);
+
+       if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
+               *(u8 *) mailbox->buf         = !!reset_qkey_viols << 6;
+               ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
+       } else {
+               ((u8 *) mailbox->buf)[3]     = !!reset_qkey_viols;
+               ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
+       }
+
+       err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
+                      MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
+                      MLX4_CMD_WRAPPED);
+
+       mlx4_free_cmd_mailbox(dev->dev, mailbox);
+       return err;
+}
+
+static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
+                              struct ib_port_modify *props)
+{
+       struct mlx4_ib_dev *mdev = to_mdev(ibdev);
+       u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
+       struct ib_port_attr attr;
+       u32 cap_mask;
+       int err;
+
+       /* return OK if this is RoCE. CM calls ib_modify_port() regardless
+        * of whether port link layer is ETH or IB. For ETH ports, qkey
+        * violations and port capabilities are not meaningful.
+        */
+       if (is_eth)
+               return 0;
+
+       mutex_lock(&mdev->cap_mask_mutex);
+
+       err = mlx4_ib_query_port(ibdev, port, &attr);
+       if (err)
+               goto out;
+
+       cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
+               ~props->clr_port_cap_mask;
+
+       err = mlx4_ib_SET_PORT(mdev, port,
+                              !!(mask & IB_PORT_RESET_QKEY_CNTR),
+                              cap_mask);
+
+out:
+       mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
+       return err;
+}
+
+static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
+                                                 struct ib_udata *udata)
+{
+       struct mlx4_ib_dev *dev = to_mdev(ibdev);
+       struct mlx4_ib_ucontext *context;
+       struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
+       struct mlx4_ib_alloc_ucontext_resp resp;
+       int err;
+
+       if (!dev->ib_active)
+               return ERR_PTR(-EAGAIN);
+
+       if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
+               resp_v3.qp_tab_size      = dev->dev->caps.num_qps;
+               resp_v3.bf_reg_size      = dev->dev->caps.bf_reg_size;
+               resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
+       } else {
+               resp.dev_caps         = dev->dev->caps.userspace_caps;
+               resp.qp_tab_size      = dev->dev->caps.num_qps;
+               resp.bf_reg_size      = dev->dev->caps.bf_reg_size;
+               resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
+               resp.cqe_size         = dev->dev->caps.cqe_size;
+       }
+
+       context = kmalloc(sizeof *context, GFP_KERNEL);
+       if (!context)
+               return ERR_PTR(-ENOMEM);
+
+       err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
+       if (err) {
+               kfree(context);
+               return ERR_PTR(err);
+       }
+
+       INIT_LIST_HEAD(&context->db_page_list);
+       mutex_init(&context->db_page_mutex);
+
+       if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
+               err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
+       else
+               err = ib_copy_to_udata(udata, &resp, sizeof(resp));
+
+       if (err) {
+               mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
+               kfree(context);
+               return ERR_PTR(-EFAULT);
+       }
+
+       return &context->ibucontext;
+}
+
+static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
+{
+       struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
+
+       mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
+       kfree(context);
+
+       return 0;
+}
+
+#if 0  /* AKAROS */
+
+static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
+{
+       struct mlx4_ib_dev *dev = to_mdev(context->device);
+
+       if (vma->vm_end - vma->vm_start != PAGE_SIZE)
+               return -EINVAL;
+
+       if (vma->vm_pgoff == 0) {
+               vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+               if (io_remap_pfn_range(vma, vma->vm_start,
+                                      to_mucontext(context)->uar.pfn,
+                                      PAGE_SIZE, vma->vm_page_prot))
+                       return -EAGAIN;
+       } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
+               vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+
+               if (io_remap_pfn_range(vma, vma->vm_start,
+                                      to_mucontext(context)->uar.pfn +
+                                      dev->dev->caps.num_uars,
+                                      PAGE_SIZE, vma->vm_page_prot))
+                       return -EAGAIN;
+       } else
+               return -EINVAL;
+
+       return 0;
+}
+
+#else  /* AKAROS */
+
+static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_region *vma)
+{
+       struct mlx4_ib_dev *dev = to_mdev(context->device);
+       int pteprot;
+
+       if (vma->vm_end - vma->vm_base != PAGE_SIZE)
+               return -EINVAL;
+
+       if (vma->vm_foff == 0) {
+               pteprot = pgprot_noncached(vma->vm_prot);
+
+               if (io_remap_pfn_range(vma, vma->vm_start,
+                                      to_mucontext(context)->uar.pfn,
+                                      PAGE_SIZE, pteprot))
+                       return -EAGAIN;
+       } else if ((vma->vm_foff >> PAGE_SHIFT) == 1 && dev->dev->caps.bf_reg_size != 0) {
+               pteprot = pgprot_writecombine(vma->vm_prot);
+
+               if (io_remap_pfn_range(vma, vma->vm_start,
+                                      to_mucontext(context)->uar.pfn +
+                                      dev->dev->caps.num_uars,
+                                      PAGE_SIZE, pteprot))
+                       return -EAGAIN;
+       } else
+               return -EINVAL;
+
+       return 0;
+}
+
+#endif /* AKAROS */
+
+static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
+                                     struct ib_ucontext *context,
+                                     struct ib_udata *udata)
+{
+       struct mlx4_ib_pd *pd;
+       int err;
+
+       pd = kmalloc(sizeof *pd, GFP_KERNEL);
+       if (!pd)
+               return ERR_PTR(-ENOMEM);
+
+       err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
+       if (err) {
+               kfree(pd);
+               return ERR_PTR(err);
+       }
+
+       if (context)
+               if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
+                       mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
+                       kfree(pd);
+                       return ERR_PTR(-EFAULT);
+               }
+
+       return &pd->ibpd;
+}
+
+static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
+{
+       mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
+       kfree(pd);
+
+       return 0;
+}
+
+static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
+                                         struct ib_ucontext *context,
+                                         struct ib_udata *udata)
+{
+       struct mlx4_ib_xrcd *xrcd;
+       int err;
+
+       if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
+               return ERR_PTR(-ENOSYS);
+
+       xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
+       if (!xrcd)
+               return ERR_PTR(-ENOMEM);
+
+       err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
+       if (err)
+               goto err1;
+
+       xrcd->pd = ib_alloc_pd(ibdev);
+       if (IS_ERR(xrcd->pd)) {
+               err = PTR_ERR(xrcd->pd);
+               goto err2;
+       }
+
+       xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, 1, 0);
+       if (IS_ERR(xrcd->cq)) {
+               err = PTR_ERR(xrcd->cq);
+               goto err3;
+       }
+
+       return &xrcd->ibxrcd;
+
+err3:
+       ib_dealloc_pd(xrcd->pd);
+err2:
+       mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
+err1:
+       kfree(xrcd);
+       return ERR_PTR(err);
+}
+
+static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
+{
+       ib_destroy_cq(to_mxrcd(xrcd)->cq);
+       ib_dealloc_pd(to_mxrcd(xrcd)->pd);
+       mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
+       kfree(xrcd);
+
+       return 0;
+}
+
+static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
+{
+       struct mlx4_ib_qp *mqp = to_mqp(ibqp);
+       struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
+       struct mlx4_ib_gid_entry *ge;
+
+       ge = kzalloc(sizeof *ge, GFP_KERNEL);
+       if (!ge)
+               return -ENOMEM;
+
+       ge->gid = *gid;
+       if (mlx4_ib_add_mc(mdev, mqp, gid)) {
+               ge->port = mqp->port;
+               ge->added = 1;
+       }
+
+       mutex_lock(&mqp->mutex);
+       list_add_tail(&ge->list, &mqp->gid_list);
+       mutex_unlock(&mqp->mutex);
+
+       return 0;
+}
+
+int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
+                  union ib_gid *gid)
+{
+       struct net_device *ndev;
+       int ret = 0;
+
+       if (!mqp->port)
+               return 0;
+
+       spin_lock_bh(&mdev->iboe.lock);
+       ndev = mdev->iboe.netdevs[mqp->port - 1];
+       if (ndev)
+               dev_hold(ndev);
+       spin_unlock_bh(&mdev->iboe.lock);
+
+       if (ndev) {
+               ret = 1;
+               dev_put(ndev);
+       }
+
+       return ret;
+}
+
+struct mlx4_ib_steering {
+       struct list_head list;
+       struct mlx4_flow_reg_id reg_id;
+       union ib_gid gid;
+};
+
+static int parse_flow_attr(struct mlx4_dev *dev,
+                          u32 qp_num,
+                          union ib_flow_spec *ib_spec,
+                          struct _rule_hw *mlx4_spec)
+{
+       enum mlx4_net_trans_rule_id type;
+
+       switch (ib_spec->type) {
+       case IB_FLOW_SPEC_ETH:
+               type = MLX4_NET_TRANS_RULE_ID_ETH;
+               memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
+                      ETH_ALEN);
+               memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
+                      ETH_ALEN);
+               mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
+               mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
+               break;
+       case IB_FLOW_SPEC_IB:
+               type = MLX4_NET_TRANS_RULE_ID_IB;
+               mlx4_spec->ib.l3_qpn =
+                       cpu_to_be32(qp_num);
+               mlx4_spec->ib.qpn_mask =
+                       cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
+               break;
+
+
+       case IB_FLOW_SPEC_IPV4:
+               type = MLX4_NET_TRANS_RULE_ID_IPV4;
+               mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
+               mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
+               mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
+               mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
+               break;
+
+       case IB_FLOW_SPEC_TCP:
+       case IB_FLOW_SPEC_UDP:
+               type = ib_spec->type == IB_FLOW_SPEC_TCP ?
+                                       MLX4_NET_TRANS_RULE_ID_TCP :
+                                       MLX4_NET_TRANS_RULE_ID_UDP;
+               mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
+               mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
+               mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
+               mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
+               break;
+
+       default:
+               return -EINVAL;
+       }
+       if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
+           mlx4_hw_rule_sz(dev, type) < 0)
+               return -EINVAL;
+       mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
+       mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
+       return mlx4_hw_rule_sz(dev, type);
+}
+
+struct default_rules {
+       __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
+       __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
+       __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
+       __u8  link_layer;
+};
+static const struct default_rules default_table[] = {
+       {
+               .mandatory_fields = {IB_FLOW_SPEC_IPV4},
+               .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
+               .rules_create_list = {IB_FLOW_SPEC_IB},
+               .link_layer = IB_LINK_LAYER_INFINIBAND
+       }
+};
+
+static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
+                                        struct ib_flow_attr *flow_attr)
+{
+       int i, j, k;
+       void *ib_flow;
+       const struct default_rules *pdefault_rules = default_table;
+       u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
+
+       for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
+               __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
+               memset(&field_types, 0, sizeof(field_types));
+
+               if (link_layer != pdefault_rules->link_layer)
+                       continue;
+
+               ib_flow = flow_attr + 1;
+               /* we assume the specs are sorted */
+               for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
+                    j < flow_attr->num_of_specs; k++) {
+                       union ib_flow_spec *current_flow =
+                               (union ib_flow_spec *)ib_flow;
+
+                       /* same layer but different type */
+                       if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
+                            (pdefault_rules->mandatory_fields[k] &
+                             IB_FLOW_SPEC_LAYER_MASK)) &&
+                           (current_flow->type !=
+                            pdefault_rules->mandatory_fields[k]))
+                               goto out;
+
+                       /* same layer, try match next one */
+                       if (current_flow->type ==
+                           pdefault_rules->mandatory_fields[k]) {
+                               j++;
+                               ib_flow +=
+                                       ((union ib_flow_spec *)ib_flow)->size;
+                       }
+               }
+
+               ib_flow = flow_attr + 1;
+               for (j = 0; j < flow_attr->num_of_specs;
+                    j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
+                       for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
+                               /* same layer and same type */
+                               if (((union ib_flow_spec *)ib_flow)->type ==
+                                   pdefault_rules->mandatory_not_fields[k])
+                                       goto out;
+
+               return i;
+       }
+out:
+       return -1;
+}
+
+static int __mlx4_ib_create_default_rules(
+               struct mlx4_ib_dev *mdev,
+               struct ib_qp *qp,
+               const struct default_rules *pdefault_rules,
+               struct _rule_hw *mlx4_spec) {
+       int size = 0;
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
+               int ret;
+               union ib_flow_spec ib_spec;
+               switch (pdefault_rules->rules_create_list[i]) {
+               case 0:
+                       /* no rule */
+                       continue;
+               case IB_FLOW_SPEC_IB:
+                       ib_spec.type = IB_FLOW_SPEC_IB;
+                       ib_spec.size = sizeof(struct ib_flow_spec_ib);
+
+                       break;
+               default:
+                       /* invalid rule */
+                       return -EINVAL;
+               }
+               /* We must put empty rule, qpn is being ignored */
+               ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
+                                     mlx4_spec);
+               if (ret < 0) {
+                       pr_info("invalid parsing\n");
+                       return -EINVAL;
+               }
+
+               mlx4_spec = (void *)mlx4_spec + ret;
+               size += ret;
+       }
+       return size;
+}
+
+static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
+                         int domain,
+                         enum mlx4_net_trans_promisc_mode flow_type,
+                         u64 *reg_id)
+{
+       int ret, i;
+       int size = 0;
+       void *ib_flow;
+       struct mlx4_ib_dev *mdev = to_mdev(qp->device);
+       struct mlx4_cmd_mailbox *mailbox;
+       struct mlx4_net_trans_rule_hw_ctrl *ctrl;
+       int default_flow;
+
+       static const u16 __mlx4_domain[] = {
+               [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
+               [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
+               [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
+               [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
+       };
+
+       if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
+               pr_err("Invalid priority value %d\n", flow_attr->priority);
+               return -EINVAL;
+       }
+
+       if (domain >= IB_FLOW_DOMAIN_NUM) {
+               pr_err("Invalid domain value %d\n", domain);
+               return -EINVAL;
+       }
+
+       if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
+               return -EINVAL;
+
+       mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
+       if (IS_ERR(mailbox))
+               return PTR_ERR(mailbox);
+       ctrl = mailbox->buf;
+
+       ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
+                                flow_attr->priority);
+       ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
+       ctrl->port = flow_attr->port;
+       ctrl->qpn = cpu_to_be32(qp->qp_num);
+
+       ib_flow = flow_attr + 1;
+       size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
+       /* Add default flows */
+       default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
+       if (default_flow >= 0) {
+               ret = __mlx4_ib_create_default_rules(
+                               mdev, qp, default_table + default_flow,
+                               mailbox->buf + size);
+               if (ret < 0) {
+                       mlx4_free_cmd_mailbox(mdev->dev, mailbox);
+                       return -EINVAL;
+               }
+               size += ret;
+       }
+       for (i = 0; i < flow_attr->num_of_specs; i++) {
+               ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
+                                     mailbox->buf + size);
+               if (ret < 0) {
+                       mlx4_free_cmd_mailbox(mdev->dev, mailbox);
+                       return -EINVAL;
+               }
+               ib_flow += ((union ib_flow_spec *) ib_flow)->size;
+               size += ret;
+       }
+
+       ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
+                          MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
+                          MLX4_CMD_NATIVE);
+       if (ret == -ENOMEM)
+               pr_err("mcg table is full. Fail to register network rule.\n");
+       else if (ret == -ENXIO)
+               pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
+       else if (ret)
+               pr_err("Invalid argumant. Fail to register network rule.\n");
+
+       mlx4_free_cmd_mailbox(mdev->dev, mailbox);
+       return ret;
+}
+
+static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
+{
+       int err;
+       err = mlx4_cmd(dev, reg_id, 0, 0,
+                      MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
+                      MLX4_CMD_NATIVE);
+       if (err)
+               pr_err("Fail to detach network rule. registration id = 0x%llx\n",
+                      reg_id);
+       return err;
+}
+
+static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
+                                   u64 *reg_id)
+{
+       void *ib_flow;
+       union ib_flow_spec *ib_spec;
+       struct mlx4_dev *dev = to_mdev(qp->device)->dev;
+       int err = 0;
+
+       if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
+           dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
+               return 0; /* do nothing */
+
+       ib_flow = flow_attr + 1;
+       ib_spec = (union ib_flow_spec *)ib_flow;
+
+       if (ib_spec->type !=  IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
+               return 0; /* do nothing */
+
+       err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
+                                   flow_attr->port, qp->qp_num,
+                                   MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
+                                   reg_id);
+       return err;
+}
+
+static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
+                                   struct ib_flow_attr *flow_attr,
+                                   int domain)
+{
+       int err = 0, i = 0, j = 0;
+       struct mlx4_ib_flow *mflow;
+       enum mlx4_net_trans_promisc_mode type[2];
+       struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
+       int is_bonded = mlx4_is_bonded(dev);
+
+       memset(type, 0, sizeof(type));
+
+       mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
+       if (!mflow) {
+               err = -ENOMEM;
+               goto err_free;
+       }
+
+       switch (flow_attr->type) {
+       case IB_FLOW_ATTR_NORMAL:
+               type[0] = MLX4_FS_REGULAR;
+               break;
+
+       case IB_FLOW_ATTR_ALL_DEFAULT:
+               type[0] = MLX4_FS_ALL_DEFAULT;
+               break;
+
+       case IB_FLOW_ATTR_MC_DEFAULT:
+               type[0] = MLX4_FS_MC_DEFAULT;
+               break;
+
+       case IB_FLOW_ATTR_SNIFFER:
+               type[0] = MLX4_FS_UC_SNIFFER;
+               type[1] = MLX4_FS_MC_SNIFFER;
+               break;
+
+       default:
+               err = -EINVAL;
+               goto err_free;
+       }
+
+       while (i < ARRAY_SIZE(type) && type[i]) {
+               err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
+                                           &mflow->reg_id[i].id);
+               if (err)
+                       goto err_create_flow;
+               i++;
+               if (is_bonded) {
+                       /* Application always sees one port so the mirror rule
+                        * must be on port #2
+                        */
+                       flow_attr->port = 2;
+                       err = __mlx4_ib_create_flow(qp, flow_attr,
+                                                   domain, type[j],
+                                                   &mflow->reg_id[j].mirror);
+                       flow_attr->port = 1;
+                       if (err)
+                               goto err_create_flow;
+                       j++;
+               }
+
+       }
+
+       if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
+               err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
+                                              &mflow->reg_id[i].id);
+               if (err)
+                       goto err_create_flow;
+               i++;
+               if (is_bonded) {
+                       flow_attr->port = 2;
+                       err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
+                                                      &mflow->reg_id[j].mirror);
+                       flow_attr->port = 1;
+                       if (err)
+                               goto err_create_flow;
+                       j++;
+               }
+               /* function to create mirror rule */
+       }
+
+       return &mflow->ibflow;
+
+err_create_flow:
+       while (i) {
+               (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
+                                            mflow->reg_id[i].id);
+               i--;
+       }
+
+       while (j) {
+               (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
+                                            mflow->reg_id[j].mirror);
+               j--;
+       }
+err_free:
+       kfree(mflow);
+       return ERR_PTR(err);
+}
+
+static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
+{
+       int err, ret = 0;
+       int i = 0;
+       struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
+       struct mlx4_ib_flow *mflow = to_mflow(flow_id);
+
+       while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
+               err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
+               if (err)
+                       ret = err;
+               if (mflow->reg_id[i].mirror) {
+                       err = __mlx4_ib_destroy_flow(mdev->dev,
+                                                    mflow->reg_id[i].mirror);
+                       if (err)
+                               ret = err;
+               }
+               i++;
+       }
+
+       kfree(mflow);
+       return ret;
+}
+
+static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
+{
+       int err;
+       struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
+       struct mlx4_dev *dev = mdev->dev;
+       struct mlx4_ib_qp *mqp = to_mqp(ibqp);
+       struct mlx4_ib_steering *ib_steering = NULL;
+       enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
+       struct mlx4_flow_reg_id reg_id;
+
+       if (mdev->dev->caps.steering_mode ==
+           MLX4_STEERING_MODE_DEVICE_MANAGED) {
+               ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
+               if (!ib_steering)
+                       return -ENOMEM;
+       }
+
+       err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
+                                   !!(mqp->flags &
+                                      MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
+                                   prot, &reg_id.id);
+       if (err) {
+               pr_err("multicast attach op failed, err %d\n", err);
+               goto err_malloc;
+       }
+
+       reg_id.mirror = 0;
+       if (mlx4_is_bonded(dev)) {
+               err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
+                                           (mqp->port == 1) ? 2 : 1,
+                                           !!(mqp->flags &
+                                           MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
+                                           prot, &reg_id.mirror);
+               if (err)
+                       goto err_add;
+       }
+
+       err = add_gid_entry(ibqp, gid);
+       if (err)
+               goto err_add;
+
+       if (ib_steering) {
+               memcpy(ib_steering->gid.raw, gid->raw, 16);
+               ib_steering->reg_id = reg_id;
+               mutex_lock(&mqp->mutex);
+               list_add(&ib_steering->list, &mqp->steering_rules);
+               mutex_unlock(&mqp->mutex);
+       }
+       return 0;
+
+err_add:
+       mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
+                             prot, reg_id.id);
+       if (reg_id.mirror)
+               mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
+                                     prot, reg_id.mirror);
+err_malloc:
+       kfree(ib_steering);
+
+       return err;
+}
+
+static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
+{
+       struct mlx4_ib_gid_entry *ge;
+       struct mlx4_ib_gid_entry *tmp;
+       struct mlx4_ib_gid_entry *ret = NULL;
+
+       list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
+               if (!memcmp(raw, ge->gid.raw, 16)) {
+                       ret = ge;
+                       break;
+               }
+       }
+
+       return ret;
+}
+
+static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
+{
+       int err;
+       struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
+       struct mlx4_dev *dev = mdev->dev;
+       struct mlx4_ib_qp *mqp = to_mqp(ibqp);
+       struct net_device *ndev;
+       struct mlx4_ib_gid_entry *ge;
+       struct mlx4_flow_reg_id reg_id = {0, 0};
+       enum mlx4_protocol prot =  MLX4_PROT_IB_IPV6;
+
+       if (mdev->dev->caps.steering_mode ==
+           MLX4_STEERING_MODE_DEVICE_MANAGED) {
+               struct mlx4_ib_steering *ib_steering;
+
+               mutex_lock(&mqp->mutex);
+               list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
+                       if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
+                               list_del(&ib_steering->list);
+                               break;
+                       }
+               }
+               mutex_unlock(&mqp->mutex);
+               if (&ib_steering->list == &mqp->steering_rules) {
+                       pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
+                       return -EINVAL;
+               }
+               reg_id = ib_steering->reg_id;
+               kfree(ib_steering);
+       }
+
+       err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
+                                   prot, reg_id.id);
+       if (err)
+               return err;
+
+       if (mlx4_is_bonded(dev)) {
+               err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
+                                           prot, reg_id.mirror);
+               if (err)
+                       return err;
+       }
+
+       mutex_lock(&mqp->mutex);
+       ge = find_gid_entry(mqp, gid->raw);
+       if (ge) {
+               spin_lock_bh(&mdev->iboe.lock);
+               ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
+               if (ndev)
+                       dev_hold(ndev);
+               spin_unlock_bh(&mdev->iboe.lock);
+               if (ndev)
+                       dev_put(ndev);
+               list_del(&ge->list);
+               kfree(ge);
+       } else
+               pr_warn("could not find mgid entry\n");
+
+       mutex_unlock(&mqp->mutex);
+
+       return 0;
+}
+
+static int init_node_data(struct mlx4_ib_dev *dev)
+{
+       struct ib_smp *in_mad  = NULL;
+       struct ib_smp *out_mad = NULL;
+       int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
+       int err = -ENOMEM;
+
+       in_mad  = kzalloc(sizeof *in_mad, GFP_KERNEL);
+       out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
+       if (!in_mad || !out_mad)
+               goto out;
+
+       init_query_mad(in_mad);
+       in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
+       if (mlx4_is_master(dev->dev))
+               mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
+
+       err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
+       if (err)
+               goto out;
+
+       memcpy(dev->ib_dev.node_desc, out_mad->data, 64);
+
+       in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
+
+       err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
+       if (err)
+               goto out;
+
+       dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
+       memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
+
+out:
+       kfree(in_mad);
+       kfree(out_mad);
+       return err;
+}
+
+#if 0  /* AKAROS */
+
+static ssize_t show_hca(struct device *device, struct device_attribute *attr,
+                       char *buf)
+{
+       struct mlx4_ib_dev *dev =
+               container_of(device, struct mlx4_ib_dev, ib_dev.dev);
+       return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
+}
+
+static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
+                          char *buf)
+{
+       struct mlx4_ib_dev *dev =
+               container_of(device, struct mlx4_ib_dev, ib_dev.dev);
+       return sprintf(buf, "%d.%d.%d\n", (int) (dev->dev->caps.fw_ver >> 32),
+                      (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
+                      (int) dev->dev->caps.fw_ver & 0xffff);
+}
+
+static ssize_t show_rev(struct device *device, struct device_attribute *attr,
+                       char *buf)
+{
+       struct mlx4_ib_dev *dev =
+               container_of(device, struct mlx4_ib_dev, ib_dev.dev);
+       return sprintf(buf, "%x\n", dev->dev->rev_id);
+}
+
+static ssize_t show_board(struct device *device, struct device_attribute *attr,
+                         char *buf)
+{
+       struct mlx4_ib_dev *dev =
+               container_of(device, struct mlx4_ib_dev, ib_dev.dev);
+       return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
+                      dev->dev->board_id);
+}
+
+static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
+static DEVICE_ATTR(fw_ver,   S_IRUGO, show_fw_ver, NULL);
+static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
+static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
+
+static struct device_attribute *mlx4_class_attributes[] = {
+       &dev_attr_hw_rev,
+       &dev_attr_fw_ver,
+       &dev_attr_hca_type,
+       &dev_attr_board_id
+};
+
+#endif /* AKAROS */
+
+static void mlx4_addrconf_ifid_eui48(u8 *eui, u16 vlan_id,
+                                    struct net_device *dev)
+{
+       memcpy(eui, dev->dev_addr, 3);
+       memcpy(eui + 5, dev->dev_addr + 3, 3);
+       if (vlan_id < 0x1000) {
+               eui[3] = vlan_id >> 8;
+               eui[4] = vlan_id & 0xff;
+       } else {
+               eui[3] = 0xff;
+               eui[4] = 0xfe;
+       }
+       eui[0] ^= 2;
+}
+
+static void update_gids_task(struct work_struct *work)
+{
+       struct update_gid_work *gw = container_of(work, struct update_gid_work, work);
+       struct mlx4_cmd_mailbox *mailbox;
+       union ib_gid *gids;
+       int err;
+       struct mlx4_dev *dev = gw->dev->dev;
+       int is_bonded = mlx4_is_bonded(dev);
+
+       if (!gw->dev->ib_active)
+               return;
+
+       mailbox = mlx4_alloc_cmd_mailbox(dev);
+       if (IS_ERR(mailbox)) {
+               pr_warn("update gid table failed %ld\n", PTR_ERR(mailbox));
+               return;
+       }
+
+       gids = mailbox->buf;
+       memcpy(gids, gw->gids, sizeof gw->gids);
+
+       err = mlx4_cmd(dev, mailbox->dma, MLX4_SET_PORT_GID_TABLE << 8 | gw->port,
+                      MLX4_SET_PORT_ETH_OPCODE, MLX4_CMD_SET_PORT,
+                      MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
+       if (err)
+               pr_warn("set port command failed\n");
+       else
+               if ((gw->port == 1) || !is_bonded)
+                       mlx4_ib_dispatch_event(gw->dev,
+                                              is_bonded ? 1 : gw->port,
+                                              IB_EVENT_GID_CHANGE);
+
+       mlx4_free_cmd_mailbox(dev, mailbox);
+       kfree(gw);
+}
+
+static void reset_gids_task(struct work_struct *work)
+{
+       struct update_gid_work *gw =
+                       container_of(work, struct update_gid_work, work);
+       struct mlx4_cmd_mailbox *mailbox;
+       union ib_gid *gids;
+       int err;
+       struct mlx4_dev *dev = gw->dev->dev;
+
+       if (!gw->dev->ib_active)
+               return;
+
+       mailbox = mlx4_alloc_cmd_mailbox(dev);
+       if (IS_ERR(mailbox)) {
+               pr_warn("reset gid table failed\n");
+               goto free;
+       }
+
+       gids = mailbox->buf;
+       memcpy(gids, gw->gids, sizeof(gw->gids));
+
+       if (mlx4_ib_port_link_layer(&gw->dev->ib_dev, gw->port) ==
+                                   IB_LINK_LAYER_ETHERNET) {
+               err = mlx4_cmd(dev, mailbox->dma,
+                              MLX4_SET_PORT_GID_TABLE << 8 | gw->port,
+                              MLX4_SET_PORT_ETH_OPCODE, MLX4_CMD_SET_PORT,
+                              MLX4_CMD_TIME_CLASS_B,
+                              MLX4_CMD_WRAPPED);
+               if (err)
+                       pr_warn("set port %d command failed\n", gw->port);
+       }
+
+       mlx4_free_cmd_mailbox(dev, mailbox);
+free:
+       kfree(gw);
+}
+
+static int update_gid_table(struct mlx4_ib_dev *dev, int port,
+                           union ib_gid *gid, int clear,
+                           int default_gid)
+{
+       struct update_gid_work *work;
+       int i;
+       int need_update = 0;
+       int free = -1;
+       int found = -1;
+       int max_gids;
+
+       if (default_gid) {
+               free = 0;
+       } else {
+               max_gids = dev->dev->caps.gid_table_len[port];
+               for (i = 1; i < max_gids; ++i) {
+                       if (!memcmp(&dev->iboe.gid_table[port - 1][i], gid,
+                                   sizeof(*gid)))
+                               found = i;
+
+                       if (clear) {
+                               if (found >= 0) {
+                                       need_update = 1;
+                                       dev->iboe.gid_table[port - 1][found] =
+                                               zgid;
+                                       break;
+                               }
+                       } else {
+                               if (found >= 0)
+                                       break;
+
+                               if (free < 0 &&
+                                   !memcmp(&dev->iboe.gid_table[port - 1][i],
+                                           &zgid, sizeof(*gid)))
+                                       free = i;
+                       }
+               }
+       }
+
+       if (found == -1 && !clear && free >= 0) {
+               dev->iboe.gid_table[port - 1][free] = *gid;
+               need_update = 1;
+       }
+
+       if (!need_update)
+               return 0;
+
+       work = kzalloc(sizeof(*work), GFP_ATOMIC);
+       if (!work)
+               return -ENOMEM;
+
+       memcpy(work->gids, dev->iboe.gid_table[port - 1], sizeof(work->gids));
+       INIT_WORK(&work->work, update_gids_task);
+       work->port = port;
+       work->dev = dev;
+       queue_work(wq, &work->work);
+
+       return 0;
+}
+
+static void mlx4_make_default_gid(struct  net_device *dev, union ib_gid *gid)
+{
+       gid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
+       mlx4_addrconf_ifid_eui48(&gid->raw[8], 0xffff, dev);
+}
+
+
+static int reset_gid_table(struct mlx4_ib_dev *dev, u8 port)
+{
+       struct update_gid_work *work;
+
+       work = kzalloc(sizeof(*work), GFP_ATOMIC);
+       if (!work)
+               return -ENOMEM;
+
+       memset(dev->iboe.gid_table[port - 1], 0, sizeof(work->gids));
+       memset(work->gids, 0, sizeof(work->gids));
+#if 1  /* AKAROS */
+       return 0;
+#endif /* AKAROS */
+       INIT_WORK(&work->work, reset_gids_task);
+       work->dev = dev;
+       work->port = port;
+       queue_work(wq, &work->work);
+       return 0;
+}
+
+#if 0  /* AKAROS */
+
+static int mlx4_ib_addr_event(int event, struct net_device *event_netdev,
+                             struct mlx4_ib_dev *ibdev, union ib_gid *gid)
+{
+       struct mlx4_ib_iboe *iboe;
+       int port = 0;
+       struct net_device *real_dev = rdma_vlan_dev_real_dev(event_netdev) ?
+                               rdma_vlan_dev_real_dev(event_netdev) :
+                               event_netdev;
+       union ib_gid default_gid;
+
+       mlx4_make_default_gid(real_dev, &default_gid);
+
+       if (!memcmp(gid, &default_gid, sizeof(*gid)))
+               return 0;
+
+       if (event != NETDEV_DOWN && event != NETDEV_UP)
+               return 0;
+
+       if ((real_dev != event_netdev) &&
+           (event == NETDEV_DOWN) &&
+           rdma_link_local_addr((struct in6_addr *)gid))
+               return 0;
+
+       iboe = &ibdev->iboe;
+       spin_lock_bh(&iboe->lock);
+
+       for (port = 1; port <= ibdev->dev->caps.num_ports; ++port)
+               if ((netif_is_bond_master(real_dev) &&
+                    (real_dev == iboe->masters[port - 1])) ||
+                    (!netif_is_bond_master(real_dev) &&
+                    (real_dev == iboe->netdevs[port - 1])))
+                       update_gid_table(ibdev, port, gid,
+                                        event == NETDEV_DOWN, 0);
+
+       spin_unlock_bh(&iboe->lock);
+       return 0;
+
+}
+
+static u8 mlx4_ib_get_dev_port(struct net_device *dev,
+                              struct mlx4_ib_dev *ibdev)
+{
+       u8 port = 0;
+       struct mlx4_ib_iboe *iboe;
+       struct net_device *real_dev = rdma_vlan_dev_real_dev(dev) ?
+                               rdma_vlan_dev_real_dev(dev) : dev;
+
+       iboe = &ibdev->iboe;
+
+       for (port = 1; port <= ibdev->dev->caps.num_ports; ++port)
+               if ((netif_is_bond_master(real_dev) &&
+                    (real_dev == iboe->masters[port - 1])) ||
+                    (!netif_is_bond_master(real_dev) &&
+                    (real_dev == iboe->netdevs[port - 1])))
+                       break;
+
+       if ((port == 0) || (port > ibdev->dev->caps.num_ports))
+               return 0;
+       else
+               return port;
+}
+
+static int mlx4_ib_inet_event(struct notifier_block *this, unsigned long event,
+                               void *ptr)
+{
+       struct mlx4_ib_dev *ibdev;
+       struct in_ifaddr *ifa = ptr;
+       union ib_gid gid;
+       struct net_device *event_netdev = ifa->ifa_dev->dev;
+
+       ipv6_addr_set_v4mapped(ifa->ifa_address, (struct in6_addr *)&gid);
+
+       ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb_inet);
+
+       mlx4_ib_addr_event(event, event_netdev, ibdev, &gid);
+       return NOTIFY_DONE;
+}
+
+#if IS_ENABLED(CONFIG_IPV6)
+static int mlx4_ib_inet6_event(struct notifier_block *this, unsigned long event,
+                               void *ptr)
+{
+       struct mlx4_ib_dev *ibdev;
+       struct inet6_ifaddr *ifa = ptr;
+       union  ib_gid *gid = (union ib_gid *)&ifa->addr;
+       struct net_device *event_netdev = ifa->idev->dev;
+
+       ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb_inet6);
+
+       mlx4_ib_addr_event(event, event_netdev, ibdev, gid);
+       return NOTIFY_DONE;
+}
+#endif
+
+#define MLX4_IB_INVALID_MAC    ((u64)-1)
+static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
+                              struct net_device *dev,
+                              int port)
+{
+       u64 new_smac = 0;
+       u64 release_mac = MLX4_IB_INVALID_MAC;
+       struct mlx4_ib_qp *qp;
+
+       read_lock(&dev_base_lock);
+       new_smac = mlx4_mac_to_u64(dev->dev_addr);
+       read_unlock(&dev_base_lock);
+
+       atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
+
+       /* no need for update QP1 and mac registration in non-SRIOV */
+       if (!mlx4_is_mfunc(ibdev->dev))
+               return;
+
+       mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
+       qp = ibdev->qp1_proxy[port - 1];
+       if (qp) {
+               int new_smac_index;
+               u64 old_smac;
+               struct mlx4_update_qp_params update_params;
+
+               mutex_lock(&qp->mutex);
+               old_smac = qp->pri.smac;
+               if (new_smac == old_smac)
+                       goto unlock;
+
+               new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
+
+               if (new_smac_index < 0)
+                       goto unlock;
+
+               update_params.smac_index = new_smac_index;
+               if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
+                                  &update_params)) {
+                       release_mac = new_smac;
+                       goto unlock;
+               }
+               /* if old port was zero, no mac was yet registered for this QP */
+               if (qp->pri.smac_port)
+                       release_mac = old_smac;
+               qp->pri.smac = new_smac;
+               qp->pri.smac_port = port;
+               qp->pri.smac_index = new_smac_index;
+       }
+
+unlock:
+       if (release_mac != MLX4_IB_INVALID_MAC)
+               mlx4_unregister_mac(ibdev->dev, port, release_mac);
+       if (qp)
+               mutex_unlock(&qp->mutex);
+       mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
+}
+
+static void mlx4_ib_get_dev_addr(struct net_device *dev,
+                                struct mlx4_ib_dev *ibdev, u8 port)
+{
+       struct in_device *in_dev;
+#if IS_ENABLED(CONFIG_IPV6)
+       struct inet6_dev *in6_dev;
+       union ib_gid  *pgid;
+       struct inet6_ifaddr *ifp;
+       union ib_gid default_gid;
+#endif
+       union ib_gid gid;
+
+
+       if ((port == 0) || (port > ibdev->dev->caps.num_ports))
+               return;
+
+       /* IPv4 gids */
+       in_dev = in_dev_get(dev);
+       if (in_dev) {
+               for_ifa(in_dev) {
+                       /*ifa->ifa_address;*/
+                       ipv6_addr_set_v4mapped(ifa->ifa_address,
+                                              (struct in6_addr *)&gid);
+                       update_gid_table(ibdev, port, &gid, 0, 0);
+               }
+               endfor_ifa(in_dev);
+               in_dev_put(in_dev);
+       }
+#if IS_ENABLED(CONFIG_IPV6)
+       mlx4_make_default_gid(dev, &default_gid);
+       /* IPv6 gids */
+       in6_dev = in6_dev_get(dev);
+       if (in6_dev) {
+               read_lock_bh(&in6_dev->lock);
+               list_for_each_entry(ifp, &in6_dev->addr_list, if_list) {
+                       pgid = (union ib_gid *)&ifp->addr;
+                       if (!memcmp(pgid, &default_gid, sizeof(*pgid)))
+                               continue;
+                       update_gid_table(ibdev, port, pgid, 0, 0);
+               }
+               read_unlock_bh(&in6_dev->lock);
+               in6_dev_put(in6_dev);
+       }
+#endif
+}
+
+#endif /* AKAROS */
+
+static void mlx4_ib_set_default_gid(struct mlx4_ib_dev *ibdev,
+                                struct  net_device *dev, u8 port)
+{
+       union ib_gid gid;
+       mlx4_make_default_gid(dev, &gid);
+       update_gid_table(ibdev, port, &gid, 0, 1);
+}
+
+static int mlx4_ib_init_gid_table(struct mlx4_ib_dev *ibdev)
+{
+       struct  net_device *dev;
+       struct mlx4_ib_iboe *iboe = &ibdev->iboe;
+       int i;
+       int err = 0;
+
+       for (i = 1; i <= ibdev->num_ports; ++i) {
+               if (rdma_port_get_link_layer(&ibdev->ib_dev, i) ==
+                   IB_LINK_LAYER_ETHERNET) {
+                       err = reset_gid_table(ibdev, i);
+                       if (err)
+                               goto out;
+               }
+       }
+
+#if 0  /* AKAROS */
+       read_lock(&dev_base_lock);
+       spin_lock_bh(&iboe->lock);
+
+       for_each_netdev(&init_net, dev) {
+               u8 port = mlx4_ib_get_dev_port(dev, ibdev);
+               /* port will be non-zero only for ETH ports */
+               if (port) {
+                       mlx4_ib_set_default_gid(ibdev, dev, port);
+                       mlx4_ib_get_dev_addr(dev, ibdev, port);
+               }
+       }
+
+       spin_unlock_bh(&iboe->lock);
+       read_unlock(&dev_base_lock);
+#endif /* AKAROS */
+out:
+       return err;
+}
+
+#if 0  /* AKAROS */
+
+static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
+                                struct net_device *dev,
+                                unsigned long event)
+
+{
+       struct mlx4_ib_iboe *iboe;
+       int update_qps_port = -1;
+       int port;
+
+       iboe = &ibdev->iboe;
+
+       spin_lock_bh(&iboe->lock);
+       mlx4_foreach_ib_transport_port(port, ibdev->dev) {
+               enum ib_port_state      port_state = IB_PORT_NOP;
+               struct net_device *old_master = iboe->masters[port - 1];
+               struct net_device *curr_netdev;
+               struct net_device *curr_master;
+
+               iboe->netdevs[port - 1] =
+                       mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
+               if (iboe->netdevs[port - 1])
+                       mlx4_ib_set_default_gid(ibdev,
+                                               iboe->netdevs[port - 1], port);
+               curr_netdev = iboe->netdevs[port - 1];
+
+               if (iboe->netdevs[port - 1] &&
+                   netif_is_bond_slave(iboe->netdevs[port - 1])) {
+                       iboe->masters[port - 1] = netdev_master_upper_dev_get(
+                               iboe->netdevs[port - 1]);
+               } else {
+                       iboe->masters[port - 1] = NULL;
+               }
+               curr_master = iboe->masters[port - 1];
+
+               if (dev == iboe->netdevs[port - 1] &&
+                   (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
+                    event == NETDEV_UP || event == NETDEV_CHANGE))
+                       update_qps_port = port;
+
+               if (curr_netdev) {
+                       port_state = (netif_running(curr_netdev) && netif_carrier_ok(curr_netdev)) ?
+                                               IB_PORT_ACTIVE : IB_PORT_DOWN;
+                       mlx4_ib_set_default_gid(ibdev, curr_netdev, port);
+                       if (curr_master) {
+                               /* if using bonding/team and a slave port is down, we
+                                * don't want the bond IP based gids in the table since
+                                * flows that select port by gid may get the down port.
+                               */
+                               if (port_state == IB_PORT_DOWN &&
+                                   !mlx4_is_bonded(ibdev->dev)) {
+                                       reset_gid_table(ibdev, port);
+                                       mlx4_ib_set_default_gid(ibdev,
+                                                               curr_netdev,
+                                                               port);
+                               } else {
+                                       /* gids from the upper dev (bond/team)
+                                        * should appear in port's gid table
+                                       */
+                                       mlx4_ib_get_dev_addr(curr_master,
+                                                            ibdev, port);
+                               }
+                       }
+                       /* if bonding is used it is possible that we add it to
+                        * masters only after IP address is assigned to the
+                        * net bonding interface.
+                       */
+                       if (curr_master && (old_master != curr_master)) {
+                               reset_gid_table(ibdev, port);
+                               mlx4_ib_set_default_gid(ibdev,
+                                                       curr_netdev, port);
+                               mlx4_ib_get_dev_addr(curr_master, ibdev, port);
+                       }
+
+                       if (!curr_master && (old_master != curr_master)) {
+                               reset_gid_table(ibdev, port);
+                               mlx4_ib_set_default_gid(ibdev,
+                                                       curr_netdev, port);
+                               mlx4_ib_get_dev_addr(curr_netdev, ibdev, port);
+                       }
+               } else {
+                       reset_gid_table(ibdev, port);
+               }
+       }
+
+       spin_unlock_bh(&iboe->lock);
+
+       if (update_qps_port > 0)
+               mlx4_ib_update_qps(ibdev, dev, update_qps_port);
+}
+
+static int mlx4_ib_netdev_event(struct notifier_block *this,
+                               unsigned long event, void *ptr)
+{
+       struct net_device *dev = netdev_notifier_info_to_dev(ptr);
+       struct mlx4_ib_dev *ibdev;
+
+       if (!net_eq(dev_net(dev), &init_net))
+               return NOTIFY_DONE;
+
+       ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
+       mlx4_ib_scan_netdevs(ibdev, dev, event);
+
+       return NOTIFY_DONE;
+}
+
+#endif /* AKAROS */
+
+static void init_pkeys(struct mlx4_ib_dev *ibdev)
+{
+       int port;
+       int slave;
+       int i;
+
+       if (mlx4_is_master(ibdev->dev)) {
+               for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
+                    ++slave) {
+                       for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
+                               for (i = 0;
+                                    i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
+                                    ++i) {
+                                       ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
+                                       /* master has the identity virt2phys pkey mapping */
+                                               (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
+                                                       ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
+                                       mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
+                                                            ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
+                               }
+                       }
+               }
+               /* initialize pkey cache */
+               for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
+                       for (i = 0;
+                            i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
+                            ++i)
+                               ibdev->pkeys.phys_pkey_cache[port-1][i] =
+                                       (i) ? 0 : 0xFFFF;
+               }
+       }
+}
+
+static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
+{
+       char name[80];
+       int eq_per_port = 0;
+       int added_eqs = 0;
+       int total_eqs = 0;
+       int i, j, eq;
+
+       /* Legacy mode or comp_pool is not large enough */
+       if (dev->caps.comp_pool == 0 ||
+           dev->caps.num_ports > dev->caps.comp_pool)
+               return;
+
+       eq_per_port = dev->caps.comp_pool / dev->caps.num_ports;
+
+       /* Init eq table */
+       added_eqs = 0;
+       mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
+               added_eqs += eq_per_port;
+
+       total_eqs = dev->caps.num_comp_vectors + added_eqs;
+
+       ibdev->eq_table = kzalloc(total_eqs * sizeof(int), GFP_KERNEL);
+       if (!ibdev->eq_table)
+               return;
+
+       ibdev->eq_added = added_eqs;
+
+       eq = 0;
+       mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) {
+               for (j = 0; j < eq_per_port; j++) {
+#if 0  /* AKAROS */
+                       snprintf(name, sizeof(name), "mlx4-ib-%d-%d@%s",
+                                i, j, dev->persist->pdev->bus->name);
+#else  /* AKAROS */
+                       snprintf(name, sizeof(name), "mlx4-ib-%d-%d@%s",
+                                i, j, dev->persist->pdev->bus);
+#endif /* AKAROS */
+                       /* Set IRQ for specific name (per ring) */
+                       if (mlx4_assign_eq(dev, name, NULL,
+                                          &ibdev->eq_table[eq])) {
+                               /* Use legacy (same as mlx4_en driver) */
+                               pr_warn("Can't allocate EQ %d; reverting to legacy\n", eq);
+                               ibdev->eq_table[eq] =
+                                       (eq % dev->caps.num_comp_vectors);
+                       }
+                       eq++;
+               }
+       }
+
+       /* Fill the reset of the vector with legacy EQ */
+       for (i = 0, eq = added_eqs; i < dev->caps.num_comp_vectors; i++)
+               ibdev->eq_table[eq++] = i;
+
+       /* Advertise the new number of EQs to clients */
+       ibdev->ib_dev.num_comp_vectors = total_eqs;
+}
+
+static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
+{
+       int i;
+
+       /* no additional eqs were added */
+       if (!ibdev->eq_table)
+               return;
+
+       /* Reset the advertised EQ number */
+       ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
+
+       /* Free only the added eqs */
+       for (i = 0; i < ibdev->eq_added; i++) {
+               /* Don't free legacy eqs if used */
+               if (ibdev->eq_table[i] <= dev->caps.num_comp_vectors)
+                       continue;
+               mlx4_release_eq(dev, ibdev->eq_table[i]);
+       }
+
+       kfree(ibdev->eq_table);
+}
+
+static void *mlx4_ib_add(struct mlx4_dev *dev)
+{
+       struct mlx4_ib_dev *ibdev;
+       int num_ports = 0;
+       int i, j;
+       int err;
+       struct mlx4_ib_iboe *iboe;
+       int ib_num_ports = 0;
+       int num_req_counters;
+
+       pr_info_once("%s", mlx4_ib_version);
+
+       num_ports = 0;
+       mlx4_foreach_ib_transport_port(i, dev)
+               num_ports++;
+
+       /* No point in registering a device with no ports... */
+       if (num_ports == 0)
+               return NULL;
+
+       ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
+       if (!ibdev) {
+               dev_err(&dev->persist->pdev->dev,
+                       "Device struct alloc failed\n");
+               return NULL;
+       }
+
+       iboe = &ibdev->iboe;
+
+       if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
+               goto err_dealloc;
+
+       if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
+               goto err_pd;
+
+       ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
+                                PAGE_SIZE);
+       if (!ibdev->uar_map)
+               goto err_uar;
+       MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
+
+       ibdev->dev = dev;
+       ibdev->bond_next_port   = 0;
+
+       strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
+       ibdev->ib_dev.owner             = THIS_MODULE;
+       ibdev->ib_dev.node_type         = RDMA_NODE_IB_CA;
+       ibdev->ib_dev.local_dma_lkey    = dev->caps.reserved_lkey;
+       ibdev->num_ports                = num_ports;
+       ibdev->ib_dev.phys_port_cnt     = mlx4_is_bonded(dev) ?
+                                               1 : ibdev->num_ports;
+       ibdev->ib_dev.num_comp_vectors  = dev->caps.num_comp_vectors;
+#if 0  /* AKAROS */
+       ibdev->ib_dev.dma_device        = &dev->persist->pdev->dev;
+#endif /* AKAROS */
+
+       if (dev->caps.userspace_caps)
+               ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
+       else
+               ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
+
+#if 0  /* AKAROS */
+       ibdev->ib_dev.uverbs_cmd_mask   =
+               (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
+               (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
+               (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
+               (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
+               (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
+               (1ull << IB_USER_VERBS_CMD_REG_MR)              |
+               (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
+               (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
+               (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
+               (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
+               (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
+               (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
+               (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
+               (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
+               (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
+               (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
+               (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
+               (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
+               (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
+               (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
+               (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
+               (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
+               (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
+               (1ull << IB_USER_VERBS_CMD_OPEN_QP);
+#else  /* AKAROS */
+       ibdev->ib_dev.uverbs_cmd_mask   =
+               (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
+               (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
+               (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
+               (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
+               (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
+               (1ull << IB_USER_VERBS_CMD_REG_MR)              |
+               (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
+               (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
+               (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
+               (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
+               (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
+               (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
+               (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
+               (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
+               (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
+               (1ull << IB_USER_VERBS_CMD_DETACH_MCAST);
+#endif /* AKAROS */
+
+       ibdev->ib_dev.query_device      = mlx4_ib_query_device;
+       ibdev->ib_dev.query_port        = mlx4_ib_query_port;
+       ibdev->ib_dev.get_link_layer    = mlx4_ib_port_link_layer;
+       ibdev->ib_dev.query_gid         = mlx4_ib_query_gid;
+       ibdev->ib_dev.query_pkey        = mlx4_ib_query_pkey;
+       ibdev->ib_dev.modify_device     = mlx4_ib_modify_device;
+       ibdev->ib_dev.modify_port       = mlx4_ib_modify_port;
+       ibdev->ib_dev.alloc_ucontext    = mlx4_ib_alloc_ucontext;
+       ibdev->ib_dev.dealloc_ucontext  = mlx4_ib_dealloc_ucontext;
+       ibdev->ib_dev.mmap              = mlx4_ib_mmap;
+       ibdev->ib_dev.alloc_pd          = mlx4_ib_alloc_pd;
+       ibdev->ib_dev.dealloc_pd        = mlx4_ib_dealloc_pd;
+       ibdev->ib_dev.create_ah         = mlx4_ib_create_ah;
+#if 0  /* AKAROS */
+       ibdev->ib_dev.query_ah          = mlx4_ib_query_ah;
+#endif /* AKAROS */
+       ibdev->ib_dev.destroy_ah        = mlx4_ib_destroy_ah;
+#if 0  /* AKAROS */
+       ibdev->ib_dev.create_srq        = mlx4_ib_create_srq;
+       ibdev->ib_dev.modify_srq        = mlx4_ib_modify_srq;
+       ibdev->ib_dev.query_srq         = mlx4_ib_query_srq;
+       ibdev->ib_dev.destroy_srq       = mlx4_ib_destroy_srq;
+       ibdev->ib_dev.post_srq_recv     = mlx4_ib_post_srq_recv;
+#endif /* AKAROS */
+       ibdev->ib_dev.create_qp         = mlx4_ib_create_qp;
+       ibdev->ib_dev.modify_qp         = mlx4_ib_modify_qp;
+       ibdev->ib_dev.query_qp          = mlx4_ib_query_qp;
+       ibdev->ib_dev.destroy_qp        = mlx4_ib_destroy_qp;
+       ibdev->ib_dev.post_send         = mlx4_ib_post_send;
+       ibdev->ib_dev.post_recv         = mlx4_ib_post_recv;
+       ibdev->ib_dev.create_cq         = mlx4_ib_create_cq;
+       ibdev->ib_dev.modify_cq         = mlx4_ib_modify_cq;
+       ibdev->ib_dev.resize_cq         = mlx4_ib_resize_cq;
+       ibdev->ib_dev.destroy_cq        = mlx4_ib_destroy_cq;
+       ibdev->ib_dev.poll_cq           = mlx4_ib_poll_cq;
+       ibdev->ib_dev.req_notify_cq     = mlx4_ib_arm_cq;
+       ibdev->ib_dev.get_dma_mr        = mlx4_ib_get_dma_mr;
+       ibdev->ib_dev.reg_user_mr       = mlx4_ib_reg_user_mr;
+#if 0  /* AKAROS */
+       ibdev->ib_dev.rereg_user_mr     = mlx4_ib_rereg_user_mr;
+#endif /* AKAROS */
+       ibdev->ib_dev.dereg_mr          = mlx4_ib_dereg_mr;
+#if 0  /* AKAROS */
+       ibdev->ib_dev.alloc_fast_reg_mr = mlx4_ib_alloc_fast_reg_mr;
+       ibdev->ib_dev.alloc_fast_reg_page_list = mlx4_ib_alloc_fast_reg_page_list;
+       ibdev->ib_dev.free_fast_reg_page_list  = mlx4_ib_free_fast_reg_page_list;
+#endif /* AKAROS */
+       ibdev->ib_dev.attach_mcast      = mlx4_ib_mcg_attach;
+       ibdev->ib_dev.detach_mcast      = mlx4_ib_mcg_detach;
+#if 0  /* AKAROS */
+       ibdev->ib_dev.process_mad       = mlx4_ib_process_mad;
+#endif /* AKAROS */
+
+       if (!mlx4_is_slave(ibdev->dev)) {
+               ibdev->ib_dev.alloc_fmr         = mlx4_ib_fmr_alloc;
+               ibdev->ib_dev.map_phys_fmr      = mlx4_ib_map_phys_fmr;
+               ibdev->ib_dev.unmap_fmr         = mlx4_ib_unmap_fmr;
+               ibdev->ib_dev.dealloc_fmr       = mlx4_ib_fmr_dealloc;
+       }
+
+       if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
+           dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
+               ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
+               ibdev->ib_dev.bind_mw = mlx4_ib_bind_mw;
+               ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
+
+               ibdev->ib_dev.uverbs_cmd_mask |=
+                       (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
+                       (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
+       }
+
+       if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
+               ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
+               ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
+               ibdev->ib_dev.uverbs_cmd_mask |=
+                       (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
+                       (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
+       }
+
+       if (check_flow_steering_support(dev)) {
+               ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
+               ibdev->ib_dev.create_flow       = mlx4_ib_create_flow;
+               ibdev->ib_dev.destroy_flow      = mlx4_ib_destroy_flow;
+
+               ibdev->ib_dev.uverbs_ex_cmd_mask        |=
+                       (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
+                       (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
+       }
+
+       mlx4_ib_alloc_eqs(dev, ibdev);
+
+       spin_lock_init(&iboe->lock);
+
+       if (init_node_data(ibdev))
+               goto err_map;
+
+       num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
+       for (i = 0; i < num_req_counters; ++i) {
+               mutex_init(&ibdev->qp1_proxy_lock[i]);
+               if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
+                                               IB_LINK_LAYER_ETHERNET) {
+                       err = mlx4_counter_alloc(ibdev->dev, &ibdev->counters[i]);
+                       if (err)
+                               ibdev->counters[i] = -1;
+               } else {
+                       ibdev->counters[i] = -1;
+               }
+       }
+       if (mlx4_is_bonded(dev))
+               for (i = 1; i < ibdev->num_ports ; ++i)
+                       ibdev->counters[i] = ibdev->counters[0];
+
+
+       mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
+               ib_num_ports++;
+
+       spin_lock_init(&ibdev->sm_lock);
+       mutex_init(&ibdev->cap_mask_mutex);
+       INIT_LIST_HEAD(&ibdev->qp_list);
+       spin_lock_init(&ibdev->reset_flow_resource_lock);
+
+       if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
+           ib_num_ports) {
+               ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
+               err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
+                                           MLX4_IB_UC_STEER_QPN_ALIGN,
+                                           &ibdev->steer_qpn_base, 0);
+               if (err)
+                       goto err_counter;
+
+               ibdev->ib_uc_qpns_bitmap =
+                       kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
+                               sizeof(long),
+                               GFP_KERNEL);
+               if (!ibdev->ib_uc_qpns_bitmap) {
+                       dev_err(&dev->persist->pdev->dev,
+                               "bit map alloc failed\n");
+                       goto err_steer_qp_release;
+               }
+
+               bitmap_zero(ibdev->ib_uc_qpns_bitmap, ibdev->steer_qpn_count);
+
+               err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
+                               dev, ibdev->steer_qpn_base,
+                               ibdev->steer_qpn_base +
+                               ibdev->steer_qpn_count - 1);
+               if (err)
+                       goto err_steer_free_bitmap;
+       }
+
+       for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
+               atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
+
+       if (ib_register_device(&ibdev->ib_dev, NULL))
+               goto err_steer_free_bitmap;
+
+       if (mlx4_ib_mad_init(ibdev))
+               goto err_reg;
+
+       if (mlx4_ib_init_sriov(ibdev))
+               goto err_mad;
+
+       if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) {
+#if 0  /* AKAROS */
+               if (!iboe->nb.notifier_call) {
+                       iboe->nb.notifier_call = mlx4_ib_netdev_event;
+                       err = register_netdevice_notifier(&iboe->nb);
+                       if (err) {
+                               iboe->nb.notifier_call = NULL;
+                               goto err_notif;
+                       }
+               }
+               if (!iboe->nb_inet.notifier_call) {
+                       iboe->nb_inet.notifier_call = mlx4_ib_inet_event;
+                       err = register_inetaddr_notifier(&iboe->nb_inet);
+                       if (err) {
+                               iboe->nb_inet.notifier_call = NULL;
+                               goto err_notif;
+                       }
+               }
+#if IS_ENABLED(CONFIG_IPV6)
+               if (!iboe->nb_inet6.notifier_call) {
+                       iboe->nb_inet6.notifier_call = mlx4_ib_inet6_event;
+                       err = register_inet6addr_notifier(&iboe->nb_inet6);
+                       if (err) {
+                               iboe->nb_inet6.notifier_call = NULL;
+                               goto err_notif;
+                       }
+               }
+#endif
+#endif /* AKAROS */
+               if (mlx4_ib_init_gid_table(ibdev))
+                       goto err_notif;
+       }
+
+#if 0  /* AKAROS */
+       for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
+               if (device_create_file(&ibdev->ib_dev.dev,
+                                      mlx4_class_attributes[j]))
+                       goto err_notif;
+       }
+#endif /* AKAROS */
+
+       ibdev->ib_active = true;
+
+       if (mlx4_is_mfunc(ibdev->dev))
+               init_pkeys(ibdev);
+
+       /* create paravirt contexts for any VFs which are active */
+       if (mlx4_is_master(ibdev->dev)) {
+               for (j = 0; j < MLX4_MFUNC_MAX; j++) {
+                       if (j == mlx4_master_func_num(ibdev->dev))
+                               continue;
+                       if (mlx4_is_slave_active(ibdev->dev, j))
+                               do_slave_init(ibdev, j, 1);
+               }
+       }
+       return ibdev;
+
+err_notif:
+#if 0  /* AKAROS */
+       if (ibdev->iboe.nb.notifier_call) {
+               if (unregister_netdevice_notifier(&ibdev->iboe.nb))
+                       pr_warn("failure unregistering notifier\n");
+               ibdev->iboe.nb.notifier_call = NULL;
+       }
+       if (ibdev->iboe.nb_inet.notifier_call) {
+               if (unregister_inetaddr_notifier(&ibdev->iboe.nb_inet))
+                       pr_warn("failure unregistering notifier\n");
+               ibdev->iboe.nb_inet.notifier_call = NULL;
+       }
+#if IS_ENABLED(CONFIG_IPV6)
+       if (ibdev->iboe.nb_inet6.notifier_call) {
+               if (unregister_inet6addr_notifier(&ibdev->iboe.nb_inet6))
+                       pr_warn("failure unregistering notifier\n");
+               ibdev->iboe.nb_inet6.notifier_call = NULL;
+       }
+#endif /* AKAROS */
+#endif
+       flush_workqueue(wq);
+
+       mlx4_ib_close_sriov(ibdev);
+
+err_mad:
+       mlx4_ib_mad_cleanup(ibdev);
+
+err_reg:
+       ib_unregister_device(&ibdev->ib_dev);
+
+err_steer_free_bitmap:
+       kfree(ibdev->ib_uc_qpns_bitmap);
+
+err_steer_qp_release:
+       if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
+               mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
+                                     ibdev->steer_qpn_count);
+err_counter:
+       for (; i; --i)
+               if (ibdev->counters[i - 1] != -1)
+                       mlx4_counter_free(ibdev->dev, ibdev->counters[i - 1]);
+
+err_map:
+       iounmap(ibdev->uar_map);
+
+err_uar:
+       mlx4_uar_free(dev, &ibdev->priv_uar);
+
+err_pd:
+       mlx4_pd_free(dev, ibdev->priv_pdn);
+
+err_dealloc:
+       ib_dealloc_device(&ibdev->ib_dev);
+
+       return NULL;
+}
+
+int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
+{
+       int offset;
+
+       WARN_ON(!dev->ib_uc_qpns_bitmap);
+
+       offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
+                                        dev->steer_qpn_count,
+                                        get_count_order(count));
+       if (offset < 0)
+               return offset;
+
+       *qpn = dev->steer_qpn_base + offset;
+       return 0;
+}
+
+void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
+{
+       if (!qpn ||
+           dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
+               return;
+
+       BUG_ON(qpn < dev->steer_qpn_base);
+
+       bitmap_release_region(dev->ib_uc_qpns_bitmap,
+                             qpn - dev->steer_qpn_base,
+                             get_count_order(count));
+}
+
+int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
+                        int is_attach)
+{
+       int err;
+       size_t flow_size;
+       struct ib_flow_attr *flow = NULL;
+       struct ib_flow_spec_ib *ib_spec;
+
+       if (is_attach) {
+               flow_size = sizeof(struct ib_flow_attr) +
+                           sizeof(struct ib_flow_spec_ib);
+               flow = kzalloc(flow_size, GFP_KERNEL);
+               if (!flow)
+                       return -ENOMEM;
+               flow->port = mqp->port;
+               flow->num_of_specs = 1;
+               flow->size = flow_size;
+               ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
+               ib_spec->type = IB_FLOW_SPEC_IB;
+               ib_spec->size = sizeof(struct ib_flow_spec_ib);
+               /* Add an empty rule for IB L2 */
+               memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
+
+               err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
+                                           IB_FLOW_DOMAIN_NIC,
+                                           MLX4_FS_REGULAR,
+                                           &mqp->reg_id);
+       } else {
+               err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
+       }
+       kfree(flow);
+       return err;
+}
+
+static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
+{
+       struct mlx4_ib_dev *ibdev = ibdev_ptr;
+       int p;
+
+       ibdev->ib_active = false;
+       flush_workqueue(wq);
+
+       mlx4_ib_close_sriov(ibdev);
+       mlx4_ib_mad_cleanup(ibdev);
+       ib_unregister_device(&ibdev->ib_dev);
+#if 0  /* AKAROS */
+       if (ibdev->iboe.nb.notifier_call) {
+               if (unregister_netdevice_notifier(&ibdev->iboe.nb))
+                       pr_warn("failure unregistering notifier\n");
+               ibdev->iboe.nb.notifier_call = NULL;
+       }
+#endif /* AKAROS */
+
+       if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) {
+               mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
+                                     ibdev->steer_qpn_count);
+               kfree(ibdev->ib_uc_qpns_bitmap);
+       }
+
+#if 0  /* AKAROS */
+       if (ibdev->iboe.nb_inet.notifier_call) {
+               if (unregister_inetaddr_notifier(&ibdev->iboe.nb_inet))
+                       pr_warn("failure unregistering notifier\n");
+               ibdev->iboe.nb_inet.notifier_call = NULL;
+       }
+#if IS_ENABLED(CONFIG_IPV6)
+       if (ibdev->iboe.nb_inet6.notifier_call) {
+               if (unregister_inet6addr_notifier(&ibdev->iboe.nb_inet6))
+                       pr_warn("failure unregistering notifier\n");
+               ibdev->iboe.nb_inet6.notifier_call = NULL;
+       }
+#endif
+#endif /* AKAROS */
+
+       iounmap(ibdev->uar_map);
+       for (p = 0; p < ibdev->num_ports; ++p)
+               if (ibdev->counters[p] != -1)
+                       mlx4_counter_free(ibdev->dev, ibdev->counters[p]);
+       mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
+               mlx4_CLOSE_PORT(dev, p);
+
+       mlx4_ib_free_eqs(dev, ibdev);
+
+       mlx4_uar_free(dev, &ibdev->priv_uar);
+       mlx4_pd_free(dev, ibdev->priv_pdn);
+       ib_dealloc_device(&ibdev->ib_dev);
+}
+
+static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
+{
+       struct mlx4_ib_demux_work **dm = NULL;
+       struct mlx4_dev *dev = ibdev->dev;
+       int i;
+       unsigned long flags;
+       struct mlx4_active_ports actv_ports;
+       unsigned int ports;
+       unsigned int first_port;
+
+       if (!mlx4_is_master(dev))
+               return;
+
+       actv_ports = mlx4_get_active_ports(dev, slave);
+       ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
+       first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
+
+       dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
+       if (!dm) {
+               pr_err("failed to allocate memory for tunneling qp update\n");
+               goto out;
+       }
+
+       for (i = 0; i < ports; i++) {
+               dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
+               if (!dm[i]) {
+                       pr_err("failed to allocate memory for tunneling qp update work struct\n");
+                       for (i = 0; i < dev->caps.num_ports; i++) {
+                               if (dm[i])
+                                       kfree(dm[i]);
+                       }
+                       goto out;
+               }
+       }
+       /* initialize or tear down tunnel QPs for the slave */
+       for (i = 0; i < ports; i++) {
+               INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
+               dm[i]->port = first_port + i + 1;
+               dm[i]->slave = slave;
+               dm[i]->do_init = do_init;
+               dm[i]->dev = ibdev;
+               spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
+               if (!ibdev->sriov.is_going_down)
+                       queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
+               spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
+       }
+out:
+       kfree(dm);
+       return;
+}
+
+static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
+{
+       struct mlx4_ib_qp *mqp;
+       unsigned long flags_qp;
+       unsigned long flags_cq;
+       struct mlx4_ib_cq *send_mcq, *recv_mcq;
+       struct list_head    cq_notify_list;
+       struct mlx4_cq *mcq;
+       unsigned long flags;
+
+       pr_warn("mlx4_ib_handle_catas_error was started\n");
+       INIT_LIST_HEAD(&cq_notify_list);
+
+       /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
+       spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
+
+       list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
+               spin_lock_irqsave(&mqp->sq.lock, flags_qp);
+               if (mqp->sq.tail != mqp->sq.head) {
+                       send_mcq = to_mcq(mqp->ibqp.send_cq);
+                       spin_lock_irqsave(&send_mcq->lock, flags_cq);
+                       if (send_mcq->mcq.comp &&
+                           mqp->ibqp.send_cq->comp_handler) {
+                               if (!send_mcq->mcq.reset_notify_added) {
+                                       send_mcq->mcq.reset_notify_added = 1;
+                                       list_add_tail(&send_mcq->mcq.reset_notify,
+                                                     &cq_notify_list);
+                               }
+                       }
+                       spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
+               }
+               spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
+               /* Now, handle the QP's receive queue */
+               spin_lock_irqsave(&mqp->rq.lock, flags_qp);
+               /* no handling is needed for SRQ */
+               if (!mqp->ibqp.srq) {
+                       if (mqp->rq.tail != mqp->rq.head) {
+                               recv_mcq = to_mcq(mqp->ibqp.recv_cq);
+                               spin_lock_irqsave(&recv_mcq->lock, flags_cq);
+                               if (recv_mcq->mcq.comp &&
+                                   mqp->ibqp.recv_cq->comp_handler) {
+                                       if (!recv_mcq->mcq.reset_notify_added) {
+                                               recv_mcq->mcq.reset_notify_added = 1;
+                                               list_add_tail(&recv_mcq->mcq.reset_notify,
+                                                             &cq_notify_list);
+                                       }
+                               }
+                               spin_unlock_irqrestore(&recv_mcq->lock,
+                                                      flags_cq);
+                       }
+               }
+               spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
+       }
+
+       list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
+               mcq->comp(mcq);
+       }
+       spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
+       pr_warn("mlx4_ib_handle_catas_error ended\n");
+}
+
+static void handle_bonded_port_state_event(struct work_struct *work)
+{
+       struct ib_event_work *ew =
+               container_of(work, struct ib_event_work, work);
+       struct mlx4_ib_dev *ibdev = ew->ib_dev;
+       enum ib_port_state bonded_port_state = IB_PORT_NOP;
+       int i;
+       struct ib_event ibev;
+
+       kfree(ew);
+       spin_lock_bh(&ibdev->iboe.lock);
+       for (i = 0; i < MLX4_MAX_PORTS; ++i) {
+               struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
+               enum ib_port_state curr_port_state;
+
+               if (!curr_netdev)
+                       continue;
+
+               curr_port_state =
+                       (netif_running(curr_netdev) &&
+                        netif_carrier_ok(curr_netdev)) ?
+                       IB_PORT_ACTIVE : IB_PORT_DOWN;
+
+               bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
+                       curr_port_state : IB_PORT_ACTIVE;
+       }
+       spin_unlock_bh(&ibdev->iboe.lock);
+
+       ibev.device = &ibdev->ib_dev;
+       ibev.element.port_num = 1;
+       ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
+               IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
+
+       ib_dispatch_event(&ibev);
+}
+
+static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
+                         enum mlx4_dev_event event, unsigned long param)
+{
+       struct ib_event ibev;
+       struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
+       struct mlx4_eqe *eqe = NULL;
+       struct ib_event_work *ew;
+       int p = 0;
+
+       if (mlx4_is_bonded(dev) &&
+           ((event == MLX4_DEV_EVENT_PORT_UP) ||
+           (event == MLX4_DEV_EVENT_PORT_DOWN))) {
+               ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
+               if (!ew)
+                       return;
+               INIT_WORK(&ew->work, handle_bonded_port_state_event);
+               ew->ib_dev = ibdev;
+               queue_work(wq, &ew->work);
+               return;
+       }
+
+       if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
+               eqe = (struct mlx4_eqe *)param;
+       else
+               p = (int) param;
+
+       switch (event) {
+       case MLX4_DEV_EVENT_PORT_UP:
+               if (p > ibdev->num_ports)
+                       return;
+               if (mlx4_is_master(dev) &&
+                   rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
+                       IB_LINK_LAYER_INFINIBAND) {
+                       mlx4_ib_invalidate_all_guid_record(ibdev, p);
+               }
+               ibev.event = IB_EVENT_PORT_ACTIVE;
+               break;
+
+       case MLX4_DEV_EVENT_PORT_DOWN:
+               if (p > ibdev->num_ports)
+                       return;
+               ibev.event = IB_EVENT_PORT_ERR;
+               break;
+
+       case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
+               ibdev->ib_active = false;
+               ibev.event = IB_EVENT_DEVICE_FATAL;
+               mlx4_ib_handle_catas_error(ibdev);
+               break;
+
+       case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
+               ew = kmalloc(sizeof *ew, GFP_ATOMIC);
+               if (!ew) {
+                       pr_err("failed to allocate memory for events work\n");
+                       break;
+               }
+
+               INIT_WORK(&ew->work, handle_port_mgmt_change_event);
+               memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
+               ew->ib_dev = ibdev;
+               /* need to queue only for port owner, which uses GEN_EQE */
+               if (mlx4_is_master(dev))
+                       queue_work(wq, &ew->work);
+               else
+                       handle_port_mgmt_change_event(&ew->work);
+               return;
+
+       case MLX4_DEV_EVENT_SLAVE_INIT:
+               /* here, p is the slave id */
+               do_slave_init(ibdev, p, 1);
+               if (mlx4_is_master(dev)) {
+                       int i;
+
+                       for (i = 1; i <= ibdev->num_ports; i++) {
+                               if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
+                                       == IB_LINK_LAYER_INFINIBAND)
+                                       mlx4_ib_slave_alias_guid_event(ibdev,
+                                                                      p, i,
+                                                                      1);
+                       }
+               }
+               return;
+
+       case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
+               if (mlx4_is_master(dev)) {
+                       int i;
+
+                       for (i = 1; i <= ibdev->num_ports; i++) {
+                               if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
+                                       == IB_LINK_LAYER_INFINIBAND)
+                                       mlx4_ib_slave_alias_guid_event(ibdev,
+                                                                      p, i,
+                                                                      0);
+                       }
+               }
+               /* here, p is the slave id */
+               do_slave_init(ibdev, p, 0);
+               return;
+
+       default:
+               return;
+       }
+
+       ibev.device           = ibdev_ptr;
+       ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
+
+       ib_dispatch_event(&ibev);
+}
+
+static struct mlx4_interface mlx4_ib_interface = {
+       .add            = mlx4_ib_add,
+       .remove         = mlx4_ib_remove,
+       .event          = mlx4_ib_event,
+       .protocol       = MLX4_PROT_IB_IPV6,
+       .flags          = MLX4_INTFF_BONDING
+};
+
+#if 0  /* AKAROS */
+static int __init mlx4_ib_init(void)
+#else  /* AKAROS */
+int __init mlx4_ib_init(void)
+#endif /* AKAROS */
+{
+       int err;
+
+       wq = create_singlethread_workqueue("mlx4_ib");
+       if (!wq)
+               return -ENOMEM;
+
+       err = mlx4_ib_mcg_init();
+       if (err)
+               goto clean_wq;
+
+       err = mlx4_register_interface(&mlx4_ib_interface);
+       if (err)
+               goto clean_mcg;
+
+       return 0;
+
+clean_mcg:
+       mlx4_ib_mcg_destroy();
+
+clean_wq:
+       destroy_workqueue(wq);
+       return err;
+}
+
+static void __exit mlx4_ib_cleanup(void)
+{
+       mlx4_unregister_interface(&mlx4_ib_interface);
+       mlx4_ib_mcg_destroy();
+       destroy_workqueue(wq);
+}
+
+module_init(mlx4_ib_init);
+module_exit(mlx4_ib_cleanup);
diff --git a/kern/drivers/net/mlx4u/mlx4_ib.h b/kern/drivers/net/mlx4u/mlx4_ib.h
new file mode 100644 (file)
index 0000000..a49fb77
--- /dev/null
@@ -0,0 +1,830 @@
+/*
+ * Copyright (c) 2006, 2007 Cisco Systems.  All rights reserved.
+ * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef MLX4_IB_H
+#define MLX4_IB_H
+
+#if 1  /* AKAROS */
+#include <linux/rdma/ib_verbs.h>
+#include <linux/rdma/ib_mad.h>
+#include <linux/mlx4/device.h>
+#include <linux/mlx4/doorbell.h>
+#include <linux/rdma/ib_umem.h>
+#define        IB_SA_METHOD_DELETE     0x15    /* lets avoid ib_sa.h */
+#endif /* AKAROS */
+
+#if 0  /* AKAROS */
+#include <linux/compiler.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/idr.h>
+
+#include <rdma/ib_verbs.h>
+#include <rdma/ib_umem.h>
+#include <rdma/ib_mad.h>
+#include <rdma/ib_sa.h>
+
+#include <linux/mlx4/device.h>
+#include <linux/mlx4/doorbell.h>
+#endif /* AKAROS */
+
+#define MLX4_IB_DRV_NAME       "mlx4_ib"
+
+#ifdef pr_fmt
+#undef pr_fmt
+#endif
+#define pr_fmt(fmt)    "<" MLX4_IB_DRV_NAME "> %s: " fmt, __func__
+
+#define mlx4_ib_warn(ibdev, format, arg...) \
+       dev_warn((ibdev)->dma_device, MLX4_IB_DRV_NAME ": " format, ## arg)
+
+enum {
+       MLX4_IB_SQ_MIN_WQE_SHIFT = 6,
+       MLX4_IB_MAX_HEADROOM     = 2048
+};
+
+#define MLX4_IB_SQ_HEADROOM(shift)     ((MLX4_IB_MAX_HEADROOM >> (shift)) + 1)
+#define MLX4_IB_SQ_MAX_SPARE           (MLX4_IB_SQ_HEADROOM(MLX4_IB_SQ_MIN_WQE_SHIFT))
+
+/*module param to indicate if SM assigns the alias_GUID*/
+extern int mlx4_ib_sm_guid_assign;
+
+#define MLX4_IB_UC_STEER_QPN_ALIGN 1
+#define MLX4_IB_UC_MAX_NUM_QPS     256
+struct mlx4_ib_ucontext {
+       struct ib_ucontext      ibucontext;
+       struct mlx4_uar         uar;
+       struct list_head        db_page_list;
+       struct mutex            db_page_mutex;
+};
+
+struct mlx4_ib_pd {
+       struct ib_pd            ibpd;
+       u32                     pdn;
+};
+
+struct mlx4_ib_xrcd {
+       struct ib_xrcd          ibxrcd;
+       u32                     xrcdn;
+       struct ib_pd           *pd;
+       struct ib_cq           *cq;
+};
+
+struct mlx4_ib_cq_buf {
+       struct mlx4_buf         buf;
+       struct mlx4_mtt         mtt;
+       int                     entry_size;
+};
+
+struct mlx4_ib_cq_resize {
+       struct mlx4_ib_cq_buf   buf;
+       int                     cqe;
+};
+
+struct mlx4_ib_cq {
+       struct ib_cq            ibcq;
+       struct mlx4_cq          mcq;
+       struct mlx4_ib_cq_buf   buf;
+       struct mlx4_ib_cq_resize *resize_buf;
+       struct mlx4_db          db;
+       spinlock_t              lock;
+       struct mutex            resize_mutex;
+       struct ib_umem         *umem;
+       struct ib_umem         *resize_umem;
+       /* List of qps that it serves.*/
+       struct list_head                send_qp_list;
+       struct list_head                recv_qp_list;
+};
+
+struct mlx4_ib_mr {
+       struct ib_mr            ibmr;
+       struct mlx4_mr          mmr;
+       struct ib_umem         *umem;
+};
+
+struct mlx4_ib_mw {
+       struct ib_mw            ibmw;
+       struct mlx4_mw          mmw;
+};
+
+struct mlx4_ib_fast_reg_page_list {
+       struct ib_fast_reg_page_list    ibfrpl;
+       __be64                         *mapped_page_list;
+       dma_addr_t                      map;
+};
+
+struct mlx4_ib_fmr {
+       struct ib_fmr           ibfmr;
+       struct mlx4_fmr         mfmr;
+};
+
+#define MAX_REGS_PER_FLOW 2
+
+struct mlx4_flow_reg_id {
+       u64 id;
+       u64 mirror;
+};
+
+struct mlx4_ib_flow {
+       struct ib_flow ibflow;
+       /* translating DMFS verbs sniffer rule to FW API requires two reg IDs */
+       struct mlx4_flow_reg_id reg_id[MAX_REGS_PER_FLOW];
+};
+
+struct mlx4_ib_wq {
+       u64                    *wrid;
+       spinlock_t              lock;
+       int                     wqe_cnt;
+       int                     max_post;
+       int                     max_gs;
+       int                     offset;
+       int                     wqe_shift;
+       unsigned                head;
+       unsigned                tail;
+};
+
+enum mlx4_ib_qp_flags {
+       MLX4_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO,
+       MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
+       MLX4_IB_QP_NETIF = IB_QP_CREATE_NETIF_QP,
+       MLX4_IB_QP_CREATE_USE_GFP_NOIO = IB_QP_CREATE_USE_GFP_NOIO,
+       MLX4_IB_SRIOV_TUNNEL_QP = 1 << 30,
+       MLX4_IB_SRIOV_SQP = 1 << 31,
+};
+
+struct mlx4_ib_gid_entry {
+       struct list_head        list;
+       union ib_gid            gid;
+       int                     added;
+       u8                      port;
+};
+
+enum mlx4_ib_qp_type {
+       /*
+        * IB_QPT_SMI and IB_QPT_GSI have to be the first two entries
+        * here (and in that order) since the MAD layer uses them as
+        * indices into a 2-entry table.
+        */
+       MLX4_IB_QPT_SMI = IB_QPT_SMI,
+       MLX4_IB_QPT_GSI = IB_QPT_GSI,
+
+       MLX4_IB_QPT_RC = IB_QPT_RC,
+       MLX4_IB_QPT_UC = IB_QPT_UC,
+       MLX4_IB_QPT_UD = IB_QPT_UD,
+       MLX4_IB_QPT_RAW_IPV6 = IB_QPT_RAW_IPV6,
+       MLX4_IB_QPT_RAW_ETHERTYPE = IB_QPT_RAW_ETHERTYPE,
+       MLX4_IB_QPT_RAW_PACKET = IB_QPT_RAW_PACKET,
+       MLX4_IB_QPT_XRC_INI = IB_QPT_XRC_INI,
+       MLX4_IB_QPT_XRC_TGT = IB_QPT_XRC_TGT,
+
+       MLX4_IB_QPT_PROXY_SMI_OWNER     = 1 << 16,
+       MLX4_IB_QPT_PROXY_SMI           = 1 << 17,
+       MLX4_IB_QPT_PROXY_GSI           = 1 << 18,
+       MLX4_IB_QPT_TUN_SMI_OWNER       = 1 << 19,
+       MLX4_IB_QPT_TUN_SMI             = 1 << 20,
+       MLX4_IB_QPT_TUN_GSI             = 1 << 21,
+};
+
+#define MLX4_IB_QPT_ANY_SRIOV  (MLX4_IB_QPT_PROXY_SMI_OWNER | \
+       MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER | \
+       MLX4_IB_QPT_TUN_SMI | MLX4_IB_QPT_TUN_GSI)
+
+enum mlx4_ib_mad_ifc_flags {
+       MLX4_MAD_IFC_IGNORE_MKEY        = 1,
+       MLX4_MAD_IFC_IGNORE_BKEY        = 2,
+       MLX4_MAD_IFC_IGNORE_KEYS        = (MLX4_MAD_IFC_IGNORE_MKEY |
+                                          MLX4_MAD_IFC_IGNORE_BKEY),
+       MLX4_MAD_IFC_NET_VIEW           = 4,
+};
+
+enum {
+       MLX4_NUM_TUNNEL_BUFS            = 256,
+};
+
+struct mlx4_ib_tunnel_header {
+       struct mlx4_av av;
+       __be32 remote_qpn;
+       __be32 qkey;
+       __be16 vlan;
+       u8 mac[6];
+       __be16 pkey_index;
+       u8 reserved[6];
+};
+
+struct mlx4_ib_buf {
+       void *addr;
+       dma_addr_t map;
+};
+
+struct mlx4_rcv_tunnel_hdr {
+       __be32 flags_src_qp; /* flags[6:5] is defined for VLANs:
+                             * 0x0 - no vlan was in the packet
+                             * 0x01 - C-VLAN was in the packet */
+       u8 g_ml_path; /* gid bit stands for ipv6/4 header in RoCE */
+       u8 reserved;
+       __be16 pkey_index;
+       __be16 sl_vid;
+       __be16 slid_mac_47_32;
+       __be32 mac_31_0;
+};
+
+struct mlx4_ib_proxy_sqp_hdr {
+       struct ib_grh grh;
+       struct mlx4_rcv_tunnel_hdr tun;
+}  __packed;
+
+struct mlx4_roce_smac_vlan_info {
+       u64 smac;
+       int smac_index;
+       int smac_port;
+       u64 candidate_smac;
+       int candidate_smac_index;
+       int candidate_smac_port;
+       u16 vid;
+       int vlan_index;
+       int vlan_port;
+       u16 candidate_vid;
+       int candidate_vlan_index;
+       int candidate_vlan_port;
+       int update_vid;
+};
+
+struct mlx4_ib_qp {
+       struct ib_qp            ibqp;
+       struct mlx4_qp          mqp;
+       struct mlx4_buf         buf;
+
+       struct mlx4_db          db;
+       struct mlx4_ib_wq       rq;
+
+       u32                     doorbell_qpn;
+       __be32                  sq_signal_bits;
+       unsigned                sq_next_wqe;
+       int                     sq_max_wqes_per_wr;
+       int                     sq_spare_wqes;
+       struct mlx4_ib_wq       sq;
+
+       enum mlx4_ib_qp_type    mlx4_ib_qp_type;
+       struct ib_umem         *umem;
+       struct mlx4_mtt         mtt;
+       int                     buf_size;
+       struct mutex            mutex;
+       u16                     xrcdn;
+       u32                     flags;
+       u8                      port;
+       u8                      alt_port;
+       u8                      atomic_rd_en;
+       u8                      resp_depth;
+       u8                      sq_no_prefetch;
+       u8                      state;
+       int                     mlx_type;
+       struct list_head        gid_list;
+       struct list_head        steering_rules;
+       struct mlx4_ib_buf      *sqp_proxy_rcv;
+       struct mlx4_roce_smac_vlan_info pri;
+       struct mlx4_roce_smac_vlan_info alt;
+       u64                     reg_id;
+       struct list_head        qps_list;
+       struct list_head        cq_recv_list;
+       struct list_head        cq_send_list;
+};
+
+struct mlx4_ib_srq {
+       struct ib_srq           ibsrq;
+       struct mlx4_srq         msrq;
+       struct mlx4_buf         buf;
+       struct mlx4_db          db;
+       u64                    *wrid;
+       spinlock_t              lock;
+       int                     head;
+       int                     tail;
+       u16                     wqe_ctr;
+       struct ib_umem         *umem;
+       struct mlx4_mtt         mtt;
+       struct mutex            mutex;
+};
+
+struct mlx4_ib_ah {
+       struct ib_ah            ibah;
+       union mlx4_ext_av       av;
+};
+
+/****************************************/
+/* alias guid support */
+/****************************************/
+#define NUM_PORT_ALIAS_GUID            2
+#define NUM_ALIAS_GUID_IN_REC          8
+#define NUM_ALIAS_GUID_REC_IN_PORT     16
+#define GUID_REC_SIZE                  8
+#define NUM_ALIAS_GUID_PER_PORT                128
+#define MLX4_NOT_SET_GUID              (0x00LL)
+#define MLX4_GUID_FOR_DELETE_VAL       (~(0x00LL))
+
+enum mlx4_guid_alias_rec_status {
+       MLX4_GUID_INFO_STATUS_IDLE,
+       MLX4_GUID_INFO_STATUS_SET,
+};
+
+#define GUID_STATE_NEED_PORT_INIT 0x01
+
+enum mlx4_guid_alias_rec_method {
+       MLX4_GUID_INFO_RECORD_SET       = IB_MGMT_METHOD_SET,
+       MLX4_GUID_INFO_RECORD_DELETE    = IB_SA_METHOD_DELETE,
+};
+
+struct mlx4_sriov_alias_guid_info_rec_det {
+       u8 all_recs[GUID_REC_SIZE * NUM_ALIAS_GUID_IN_REC];
+       ib_sa_comp_mask guid_indexes; /*indicates what from the 8 records are valid*/
+       enum mlx4_guid_alias_rec_status status; /*indicates the administraively status of the record.*/
+       unsigned int guids_retry_schedule[NUM_ALIAS_GUID_IN_REC];
+       u64 time_to_run;
+};
+
+struct mlx4_sriov_alias_guid_port_rec_det {
+       struct mlx4_sriov_alias_guid_info_rec_det all_rec_per_port[NUM_ALIAS_GUID_REC_IN_PORT];
+       struct workqueue_struct *wq;
+       struct delayed_work alias_guid_work;
+       u8 port;
+       u32 state_flags;
+       struct mlx4_sriov_alias_guid *parent;
+       struct list_head cb_list;
+};
+
+struct mlx4_sriov_alias_guid {
+       struct mlx4_sriov_alias_guid_port_rec_det ports_guid[MLX4_MAX_PORTS];
+       spinlock_t ag_work_lock;
+       struct ib_sa_client *sa_client;
+};
+
+struct mlx4_ib_demux_work {
+       struct work_struct      work;
+       struct mlx4_ib_dev     *dev;
+       int                     slave;
+       int                     do_init;
+       u8                      port;
+
+};
+
+struct mlx4_ib_tun_tx_buf {
+       struct mlx4_ib_buf buf;
+       struct ib_ah *ah;
+};
+
+struct mlx4_ib_demux_pv_qp {
+       struct ib_qp *qp;
+       enum ib_qp_type proxy_qpt;
+       struct mlx4_ib_buf *ring;
+       struct mlx4_ib_tun_tx_buf *tx_ring;
+       spinlock_t tx_lock;
+       unsigned tx_ix_head;
+       unsigned tx_ix_tail;
+};
+
+enum mlx4_ib_demux_pv_state {
+       DEMUX_PV_STATE_DOWN,
+       DEMUX_PV_STATE_STARTING,
+       DEMUX_PV_STATE_ACTIVE,
+       DEMUX_PV_STATE_DOWNING,
+};
+
+struct mlx4_ib_demux_pv_ctx {
+       int port;
+       int slave;
+       enum mlx4_ib_demux_pv_state state;
+       int has_smi;
+       struct ib_device *ib_dev;
+       struct ib_cq *cq;
+       struct ib_pd *pd;
+       struct ib_mr *mr;
+       struct work_struct work;
+       struct workqueue_struct *wq;
+       struct mlx4_ib_demux_pv_qp qp[2];
+};
+
+struct mlx4_ib_demux_ctx {
+       struct ib_device *ib_dev;
+       int port;
+       struct workqueue_struct *wq;
+       struct workqueue_struct *ud_wq;
+       spinlock_t ud_lock;
+       __be64 subnet_prefix;
+       __be64 guid_cache[128];
+       struct mlx4_ib_dev *dev;
+       /* the following lock protects both mcg_table and mcg_mgid0_list */
+       struct mutex            mcg_table_lock;
+       struct rb_root          mcg_table;
+       struct list_head        mcg_mgid0_list;
+       struct workqueue_struct *mcg_wq;
+       struct mlx4_ib_demux_pv_ctx **tun;
+       atomic_t tid;
+       int    flushing; /* flushing the work queue */
+};
+
+struct mlx4_ib_sriov {
+       struct mlx4_ib_demux_ctx demux[MLX4_MAX_PORTS];
+       struct mlx4_ib_demux_pv_ctx *sqps[MLX4_MAX_PORTS];
+       /* when using this spinlock you should use "irq" because
+        * it may be called from interrupt context.*/
+       spinlock_t going_down_lock;
+       int is_going_down;
+
+       struct mlx4_sriov_alias_guid alias_guid;
+
+       /* CM paravirtualization fields */
+       struct list_head cm_list;
+       spinlock_t id_map_lock;
+       struct rb_root sl_id_map;
+       struct idr pv_id_table;
+};
+
+struct mlx4_ib_iboe {
+       spinlock_t              lock;
+       struct net_device      *netdevs[MLX4_MAX_PORTS];
+       struct net_device      *masters[MLX4_MAX_PORTS];
+       atomic64_t              mac[MLX4_MAX_PORTS];
+       struct notifier_block   nb;
+       struct notifier_block   nb_inet;
+       struct notifier_block   nb_inet6;
+       union ib_gid            gid_table[MLX4_MAX_PORTS][128];
+};
+
+struct pkey_mgt {
+       u8                      virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
+       u16                     phys_pkey_cache[MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
+       struct list_head        pkey_port_list[MLX4_MFUNC_MAX];
+       struct kobject         *device_parent[MLX4_MFUNC_MAX];
+};
+
+struct mlx4_ib_iov_sysfs_attr {
+       void *ctx;
+       struct kobject *kobj;
+       unsigned long data;
+       u32 entry_num;
+       char name[15];
+       struct device_attribute dentry;
+       struct device *dev;
+};
+
+struct mlx4_ib_iov_sysfs_attr_ar {
+       struct mlx4_ib_iov_sysfs_attr dentries[3 * NUM_ALIAS_GUID_PER_PORT + 1];
+};
+
+struct mlx4_ib_iov_port {
+       char name[100];
+       u8 num;
+       struct mlx4_ib_dev *dev;
+       struct list_head list;
+       struct mlx4_ib_iov_sysfs_attr_ar *dentr_ar;
+       struct ib_port_attr attr;
+       struct kobject  *cur_port;
+       struct kobject  *admin_alias_parent;
+       struct kobject  *gids_parent;
+       struct kobject  *pkeys_parent;
+       struct kobject  *mcgs_parent;
+       struct mlx4_ib_iov_sysfs_attr mcg_dentry;
+};
+
+struct mlx4_ib_dev {
+       struct ib_device        ib_dev;
+       struct mlx4_dev        *dev;
+       int                     num_ports;
+       void __iomem           *uar_map;
+
+       struct mlx4_uar         priv_uar;
+       u32                     priv_pdn;
+       MLX4_DECLARE_DOORBELL_LOCK(uar_lock);
+
+       struct ib_mad_agent    *send_agent[MLX4_MAX_PORTS][2];
+       struct ib_ah           *sm_ah[MLX4_MAX_PORTS];
+       spinlock_t              sm_lock;
+       struct mlx4_ib_sriov    sriov;
+
+       struct mutex            cap_mask_mutex;
+       bool                    ib_active;
+       struct mlx4_ib_iboe     iboe;
+       int                     counters[MLX4_MAX_PORTS];
+       int                    *eq_table;
+       int                     eq_added;
+       struct kobject         *iov_parent;
+       struct kobject         *ports_parent;
+       struct kobject         *dev_ports_parent[MLX4_MFUNC_MAX];
+       struct mlx4_ib_iov_port iov_ports[MLX4_MAX_PORTS];
+       struct pkey_mgt         pkeys;
+       unsigned long *ib_uc_qpns_bitmap;
+       int steer_qpn_count;
+       int steer_qpn_base;
+       int steering_support;
+       struct mlx4_ib_qp      *qp1_proxy[MLX4_MAX_PORTS];
+       /* lock when destroying qp1_proxy and getting netdev events */
+       struct mutex            qp1_proxy_lock[MLX4_MAX_PORTS];
+       u8                      bond_next_port;
+       /* protect resources needed as part of reset flow */
+       spinlock_t              reset_flow_resource_lock;
+       struct list_head                qp_list;
+};
+
+struct ib_event_work {
+       struct work_struct      work;
+       struct mlx4_ib_dev      *ib_dev;
+       struct mlx4_eqe         ib_eqe;
+};
+
+struct mlx4_ib_qp_tunnel_init_attr {
+       struct ib_qp_init_attr init_attr;
+       int slave;
+       enum ib_qp_type proxy_qp_type;
+       u8 port;
+};
+
+static inline struct mlx4_ib_dev *to_mdev(struct ib_device *ibdev)
+{
+       return container_of(ibdev, struct mlx4_ib_dev, ib_dev);
+}
+
+static inline struct mlx4_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
+{
+       return container_of(ibucontext, struct mlx4_ib_ucontext, ibucontext);
+}
+
+static inline struct mlx4_ib_pd *to_mpd(struct ib_pd *ibpd)
+{
+       return container_of(ibpd, struct mlx4_ib_pd, ibpd);
+}
+
+static inline struct mlx4_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
+{
+       return container_of(ibxrcd, struct mlx4_ib_xrcd, ibxrcd);
+}
+
+static inline struct mlx4_ib_cq *to_mcq(struct ib_cq *ibcq)
+{
+       return container_of(ibcq, struct mlx4_ib_cq, ibcq);
+}
+
+static inline struct mlx4_ib_cq *to_mibcq(struct mlx4_cq *mcq)
+{
+       return container_of(mcq, struct mlx4_ib_cq, mcq);
+}
+
+static inline struct mlx4_ib_mr *to_mmr(struct ib_mr *ibmr)
+{
+       return container_of(ibmr, struct mlx4_ib_mr, ibmr);
+}
+
+static inline struct mlx4_ib_mw *to_mmw(struct ib_mw *ibmw)
+{
+       return container_of(ibmw, struct mlx4_ib_mw, ibmw);
+}
+
+static inline struct mlx4_ib_fast_reg_page_list *to_mfrpl(struct ib_fast_reg_page_list *ibfrpl)
+{
+       return container_of(ibfrpl, struct mlx4_ib_fast_reg_page_list, ibfrpl);
+}
+
+static inline struct mlx4_ib_fmr *to_mfmr(struct ib_fmr *ibfmr)
+{
+       return container_of(ibfmr, struct mlx4_ib_fmr, ibfmr);
+}
+
+static inline struct mlx4_ib_flow *to_mflow(struct ib_flow *ibflow)
+{
+       return container_of(ibflow, struct mlx4_ib_flow, ibflow);
+}
+
+static inline struct mlx4_ib_qp *to_mqp(struct ib_qp *ibqp)
+{
+       return container_of(ibqp, struct mlx4_ib_qp, ibqp);
+}
+
+static inline struct mlx4_ib_qp *to_mibqp(struct mlx4_qp *mqp)
+{
+       return container_of(mqp, struct mlx4_ib_qp, mqp);
+}
+
+static inline struct mlx4_ib_srq *to_msrq(struct ib_srq *ibsrq)
+{
+       return container_of(ibsrq, struct mlx4_ib_srq, ibsrq);
+}
+
+static inline struct mlx4_ib_srq *to_mibsrq(struct mlx4_srq *msrq)
+{
+       return container_of(msrq, struct mlx4_ib_srq, msrq);
+}
+
+static inline struct mlx4_ib_ah *to_mah(struct ib_ah *ibah)
+{
+       return container_of(ibah, struct mlx4_ib_ah, ibah);
+}
+
+static inline u8 mlx4_ib_bond_next_port(struct mlx4_ib_dev *dev)
+{
+       dev->bond_next_port = (dev->bond_next_port + 1) % dev->num_ports;
+
+       return dev->bond_next_port + 1;
+}
+
+int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev);
+void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev);
+
+int mlx4_ib_db_map_user(struct mlx4_ib_ucontext *context, unsigned long virt,
+                       struct mlx4_db *db);
+void mlx4_ib_db_unmap_user(struct mlx4_ib_ucontext *context, struct mlx4_db *db);
+
+struct ib_mr *mlx4_ib_get_dma_mr(struct ib_pd *pd, int acc);
+int mlx4_ib_umem_write_mtt(struct mlx4_ib_dev *dev, struct mlx4_mtt *mtt,
+                          struct ib_umem *umem);
+struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
+                                 u64 virt_addr, int access_flags,
+                                 struct ib_udata *udata);
+int mlx4_ib_dereg_mr(struct ib_mr *mr);
+struct ib_mw *mlx4_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type);
+int mlx4_ib_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
+                   struct ib_mw_bind *mw_bind);
+int mlx4_ib_dealloc_mw(struct ib_mw *mw);
+struct ib_mr *mlx4_ib_alloc_fast_reg_mr(struct ib_pd *pd,
+                                       int max_page_list_len);
+struct ib_fast_reg_page_list *mlx4_ib_alloc_fast_reg_page_list(struct ib_device *ibdev,
+                                                              int page_list_len);
+void mlx4_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list);
+
+int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
+int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
+struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector,
+                               struct ib_ucontext *context,
+                               struct ib_udata *udata);
+int mlx4_ib_destroy_cq(struct ib_cq *cq);
+int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
+int mlx4_ib_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
+void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq);
+void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq);
+
+struct ib_ah *mlx4_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr);
+int mlx4_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr);
+int mlx4_ib_destroy_ah(struct ib_ah *ah);
+
+struct ib_srq *mlx4_ib_create_srq(struct ib_pd *pd,
+                                 struct ib_srq_init_attr *init_attr,
+                                 struct ib_udata *udata);
+int mlx4_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
+                      enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
+int mlx4_ib_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);
+int mlx4_ib_destroy_srq(struct ib_srq *srq);
+void mlx4_ib_free_srq_wqe(struct mlx4_ib_srq *srq, int wqe_index);
+int mlx4_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
+                         struct ib_recv_wr **bad_wr);
+
+struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
+                               struct ib_qp_init_attr *init_attr,
+                               struct ib_udata *udata);
+int mlx4_ib_destroy_qp(struct ib_qp *qp);
+int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
+                     int attr_mask, struct ib_udata *udata);
+int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
+                    struct ib_qp_init_attr *qp_init_attr);
+int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
+                     struct ib_send_wr **bad_wr);
+int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
+                     struct ib_recv_wr **bad_wr);
+
+int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags,
+                int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
+                void *in_mad, void *response_mad);
+int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags,        u8 port_num,
+                       struct ib_wc *in_wc, struct ib_grh *in_grh,
+                       struct ib_mad *in_mad, struct ib_mad *out_mad);
+int mlx4_ib_mad_init(struct mlx4_ib_dev *dev);
+void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev);
+
+struct ib_fmr *mlx4_ib_fmr_alloc(struct ib_pd *pd, int mr_access_flags,
+                                 struct ib_fmr_attr *fmr_attr);
+int mlx4_ib_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, int npages,
+                        u64 iova);
+int mlx4_ib_unmap_fmr(struct list_head *fmr_list);
+int mlx4_ib_fmr_dealloc(struct ib_fmr *fmr);
+int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
+                        struct ib_port_attr *props, int netw_view);
+int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
+                        u16 *pkey, int netw_view);
+
+int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
+                       union ib_gid *gid, int netw_view);
+
+static inline bool mlx4_ib_ah_grh_present(struct mlx4_ib_ah *ah)
+{
+       u8 port = be32_to_cpu(ah->av.ib.port_pd) >> 24 & 3;
+
+       if (rdma_port_get_link_layer(ah->ibah.device, port) == IB_LINK_LAYER_ETHERNET)
+               return true;
+
+       return !!(ah->av.ib.g_slid & 0x80);
+}
+
+int mlx4_ib_mcg_port_init(struct mlx4_ib_demux_ctx *ctx);
+void mlx4_ib_mcg_port_cleanup(struct mlx4_ib_demux_ctx *ctx, int destroy_wq);
+void clean_vf_mcast(struct mlx4_ib_demux_ctx *ctx, int slave);
+int mlx4_ib_mcg_init(void);
+void mlx4_ib_mcg_destroy(void);
+
+int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid);
+
+int mlx4_ib_mcg_multiplex_handler(struct ib_device *ibdev, int port, int slave,
+                                 struct ib_sa_mad *sa_mad);
+int mlx4_ib_mcg_demux_handler(struct ib_device *ibdev, int port, int slave,
+                             struct ib_sa_mad *mad);
+
+int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
+                  union ib_gid *gid);
+
+void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num,
+                           enum ib_event_type type);
+
+void mlx4_ib_tunnels_update_work(struct work_struct *work);
+
+int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port,
+                         enum ib_qp_type qpt, struct ib_wc *wc,
+                         struct ib_grh *grh, struct ib_mad *mad);
+
+int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port,
+                        enum ib_qp_type dest_qpt, u16 pkey_index, u32 remote_qpn,
+                        u32 qkey, struct ib_ah_attr *attr, u8 *s_mac,
+                        struct ib_mad *mad);
+
+__be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx);
+
+int mlx4_ib_demux_cm_handler(struct ib_device *ibdev, int port, int *slave,
+               struct ib_mad *mad);
+
+int mlx4_ib_multiplex_cm_handler(struct ib_device *ibdev, int port, int slave_id,
+               struct ib_mad *mad);
+
+void mlx4_ib_cm_paravirt_init(struct mlx4_ib_dev *dev);
+void mlx4_ib_cm_paravirt_clean(struct mlx4_ib_dev *dev, int slave_id);
+
+/* alias guid support */
+void mlx4_ib_init_alias_guid_work(struct mlx4_ib_dev *dev, int port);
+int mlx4_ib_init_alias_guid_service(struct mlx4_ib_dev *dev);
+void mlx4_ib_destroy_alias_guid_service(struct mlx4_ib_dev *dev);
+void mlx4_ib_invalidate_all_guid_record(struct mlx4_ib_dev *dev, int port);
+
+void mlx4_ib_notify_slaves_on_guid_change(struct mlx4_ib_dev *dev,
+                                         int block_num,
+                                         u8 port_num, u8 *p_data);
+
+void mlx4_ib_update_cache_on_guid_change(struct mlx4_ib_dev *dev,
+                                        int block_num, u8 port_num,
+                                        u8 *p_data);
+
+int add_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num,
+                           struct attribute *attr);
+void del_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num,
+                            struct attribute *attr);
+ib_sa_comp_mask mlx4_ib_get_aguid_comp_mask_from_ix(int index);
+void mlx4_ib_slave_alias_guid_event(struct mlx4_ib_dev *dev, int slave,
+                                   int port, int slave_init);
+
+int mlx4_ib_device_register_sysfs(struct mlx4_ib_dev *device) ;
+
+void mlx4_ib_device_unregister_sysfs(struct mlx4_ib_dev *device);
+
+__be64 mlx4_ib_gen_node_guid(void);
+
+int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn);
+void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count);
+int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
+                        int is_attach);
+int mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags,
+                         u64 start, u64 length, u64 virt_addr,
+                         int mr_access_flags, struct ib_pd *pd,
+                         struct ib_udata *udata);
+
+#endif /* MLX4_IB_H */
diff --git a/kern/drivers/net/mlx4u/mr.c b/kern/drivers/net/mlx4u/mr.c
new file mode 100644 (file)
index 0000000..4f2114e
--- /dev/null
@@ -0,0 +1,525 @@
+/*
+ * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
+ * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+//#include <linux/slab.h>      /* AKAROS */
+
+#include "mlx4_ib.h"
+
+static u32 convert_access(int acc)
+{
+       return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX4_PERM_ATOMIC       : 0) |
+              (acc & IB_ACCESS_REMOTE_WRITE  ? MLX4_PERM_REMOTE_WRITE : 0) |
+              (acc & IB_ACCESS_REMOTE_READ   ? MLX4_PERM_REMOTE_READ  : 0) |
+              (acc & IB_ACCESS_LOCAL_WRITE   ? MLX4_PERM_LOCAL_WRITE  : 0) |
+              (acc & IB_ACCESS_MW_BIND       ? MLX4_PERM_BIND_MW      : 0) |
+              MLX4_PERM_LOCAL_READ;
+}
+
+static enum mlx4_mw_type to_mlx4_type(enum ib_mw_type type)
+{
+       switch (type) {
+       case IB_MW_TYPE_1:      return MLX4_MW_TYPE_1;
+       case IB_MW_TYPE_2:      return MLX4_MW_TYPE_2;
+       default:                return -1;
+       }
+}
+
+struct ib_mr *mlx4_ib_get_dma_mr(struct ib_pd *pd, int acc)
+{
+       struct mlx4_ib_mr *mr;
+       int err;
+
+       mr = kmalloc(sizeof *mr, GFP_KERNEL);
+       if (!mr)
+               return ERR_PTR(-ENOMEM);
+
+       err = mlx4_mr_alloc(to_mdev(pd->device)->dev, to_mpd(pd)->pdn, 0,
+                           ~0ull, convert_access(acc), 0, 0, &mr->mmr);
+       if (err)
+               goto err_free;
+
+       err = mlx4_mr_enable(to_mdev(pd->device)->dev, &mr->mmr);
+       if (err)
+               goto err_mr;
+
+       mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key;
+       mr->umem = NULL;
+
+       return &mr->ibmr;
+
+err_mr:
+       (void) mlx4_mr_free(to_mdev(pd->device)->dev, &mr->mmr);
+
+err_free:
+       kfree(mr);
+
+       return ERR_PTR(err);
+}
+
+int mlx4_ib_umem_write_mtt(struct mlx4_ib_dev *dev, struct mlx4_mtt *mtt,
+                          struct ib_umem *umem)
+{
+       u64 *pages;
+       int i, k, entry;
+       int n;
+       int len;
+       int err = 0;
+       struct scatterlist *sg;
+
+       pages = (u64 *) __get_free_page(GFP_KERNEL);
+       if (!pages)
+               return -ENOMEM;
+
+       i = n = 0;
+
+       for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
+               len = sg_dma_len(sg) >> mtt->page_shift;
+               for (k = 0; k < len; ++k) {
+                       pages[i++] = sg_dma_address(sg) +
+                               umem->page_size * k;
+                       /*
+                        * Be friendly to mlx4_write_mtt() and
+                        * pass it chunks of appropriate size.
+                        */
+                       if (i == PAGE_SIZE / sizeof (u64)) {
+                               err = mlx4_write_mtt(dev->dev, mtt, n,
+                                                    i, pages);
+                               if (err)
+                                       goto out;
+                               n += i;
+                               i = 0;
+                       }
+               }
+       }
+
+       if (i)
+               err = mlx4_write_mtt(dev->dev, mtt, n, i, pages);
+
+out:
+       free_page((unsigned long) pages);
+       return err;
+}
+
+struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
+                                 u64 virt_addr, int access_flags,
+                                 struct ib_udata *udata)
+{
+       struct mlx4_ib_dev *dev = to_mdev(pd->device);
+       struct mlx4_ib_mr *mr;
+       int shift;
+       int err;
+       int n;
+
+       mr = kmalloc(sizeof *mr, GFP_KERNEL);
+       if (!mr)
+               return ERR_PTR(-ENOMEM);
+
+       /* Force registering the memory as writable. */
+       /* Used for memory re-registeration. HCA protects the access */
+       mr->umem = ib_umem_get(pd->uobject->context, start, length,
+                              access_flags | IB_ACCESS_LOCAL_WRITE, 0);
+       if (IS_ERR(mr->umem)) {
+               err = PTR_ERR(mr->umem);
+               goto err_free;
+       }
+
+       n = ib_umem_page_count(mr->umem);
+       shift = ilog2(mr->umem->page_size);
+
+       err = mlx4_mr_alloc(dev->dev, to_mpd(pd)->pdn, virt_addr, length,
+                           convert_access(access_flags), n, shift, &mr->mmr);
+       if (err)
+               goto err_umem;
+
+       err = mlx4_ib_umem_write_mtt(dev, &mr->mmr.mtt, mr->umem);
+       if (err)
+               goto err_mr;
+
+       err = mlx4_mr_enable(dev->dev, &mr->mmr);
+       if (err)
+               goto err_mr;
+
+       mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key;
+
+       return &mr->ibmr;
+
+err_mr:
+       (void) mlx4_mr_free(to_mdev(pd->device)->dev, &mr->mmr);
+
+err_umem:
+       ib_umem_release(mr->umem);
+
+err_free:
+       kfree(mr);
+
+       return ERR_PTR(err);
+}
+
+int mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags,
+                         u64 start, u64 length, u64 virt_addr,
+                         int mr_access_flags, struct ib_pd *pd,
+                         struct ib_udata *udata)
+{
+       struct mlx4_ib_dev *dev = to_mdev(mr->device);
+       struct mlx4_ib_mr *mmr = to_mmr(mr);
+       struct mlx4_mpt_entry *mpt_entry;
+       struct mlx4_mpt_entry **pmpt_entry = &mpt_entry;
+       int err;
+
+       /* Since we synchronize this call and mlx4_ib_dereg_mr via uverbs,
+        * we assume that the calls can't run concurrently. Otherwise, a
+        * race exists.
+        */
+       err =  mlx4_mr_hw_get_mpt(dev->dev, &mmr->mmr, &pmpt_entry);
+
+       if (err)
+               return err;
+
+       if (flags & IB_MR_REREG_PD) {
+               err = mlx4_mr_hw_change_pd(dev->dev, *pmpt_entry,
+                                          to_mpd(pd)->pdn);
+
+               if (err)
+                       goto release_mpt_entry;
+       }
+
+       if (flags & IB_MR_REREG_ACCESS) {
+               err = mlx4_mr_hw_change_access(dev->dev, *pmpt_entry,
+                                              convert_access(mr_access_flags));
+
+               if (err)
+                       goto release_mpt_entry;
+       }
+
+       if (flags & IB_MR_REREG_TRANS) {
+               int shift;
+               int n;
+
+               mlx4_mr_rereg_mem_cleanup(dev->dev, &mmr->mmr);
+               ib_umem_release(mmr->umem);
+               mmr->umem = ib_umem_get(mr->uobject->context, start, length,
+                                       mr_access_flags |
+                                       IB_ACCESS_LOCAL_WRITE,
+                                       0);
+               if (IS_ERR(mmr->umem)) {
+                       err = PTR_ERR(mmr->umem);
+                       /* Prevent mlx4_ib_dereg_mr from free'ing invalid pointer */
+                       mmr->umem = NULL;
+                       goto release_mpt_entry;
+               }
+               n = ib_umem_page_count(mmr->umem);
+               shift = ilog2(mmr->umem->page_size);
+
+               err = mlx4_mr_rereg_mem_write(dev->dev, &mmr->mmr,
+                                             virt_addr, length, n, shift,
+                                             *pmpt_entry);
+               if (err) {
+                       ib_umem_release(mmr->umem);
+                       goto release_mpt_entry;
+               }
+               mmr->mmr.iova       = virt_addr;
+               mmr->mmr.size       = length;
+
+               err = mlx4_ib_umem_write_mtt(dev, &mmr->mmr.mtt, mmr->umem);
+               if (err) {
+                       mlx4_mr_rereg_mem_cleanup(dev->dev, &mmr->mmr);
+                       ib_umem_release(mmr->umem);
+                       goto release_mpt_entry;
+               }
+       }
+
+       /* If we couldn't transfer the MR to the HCA, just remember to
+        * return a failure. But dereg_mr will free the resources.
+        */
+       err = mlx4_mr_hw_write_mpt(dev->dev, &mmr->mmr, pmpt_entry);
+       if (!err && flags & IB_MR_REREG_ACCESS)
+               mmr->mmr.access = mr_access_flags;
+
+release_mpt_entry:
+       mlx4_mr_hw_put_mpt(dev->dev, pmpt_entry);
+
+       return err;
+}
+
+int mlx4_ib_dereg_mr(struct ib_mr *ibmr)
+{
+       struct mlx4_ib_mr *mr = to_mmr(ibmr);
+       int ret;
+
+       ret = mlx4_mr_free(to_mdev(ibmr->device)->dev, &mr->mmr);
+       if (ret)
+               return ret;
+       if (mr->umem)
+               ib_umem_release(mr->umem);
+       kfree(mr);
+
+       return 0;
+}
+
+struct ib_mw *mlx4_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type)
+{
+       struct mlx4_ib_dev *dev = to_mdev(pd->device);
+       struct mlx4_ib_mw *mw;
+       int err;
+
+       mw = kmalloc(sizeof(*mw), GFP_KERNEL);
+       if (!mw)
+               return ERR_PTR(-ENOMEM);
+
+       err = mlx4_mw_alloc(dev->dev, to_mpd(pd)->pdn,
+                           to_mlx4_type(type), &mw->mmw);
+       if (err)
+               goto err_free;
+
+       err = mlx4_mw_enable(dev->dev, &mw->mmw);
+       if (err)
+               goto err_mw;
+
+       mw->ibmw.rkey = mw->mmw.key;
+
+       return &mw->ibmw;
+
+err_mw:
+       mlx4_mw_free(dev->dev, &mw->mmw);
+
+err_free:
+       kfree(mw);
+
+       return ERR_PTR(err);
+}
+
+int mlx4_ib_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
+                   struct ib_mw_bind *mw_bind)
+{
+       struct ib_send_wr  wr;
+       struct ib_send_wr *bad_wr;
+       int ret;
+
+       memset(&wr, 0, sizeof(wr));
+       wr.opcode               = IB_WR_BIND_MW;
+       wr.wr_id                = mw_bind->wr_id;
+       wr.send_flags           = mw_bind->send_flags;
+       wr.wr.bind_mw.mw        = mw;
+       wr.wr.bind_mw.bind_info = mw_bind->bind_info;
+       wr.wr.bind_mw.rkey      = ib_inc_rkey(mw->rkey);
+
+       ret = mlx4_ib_post_send(qp, &wr, &bad_wr);
+       if (!ret)
+               mw->rkey = wr.wr.bind_mw.rkey;
+
+       return ret;
+}
+
+int mlx4_ib_dealloc_mw(struct ib_mw *ibmw)
+{
+       struct mlx4_ib_mw *mw = to_mmw(ibmw);
+
+       mlx4_mw_free(to_mdev(ibmw->device)->dev, &mw->mmw);
+       kfree(mw);
+
+       return 0;
+}
+
+struct ib_mr *mlx4_ib_alloc_fast_reg_mr(struct ib_pd *pd,
+                                       int max_page_list_len)
+{
+       struct mlx4_ib_dev *dev = to_mdev(pd->device);
+       struct mlx4_ib_mr *mr;
+       int err;
+
+       mr = kmalloc(sizeof *mr, GFP_KERNEL);
+       if (!mr)
+               return ERR_PTR(-ENOMEM);
+
+       err = mlx4_mr_alloc(dev->dev, to_mpd(pd)->pdn, 0, 0, 0,
+                           max_page_list_len, 0, &mr->mmr);
+       if (err)
+               goto err_free;
+
+       err = mlx4_mr_enable(dev->dev, &mr->mmr);
+       if (err)
+               goto err_mr;
+
+       mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key;
+       mr->umem = NULL;
+
+       return &mr->ibmr;
+
+err_mr:
+       (void) mlx4_mr_free(dev->dev, &mr->mmr);
+
+err_free:
+       kfree(mr);
+       return ERR_PTR(err);
+}
+
+struct ib_fast_reg_page_list *mlx4_ib_alloc_fast_reg_page_list(struct ib_device *ibdev,
+                                                              int page_list_len)
+{
+       struct mlx4_ib_dev *dev = to_mdev(ibdev);
+       struct mlx4_ib_fast_reg_page_list *mfrpl;
+       int size = page_list_len * sizeof (u64);
+
+       if (page_list_len > MLX4_MAX_FAST_REG_PAGES)
+               return ERR_PTR(-EINVAL);
+
+       mfrpl = kmalloc(sizeof *mfrpl, GFP_KERNEL);
+       if (!mfrpl)
+               return ERR_PTR(-ENOMEM);
+
+       mfrpl->ibfrpl.page_list = kmalloc(size, GFP_KERNEL);
+       if (!mfrpl->ibfrpl.page_list)
+               goto err_free;
+
+       mfrpl->mapped_page_list = dma_alloc_coherent(&dev->dev->persist->
+                                                    pdev->dev,
+                                                    size, &mfrpl->map,
+                                                    GFP_KERNEL);
+       if (!mfrpl->mapped_page_list)
+               goto err_free;
+
+       WARN_ON(mfrpl->map & 0x3f);
+
+       return &mfrpl->ibfrpl;
+
+err_free:
+       kfree(mfrpl->ibfrpl.page_list);
+       kfree(mfrpl);
+       return ERR_PTR(-ENOMEM);
+}
+
+void mlx4_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list)
+{
+       struct mlx4_ib_dev *dev = to_mdev(page_list->device);
+       struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(page_list);
+       int size = page_list->max_page_list_len * sizeof (u64);
+
+       dma_free_coherent(&dev->dev->persist->pdev->dev, size,
+                         mfrpl->mapped_page_list,
+                         mfrpl->map);
+       kfree(mfrpl->ibfrpl.page_list);
+       kfree(mfrpl);
+}
+
+struct ib_fmr *mlx4_ib_fmr_alloc(struct ib_pd *pd, int acc,
+                                struct ib_fmr_attr *fmr_attr)
+{
+       struct mlx4_ib_dev *dev = to_mdev(pd->device);
+       struct mlx4_ib_fmr *fmr;
+       int err = -ENOMEM;
+
+       fmr = kmalloc(sizeof *fmr, GFP_KERNEL);
+       if (!fmr)
+               return ERR_PTR(-ENOMEM);
+
+       err = mlx4_fmr_alloc(dev->dev, to_mpd(pd)->pdn, convert_access(acc),
+                            fmr_attr->max_pages, fmr_attr->max_maps,
+                            fmr_attr->page_shift, &fmr->mfmr);
+       if (err)
+               goto err_free;
+
+       err = mlx4_fmr_enable(to_mdev(pd->device)->dev, &fmr->mfmr);
+       if (err)
+               goto err_mr;
+
+       fmr->ibfmr.rkey = fmr->ibfmr.lkey = fmr->mfmr.mr.key;
+
+       return &fmr->ibfmr;
+
+err_mr:
+       (void) mlx4_mr_free(to_mdev(pd->device)->dev, &fmr->mfmr.mr);
+
+err_free:
+       kfree(fmr);
+
+       return ERR_PTR(err);
+}
+
+int mlx4_ib_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
+                     int npages, u64 iova)
+{
+       struct mlx4_ib_fmr *ifmr = to_mfmr(ibfmr);
+       struct mlx4_ib_dev *dev = to_mdev(ifmr->ibfmr.device);
+
+       return mlx4_map_phys_fmr(dev->dev, &ifmr->mfmr, page_list, npages, iova,
+                                &ifmr->ibfmr.lkey, &ifmr->ibfmr.rkey);
+}
+
+int mlx4_ib_unmap_fmr(struct list_head *fmr_list)
+{
+       struct ib_fmr *ibfmr;
+       int err;
+       struct mlx4_dev *mdev = NULL;
+
+       list_for_each_entry(ibfmr, fmr_list, list) {
+               if (mdev && to_mdev(ibfmr->device)->dev != mdev)
+                       return -EINVAL;
+               mdev = to_mdev(ibfmr->device)->dev;
+       }
+
+       if (!mdev)
+               return 0;
+
+       list_for_each_entry(ibfmr, fmr_list, list) {
+               struct mlx4_ib_fmr *ifmr = to_mfmr(ibfmr);
+
+               mlx4_fmr_unmap(mdev, &ifmr->mfmr, &ifmr->ibfmr.lkey, &ifmr->ibfmr.rkey);
+       }
+
+       /*
+        * Make sure all MPT status updates are visible before issuing
+        * SYNC_TPT firmware command.
+        */
+       wmb();
+
+       err = mlx4_SYNC_TPT(mdev);
+       if (err)
+               pr_warn("SYNC_TPT error %d when "
+                      "unmapping FMRs\n", err);
+
+       return 0;
+}
+
+int mlx4_ib_fmr_dealloc(struct ib_fmr *ibfmr)
+{
+       struct mlx4_ib_fmr *ifmr = to_mfmr(ibfmr);
+       struct mlx4_ib_dev *dev = to_mdev(ibfmr->device);
+       int err;
+
+       err = mlx4_fmr_free(dev->dev, &ifmr->mfmr);
+
+       if (!err)
+               kfree(ifmr);
+
+       return err;
+}
diff --git a/kern/drivers/net/mlx4u/qp.c b/kern/drivers/net/mlx4u/qp.c
new file mode 100644 (file)
index 0000000..99b704e
--- /dev/null
@@ -0,0 +1,3256 @@
+/*
+ * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
+ * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#if 0  /* AKAROS */
+#include <linux/log2.h>
+#include <linux/slab.h>
+#include <linux/netdevice.h>
+
+#include <rdma/ib_cache.h>
+#include <rdma/ib_pack.h>
+#include <rdma/ib_addr.h>
+#include <rdma/ib_mad.h>
+#endif /* AKAROS */
+
+#include <linux/mlx4/driver.h>
+#include <linux/mlx4/qp.h>
+
+#include "mlx4_ib.h"
+#include "user.h"
+
+static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
+                            struct mlx4_ib_cq *recv_cq);
+static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
+                              struct mlx4_ib_cq *recv_cq);
+
+enum {
+       MLX4_IB_ACK_REQ_FREQ    = 8,
+};
+
+enum {
+       MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
+       MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
+       MLX4_IB_LINK_TYPE_IB            = 0,
+       MLX4_IB_LINK_TYPE_ETH           = 1
+};
+
+enum {
+       /*
+        * Largest possible UD header: send with GRH and immediate
+        * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
+        * tag.  (LRH would only use 8 bytes, so Ethernet is the
+        * biggest case)
+        */
+       MLX4_IB_UD_HEADER_SIZE          = 82,
+       MLX4_IB_LSO_HEADER_SPARE        = 128,
+};
+
+enum {
+       MLX4_IB_IBOE_ETHERTYPE          = 0x8915
+};
+
+struct mlx4_ib_sqp {
+       struct mlx4_ib_qp       qp;
+       int                     pkey_index;
+       u32                     qkey;
+       u32                     send_psn;
+       struct ib_ud_header     ud_header;
+       u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
+};
+
+enum {
+       MLX4_IB_MIN_SQ_STRIDE   = 6,
+       MLX4_IB_CACHE_LINE_SIZE = 64,
+};
+
+enum {
+       MLX4_RAW_QP_MTU         = 7,
+       MLX4_RAW_QP_MSGMAX      = 31,
+};
+
+#ifndef ETH_ALEN
+#define ETH_ALEN        6
+#endif
+
+static const __be32 mlx4_ib_opcode[] = {
+       [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
+       [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
+       [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
+       [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
+       [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
+       [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
+       [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
+       [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
+       [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
+       [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
+       [IB_WR_FAST_REG_MR]                     = cpu_to_be32(MLX4_OPCODE_FMR),
+       [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
+       [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
+       [IB_WR_BIND_MW]                         = cpu_to_be32(MLX4_OPCODE_BIND_MW),
+};
+
+static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
+{
+       return container_of(mqp, struct mlx4_ib_sqp, qp);
+}
+
+static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
+{
+       if (!mlx4_is_master(dev->dev))
+               return 0;
+
+       return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
+              qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
+               8 * MLX4_MFUNC_MAX;
+}
+
+static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
+{
+       int proxy_sqp = 0;
+       int real_sqp = 0;
+       int i;
+       /* PPF or Native -- real SQP */
+       real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
+                   qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
+                   qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
+       if (real_sqp)
+               return 1;
+       /* VF or PF -- proxy SQP */
+       if (mlx4_is_mfunc(dev->dev)) {
+               for (i = 0; i < dev->dev->caps.num_ports; i++) {
+                       if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
+                           qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
+                               proxy_sqp = 1;
+                               break;
+                       }
+               }
+       }
+       return proxy_sqp;
+}
+
+/* used for INIT/CLOSE port logic */
+static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
+{
+       int proxy_qp0 = 0;
+       int real_qp0 = 0;
+       int i;
+       /* PPF or Native -- real QP0 */
+       real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
+                   qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
+                   qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
+       if (real_qp0)
+               return 1;
+       /* VF or PF -- proxy QP0 */
+       if (mlx4_is_mfunc(dev->dev)) {
+               for (i = 0; i < dev->dev->caps.num_ports; i++) {
+                       if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
+                               proxy_qp0 = 1;
+                               break;
+                       }
+               }
+       }
+       return proxy_qp0;
+}
+
+static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
+{
+       return mlx4_buf_offset(&qp->buf, offset);
+}
+
+static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
+{
+       return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
+}
+
+static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
+{
+       return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
+}
+
+/*
+ * Stamp a SQ WQE so that it is invalid if prefetched by marking the
+ * first four bytes of every 64 byte chunk with
+ *     0x7FFFFFF | (invalid_ownership_value << 31).
+ *
+ * When the max work request size is less than or equal to the WQE
+ * basic block size, as an optimization, we can stamp all WQEs with
+ * 0xffffffff, and skip the very first chunk of each WQE.
+ */
+static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
+{
+       __be32 *wqe;
+       int i;
+       int s;
+       int ind;
+       void *buf;
+       __be32 stamp;
+       struct mlx4_wqe_ctrl_seg *ctrl;
+
+       if (qp->sq_max_wqes_per_wr > 1) {
+               s = roundup(size, 1U << qp->sq.wqe_shift);
+               for (i = 0; i < s; i += 64) {
+                       ind = (i >> qp->sq.wqe_shift) + n;
+                       stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
+                                                      cpu_to_be32(0xffffffff);
+                       buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
+                       wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
+                       *wqe = stamp;
+               }
+       } else {
+               ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
+               s = (ctrl->fence_size & 0x3f) << 4;
+               for (i = 64; i < s; i += 64) {
+                       wqe = buf + i;
+                       *wqe = cpu_to_be32(0xffffffff);
+               }
+       }
+}
+
+static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
+{
+       struct mlx4_wqe_ctrl_seg *ctrl;
+       struct mlx4_wqe_inline_seg *inl;
+       void *wqe;
+       int s;
+
+       ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
+       s = sizeof(struct mlx4_wqe_ctrl_seg);
+
+       if (qp->ibqp.qp_type == IB_QPT_UD) {
+               struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
+               struct mlx4_av *av = (struct mlx4_av *)dgram->av;
+               memset(dgram, 0, sizeof *dgram);
+               av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
+               s += sizeof(struct mlx4_wqe_datagram_seg);
+       }
+
+       /* Pad the remainder of the WQE with an inline data segment. */
+       if (size > s) {
+               inl = wqe + s;
+               inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
+       }
+       ctrl->srcrb_flags = 0;
+       ctrl->fence_size = size / 16;
+       /*
+        * Make sure descriptor is fully written before setting ownership bit
+        * (because HW can start executing as soon as we do).
+        */
+       wmb();
+
+       ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
+               (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
+
+       stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
+}
+
+/* Post NOP WQE to prevent wrap-around in the middle of WR */
+static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
+{
+       unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
+       if (unlikely(s < qp->sq_max_wqes_per_wr)) {
+               post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
+               ind += s;
+       }
+       return ind;
+}
+
+static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
+{
+       struct ib_event event;
+       struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
+
+       if (type == MLX4_EVENT_TYPE_PATH_MIG)
+               to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
+
+       if (ibqp->event_handler) {
+               event.device     = ibqp->device;
+               event.element.qp = ibqp;
+               switch (type) {
+               case MLX4_EVENT_TYPE_PATH_MIG:
+                       event.event = IB_EVENT_PATH_MIG;
+                       break;
+               case MLX4_EVENT_TYPE_COMM_EST:
+                       event.event = IB_EVENT_COMM_EST;
+                       break;
+               case MLX4_EVENT_TYPE_SQ_DRAINED:
+                       event.event = IB_EVENT_SQ_DRAINED;
+                       break;
+               case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
+                       event.event = IB_EVENT_QP_LAST_WQE_REACHED;
+                       break;
+               case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
+                       event.event = IB_EVENT_QP_FATAL;
+                       break;
+               case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
+                       event.event = IB_EVENT_PATH_MIG_ERR;
+                       break;
+               case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
+                       event.event = IB_EVENT_QP_REQ_ERR;
+                       break;
+               case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
+                       event.event = IB_EVENT_QP_ACCESS_ERR;
+                       break;
+               default:
+                       pr_warn("Unexpected event type %d "
+                              "on QP %06x\n", type, qp->qpn);
+                       return;
+               }
+
+               ibqp->event_handler(&event, ibqp->qp_context);
+       }
+}
+
+static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
+{
+       /*
+        * UD WQEs must have a datagram segment.
+        * RC and UC WQEs might have a remote address segment.
+        * MLX WQEs need two extra inline data segments (for the UD
+        * header and space for the ICRC).
+        */
+       switch (type) {
+       case MLX4_IB_QPT_UD:
+               return sizeof (struct mlx4_wqe_ctrl_seg) +
+                       sizeof (struct mlx4_wqe_datagram_seg) +
+                       ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
+       case MLX4_IB_QPT_PROXY_SMI_OWNER:
+       case MLX4_IB_QPT_PROXY_SMI:
+       case MLX4_IB_QPT_PROXY_GSI:
+               return sizeof (struct mlx4_wqe_ctrl_seg) +
+                       sizeof (struct mlx4_wqe_datagram_seg) + 64;
+       case MLX4_IB_QPT_TUN_SMI_OWNER:
+       case MLX4_IB_QPT_TUN_GSI:
+               return sizeof (struct mlx4_wqe_ctrl_seg) +
+                       sizeof (struct mlx4_wqe_datagram_seg);
+
+       case MLX4_IB_QPT_UC:
+               return sizeof (struct mlx4_wqe_ctrl_seg) +
+                       sizeof (struct mlx4_wqe_raddr_seg);
+       case MLX4_IB_QPT_RC:
+               return sizeof (struct mlx4_wqe_ctrl_seg) +
+                       sizeof (struct mlx4_wqe_atomic_seg) +
+                       sizeof (struct mlx4_wqe_raddr_seg);
+       case MLX4_IB_QPT_SMI:
+       case MLX4_IB_QPT_GSI:
+               return sizeof (struct mlx4_wqe_ctrl_seg) +
+                       ALIGN(MLX4_IB_UD_HEADER_SIZE +
+                             DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
+                                          MLX4_INLINE_ALIGN) *
+                             sizeof (struct mlx4_wqe_inline_seg),
+                             sizeof (struct mlx4_wqe_data_seg)) +
+                       ALIGN(4 +
+                             sizeof (struct mlx4_wqe_inline_seg),
+                             sizeof (struct mlx4_wqe_data_seg));
+       default:
+               return sizeof (struct mlx4_wqe_ctrl_seg);
+       }
+}
+
+static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
+                      int is_user, int has_rq, struct mlx4_ib_qp *qp)
+{
+       /* Sanity check RQ size before proceeding */
+       if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
+           cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
+               return -EINVAL;
+
+       if (!has_rq) {
+               if (cap->max_recv_wr)
+                       return -EINVAL;
+
+               qp->rq.wqe_cnt = qp->rq.max_gs = 0;
+       } else {
+               /* HW requires >= 1 RQ entry with >= 1 gather entry */
+               if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
+                       return -EINVAL;
+
+               qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
+               qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
+               qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
+       }
+
+       /* leave userspace return values as they were, so as not to break ABI */
+       if (is_user) {
+               cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
+               cap->max_recv_sge = qp->rq.max_gs;
+       } else {
+               cap->max_recv_wr  = qp->rq.max_post =
+                       min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
+               cap->max_recv_sge = min(qp->rq.max_gs,
+                                       min(dev->dev->caps.max_sq_sg,
+                                           dev->dev->caps.max_rq_sg));
+       }
+
+       return 0;
+}
+
+static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
+                             enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
+{
+       int s;
+
+       /* Sanity check SQ size before proceeding */
+       if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
+           cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
+           cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
+           sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
+               return -EINVAL;
+
+       /*
+        * For MLX transport we need 2 extra S/G entries:
+        * one for the header and one for the checksum at the end
+        */
+       if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
+            type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
+           cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
+               return -EINVAL;
+
+       s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
+               cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
+               send_wqe_overhead(type, qp->flags);
+
+       if (s > dev->dev->caps.max_sq_desc_sz)
+               return -EINVAL;
+
+       /*
+        * Hermon supports shrinking WQEs, such that a single work
+        * request can include multiple units of 1 << wqe_shift.  This
+        * way, work requests can differ in size, and do not have to
+        * be a power of 2 in size, saving memory and speeding up send
+        * WR posting.  Unfortunately, if we do this then the
+        * wqe_index field in CQEs can't be used to look up the WR ID
+        * anymore, so we do this only if selective signaling is off.
+        *
+        * Further, on 32-bit platforms, we can't use vmap() to make
+        * the QP buffer virtually contiguous.  Thus we have to use
+        * constant-sized WRs to make sure a WR is always fully within
+        * a single page-sized chunk.
+        *
+        * Finally, we use NOP work requests to pad the end of the
+        * work queue, to avoid wrap-around in the middle of WR.  We
+        * set NEC bit to avoid getting completions with error for
+        * these NOP WRs, but since NEC is only supported starting
+        * with firmware 2.2.232, we use constant-sized WRs for older
+        * firmware.
+        *
+        * And, since MLX QPs only support SEND, we use constant-sized
+        * WRs in this case.
+        *
+        * We look for the smallest value of wqe_shift such that the
+        * resulting number of wqes does not exceed device
+        * capabilities.
+        *
+        * We set WQE size to at least 64 bytes, this way stamping
+        * invalidates each WQE.
+        */
+       if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
+           qp->sq_signal_bits && BITS_PER_LONG == 64 &&
+           type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
+           !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
+                     MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
+               qp->sq.wqe_shift = ilog2(64);
+       else
+               qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
+
+       for (;;) {
+               qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
+
+               /*
+                * We need to leave 2 KB + 1 WR of headroom in the SQ to
+                * allow HW to prefetch.
+                */
+               qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
+               qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
+                                                   qp->sq_max_wqes_per_wr +
+                                                   qp->sq_spare_wqes);
+
+               if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
+                       break;
+
+               if (qp->sq_max_wqes_per_wr <= 1)
+                       return -EINVAL;
+
+               ++qp->sq.wqe_shift;
+       }
+
+       qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
+                            (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
+                        send_wqe_overhead(type, qp->flags)) /
+               sizeof (struct mlx4_wqe_data_seg);
+
+       qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
+               (qp->sq.wqe_cnt << qp->sq.wqe_shift);
+       if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
+               qp->rq.offset = 0;
+               qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
+       } else {
+               qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
+               qp->sq.offset = 0;
+       }
+
+       cap->max_send_wr  = qp->sq.max_post =
+               (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
+       cap->max_send_sge = min(qp->sq.max_gs,
+                               min(dev->dev->caps.max_sq_sg,
+                                   dev->dev->caps.max_rq_sg));
+       /* We don't support inline sends for kernel QPs (yet) */
+       cap->max_inline_data = 0;
+
+       return 0;
+}
+
+static int set_user_sq_size(struct mlx4_ib_dev *dev,
+                           struct mlx4_ib_qp *qp,
+                           struct mlx4_ib_create_qp *ucmd)
+{
+       /* Sanity check SQ size before proceeding */
+       if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
+           ucmd->log_sq_stride >
+               ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
+           ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
+               return -EINVAL;
+
+       qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
+       qp->sq.wqe_shift = ucmd->log_sq_stride;
+
+       qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
+               (qp->sq.wqe_cnt << qp->sq.wqe_shift);
+
+       return 0;
+}
+
+static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
+{
+       int i;
+
+       qp->sqp_proxy_rcv =
+               kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
+                       GFP_KERNEL);
+       if (!qp->sqp_proxy_rcv)
+               return -ENOMEM;
+       for (i = 0; i < qp->rq.wqe_cnt; i++) {
+               qp->sqp_proxy_rcv[i].addr =
+                       kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
+                               GFP_KERNEL);
+               if (!qp->sqp_proxy_rcv[i].addr)
+                       goto err;
+               qp->sqp_proxy_rcv[i].map =
+                       ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
+                                         sizeof (struct mlx4_ib_proxy_sqp_hdr),
+                                         DMA_FROM_DEVICE);
+               if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
+                       kfree(qp->sqp_proxy_rcv[i].addr);
+                       goto err;
+               }
+       }
+       return 0;
+
+err:
+       while (i > 0) {
+               --i;
+               ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
+                                   sizeof (struct mlx4_ib_proxy_sqp_hdr),
+                                   DMA_FROM_DEVICE);
+               kfree(qp->sqp_proxy_rcv[i].addr);
+       }
+       kfree(qp->sqp_proxy_rcv);
+       qp->sqp_proxy_rcv = NULL;
+       return -ENOMEM;
+}
+
+static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
+{
+       int i;
+
+       for (i = 0; i < qp->rq.wqe_cnt; i++) {
+               ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
+                                   sizeof (struct mlx4_ib_proxy_sqp_hdr),
+                                   DMA_FROM_DEVICE);
+               kfree(qp->sqp_proxy_rcv[i].addr);
+       }
+       kfree(qp->sqp_proxy_rcv);
+}
+
+static int qp_has_rq(struct ib_qp_init_attr *attr)
+{
+       if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
+               return 0;
+
+       return !attr->srq;
+}
+
+static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
+{
+       int i;
+       for (i = 0; i < dev->caps.num_ports; i++) {
+               if (qpn == dev->caps.qp0_proxy[i])
+                       return !!dev->caps.qp0_qkey[i];
+       }
+       return 0;
+}
+
+static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
+                           struct ib_qp_init_attr *init_attr,
+                           struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
+                           gfp_t gfp)
+{
+       int qpn;
+       int err;
+       struct mlx4_ib_sqp *sqp;
+       struct mlx4_ib_qp *qp;
+       enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
+       struct mlx4_ib_cq *mcq;
+       unsigned long flags;
+
+       /* When tunneling special qps, we use a plain UD qp */
+       if (sqpn) {
+               if (mlx4_is_mfunc(dev->dev) &&
+                   (!mlx4_is_master(dev->dev) ||
+                    !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
+                       if (init_attr->qp_type == IB_QPT_GSI)
+                               qp_type = MLX4_IB_QPT_PROXY_GSI;
+                       else {
+                               if (mlx4_is_master(dev->dev) ||
+                                   qp0_enabled_vf(dev->dev, sqpn))
+                                       qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
+                               else
+                                       qp_type = MLX4_IB_QPT_PROXY_SMI;
+                       }
+               }
+               qpn = sqpn;
+               /* add extra sg entry for tunneling */
+               init_attr->cap.max_recv_sge++;
+       } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
+               struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
+                       container_of(init_attr,
+                                    struct mlx4_ib_qp_tunnel_init_attr, init_attr);
+               if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
+                    tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
+                   !mlx4_is_master(dev->dev))
+                       return -EINVAL;
+               if (tnl_init->proxy_qp_type == IB_QPT_GSI)
+                       qp_type = MLX4_IB_QPT_TUN_GSI;
+               else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
+                        mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
+                                            tnl_init->port))
+                       qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
+               else
+                       qp_type = MLX4_IB_QPT_TUN_SMI;
+               /* we are definitely in the PPF here, since we are creating
+                * tunnel QPs. base_tunnel_sqpn is therefore valid. */
+               qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
+                       + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
+               sqpn = qpn;
+       }
+
+       if (!*caller_qp) {
+               if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
+                   (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
+                               MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
+                       sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
+                       if (!sqp)
+                               return -ENOMEM;
+                       qp = &sqp->qp;
+                       qp->pri.vid = 0xFFFF;
+                       qp->alt.vid = 0xFFFF;
+               } else {
+                       qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
+                       if (!qp)
+                               return -ENOMEM;
+                       qp->pri.vid = 0xFFFF;
+                       qp->alt.vid = 0xFFFF;
+               }
+       } else
+               qp = *caller_qp;
+
+       qp->mlx4_ib_qp_type = qp_type;
+
+       mutex_init(&qp->mutex);
+       spin_lock_init(&qp->sq.lock);
+       spin_lock_init(&qp->rq.lock);
+       INIT_LIST_HEAD(&qp->gid_list);
+       INIT_LIST_HEAD(&qp->steering_rules);
+
+       qp->state        = IB_QPS_RESET;
+       if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
+               qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
+
+       err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
+       if (err)
+               goto err;
+
+       if (pd->uobject) {
+               struct mlx4_ib_create_qp ucmd;
+
+               if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
+                       err = -EFAULT;
+                       goto err;
+               }
+
+               qp->sq_no_prefetch = ucmd.sq_no_prefetch;
+
+               err = set_user_sq_size(dev, qp, &ucmd);
+               if (err)
+                       goto err;
+
+               qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
+                                      qp->buf_size, 0, 0);
+               if (IS_ERR(qp->umem)) {
+                       err = PTR_ERR(qp->umem);
+                       goto err;
+               }
+
+               err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
+                                   ilog2(qp->umem->page_size), &qp->mtt);
+               if (err)
+                       goto err_buf;
+
+               err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
+               if (err)
+                       goto err_mtt;
+
+               if (qp_has_rq(init_attr)) {
+                       err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
+                                                 ucmd.db_addr, &qp->db);
+                       if (err)
+                               goto err_mtt;
+               }
+       } else {
+               qp->sq_no_prefetch = 0;
+
+               if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
+                       qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
+
+               if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
+                       qp->flags |= MLX4_IB_QP_LSO;
+
+               if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
+                       if (dev->steering_support ==
+                           MLX4_STEERING_MODE_DEVICE_MANAGED)
+                               qp->flags |= MLX4_IB_QP_NETIF;
+                       else
+                               goto err;
+               }
+
+               err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
+               if (err)
+                       goto err;
+
+               if (qp_has_rq(init_attr)) {
+                       err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
+                       if (err)
+                               goto err;
+
+                       *qp->db.db = 0;
+               }
+
+               if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
+                       err = -ENOMEM;
+                       goto err_db;
+               }
+
+               err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
+                                   &qp->mtt);
+               if (err)
+                       goto err_buf;
+
+               err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
+               if (err)
+                       goto err_mtt;
+
+               qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), gfp);
+               qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), gfp);
+               if (!qp->sq.wrid || !qp->rq.wrid) {
+                       err = -ENOMEM;
+                       goto err_wrid;
+               }
+       }
+
+       if (sqpn) {
+               if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
+                   MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
+                       if (alloc_proxy_bufs(pd->device, qp)) {
+                               err = -ENOMEM;
+                               goto err_wrid;
+                       }
+               }
+       } else {
+               /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
+                * otherwise, the WQE BlueFlame setup flow wrongly causes
+                * VLAN insertion. */
+               if (init_attr->qp_type == IB_QPT_RAW_PACKET)
+                       err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
+                                                   (init_attr->cap.max_send_wr ?
+                                                    MLX4_RESERVE_ETH_BF_QP : 0) |
+                                                   (init_attr->cap.max_recv_wr ?
+                                                    MLX4_RESERVE_A0_QP : 0));
+               else
+                       if (qp->flags & MLX4_IB_QP_NETIF)
+                               err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
+                       else
+                               err = mlx4_qp_reserve_range(dev->dev, 1, 1,
+                                                           &qpn, 0);
+               if (err)
+                       goto err_proxy;
+       }
+
+       err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
+       if (err)
+               goto err_qpn;
+
+       if (init_attr->qp_type == IB_QPT_XRC_TGT)
+               qp->mqp.qpn |= (1 << 23);
+
+       /*
+        * Hardware wants QPN written in big-endian order (after
+        * shifting) for send doorbell.  Precompute this value to save
+        * a little bit when posting sends.
+        */
+       qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
+
+       qp->mqp.event = mlx4_ib_qp_event;
+       if (!*caller_qp)
+               *caller_qp = qp;
+
+       spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
+       mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
+                        to_mcq(init_attr->recv_cq));
+       /* Maintain device to QPs access, needed for further handling
+        * via reset flow
+        */
+       list_add_tail(&qp->qps_list, &dev->qp_list);
+       /* Maintain CQ to QPs access, needed for further handling
+        * via reset flow
+        */
+       mcq = to_mcq(init_attr->send_cq);
+       list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
+       mcq = to_mcq(init_attr->recv_cq);
+       list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
+       mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
+                          to_mcq(init_attr->recv_cq));
+       spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
+       return 0;
+
+err_qpn:
+       if (!sqpn) {
+               if (qp->flags & MLX4_IB_QP_NETIF)
+                       mlx4_ib_steer_qp_free(dev, qpn, 1);
+               else
+                       mlx4_qp_release_range(dev->dev, qpn, 1);
+       }
+err_proxy:
+       if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
+               free_proxy_bufs(pd->device, qp);
+err_wrid:
+       if (pd->uobject) {
+               if (qp_has_rq(init_attr))
+                       mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
+       } else {
+               kfree(qp->sq.wrid);
+               kfree(qp->rq.wrid);
+       }
+
+err_mtt:
+       mlx4_mtt_cleanup(dev->dev, &qp->mtt);
+
+err_buf:
+       if (pd->uobject)
+               ib_umem_release(qp->umem);
+       else
+               mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
+
+err_db:
+       if (!pd->uobject && qp_has_rq(init_attr))
+               mlx4_db_free(dev->dev, &qp->db);
+
+err:
+       if (!*caller_qp)
+               kfree(qp);
+       return err;
+}
+
+static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
+{
+       switch (state) {
+       case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
+       case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
+       case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
+       case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
+       case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
+       case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
+       case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
+       default:                return -1;
+       }
+}
+
+static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
+       __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
+{
+       if (send_cq == recv_cq) {
+               spin_lock(&send_cq->lock);
+               __acquire(&recv_cq->lock);
+       } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
+               spin_lock(&send_cq->lock);
+               spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
+       } else {
+               spin_lock(&recv_cq->lock);
+               spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
+       }
+}
+
+static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
+       __releases(&send_cq->lock) __releases(&recv_cq->lock)
+{
+       if (send_cq == recv_cq) {
+               __release(&recv_cq->lock);
+               spin_unlock(&send_cq->lock);
+       } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
+               spin_unlock(&recv_cq->lock);
+               spin_unlock(&send_cq->lock);
+       } else {
+               spin_unlock(&send_cq->lock);
+               spin_unlock(&recv_cq->lock);
+       }
+}
+
+static void del_gid_entries(struct mlx4_ib_qp *qp)
+{
+       struct mlx4_ib_gid_entry *ge, *tmp;
+
+       list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
+               list_del(&ge->list);
+               kfree(ge);
+       }
+}
+
+static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
+{
+       if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
+               return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
+       else
+               return to_mpd(qp->ibqp.pd);
+}
+
+static void get_cqs(struct mlx4_ib_qp *qp,
+                   struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
+{
+       switch (qp->ibqp.qp_type) {
+       case IB_QPT_XRC_TGT:
+               *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
+               *recv_cq = *send_cq;
+               break;
+       case IB_QPT_XRC_INI:
+               *send_cq = to_mcq(qp->ibqp.send_cq);
+               *recv_cq = *send_cq;
+               break;
+       default:
+               *send_cq = to_mcq(qp->ibqp.send_cq);
+               *recv_cq = to_mcq(qp->ibqp.recv_cq);
+               break;
+       }
+}
+
+static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
+                             int is_user)
+{
+       struct mlx4_ib_cq *send_cq, *recv_cq;
+       unsigned long flags;
+
+       if (qp->state != IB_QPS_RESET) {
+               if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
+                                  MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
+                       pr_warn("modify QP %06x to RESET failed.\n",
+                              qp->mqp.qpn);
+               if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
+                       mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
+                       qp->pri.smac = 0;
+                       qp->pri.smac_port = 0;
+               }
+               if (qp->alt.smac) {
+                       mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
+                       qp->alt.smac = 0;
+               }
+               if (qp->pri.vid < 0x1000) {
+                       mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
+                       qp->pri.vid = 0xFFFF;
+                       qp->pri.candidate_vid = 0xFFFF;
+                       qp->pri.update_vid = 0;
+               }
+               if (qp->alt.vid < 0x1000) {
+                       mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
+                       qp->alt.vid = 0xFFFF;
+                       qp->alt.candidate_vid = 0xFFFF;
+                       qp->alt.update_vid = 0;
+               }
+       }
+
+       get_cqs(qp, &send_cq, &recv_cq);
+
+       spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
+       mlx4_ib_lock_cqs(send_cq, recv_cq);
+
+       /* del from lists under both locks above to protect reset flow paths */
+       list_del(&qp->qps_list);
+       list_del(&qp->cq_send_list);
+       list_del(&qp->cq_recv_list);
+       if (!is_user) {
+               __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
+                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
+               if (send_cq != recv_cq)
+                       __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
+       }
+
+       mlx4_qp_remove(dev->dev, &qp->mqp);
+
+       mlx4_ib_unlock_cqs(send_cq, recv_cq);
+       spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
+
+       mlx4_qp_free(dev->dev, &qp->mqp);
+
+       if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
+               if (qp->flags & MLX4_IB_QP_NETIF)
+                       mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
+               else
+                       mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
+       }
+
+       mlx4_mtt_cleanup(dev->dev, &qp->mtt);
+
+       if (is_user) {
+               if (qp->rq.wqe_cnt)
+                       mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
+                                             &qp->db);
+               ib_umem_release(qp->umem);
+       } else {
+               kfree(qp->sq.wrid);
+               kfree(qp->rq.wrid);
+               if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
+                   MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
+                       free_proxy_bufs(&dev->ib_dev, qp);
+               mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
+               if (qp->rq.wqe_cnt)
+                       mlx4_db_free(dev->dev, &qp->db);
+       }
+
+       del_gid_entries(qp);
+}
+
+static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
+{
+       /* Native or PPF */
+       if (!mlx4_is_mfunc(dev->dev) ||
+           (mlx4_is_master(dev->dev) &&
+            attr->create_flags & MLX4_IB_SRIOV_SQP)) {
+               return  dev->dev->phys_caps.base_sqpn +
+                       (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
+                       attr->port_num - 1;
+       }
+       /* PF or VF -- creating proxies */
+       if (attr->qp_type == IB_QPT_SMI)
+               return dev->dev->caps.qp0_proxy[attr->port_num - 1];
+       else
+               return dev->dev->caps.qp1_proxy[attr->port_num - 1];
+}
+
+struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
+                               struct ib_qp_init_attr *init_attr,
+                               struct ib_udata *udata)
+{
+       struct mlx4_ib_qp *qp = NULL;
+       int err;
+       u16 xrcdn = 0;
+       gfp_t gfp;
+
+       gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
+               GFP_NOIO : GFP_KERNEL;
+       /*
+        * We only support LSO, vendor flag1, and multicast loopback blocking,
+        * and only for kernel UD QPs.
+        */
+       if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
+                                       MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
+                                       MLX4_IB_SRIOV_TUNNEL_QP |
+                                       MLX4_IB_SRIOV_SQP |
+                                       MLX4_IB_QP_NETIF |
+                                       MLX4_IB_QP_CREATE_USE_GFP_NOIO))
+               return ERR_PTR(-EINVAL);
+
+       if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
+               if (init_attr->qp_type != IB_QPT_UD)
+                       return ERR_PTR(-EINVAL);
+       }
+
+       if (init_attr->create_flags &&
+           (udata ||
+            ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | MLX4_IB_QP_CREATE_USE_GFP_NOIO)) &&
+             init_attr->qp_type != IB_QPT_UD) ||
+            ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
+             init_attr->qp_type > IB_QPT_GSI)))
+               return ERR_PTR(-EINVAL);
+
+       switch (init_attr->qp_type) {
+       case IB_QPT_XRC_TGT:
+               pd = to_mxrcd(init_attr->xrcd)->pd;
+               xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
+               init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
+               /* fall through */
+       case IB_QPT_XRC_INI:
+               if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
+                       return ERR_PTR(-ENOSYS);
+               init_attr->recv_cq = init_attr->send_cq;
+               /* fall through */
+       case IB_QPT_RC:
+       case IB_QPT_UC:
+       case IB_QPT_RAW_PACKET:
+               qp = kzalloc(sizeof *qp, gfp);
+               if (!qp)
+                       return ERR_PTR(-ENOMEM);
+               qp->pri.vid = 0xFFFF;
+               qp->alt.vid = 0xFFFF;
+               /* fall through */
+       case IB_QPT_UD:
+       {
+               err = create_qp_common(to_mdev(pd->device), pd, init_attr,
+                                      udata, 0, &qp, gfp);
+               if (err)
+                       return ERR_PTR(err);
+
+               qp->ibqp.qp_num = qp->mqp.qpn;
+               qp->xrcdn = xrcdn;
+
+               break;
+       }
+       case IB_QPT_SMI:
+       case IB_QPT_GSI:
+       {
+               /* Userspace is not allowed to create special QPs: */
+               if (udata)
+                       return ERR_PTR(-EINVAL);
+
+               err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
+                                      get_sqp_num(to_mdev(pd->device), init_attr),
+                                      &qp, gfp);
+               if (err)
+                       return ERR_PTR(err);
+
+               qp->port        = init_attr->port_num;
+               qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
+
+               break;
+       }
+       default:
+               /* Don't support raw QPs */
+               return ERR_PTR(-EINVAL);
+       }
+
+       return &qp->ibqp;
+}
+
+int mlx4_ib_destroy_qp(struct ib_qp *qp)
+{
+       struct mlx4_ib_dev *dev = to_mdev(qp->device);
+       struct mlx4_ib_qp *mqp = to_mqp(qp);
+       struct mlx4_ib_pd *pd;
+
+       if (is_qp0(dev, mqp))
+               mlx4_CLOSE_PORT(dev->dev, mqp->port);
+
+       if (dev->qp1_proxy[mqp->port - 1] == mqp) {
+               mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
+               dev->qp1_proxy[mqp->port - 1] = NULL;
+               mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
+       }
+
+       pd = get_pd(mqp);
+       destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
+
+       if (is_sqp(dev, mqp))
+               kfree(to_msqp(mqp));
+       else
+               kfree(mqp);
+
+       return 0;
+}
+
+static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
+{
+       switch (type) {
+       case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
+       case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
+       case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
+       case MLX4_IB_QPT_XRC_INI:
+       case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
+       case MLX4_IB_QPT_SMI:
+       case MLX4_IB_QPT_GSI:
+       case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
+
+       case MLX4_IB_QPT_PROXY_SMI_OWNER:
+       case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
+                                               MLX4_QP_ST_MLX : -1);
+       case MLX4_IB_QPT_PROXY_SMI:
+       case MLX4_IB_QPT_TUN_SMI:
+       case MLX4_IB_QPT_PROXY_GSI:
+       case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
+                                               MLX4_QP_ST_UD : -1);
+       default:                        return -1;
+       }
+}
+
+static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
+                                  int attr_mask)
+{
+       u8 dest_rd_atomic;
+       u32 access_flags;
+       u32 hw_access_flags = 0;
+
+       if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
+               dest_rd_atomic = attr->max_dest_rd_atomic;
+       else
+               dest_rd_atomic = qp->resp_depth;
+
+       if (attr_mask & IB_QP_ACCESS_FLAGS)
+               access_flags = attr->qp_access_flags;
+       else
+               access_flags = qp->atomic_rd_en;
+
+       if (!dest_rd_atomic)
+               access_flags &= IB_ACCESS_REMOTE_WRITE;
+
+       if (access_flags & IB_ACCESS_REMOTE_READ)
+               hw_access_flags |= MLX4_QP_BIT_RRE;
+       if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
+               hw_access_flags |= MLX4_QP_BIT_RAE;
+       if (access_flags & IB_ACCESS_REMOTE_WRITE)
+               hw_access_flags |= MLX4_QP_BIT_RWE;
+
+       return cpu_to_be32(hw_access_flags);
+}
+
+static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
+                           int attr_mask)
+{
+       if (attr_mask & IB_QP_PKEY_INDEX)
+               sqp->pkey_index = attr->pkey_index;
+       if (attr_mask & IB_QP_QKEY)
+               sqp->qkey = attr->qkey;
+       if (attr_mask & IB_QP_SQ_PSN)
+               sqp->send_psn = attr->sq_psn;
+}
+
+static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
+{
+       path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
+}
+
+static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
+                         u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
+                         struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
+{
+       int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
+               IB_LINK_LAYER_ETHERNET;
+       int vidx;
+       int smac_index;
+       int err;
+
+
+       path->grh_mylmc     = ah->src_path_bits & 0x7f;
+       path->rlid          = cpu_to_be16(ah->dlid);
+       if (ah->static_rate) {
+               path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
+               while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
+                      !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
+                       --path->static_rate;
+       } else
+               path->static_rate = 0;
+
+       if (ah->ah_flags & IB_AH_GRH) {
+               if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
+                       pr_err("sgid_index (%u) too large. max is %d\n",
+                              ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
+                       return -1;
+               }
+
+               path->grh_mylmc |= 1 << 7;
+               path->mgid_index = ah->grh.sgid_index;
+               path->hop_limit  = ah->grh.hop_limit;
+               path->tclass_flowlabel =
+                       cpu_to_be32((ah->grh.traffic_class << 20) |
+                                   (ah->grh.flow_label));
+               memcpy(path->rgid, ah->grh.dgid.raw, 16);
+       }
+
+       if (is_eth) {
+               if (!(ah->ah_flags & IB_AH_GRH))
+                       return -1;
+
+               path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
+                       ((port - 1) << 6) | ((ah->sl & 7) << 3);
+
+               path->feup |= MLX4_FEUP_FORCE_ETH_UP;
+               if (vlan_tag < 0x1000) {
+                       if (smac_info->vid < 0x1000) {
+                               /* both valid vlan ids */
+                               if (smac_info->vid != vlan_tag) {
+                                       /* different VIDs.  unreg old and reg new */
+                                       err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
+                                       if (err)
+                                               return err;
+                                       smac_info->candidate_vid = vlan_tag;
+                                       smac_info->candidate_vlan_index = vidx;
+                                       smac_info->candidate_vlan_port = port;
+                                       smac_info->update_vid = 1;
+                                       path->vlan_index = vidx;
+                               } else {
+                                       path->vlan_index = smac_info->vlan_index;
+                               }
+                       } else {
+                               /* no current vlan tag in qp */
+                               err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
+                               if (err)
+                                       return err;
+                               smac_info->candidate_vid = vlan_tag;
+                               smac_info->candidate_vlan_index = vidx;
+                               smac_info->candidate_vlan_port = port;
+                               smac_info->update_vid = 1;
+                               path->vlan_index = vidx;
+                       }
+                       path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
+                       path->fl = 1 << 6;
+               } else {
+                       /* have current vlan tag. unregister it at modify-qp success */
+                       if (smac_info->vid < 0x1000) {
+                               smac_info->candidate_vid = 0xFFFF;
+                               smac_info->update_vid = 1;
+                       }
+               }
+
+               /* get smac_index for RoCE use.
+                * If no smac was yet assigned, register one.
+                * If one was already assigned, but the new mac differs,
+                * unregister the old one and register the new one.
+               */
+               if ((!smac_info->smac && !smac_info->smac_port) ||
+                   smac_info->smac != smac) {
+                       /* register candidate now, unreg if needed, after success */
+                       smac_index = mlx4_register_mac(dev->dev, port, smac);
+                       if (smac_index >= 0) {
+                               smac_info->candidate_smac_index = smac_index;
+                               smac_info->candidate_smac = smac;
+                               smac_info->candidate_smac_port = port;
+                       } else {
+                               return -EINVAL;
+                       }
+               } else {
+                       smac_index = smac_info->smac_index;
+               }
+
+               memcpy(path->dmac, ah->dmac, 6);
+               path->ackto = MLX4_IB_LINK_TYPE_ETH;
+               /* put MAC table smac index for IBoE */
+               path->grh_mylmc = (u8) (smac_index) | 0x80;
+       } else {
+               path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
+                       ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
+       }
+
+       return 0;
+}
+
+static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
+                        enum ib_qp_attr_mask qp_attr_mask,
+                        struct mlx4_ib_qp *mqp,
+                        struct mlx4_qp_path *path, u8 port)
+{
+       return _mlx4_set_path(dev, &qp->ah_attr,
+                             mlx4_mac_to_u64((u8 *)qp->smac),
+                             (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
+                             path, &mqp->pri, port);
+}
+
+static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
+                            const struct ib_qp_attr *qp,
+                            enum ib_qp_attr_mask qp_attr_mask,
+                            struct mlx4_ib_qp *mqp,
+                            struct mlx4_qp_path *path, u8 port)
+{
+       return _mlx4_set_path(dev, &qp->alt_ah_attr,
+                             mlx4_mac_to_u64((u8 *)qp->alt_smac),
+                             (qp_attr_mask & IB_QP_ALT_VID) ?
+                             qp->alt_vlan_id : 0xffff,
+                             path, &mqp->alt, port);
+}
+
+static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
+{
+       struct mlx4_ib_gid_entry *ge, *tmp;
+
+       list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
+               if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
+                       ge->added = 1;
+                       ge->port = qp->port;
+               }
+       }
+}
+
+static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac,
+                                   struct mlx4_qp_context *context)
+{
+       u64 u64_mac;
+       int smac_index;
+
+       u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
+
+       context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
+       if (!qp->pri.smac && !qp->pri.smac_port) {
+               smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
+               if (smac_index >= 0) {
+                       qp->pri.candidate_smac_index = smac_index;
+                       qp->pri.candidate_smac = u64_mac;
+                       qp->pri.candidate_smac_port = qp->port;
+                       context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
+               } else {
+                       return -ENOENT;
+               }
+       }
+       return 0;
+}
+
+static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
+                              const struct ib_qp_attr *attr, int attr_mask,
+                              enum ib_qp_state cur_state, enum ib_qp_state new_state)
+{
+       struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
+       struct mlx4_ib_qp *qp = to_mqp(ibqp);
+       struct mlx4_ib_pd *pd;
+       struct mlx4_ib_cq *send_cq, *recv_cq;
+       struct mlx4_qp_context *context;
+       enum mlx4_qp_optpar optpar = 0;
+       int sqd_event;
+       int steer_qp = 0;
+       int err = -EINVAL;
+
+       /* APM is not supported under RoCE */
+       if (attr_mask & IB_QP_ALT_PATH &&
+           rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
+           IB_LINK_LAYER_ETHERNET)
+               return -ENOTSUPP;
+
+       context = kzalloc(sizeof *context, GFP_KERNEL);
+       if (!context)
+               return -ENOMEM;
+
+       context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
+                                    (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
+
+       if (!(attr_mask & IB_QP_PATH_MIG_STATE))
+               context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
+       else {
+               optpar |= MLX4_QP_OPTPAR_PM_STATE;
+               switch (attr->path_mig_state) {
+               case IB_MIG_MIGRATED:
+                       context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
+                       break;
+               case IB_MIG_REARM:
+                       context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
+                       break;
+               case IB_MIG_ARMED:
+                       context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
+                       break;
+               }
+       }
+
+       if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
+               context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
+       else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
+               context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
+       else if (ibqp->qp_type == IB_QPT_UD) {
+               if (qp->flags & MLX4_IB_QP_LSO)
+                       context->mtu_msgmax = (IB_MTU_4096 << 5) |
+                                             ilog2(dev->dev->caps.max_gso_sz);
+               else
+                       context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
+       } else if (attr_mask & IB_QP_PATH_MTU) {
+               if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
+                       pr_err("path MTU (%u) is invalid\n",
+                              attr->path_mtu);
+                       goto out;
+               }
+               context->mtu_msgmax = (attr->path_mtu << 5) |
+                       ilog2(dev->dev->caps.max_msg_sz);
+       }
+
+       if (qp->rq.wqe_cnt)
+               context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
+       context->rq_size_stride |= qp->rq.wqe_shift - 4;
+
+       if (qp->sq.wqe_cnt)
+               context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
+       context->sq_size_stride |= qp->sq.wqe_shift - 4;
+
+       if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
+               context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
+               context->xrcd = cpu_to_be32((u32) qp->xrcdn);
+               if (ibqp->qp_type == IB_QPT_RAW_PACKET)
+                       context->param3 |= cpu_to_be32(1 << 30);
+       }
+
+       if (qp->ibqp.uobject)
+               context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
+       else
+               context->usr_page = cpu_to_be32(dev->priv_uar.index);
+
+       if (attr_mask & IB_QP_DEST_QPN)
+               context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
+
+       if (attr_mask & IB_QP_PORT) {
+               if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
+                   !(attr_mask & IB_QP_AV)) {
+                       mlx4_set_sched(&context->pri_path, attr->port_num);
+                       optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
+               }
+       }
+
+       if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
+               if (dev->counters[qp->port - 1] != -1) {
+                       context->pri_path.counter_index =
+                                               dev->counters[qp->port - 1];
+                       optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
+               } else
+                       context->pri_path.counter_index = 0xff;
+
+               if (qp->flags & MLX4_IB_QP_NETIF) {
+                       mlx4_ib_steer_qp_reg(dev, qp, 1);
+                       steer_qp = 1;
+               }
+       }
+
+       if (attr_mask & IB_QP_PKEY_INDEX) {
+               if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
+                       context->pri_path.disable_pkey_check = 0x40;
+               context->pri_path.pkey_index = attr->pkey_index;
+               optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
+       }
+
+       if (attr_mask & IB_QP_AV) {
+               if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
+                                 attr_mask & IB_QP_PORT ?
+                                 attr->port_num : qp->port))
+                       goto out;
+
+               optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
+                          MLX4_QP_OPTPAR_SCHED_QUEUE);
+       }
+
+       if (attr_mask & IB_QP_TIMEOUT) {
+               context->pri_path.ackto |= attr->timeout << 3;
+               optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
+       }
+
+       if (attr_mask & IB_QP_ALT_PATH) {
+               if (attr->alt_port_num == 0 ||
+                   attr->alt_port_num > dev->dev->caps.num_ports)
+                       goto out;
+
+               if (attr->alt_pkey_index >=
+                   dev->dev->caps.pkey_table_len[attr->alt_port_num])
+                       goto out;
+
+               if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
+                                     &context->alt_path,
+                                     attr->alt_port_num))
+                       goto out;
+
+               context->alt_path.pkey_index = attr->alt_pkey_index;
+               context->alt_path.ackto = attr->alt_timeout << 3;
+               optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
+       }
+
+       pd = get_pd(qp);
+       get_cqs(qp, &send_cq, &recv_cq);
+       context->pd       = cpu_to_be32(pd->pdn);
+       context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
+       context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
+       context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
+
+       /* Set "fast registration enabled" for all kernel QPs */
+       if (!qp->ibqp.uobject)
+               context->params1 |= cpu_to_be32(1 << 11);
+
+       if (attr_mask & IB_QP_RNR_RETRY) {
+               context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
+               optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
+       }
+
+       if (attr_mask & IB_QP_RETRY_CNT) {
+               context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
+               optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
+       }
+
+       if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
+               if (attr->max_rd_atomic)
+                       context->params1 |=
+                               cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
+               optpar |= MLX4_QP_OPTPAR_SRA_MAX;
+       }
+
+       if (attr_mask & IB_QP_SQ_PSN)
+               context->next_send_psn = cpu_to_be32(attr->sq_psn);
+
+       if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
+               if (attr->max_dest_rd_atomic)
+                       context->params2 |=
+                               cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
+               optpar |= MLX4_QP_OPTPAR_RRA_MAX;
+       }
+
+       if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
+               context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
+               optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
+       }
+
+       if (ibqp->srq)
+               context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
+
+       if (attr_mask & IB_QP_MIN_RNR_TIMER) {
+               context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
+               optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
+       }
+       if (attr_mask & IB_QP_RQ_PSN)
+               context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
+
+       /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
+       if (attr_mask & IB_QP_QKEY) {
+               if (qp->mlx4_ib_qp_type &
+                   (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
+                       context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
+               else {
+                       if (mlx4_is_mfunc(dev->dev) &&
+                           !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
+                           (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
+                           MLX4_RESERVED_QKEY_BASE) {
+                               pr_err("Cannot use reserved QKEY"
+                                      " 0x%x (range 0xffff0000..0xffffffff"
+                                      " is reserved)\n", attr->qkey);
+                               err = -EINVAL;
+                               goto out;
+                       }
+                       context->qkey = cpu_to_be32(attr->qkey);
+               }
+               optpar |= MLX4_QP_OPTPAR_Q_KEY;
+       }
+
+       if (ibqp->srq)
+               context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
+
+       if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
+               context->db_rec_addr = cpu_to_be64(qp->db.dma);
+
+       if (cur_state == IB_QPS_INIT &&
+           new_state == IB_QPS_RTR  &&
+           (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
+            ibqp->qp_type == IB_QPT_UD ||
+            ibqp->qp_type == IB_QPT_RAW_PACKET)) {
+               context->pri_path.sched_queue = (qp->port - 1) << 6;
+               if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
+                   qp->mlx4_ib_qp_type &
+                   (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
+                       context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
+                       if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
+                               context->pri_path.fl = 0x80;
+               } else {
+                       if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
+                               context->pri_path.fl = 0x80;
+                       context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
+               }
+               if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
+                   IB_LINK_LAYER_ETHERNET) {
+                       if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
+                           qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
+                               context->pri_path.feup = 1 << 7; /* don't fsm */
+                       /* handle smac_index */
+                       if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
+                           qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
+                           qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
+                               err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context);
+                               if (err) {
+                                       err = -EINVAL;
+                                       goto out;
+                               }
+                               if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
+                                       dev->qp1_proxy[qp->port - 1] = qp;
+                       }
+               }
+       }
+
+       if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
+               context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
+                                       MLX4_IB_LINK_TYPE_ETH;
+               if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
+                       /* set QP to receive both tunneled & non-tunneled packets */
+                       if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
+                               context->srqn = cpu_to_be32(7 << 28);
+               }
+       }
+
+       if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
+               int is_eth = rdma_port_get_link_layer(
+                               &dev->ib_dev, qp->port) ==
+                               IB_LINK_LAYER_ETHERNET;
+               if (is_eth) {
+                       context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
+                       optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
+               }
+       }
+
+
+       if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
+           attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
+               sqd_event = 1;
+       else
+               sqd_event = 0;
+
+       if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
+               context->rlkey |= (1 << 4);
+
+       /*
+        * Before passing a kernel QP to the HW, make sure that the
+        * ownership bits of the send queue are set and the SQ
+        * headroom is stamped so that the hardware doesn't start
+        * processing stale work requests.
+        */
+       if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
+               struct mlx4_wqe_ctrl_seg *ctrl;
+               int i;
+
+               for (i = 0; i < qp->sq.wqe_cnt; ++i) {
+                       ctrl = get_send_wqe(qp, i);
+                       ctrl->owner_opcode = cpu_to_be32(1 << 31);
+                       if (qp->sq_max_wqes_per_wr == 1)
+                               ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
+
+                       stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
+               }
+       }
+
+       err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
+                            to_mlx4_state(new_state), context, optpar,
+                            sqd_event, &qp->mqp);
+       if (err)
+               goto out;
+
+       qp->state = new_state;
+
+       if (attr_mask & IB_QP_ACCESS_FLAGS)
+               qp->atomic_rd_en = attr->qp_access_flags;
+       if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
+               qp->resp_depth = attr->max_dest_rd_atomic;
+       if (attr_mask & IB_QP_PORT) {
+               qp->port = attr->port_num;
+               update_mcg_macs(dev, qp);
+       }
+       if (attr_mask & IB_QP_ALT_PATH)
+               qp->alt_port = attr->alt_port_num;
+
+       if (is_sqp(dev, qp))
+               store_sqp_attrs(to_msqp(qp), attr, attr_mask);
+
+       /*
+        * If we moved QP0 to RTR, bring the IB link up; if we moved
+        * QP0 to RESET or ERROR, bring the link back down.
+        */
+       if (is_qp0(dev, qp)) {
+               if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
+                       if (mlx4_INIT_PORT(dev->dev, qp->port))
+                               pr_warn("INIT_PORT failed for port %d\n",
+                                      qp->port);
+
+               if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
+                   (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
+                       mlx4_CLOSE_PORT(dev->dev, qp->port);
+       }
+
+       /*
+        * If we moved a kernel QP to RESET, clean up all old CQ
+        * entries and reinitialize the QP.
+        */
+       if (new_state == IB_QPS_RESET) {
+               if (!ibqp->uobject) {
+                       mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
+                                        ibqp->srq ? to_msrq(ibqp->srq) : NULL);
+                       if (send_cq != recv_cq)
+                               mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
+
+                       qp->rq.head = 0;
+                       qp->rq.tail = 0;
+                       qp->sq.head = 0;
+                       qp->sq.tail = 0;
+                       qp->sq_next_wqe = 0;
+                       if (qp->rq.wqe_cnt)
+                               *qp->db.db  = 0;
+
+                       if (qp->flags & MLX4_IB_QP_NETIF)
+                               mlx4_ib_steer_qp_reg(dev, qp, 0);
+               }
+               if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
+                       mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
+                       qp->pri.smac = 0;
+                       qp->pri.smac_port = 0;
+               }
+               if (qp->alt.smac) {
+                       mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
+                       qp->alt.smac = 0;
+               }
+               if (qp->pri.vid < 0x1000) {
+                       mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
+                       qp->pri.vid = 0xFFFF;
+                       qp->pri.candidate_vid = 0xFFFF;
+                       qp->pri.update_vid = 0;
+               }
+
+               if (qp->alt.vid < 0x1000) {
+                       mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
+                       qp->alt.vid = 0xFFFF;
+                       qp->alt.candidate_vid = 0xFFFF;
+                       qp->alt.update_vid = 0;
+               }
+       }
+out:
+       if (err && steer_qp)
+               mlx4_ib_steer_qp_reg(dev, qp, 0);
+       kfree(context);
+       if (qp->pri.candidate_smac ||
+           (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
+               if (err) {
+                       mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
+               } else {
+                       if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
+                               mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
+                       qp->pri.smac = qp->pri.candidate_smac;
+                       qp->pri.smac_index = qp->pri.candidate_smac_index;
+                       qp->pri.smac_port = qp->pri.candidate_smac_port;
+               }
+               qp->pri.candidate_smac = 0;
+               qp->pri.candidate_smac_index = 0;
+               qp->pri.candidate_smac_port = 0;
+       }
+       if (qp->alt.candidate_smac) {
+               if (err) {
+                       mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
+               } else {
+                       if (qp->alt.smac)
+                               mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
+                       qp->alt.smac = qp->alt.candidate_smac;
+                       qp->alt.smac_index = qp->alt.candidate_smac_index;
+                       qp->alt.smac_port = qp->alt.candidate_smac_port;
+               }
+               qp->alt.candidate_smac = 0;
+               qp->alt.candidate_smac_index = 0;
+               qp->alt.candidate_smac_port = 0;
+       }
+
+       if (qp->pri.update_vid) {
+               if (err) {
+                       if (qp->pri.candidate_vid < 0x1000)
+                               mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
+                                                    qp->pri.candidate_vid);
+               } else {
+                       if (qp->pri.vid < 0x1000)
+                               mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
+                                                    qp->pri.vid);
+                       qp->pri.vid = qp->pri.candidate_vid;
+                       qp->pri.vlan_port = qp->pri.candidate_vlan_port;
+                       qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
+               }
+               qp->pri.candidate_vid = 0xFFFF;
+               qp->pri.update_vid = 0;
+       }
+
+       if (qp->alt.update_vid) {
+               if (err) {
+                       if (qp->alt.candidate_vid < 0x1000)
+                               mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
+                                                    qp->alt.candidate_vid);
+               } else {
+                       if (qp->alt.vid < 0x1000)
+                               mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
+                                                    qp->alt.vid);
+                       qp->alt.vid = qp->alt.candidate_vid;
+                       qp->alt.vlan_port = qp->alt.candidate_vlan_port;
+                       qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
+               }
+               qp->alt.candidate_vid = 0xFFFF;
+               qp->alt.update_vid = 0;
+       }
+
+       return err;
+}
+
+int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
+                     int attr_mask, struct ib_udata *udata)
+{
+       struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
+       struct mlx4_ib_qp *qp = to_mqp(ibqp);
+       enum ib_qp_state cur_state, new_state;
+       int err = -EINVAL;
+       int ll;
+       mutex_lock(&qp->mutex);
+
+       cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
+       new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
+
+       if (cur_state == new_state && cur_state == IB_QPS_RESET) {
+               ll = IB_LINK_LAYER_UNSPECIFIED;
+       } else {
+               int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
+               ll = rdma_port_get_link_layer(&dev->ib_dev, port);
+       }
+
+       if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
+                               attr_mask, ll)) {
+               pr_debug("qpn 0x%x: invalid attribute mask specified "
+                        "for transition %d to %d. qp_type %d,"
+                        " attr_mask 0x%x\n",
+                        ibqp->qp_num, cur_state, new_state,
+                        ibqp->qp_type, attr_mask);
+               goto out;
+       }
+
+       if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
+               if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
+                       if ((ibqp->qp_type == IB_QPT_RC) ||
+                           (ibqp->qp_type == IB_QPT_UD) ||
+                           (ibqp->qp_type == IB_QPT_UC) ||
+                           (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
+                           (ibqp->qp_type == IB_QPT_XRC_INI)) {
+                               attr->port_num = mlx4_ib_bond_next_port(dev);
+                       }
+               } else {
+                       /* no sense in changing port_num
+                        * when ports are bonded */
+                       attr_mask &= ~IB_QP_PORT;
+               }
+       }
+
+       if ((attr_mask & IB_QP_PORT) &&
+           (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
+               pr_debug("qpn 0x%x: invalid port number (%d) specified "
+                        "for transition %d to %d. qp_type %d\n",
+                        ibqp->qp_num, attr->port_num, cur_state,
+                        new_state, ibqp->qp_type);
+               goto out;
+       }
+
+       if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
+           (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
+            IB_LINK_LAYER_ETHERNET))
+               goto out;
+
+       if (attr_mask & IB_QP_PKEY_INDEX) {
+               int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
+               if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
+                       pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
+                                "for transition %d to %d. qp_type %d\n",
+                                ibqp->qp_num, attr->pkey_index, cur_state,
+                                new_state, ibqp->qp_type);
+                       goto out;
+               }
+       }
+
+       if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
+           attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
+               pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
+                        "Transition %d to %d. qp_type %d\n",
+                        ibqp->qp_num, attr->max_rd_atomic, cur_state,
+                        new_state, ibqp->qp_type);
+               goto out;
+       }
+
+       if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
+           attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
+               pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
+                        "Transition %d to %d. qp_type %d\n",
+                        ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
+                        new_state, ibqp->qp_type);
+               goto out;
+       }
+
+       if (cur_state == new_state && cur_state == IB_QPS_RESET) {
+               err = 0;
+               goto out;
+       }
+
+       err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
+
+       if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
+               attr->port_num = 1;
+
+out:
+       mutex_unlock(&qp->mutex);
+       return err;
+}
+
+#if 0  /* AKAROS */
+static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
+{
+       int i;
+       for (i = 0; i < dev->caps.num_ports; i++) {
+               if (qpn == dev->caps.qp0_proxy[i] ||
+                   qpn == dev->caps.qp0_tunnel[i]) {
+                       *qkey = dev->caps.qp0_qkey[i];
+                       return 0;
+               }
+       }
+       return -EINVAL;
+}
+
+static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
+                                 struct ib_send_wr *wr,
+                                 void *wqe, unsigned *mlx_seg_len)
+{
+       struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
+       struct ib_device *ib_dev = &mdev->ib_dev;
+       struct mlx4_wqe_mlx_seg *mlx = wqe;
+       struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
+       struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
+       u16 pkey;
+       u32 qkey;
+       int send_size;
+       int header_size;
+       int spc;
+       int i;
+
+       if (wr->opcode != IB_WR_SEND)
+               return -EINVAL;
+
+       send_size = 0;
+
+       for (i = 0; i < wr->num_sge; ++i)
+               send_size += wr->sg_list[i].length;
+
+       /* for proxy-qp0 sends, need to add in size of tunnel header */
+       /* for tunnel-qp0 sends, tunnel header is already in s/g list */
+       if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
+               send_size += sizeof (struct mlx4_ib_tunnel_header);
+
+       ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
+
+       if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
+               sqp->ud_header.lrh.service_level =
+                       be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
+               sqp->ud_header.lrh.destination_lid =
+                       cpu_to_be16(ah->av.ib.g_slid & 0x7f);
+               sqp->ud_header.lrh.source_lid =
+                       cpu_to_be16(ah->av.ib.g_slid & 0x7f);
+       }
+
+       mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
+
+       /* force loopback */
+       mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
+       mlx->rlid = sqp->ud_header.lrh.destination_lid;
+
+       sqp->ud_header.lrh.virtual_lane    = 0;
+       sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
+       ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
+       sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
+       if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
+               sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
+       else
+               sqp->ud_header.bth.destination_qpn =
+                       cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
+
+       sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
+       if (mlx4_is_master(mdev->dev)) {
+               if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
+                       return -EINVAL;
+       } else {
+               if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
+                       return -EINVAL;
+       }
+       sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
+       sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
+
+       sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
+       sqp->ud_header.immediate_present = 0;
+
+       header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
+
+       /*
+        * Inline data segments may not cross a 64 byte boundary.  If
+        * our UD header is bigger than the space available up to the
+        * next 64 byte boundary in the WQE, use two inline data
+        * segments to hold the UD header.
+        */
+       spc = MLX4_INLINE_ALIGN -
+             ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
+       if (header_size <= spc) {
+               inl->byte_count = cpu_to_be32(1 << 31 | header_size);
+               memcpy(inl + 1, sqp->header_buf, header_size);
+               i = 1;
+       } else {
+               inl->byte_count = cpu_to_be32(1 << 31 | spc);
+               memcpy(inl + 1, sqp->header_buf, spc);
+
+               inl = (void *) (inl + 1) + spc;
+               memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
+               /*
+                * Need a barrier here to make sure all the data is
+                * visible before the byte_count field is set.
+                * Otherwise the HCA prefetcher could grab the 64-byte
+                * chunk with this inline segment and get a valid (!=
+                * 0xffffffff) byte count but stale data, and end up
+                * generating a packet with bad headers.
+                *
+                * The first inline segment's byte_count field doesn't
+                * need a barrier, because it comes after a
+                * control/MLX segment and therefore is at an offset
+                * of 16 mod 64.
+                */
+               wmb();
+               inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
+               i = 2;
+       }
+
+       *mlx_seg_len =
+       ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
+       return 0;
+}
+
+static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
+{
+       int i;
+
+       for (i = ETH_ALEN; i; i--) {
+               dst_mac[i - 1] = src_mac & 0xff;
+               src_mac >>= 8;
+       }
+}
+
+static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
+                           void *wqe, unsigned *mlx_seg_len)
+{
+       struct ib_device *ib_dev = sqp->qp.ibqp.device;
+       struct mlx4_wqe_mlx_seg *mlx = wqe;
+       struct mlx4_wqe_ctrl_seg *ctrl = wqe;
+       struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
+       struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
+       union ib_gid sgid;
+       u16 pkey;
+       int send_size;
+       int header_size;
+       int spc;
+       int i;
+       int err = 0;
+       u16 vlan = 0xffff;
+       bool is_eth;
+       bool is_vlan = false;
+       bool is_grh;
+
+       send_size = 0;
+       for (i = 0; i < wr->num_sge; ++i)
+               send_size += wr->sg_list[i].length;
+
+       is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
+       is_grh = mlx4_ib_ah_grh_present(ah);
+       if (is_eth) {
+               if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
+                       /* When multi-function is enabled, the ib_core gid
+                        * indexes don't necessarily match the hw ones, so
+                        * we must use our own cache */
+                       err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
+                                                          be32_to_cpu(ah->av.ib.port_pd) >> 24,
+                                                          ah->av.ib.gid_index, &sgid.raw[0]);
+                       if (err)
+                               return err;
+               } else  {
+                       err = ib_get_cached_gid(ib_dev,
+                                               be32_to_cpu(ah->av.ib.port_pd) >> 24,
+                                               ah->av.ib.gid_index, &sgid);
+                       if (err)
+                               return err;
+               }
+
+               if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
+                       vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
+                       is_vlan = 1;
+               }
+       }
+       ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
+
+       if (!is_eth) {
+               sqp->ud_header.lrh.service_level =
+                       be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
+               sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
+               sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
+       }
+
+       if (is_grh) {
+               sqp->ud_header.grh.traffic_class =
+                       (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
+               sqp->ud_header.grh.flow_label    =
+                       ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
+               sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
+               if (is_eth)
+                       memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
+               else {
+               if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
+                       /* When multi-function is enabled, the ib_core gid
+                        * indexes don't necessarily match the hw ones, so
+                        * we must use our own cache */
+                       sqp->ud_header.grh.source_gid.global.subnet_prefix =
+                               to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
+                                                      subnet_prefix;
+                       sqp->ud_header.grh.source_gid.global.interface_id =
+                               to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
+                                              guid_cache[ah->av.ib.gid_index];
+               } else
+                       ib_get_cached_gid(ib_dev,
+                                         be32_to_cpu(ah->av.ib.port_pd) >> 24,
+                                         ah->av.ib.gid_index,
+                                         &sqp->ud_header.grh.source_gid);
+               }
+               memcpy(sqp->ud_header.grh.destination_gid.raw,
+                      ah->av.ib.dgid, 16);
+       }
+
+       mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
+
+       if (!is_eth) {
+               mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
+                                         (sqp->ud_header.lrh.destination_lid ==
+                                          IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
+                                         (sqp->ud_header.lrh.service_level << 8));
+               if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
+                       mlx->flags |= cpu_to_be32(0x1); /* force loopback */
+               mlx->rlid = sqp->ud_header.lrh.destination_lid;
+       }
+
+       switch (wr->opcode) {
+       case IB_WR_SEND:
+               sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
+               sqp->ud_header.immediate_present = 0;
+               break;
+       case IB_WR_SEND_WITH_IMM:
+               sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
+               sqp->ud_header.immediate_present = 1;
+               sqp->ud_header.immediate_data    = wr->ex.imm_data;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       if (is_eth) {
+               struct in6_addr in6;
+
+               u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
+
+               mlx->sched_prio = cpu_to_be16(pcp);
+
+               memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
+               /* FIXME: cache smac value? */
+               memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
+               memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
+               memcpy(&in6, sgid.raw, sizeof(in6));
+
+               if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
+                       u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
+                       u8 smac[ETH_ALEN];
+
+                       mlx4_u64_to_smac(smac, mac);
+                       memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
+               } else {
+                       /* use the src mac of the tunnel */
+                       memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
+               }
+
+               if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
+                       mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
+               if (!is_vlan) {
+                       sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
+               } else {
+                       sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
+                       sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
+               }
+       } else {
+               sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
+               if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
+                       sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
+       }
+       sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
+       if (!sqp->qp.ibqp.qp_num)
+               ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
+       else
+               ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
+       sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
+       sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
+       sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
+       sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
+                                              sqp->qkey : wr->wr.ud.remote_qkey);
+       sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
+
+       header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
+
+       if (0) {
+               pr_err("built UD header of size %d:\n", header_size);
+               for (i = 0; i < header_size / 4; ++i) {
+                       if (i % 8 == 0)
+                               pr_err("  [%02x] ", i * 4);
+                       pr_cont(" %08x",
+                               be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
+                       if ((i + 1) % 8 == 0)
+                               pr_cont("\n");
+               }
+               pr_err("\n");
+       }
+
+       /*
+        * Inline data segments may not cross a 64 byte boundary.  If
+        * our UD header is bigger than the space available up to the
+        * next 64 byte boundary in the WQE, use two inline data
+        * segments to hold the UD header.
+        */