Added libpfm4 library support
authorDavide Libenzi <dlibenzi@google.com>
Mon, 16 Nov 2015 15:03:55 +0000 (07:03 -0800)
committerBarret Rhoden <brho@cs.berkeley.edu>
Wed, 16 Dec 2015 21:27:06 +0000 (16:27 -0500)
Added libpfm4 library support. The libpfm4 library provides a database
of counters available on different Intel platforms.
The library source was fetched from its home page:

http://perfmon2.sourceforge.net/

Signed-off-by: Davide Libenzi <dlibenzi@google.com>
Signed-off-by: Barret Rhoden <brho@cs.berkeley.edu>
114 files changed:
Makefile
user/perfmon/Makefile [new file with mode: 0644]
user/perfmon/events/amd64_events_fam10h.h [new file with mode: 0644]
user/perfmon/events/amd64_events_fam11h.h [new file with mode: 0644]
user/perfmon/events/amd64_events_fam12h.h [new file with mode: 0644]
user/perfmon/events/amd64_events_fam14h.h [new file with mode: 0644]
user/perfmon/events/amd64_events_fam15h.h [new file with mode: 0644]
user/perfmon/events/amd64_events_fam15h_nb.h [new file with mode: 0644]
user/perfmon/events/amd64_events_k7.h [new file with mode: 0644]
user/perfmon/events/amd64_events_k8.h [new file with mode: 0644]
user/perfmon/events/intel_atom_events.h [new file with mode: 0644]
user/perfmon/events/intel_bdw_events.h [new file with mode: 0644]
user/perfmon/events/intel_core_events.h [new file with mode: 0644]
user/perfmon/events/intel_coreduo_events.h [new file with mode: 0644]
user/perfmon/events/intel_hsw_events.h [new file with mode: 0644]
user/perfmon/events/intel_ivb_events.h [new file with mode: 0644]
user/perfmon/events/intel_ivbep_unc_cbo_events.h [new file with mode: 0644]
user/perfmon/events/intel_ivbep_unc_ha_events.h [new file with mode: 0644]
user/perfmon/events/intel_ivbep_unc_imc_events.h [new file with mode: 0644]
user/perfmon/events/intel_ivbep_unc_irp_events.h [new file with mode: 0644]
user/perfmon/events/intel_ivbep_unc_pcu_events.h [new file with mode: 0644]
user/perfmon/events/intel_ivbep_unc_qpi_events.h [new file with mode: 0644]
user/perfmon/events/intel_ivbep_unc_r2pcie_events.h [new file with mode: 0644]
user/perfmon/events/intel_ivbep_unc_r3qpi_events.h [new file with mode: 0644]
user/perfmon/events/intel_ivbep_unc_ubo_events.h [new file with mode: 0644]
user/perfmon/events/intel_knc_events.h [new file with mode: 0644]
user/perfmon/events/intel_netburst_events.h [new file with mode: 0644]
user/perfmon/events/intel_nhm_events.h [new file with mode: 0644]
user/perfmon/events/intel_nhm_unc_events.h [new file with mode: 0644]
user/perfmon/events/intel_p6_events.h [new file with mode: 0644]
user/perfmon/events/intel_pii_events.h [new file with mode: 0644]
user/perfmon/events/intel_pm_events.h [new file with mode: 0644]
user/perfmon/events/intel_ppro_events.h [new file with mode: 0644]
user/perfmon/events/intel_slm_events.h [new file with mode: 0644]
user/perfmon/events/intel_snb_events.h [new file with mode: 0644]
user/perfmon/events/intel_snb_unc_events.h [new file with mode: 0644]
user/perfmon/events/intel_snbep_events.h [new file with mode: 0644]
user/perfmon/events/intel_snbep_unc_cbo_events.h [new file with mode: 0644]
user/perfmon/events/intel_snbep_unc_ha_events.h [new file with mode: 0644]
user/perfmon/events/intel_snbep_unc_imc_events.h [new file with mode: 0644]
user/perfmon/events/intel_snbep_unc_pcu_events.h [new file with mode: 0644]
user/perfmon/events/intel_snbep_unc_qpi_events.h [new file with mode: 0644]
user/perfmon/events/intel_snbep_unc_r2pcie_events.h [new file with mode: 0644]
user/perfmon/events/intel_snbep_unc_r3qpi_events.h [new file with mode: 0644]
user/perfmon/events/intel_snbep_unc_ubo_events.h [new file with mode: 0644]
user/perfmon/events/intel_wsm_events.h [new file with mode: 0644]
user/perfmon/events/intel_wsm_unc_events.h [new file with mode: 0644]
user/perfmon/events/intel_x86_arch_events.h [new file with mode: 0644]
user/perfmon/events/perf_events.h [new file with mode: 0644]
user/perfmon/examples/Makefile [new file with mode: 0644]
user/perfmon/examples/check_events.c [new file with mode: 0644]
user/perfmon/examples/showevtinfo.c [new file with mode: 0644]
user/perfmon/include/perfmon/err.h [new file with mode: 0644]
user/perfmon/include/perfmon/perf_event.h [new file with mode: 0644]
user/perfmon/include/perfmon/pfmlib.h [new file with mode: 0644]
user/perfmon/include/perfmon/pfmlib_perf_event.h [new file with mode: 0644]
user/perfmon/pfmlib_amd64.c [new file with mode: 0644]
user/perfmon/pfmlib_amd64_fam10h.c [new file with mode: 0644]
user/perfmon/pfmlib_amd64_fam11h.c [new file with mode: 0644]
user/perfmon/pfmlib_amd64_fam12h.c [new file with mode: 0644]
user/perfmon/pfmlib_amd64_fam14h.c [new file with mode: 0644]
user/perfmon/pfmlib_amd64_fam15h.c [new file with mode: 0644]
user/perfmon/pfmlib_amd64_k7.c [new file with mode: 0644]
user/perfmon/pfmlib_amd64_k8.c [new file with mode: 0644]
user/perfmon/pfmlib_amd64_priv.h [new file with mode: 0644]
user/perfmon/pfmlib_common.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_atom.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_bdw.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_core.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_coreduo.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_hsw.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_ivb.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_ivb_unc.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_ivbep_unc_cbo.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_ivbep_unc_ha.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_ivbep_unc_imc.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_ivbep_unc_irp.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_ivbep_unc_pcu.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_ivbep_unc_qpi.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_ivbep_unc_r2pcie.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_ivbep_unc_r3qpi.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_ivbep_unc_ubo.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_knc.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_netburst.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_netburst_priv.h [new file with mode: 0644]
user/perfmon/pfmlib_intel_nhm.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_nhm_unc.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_p6.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_rapl.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_slm.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_snb.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_snb_unc.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_snbep_unc.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_snbep_unc_cbo.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_snbep_unc_ha.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_snbep_unc_imc.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_snbep_unc_pcu.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_snbep_unc_priv.h [new file with mode: 0644]
user/perfmon/pfmlib_intel_snbep_unc_qpi.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_snbep_unc_r2pcie.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_snbep_unc_r3qpi.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_snbep_unc_ubo.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_wsm.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_x86.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_x86_arch.c [new file with mode: 0644]
user/perfmon/pfmlib_intel_x86_priv.h [new file with mode: 0644]
user/perfmon/pfmlib_priv.h [new file with mode: 0644]
user/perfmon/tests/Makefile [new file with mode: 0644]
user/perfmon/tests/validate.c [new file with mode: 0644]
user/perfmon/tests/validate_arm.c [new file with mode: 0644]
user/perfmon/tests/validate_arm64.c [new file with mode: 0644]
user/perfmon/tests/validate_mips.c [new file with mode: 0644]
user/perfmon/tests/validate_power.c [new file with mode: 0644]
user/perfmon/tests/validate_x86.c [new file with mode: 0644]

index 8defe95..7832ecb 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -573,7 +573,7 @@ endif #ifeq ($(mixed-targets),1)
 # List all userspace directories here, and state any dependencies between them,
 # such as how pthread depends on parlib.
 
-user-dirs = parlib pthread benchutil iplib ndblib vmm
+user-dirs = parlib pthread benchutil iplib ndblib vmm perfmon
 benchutil: parlib
 pthread: parlib benchutil
 iplib: parlib
@@ -586,6 +586,7 @@ install-libs: $(user-dirs) symlinks cc-exists
 $(user-dirs):
        @$(MAKE) -C user/$@ DEPLIBS="$^" && $(MAKE) -C user/$@ install
 
+user: $(user-dirs)
 
 PHONY += userclean $(clean-user-dirs)
 clean-user-dirs := $(addprefix _clean_user_,$(user-dirs))
@@ -656,7 +657,7 @@ realclean: userclean mrproper doxyclean objclean
 # =========================================================================
 
 PHONY += apps-install
-apps-install:
+apps-install: install-libs
        @$(call make_as_parent, -C tools/apps/busybox)
        @$(call make_as_parent, -C tools/profile/kprof2perf install)
        @$(call make_as_parent, -C tools/apps/snc install)
diff --git a/user/perfmon/Makefile b/user/perfmon/Makefile
new file mode 100644 (file)
index 0000000..fe114b3
--- /dev/null
@@ -0,0 +1,4 @@
+LIBNAME = perfmon
+CFLAGS_USER += -DBUILDING_PERFMON -DCONFIG_PFMLIB_ARCH_X86 \
+  -DCONFIG_PFMLIB_ARCH_X86_64
+include ../Makefrag-user-lib
diff --git a/user/perfmon/events/amd64_events_fam10h.h b/user/perfmon/events/amd64_events_fam10h.h
new file mode 100644 (file)
index 0000000..ab79812
--- /dev/null
@@ -0,0 +1,2418 @@
+/*
+ * Copyright (c) 2011 Google, Inc
+ * Contributed by Stephane Eranian <eranian@gmail.com>
+ *
+ * Regenerated from previous version by:
+ * Copyright (c) 2007 Advanced Micro Devices, Inc.
+ * Contributed by Robert Richter <robert.richter@amd.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * This file is part of libpfm, a performance monitoring support library for
+ * applications on Linux.
+ *
+ * This file has been automatically generated.
+ *
+ * PMU: amd64_fam10h (AMD64 Fam10h)
+ */
+
+/* History
+ *
+ * May 28 2010 -- Robert Richter, robert.richter@amd.com:
+ *
+ * Update from: BIOS and Kernel Developer's Guide (BKDG) For AMD
+ * Family 10h Processors, 31116 Rev 3.48 - April 22, 2010
+ *
+ * Feb 06 2009 -- Robert Richter, robert.richter@amd.com:
+ *
+ * Update for Family 10h RevD (Istanbul) from: BIOS and Kernel
+ * Developer's Guide (BKDG) For AMD Family 10h Processors, 31116 Rev
+ * 3.20 - February 04, 2009
+ * This file has been automatically generated.
+ *
+ * Update for Family 10h RevC (Shanghai) from: BIOS and Kernel
+ * Developer's Guide (BKDG) For AMD Family 10h Processors, 31116 Rev
+ * 3.20 - February 04, 2009
+ *
+ *
+ * Dec 12 2007 -- Robert Richter, robert.richter@amd.com:
+ *
+ * Created from: BIOS and Kernel Developer's Guide (BKDG) For AMD
+ * Family 10h Processors, 31116 Rev 3.00 - September 07, 2007
+ * PMU: amd64_fam10h (AMD64 Fam10h)
+ */
+
+static const amd64_umask_t amd64_fam10h_dispatched_fpu[]={
+   { .uname  = "OPS_ADD",
+     .udesc  = "Add pipe ops excluding load ops and SSE move ops",
+     .ucode = 0x1,
+   },
+   { .uname  = "OPS_MULTIPLY",
+     .udesc  = "Multiply pipe ops excluding load ops and SSE move ops",
+     .ucode = 0x2,
+   },
+   { .uname  = "OPS_STORE",
+     .udesc  = "Store pipe ops excluding load ops and SSE move ops",
+     .ucode = 0x4,
+   },
+   { .uname  = "OPS_ADD_PIPE_LOAD_OPS",
+     .udesc  = "Add pipe load ops and SSE move ops",
+     .ucode = 0x8,
+   },
+   { .uname  = "OPS_MULTIPLY_PIPE_LOAD_OPS",
+     .udesc  = "Multiply pipe load ops and SSE move ops",
+     .ucode = 0x10,
+   },
+   { .uname  = "OPS_STORE_PIPE_LOAD_OPS",
+     .udesc  = "Store pipe load ops and SSE move ops",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_retired_sse_operations[]={
+   { .uname  = "SINGLE_ADD_SUB_OPS",
+     .udesc  = "Single precision add/subtract ops",
+     .ucode = 0x1,
+   },
+   { .uname  = "SINGLE_MUL_OPS",
+     .udesc  = "Single precision multiply ops",
+     .ucode = 0x2,
+   },
+   { .uname  = "SINGLE_DIV_OPS",
+     .udesc  = "Single precision divide/square root ops",
+     .ucode = 0x4,
+   },
+   { .uname  = "DOUBLE_ADD_SUB_OPS",
+     .udesc  = "Double precision add/subtract ops",
+     .ucode = 0x8,
+   },
+   { .uname  = "DOUBLE_MUL_OPS",
+     .udesc  = "Double precision multiply ops",
+     .ucode = 0x10,
+   },
+   { .uname  = "DOUBLE_DIV_OPS",
+     .udesc  = "Double precision divide/square root ops",
+     .ucode = 0x20,
+   },
+   { .uname  = "OP_TYPE",
+     .udesc  = "Op type: 0=uops. 1=FLOPS",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_retired_move_ops[]={
+   { .uname  = "LOW_QW_MOVE_UOPS",
+     .udesc  = "Merging low quadword move uops",
+     .ucode = 0x1,
+   },
+   { .uname  = "HIGH_QW_MOVE_UOPS",
+     .udesc  = "Merging high quadword move uops",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL_OTHER_MERGING_MOVE_UOPS",
+     .udesc  = "All other merging move uops",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL_OTHER_MOVE_UOPS",
+     .udesc  = "All other move uops",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_retired_serializing_ops[]={
+   { .uname  = "SSE_BOTTOM_EXECUTING_UOPS",
+     .udesc  = "SSE bottom-executing uops retired",
+     .ucode = 0x1,
+   },
+   { .uname  = "SSE_BOTTOM_SERIALIZING_UOPS",
+     .udesc  = "SSE bottom-serializing uops retired",
+     .ucode = 0x2,
+   },
+   { .uname  = "X87_BOTTOM_EXECUTING_UOPS",
+     .udesc  = "X87 bottom-executing uops retired",
+     .ucode = 0x4,
+   },
+   { .uname  = "X87_BOTTOM_SERIALIZING_UOPS",
+     .udesc  = "X87 bottom-serializing uops retired",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_fp_scheduler_cycles[]={
+   { .uname  = "BOTTOM_EXECUTE_CYCLES",
+     .udesc  = "Number of cycles a bottom-execute uop is in the FP scheduler",
+     .ucode = 0x1,
+   },
+   { .uname  = "BOTTOM_SERIALIZING_CYCLES",
+     .udesc  = "Number of cycles a bottom-serializing uop is in the FP scheduler",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_segment_register_loads[]={
+   { .uname  = "ES",
+     .udesc  = "ES",
+     .ucode = 0x1,
+   },
+   { .uname  = "CS",
+     .udesc  = "CS",
+     .ucode = 0x2,
+   },
+   { .uname  = "SS",
+     .udesc  = "SS",
+     .ucode = 0x4,
+   },
+   { .uname  = "DS",
+     .udesc  = "DS",
+     .ucode = 0x8,
+   },
+   { .uname  = "FS",
+     .udesc  = "FS",
+     .ucode = 0x10,
+   },
+   { .uname  = "GS",
+     .udesc  = "GS",
+     .ucode = 0x20,
+   },
+   { .uname  = "HS",
+     .udesc  = "HS",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_locked_ops[]={
+   { .uname  = "EXECUTED",
+     .udesc  = "The number of locked instructions executed",
+     .ucode = 0x1,
+   },
+   { .uname  = "CYCLES_SPECULATIVE_PHASE",
+     .udesc  = "The number of cycles spent in speculative phase",
+     .ucode = 0x2,
+   },
+   { .uname  = "CYCLES_NON_SPECULATIVE_PHASE",
+     .udesc  = "The number of cycles spent in non-speculative phase (including cache miss penalty)",
+     .ucode = 0x4,
+   },
+   { .uname  = "CYCLES_WAITING",
+     .udesc  = "The number of cycles waiting for a cache hit (cache miss penalty).",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_cancelled_store_to_load_forward_operations[]={
+   { .uname  = "ADDRESS_MISMATCHES",
+     .udesc  = "Address mismatches (starting byte not the same).",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORE_IS_SMALLER_THAN_LOAD",
+     .udesc  = "Store is smaller than load.",
+     .ucode = 0x2,
+   },
+   { .uname  = "MISALIGNED",
+     .udesc  = "Misaligned.",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_data_cache_refills[]={
+   { .uname  = "SYSTEM",
+     .udesc  = "Refill from the Northbridge",
+     .ucode = 0x1,
+   },
+   { .uname  = "L2_SHARED",
+     .udesc  = "Shared-state line from L2",
+     .ucode = 0x2,
+   },
+   { .uname  = "L2_EXCLUSIVE",
+     .udesc  = "Exclusive-state line from L2",
+     .ucode = 0x4,
+   },
+   { .uname  = "L2_OWNED",
+     .udesc  = "Owned-state line from L2",
+     .ucode = 0x8,
+   },
+   { .uname  = "L2_MODIFIED",
+     .udesc  = "Modified-state line from L2",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_data_cache_refills_from_system[]={
+   { .uname  = "INVALID",
+     .udesc  = "Invalid",
+     .ucode = 0x1,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x2,
+   },
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x8,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_data_cache_lines_evicted[]={
+   { .uname  = "INVALID",
+     .udesc  = "Invalid",
+     .ucode = 0x1,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x2,
+   },
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x8,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified",
+     .ucode = 0x10,
+   },
+   { .uname  = "BY_PREFETCHNTA",
+     .udesc  = "Cache line evicted was brought into the cache with by a PrefetchNTA instruction.",
+     .ucode = 0x20,
+   },
+   { .uname  = "NOT_BY_PREFETCHNTA",
+     .udesc  = "Cache line evicted was not brought into the cache with by a PrefetchNTA instruction.",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_l1_dtlb_miss_and_l2_dtlb_hit[]={
+   { .uname  = "L2_4K_TLB_HIT",
+     .udesc  = "L2 4K TLB hit",
+     .ucode = 0x1,
+   },
+   { .uname  = "L2_2M_TLB_HIT",
+     .udesc  = "L2 2M TLB hit",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL | AMD64_FL_TILL_FAM10H_REV_B,
+   },
+   { .uname  = "L2_1G_TLB_HIT",
+     .udesc  = "L2 1G TLB hit",
+     .ucode = 0x4,
+     .uflags= AMD64_FL_FAM10H_REV_C,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL | AMD64_FL_FAM10H_REV_C,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_l1_dtlb_and_l2_dtlb_miss[]={
+   { .uname  = "4K_TLB_RELOAD",
+     .udesc  = "4K TLB reload",
+     .ucode = 0x1,
+   },
+   { .uname  = "2M_TLB_RELOAD",
+     .udesc  = "2M TLB reload",
+     .ucode = 0x2,
+   },
+   { .uname  = "1G_TLB_RELOAD",
+     .udesc  = "1G TLB reload",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_scrubber_single_bit_ecc_errors[]={
+   { .uname  = "SCRUBBER_ERROR",
+     .udesc  = "Scrubber error",
+     .ucode = 0x1,
+   },
+   { .uname  = "PIGGYBACK_ERROR",
+     .udesc  = "Piggyback scrubber errors",
+     .ucode = 0x2,
+   },
+   { .uname  = "LOAD_PIPE_ERROR",
+     .udesc  = "Load pipe error",
+     .ucode = 0x4,
+   },
+   { .uname  = "STORE_WRITE_PIPE_ERROR",
+     .udesc  = "Store write pipe error",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_prefetch_instructions_dispatched[]={
+   { .uname  = "LOAD",
+     .udesc  = "Load (Prefetch, PrefetchT0/T1/T2)",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORE",
+     .udesc  = "Store (PrefetchW)",
+     .ucode = 0x2,
+   },
+   { .uname  = "NTA",
+     .udesc  = "NTA (PrefetchNTA)",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_dcache_misses_by_locked_instructions[]={
+   { .uname  = "DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONS",
+     .udesc  = "Data cache misses by locked instructions",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x2,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_l1_dtlb_hit[]={
+   { .uname  = "L1_4K_TLB_HIT",
+     .udesc  = "L1 4K TLB hit",
+     .ucode = 0x1,
+   },
+   { .uname  = "L1_2M_TLB_HIT",
+     .udesc  = "L1 2M TLB hit",
+     .ucode = 0x2,
+   },
+   { .uname  = "L1_1G_TLB_HIT",
+     .udesc  = "L1 1G TLB hit",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_ineffective_sw_prefetches[]={
+   { .uname  = "SW_PREFETCH_HIT_IN_L1",
+     .udesc  = "Software prefetch hit in the L1.",
+     .ucode = 0x1,
+   },
+   { .uname  = "SW_PREFETCH_HIT_IN_L2",
+     .udesc  = "Software prefetch hit in L2.",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x9,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_memory_requests[]={
+   { .uname  = "NON_CACHEABLE",
+     .udesc  = "Requests to non-cacheable (UC) memory",
+     .ucode = 0x1,
+   },
+   { .uname  = "WRITE_COMBINING",
+     .udesc  = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory",
+     .ucode = 0x2,
+   },
+   { .uname  = "STREAMING_STORE",
+     .udesc  = "Streaming store (SS) requests",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x83,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_data_prefetches[]={
+   { .uname  = "CANCELLED",
+     .udesc  = "Cancelled prefetches",
+     .ucode = 0x1,
+   },
+   { .uname  = "ATTEMPTED",
+     .udesc  = "Prefetch attempts",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_mab_requests[]={
+   { .uname  = "BUFFER_0",
+     .udesc  = "Buffer 0",
+     .ucode = 0x0,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "BUFFER_1",
+     .udesc  = "Buffer 1",
+     .ucode = 0x1,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "BUFFER_2",
+     .udesc  = "Buffer 2",
+     .ucode = 0x2,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "BUFFER_3",
+     .udesc  = "Buffer 3",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "BUFFER_4",
+     .udesc  = "Buffer 4",
+     .ucode = 0x4,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "BUFFER_5",
+     .udesc  = "Buffer 5",
+     .ucode = 0x5,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "BUFFER_6",
+     .udesc  = "Buffer 6",
+     .ucode = 0x6,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "BUFFER_7",
+     .udesc  = "Buffer 7",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "BUFFER_8",
+     .udesc  = "Buffer 8",
+     .ucode = 0x8,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "BUFFER_9",
+     .udesc  = "Buffer 9",
+     .ucode = 0x9,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_system_read_responses[]={
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x1,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified",
+     .ucode = 0x2,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x8,
+   },
+   { .uname  = "DATA_ERROR",
+     .udesc  = "Data Error",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_quadwords_written_to_system[]={
+   { .uname  = "QUADWORD_WRITE_TRANSFER",
+     .udesc  = "Octword write transfer",
+     .ucode = 0x1,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_requests_to_l2[]={
+   { .uname  = "INSTRUCTIONS",
+     .udesc  = "IC fill",
+     .ucode = 0x1,
+   },
+   { .uname  = "DATA",
+     .udesc  = "DC fill",
+     .ucode = 0x2,
+   },
+   { .uname  = "TLB_WALK",
+     .udesc  = "TLB fill (page table walks)",
+     .ucode = 0x4,
+   },
+   { .uname  = "SNOOP",
+     .udesc  = "Tag snoop request",
+     .ucode = 0x8,
+   },
+   { .uname  = "CANCELLED",
+     .udesc  = "Cancelled request",
+     .ucode = 0x10,
+   },
+   { .uname  = "HW_PREFETCH_FROM_DC",
+     .udesc  = "Hardware prefetch from DC",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_l2_cache_miss[]={
+   { .uname  = "INSTRUCTIONS",
+     .udesc  = "IC fill",
+     .ucode = 0x1,
+   },
+   { .uname  = "DATA",
+     .udesc  = "DC fill (includes possible replays, whereas EventSelect 041h does not)",
+     .ucode = 0x2,
+   },
+   { .uname  = "TLB_WALK",
+     .udesc  = "TLB page table walk",
+     .ucode = 0x4,
+   },
+   { .uname  = "HW_PREFETCH_FROM_DC",
+     .udesc  = "Hardware prefetch from DC",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_l2_fill_writeback[]={
+   { .uname  = "L2_FILLS",
+     .udesc  = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)",
+     .ucode = 0x1,
+   },
+   { .uname  = "L2_WRITEBACKS",
+     .udesc  = "L2 Writebacks to system.",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_l1_itlb_miss_and_l2_itlb_miss[]={
+   { .uname  = "4K_PAGE_FETCHES",
+     .udesc  = "Instruction fetches to a 4K page.",
+     .ucode = 0x1,
+   },
+   { .uname  = "2M_PAGE_FETCHES",
+     .udesc  = "Instruction fetches to a 2M page.",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_instruction_cache_lines_invalidated[]={
+   { .uname  = "INVALIDATING_PROBE_NO_IN_FLIGHT",
+     .udesc  = "Invalidating probe that did not hit any in-flight instructions.",
+     .ucode = 0x1,
+   },
+   { .uname  = "INVALIDATING_PROBE_ONE_OR_MORE_IN_FLIGHT",
+     .udesc  = "Invalidating probe that hit one or more in-flight instructions.",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_retired_mmx_and_fp_instructions[]={
+   { .uname  = "X87",
+     .udesc  = "X87 instructions",
+     .ucode = 0x1,
+   },
+   { .uname  = "MMX_AND_3DNOW",
+     .udesc  = "MMX and 3DNow! instructions",
+     .ucode = 0x2,
+   },
+   { .uname  = "PACKED_SSE_AND_SSE2",
+     .udesc  = "SSE instructions (SSE, SSE2, SSE3, and SSE4A)",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_retired_fastpath_double_op_instructions[]={
+   { .uname  = "POSITION_0",
+     .udesc  = "With low op in position 0",
+     .ucode = 0x1,
+   },
+   { .uname  = "POSITION_1",
+     .udesc  = "With low op in position 1",
+     .ucode = 0x2,
+   },
+   { .uname  = "POSITION_2",
+     .udesc  = "With low op in position 2",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_fpu_exceptions[]={
+   { .uname  = "X87_RECLASS_MICROFAULTS",
+     .udesc  = "X87 reclass microfaults",
+     .ucode = 0x1,
+   },
+   { .uname  = "SSE_RETYPE_MICROFAULTS",
+     .udesc  = "SSE retype microfaults",
+     .ucode = 0x2,
+   },
+   { .uname  = "SSE_RECLASS_MICROFAULTS",
+     .udesc  = "SSE reclass microfaults",
+     .ucode = 0x4,
+   },
+   { .uname  = "SSE_AND_X87_MICROTRAPS",
+     .udesc  = "SSE and x87 microtraps",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_dram_accesses_page[]={
+   { .uname  = "HIT",
+     .udesc  = "DCT0 Page hit",
+     .ucode = 0x1,
+   },
+   { .uname  = "MISS",
+     .udesc  = "DCT0 Page Miss",
+     .ucode = 0x2,
+   },
+   { .uname  = "CONFLICT",
+     .udesc  = "DCT0 Page Conflict",
+     .ucode = 0x4,
+   },
+   { .uname  = "DCT1_PAGE_HIT",
+     .udesc  = "DCT1 Page hit",
+     .ucode = 0x8,
+   },
+   { .uname  = "DCT1_PAGE_MISS",
+     .udesc  = "DCT1 Page Miss",
+     .ucode = 0x10,
+   },
+   { .uname  = "DCT1_PAGE_CONFLICT",
+     .udesc  = "DCT1 Page Conflict",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_memory_controller_page_table_overflows[]={
+   { .uname  = "DCT0_PAGE_TABLE_OVERFLOW",
+     .udesc  = "DCT0 Page Table Overflow",
+     .ucode = 0x1,
+   },
+   { .uname  = "DCT1_PAGE_TABLE_OVERFLOW",
+     .udesc  = "DCT1 Page Table Overflow",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_memory_controller_slot_misses[]={
+   { .uname  = "DCT0_COMMAND_SLOTS_MISSED",
+     .udesc  = "DCT0 Command Slots Missed",
+     .ucode = 0x1,
+   },
+   { .uname  = "DCT1_COMMAND_SLOTS_MISSED",
+     .udesc  = "DCT1 Command Slots Missed",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_memory_controller_turnarounds[]={
+   { .uname  = "CHIP_SELECT",
+     .udesc  = "DCT0 DIMM (chip select) turnaround",
+     .ucode = 0x1,
+   },
+   { .uname  = "READ_TO_WRITE",
+     .udesc  = "DCT0 Read to write turnaround",
+     .ucode = 0x2,
+   },
+   { .uname  = "WRITE_TO_READ",
+     .udesc  = "DCT0 Write to read turnaround",
+     .ucode = 0x4,
+   },
+   { .uname  = "DCT1_DIMM",
+     .udesc  = "DCT1 DIMM (chip select) turnaround",
+     .ucode = 0x8,
+   },
+   { .uname  = "DCT1_READ_TO_WRITE_TURNAROUND",
+     .udesc  = "DCT1 Read to write turnaround",
+     .ucode = 0x10,
+   },
+   { .uname  = "DCT1_WRITE_TO_READ_TURNAROUND",
+     .udesc  = "DCT1 Write to read turnaround",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_memory_controller_bypass[]={
+   { .uname  = "HIGH_PRIORITY",
+     .udesc  = "Memory controller high priority bypass",
+     .ucode = 0x1,
+   },
+   { .uname  = "LOW_PRIORITY",
+     .udesc  = "Memory controller medium priority bypass",
+     .ucode = 0x2,
+   },
+   { .uname  = "DRAM_INTERFACE",
+     .udesc  = "DCT0 DCQ bypass",
+     .ucode = 0x4,
+   },
+   { .uname  = "DRAM_QUEUE",
+     .udesc  = "DCT1 DCQ bypass",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_thermal_status_and_ecc_errors[]={
+   { .uname  = "CLKS_DIE_TEMP_TOO_HIGH",
+     .udesc  = "Number of times the HTC trip point is crossed",
+     .ucode = 0x4,
+   },
+   { .uname  = "CLKS_TEMP_THRESHOLD_EXCEEDED",
+     .udesc  = "Number of clocks when STC trip point active",
+     .ucode = 0x8,
+   },
+   { .uname  = "STC_TRIP_POINTS_CROSSED",
+     .udesc  = "Number of times the STC trip point is crossed",
+     .ucode = 0x10,
+   },
+   { .uname  = "CLOCKS_HTC_P_STATE_INACTIVE",
+     .udesc  = "Number of clocks HTC P-state is inactive.",
+     .ucode = 0x20,
+   },
+   { .uname  = "CLOCKS_HTC_P_STATE_ACTIVE",
+     .udesc  = "Number of clocks HTC P-state is active",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7c,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_cpu_io_requests_to_memory_io[]={
+   { .uname  = "I_O_TO_I_O",
+     .udesc  = "IO to IO",
+     .ucode = 0x1,
+   },
+   { .uname  = "I_O_TO_MEM",
+     .udesc  = "IO to Mem",
+     .ucode = 0x2,
+   },
+   { .uname  = "CPU_TO_I_O",
+     .udesc  = "CPU to IO",
+     .ucode = 0x4,
+   },
+   { .uname  = "CPU_TO_MEM",
+     .udesc  = "CPU to Mem",
+     .ucode = 0x8,
+   },
+   { .uname  = "TO_REMOTE_NODE",
+     .udesc  = "To remote node",
+     .ucode = 0x10,
+   },
+   { .uname  = "TO_LOCAL_NODE",
+     .udesc  = "To local node",
+     .ucode = 0x20,
+   },
+   { .uname  = "FROM_REMOTE_NODE",
+     .udesc  = "From remote node",
+     .ucode = 0x40,
+   },
+   { .uname  = "FROM_LOCAL_NODE",
+     .udesc  = "From local node",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_cache_block[]={
+   { .uname  = "VICTIM_WRITEBACK",
+     .udesc  = "Victim Block (Writeback)",
+     .ucode = 0x1,
+   },
+   { .uname  = "DCACHE_LOAD_MISS",
+     .udesc  = "Read Block (Dcache load miss refill)",
+     .ucode = 0x4,
+   },
+   { .uname  = "SHARED_ICACHE_REFILL",
+     .udesc  = "Read Block Shared (Icache refill)",
+     .ucode = 0x8,
+   },
+   { .uname  = "READ_BLOCK_MODIFIED",
+     .udesc  = "Read Block Modified (Dcache store miss refill)",
+     .ucode = 0x10,
+   },
+   { .uname  = "READ_TO_DIRTY",
+     .udesc  = "Change-to-Dirty (first store to clean block already in cache)",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3d,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_sized_commands[]={
+   { .uname  = "NON_POSTED_WRITE_BYTE",
+     .udesc  = "Non-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytes",
+     .ucode = 0x1,
+   },
+   { .uname  = "NON_POSTED_WRITE_DWORD",
+     .udesc  = "Non-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORD",
+     .ucode = 0x2,
+   },
+   { .uname  = "POSTED_WRITE_BYTE",
+     .udesc  = "Posted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer",
+     .ucode = 0x4,
+   },
+   { .uname  = "POSTED_WRITE_DWORD",
+     .udesc  = "Posted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes",
+     .ucode = 0x8,
+   },
+   { .uname  = "READ_BYTE_4_BYTES",
+     .udesc  = "SzRd Byte (4 bytes) Legacy or mapped IO",
+     .ucode = 0x10,
+   },
+   { .uname  = "READ_DWORD_1_16_DWORDS",
+     .udesc  = "SzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_probe[]={
+   { .uname  = "MISS",
+     .udesc  = "Probe miss",
+     .ucode = 0x1,
+   },
+   { .uname  = "HIT_CLEAN",
+     .udesc  = "Probe hit clean",
+     .ucode = 0x2,
+   },
+   { .uname  = "HIT_DIRTY_NO_MEMORY_CANCEL",
+     .udesc  = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)",
+     .ucode = 0x4,
+   },
+   { .uname  = "HIT_DIRTY_WITH_MEMORY_CANCEL",
+     .udesc  = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)",
+     .ucode = 0x8,
+   },
+   { .uname  = "UPSTREAM_DISPLAY_REFRESH_READS",
+     .udesc  = "Upstream display refresh/ISOC reads",
+     .ucode = 0x10,
+   },
+   { .uname  = "UPSTREAM_NON_DISPLAY_REFRESH_READS",
+     .udesc  = "Upstream non-display refresh reads",
+     .ucode = 0x20,
+   },
+   { .uname  = "UPSTREAM_WRITES",
+     .udesc  = "Upstream ISOC writes",
+     .ucode = 0x40,
+   },
+   { .uname  = "UPSTREAM_NON_ISOC_WRITES",
+     .udesc  = "Upstream non-ISOC writes",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_gart[]={
+   { .uname  = "APERTURE_HIT_FROM_CPU",
+     .udesc  = "GART aperture hit on access from CPU",
+     .ucode = 0x1,
+   },
+   { .uname  = "APERTURE_HIT_FROM_IO",
+     .udesc  = "GART aperture hit on access from IO",
+     .ucode = 0x2,
+   },
+   { .uname  = "MISS",
+     .udesc  = "GART miss",
+     .ucode = 0x4,
+   },
+   { .uname  = "REQUEST_HIT_TABLE_WALK",
+     .udesc  = "GART/DEV Request hit table walk in progress",
+     .ucode = 0x8,
+   },
+   { .uname  = "DEV_HIT",
+     .udesc  = "DEV hit",
+     .ucode = 0x10,
+   },
+   { .uname  = "DEV_MISS",
+     .udesc  = "DEV miss",
+     .ucode = 0x20,
+   },
+   { .uname  = "DEV_ERROR",
+     .udesc  = "DEV error",
+     .ucode = 0x40,
+   },
+   { .uname  = "MULTIPLE_TABLE_WALK",
+     .udesc  = "GART/DEV multiple table walk in progress",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_memory_controller_requests[]={
+   { .uname  = "WRITE_REQUESTS",
+     .udesc  = "Write requests sent to the DCT",
+     .ucode = 0x1,
+   },
+   { .uname  = "READ_REQUESTS",
+     .udesc  = "Read requests (including prefetch requests) sent to the DCT",
+     .ucode = 0x2,
+   },
+   { .uname  = "PREFETCH_REQUESTS",
+     .udesc  = "Prefetch requests sent to the DCT",
+     .ucode = 0x4,
+   },
+   { .uname  = "32_BYTES_WRITES",
+     .udesc  = "32 Bytes Sized Writes",
+     .ucode = 0x8,
+   },
+   { .uname  = "64_BYTES_WRITES",
+     .udesc  = "64 Bytes Sized Writes",
+     .ucode = 0x10,
+   },
+   { .uname  = "32_BYTES_READS",
+     .udesc  = "32 Bytes Sized Reads",
+     .ucode = 0x20,
+   },
+   { .uname  = "64_BYTES_READS",
+     .udesc  = "64 Byte Sized Reads",
+     .ucode = 0x40,
+   },
+   { .uname  = "READ_REQUESTS_WHILE_WRITES_REQUESTS",
+     .udesc  = "Read requests sent to the DCT while writes requests are pending in the DCT",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_cpu_to_dram_requests_to_target_node[]={
+   { .uname  = "LOCAL_TO_0",
+     .udesc  = "From Local node to Node 0",
+     .ucode = 0x1,
+   },
+   { .uname  = "LOCAL_TO_1",
+     .udesc  = "From Local node to Node 1",
+     .ucode = 0x2,
+   },
+   { .uname  = "LOCAL_TO_2",
+     .udesc  = "From Local node to Node 2",
+     .ucode = 0x4,
+   },
+   { .uname  = "LOCAL_TO_3",
+     .udesc  = "From Local node to Node 3",
+     .ucode = 0x8,
+   },
+   { .uname  = "LOCAL_TO_4",
+     .udesc  = "From Local node to Node 4",
+     .ucode = 0x10,
+   },
+   { .uname  = "LOCAL_TO_5",
+     .udesc  = "From Local node to Node 5",
+     .ucode = 0x20,
+   },
+   { .uname  = "LOCAL_TO_6",
+     .udesc  = "From Local node to Node 6",
+     .ucode = 0x40,
+   },
+   { .uname  = "LOCAL_TO_7",
+     .udesc  = "From Local node to Node 7",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_cpu_read_command_latency_to_target_node_0_3[]={
+   { .uname  = "READ_BLOCK",
+     .udesc  = "Read block",
+     .ucode = 0x1,
+   },
+   { .uname  = "READ_BLOCK_SHARED",
+     .udesc  = "Read block shared",
+     .ucode = 0x2,
+   },
+   { .uname  = "READ_BLOCK_MODIFIED",
+     .udesc  = "Read block modified",
+     .ucode = 0x4,
+   },
+   { .uname  = "CHANGE_TO_DIRTY",
+     .udesc  = "Change-to-Dirty",
+     .ucode = 0x8,
+   },
+   { .uname  = "LOCAL_TO_0",
+     .udesc  = "From Local node to Node 0",
+     .ucode = 0x10,
+   },
+   { .uname  = "LOCAL_TO_1",
+     .udesc  = "From Local node to Node 1",
+     .ucode = 0x20,
+   },
+   { .uname  = "LOCAL_TO_2",
+     .udesc  = "From Local node to Node 2",
+     .ucode = 0x40,
+   },
+   { .uname  = "LOCAL_TO_3",
+     .udesc  = "From Local node to Node 3",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_cpu_read_command_latency_to_target_node_4_7[]={
+   { .uname  = "READ_BLOCK",
+     .udesc  = "Read block",
+     .ucode = 0x1,
+   },
+   { .uname  = "READ_BLOCK_SHARED",
+     .udesc  = "Read block shared",
+     .ucode = 0x2,
+   },
+   { .uname  = "READ_BLOCK_MODIFIED",
+     .udesc  = "Read block modified",
+     .ucode = 0x4,
+   },
+   { .uname  = "CHANGE_TO_DIRTY",
+     .udesc  = "Change-to-Dirty",
+     .ucode = 0x8,
+   },
+   { .uname  = "LOCAL_TO_4",
+     .udesc  = "From Local node to Node 4",
+     .ucode = 0x10,
+   },
+   { .uname  = "LOCAL_TO_5",
+     .udesc  = "From Local node to Node 5",
+     .ucode = 0x20,
+   },
+   { .uname  = "LOCAL_TO_6",
+     .udesc  = "From Local node to Node 6",
+     .ucode = 0x40,
+   },
+   { .uname  = "LOCAL_TO_7",
+     .udesc  = "From Local node to Node 7",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_cpu_command_latency_to_target_node_0_3_4_7[]={
+   { .uname  = "READ_SIZED",
+     .udesc  = "Read Sized",
+     .ucode = 0x1,
+   },
+   { .uname  = "WRITE_SIZED",
+     .udesc  = "Write Sized",
+     .ucode = 0x2,
+   },
+   { .uname  = "VICTIM_BLOCK",
+     .udesc  = "Victim Block",
+     .ucode = 0x4,
+   },
+   { .uname  = "NODE_GROUP_SELECT",
+     .udesc  = "Node Group Select. 0=Nodes 0-3. 1= Nodes 4-7.",
+     .ucode = 0x8,
+   },
+   { .uname  = "LOCAL_TO_0_4",
+     .udesc  = "From Local node to Node 0/4",
+     .ucode = 0x10,
+   },
+   { .uname  = "LOCAL_TO_1_5",
+     .udesc  = "From Local node to Node 1/5",
+     .ucode = 0x20,
+   },
+   { .uname  = "LOCAL_TO_2_6",
+     .udesc  = "From Local node to Node 2/6",
+     .ucode = 0x40,
+   },
+   { .uname  = "LOCAL_TO_3_7",
+     .udesc  = "From Local node to Node 3/7",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_hypertransport_link0[]={
+   { .uname  = "COMMAND_DWORD_SENT",
+     .udesc  = "Command DWORD sent",
+     .ucode = 0x1,
+     .grpid = 0,
+   },
+   { .uname  = "DATA_DWORD_SENT",
+     .udesc  = "Data DWORD sent",
+     .ucode = 0x2,
+     .grpid = 0,
+   },
+   { .uname  = "BUFFER_RELEASE_DWORD_SENT",
+     .udesc  = "Buffer release DWORD sent",
+     .ucode = 0x4,
+     .grpid = 0,
+   },
+   { .uname  = "NOP_DWORD_SENT",
+     .udesc  = "Nop DW sent (idle)",
+     .ucode = 0x8,
+     .grpid = 0,
+   },
+   { .uname  = "ADDRESS_EXT_DWORD_SENT",
+     .udesc  = "Address extension DWORD sent",
+     .ucode = 0x10,
+     .grpid = 0,
+   },
+   { .uname  = "PER_PACKET_CRC_SENT",
+     .udesc  = "Per packet CRC sent",
+     .ucode = 0x20,
+     .grpid = 0,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+     .grpid = 0,
+   },
+   { .uname  = "SUBLINK_MASK",
+     .udesc  = "SubLink Mask",
+     .ucode = 0x80,
+     .uflags= AMD64_FL_OMIT,
+     .grpid = 1,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_hypertransport_link3[]={
+   { .uname  = "COMMAND_DWORD_SENT",
+     .udesc  = "Command DWORD sent",
+     .ucode = 0x1,
+     .grpid = 0,
+   },
+   { .uname  = "DATA_DWORD_SENT",
+     .udesc  = "Data DWORD sent",
+     .ucode = 0x2,
+     .grpid = 0,
+   },
+   { .uname  = "BUFFER_RELEASE_DWORD_SENT",
+     .udesc  = "Buffer release DWORD sent",
+     .ucode = 0x4,
+     .grpid = 0,
+   },
+   { .uname  = "NOP_DWORD_SENT",
+     .udesc  = "Nop DW sent (idle)",
+     .ucode = 0x8,
+     .grpid = 0,
+   },
+   { .uname  = "ADDRESS_EXT_DWORD_SENT",
+     .udesc  = "Address DWORD sent",
+     .ucode = 0x10,
+     .grpid = 0,
+   },
+   { .uname  = "PER_PACKET_CRC_SENT",
+     .udesc  = "Per packet CRC sent",
+     .ucode = 0x20,
+     .grpid = 0,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+     .grpid = 0,
+   },
+   { .uname  = "SUBLINK_MASK",
+     .udesc  = "SubLink Mask",
+     .ucode = 0x80,
+     .uflags= AMD64_FL_OMIT,
+     .grpid = 1,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_read_request_to_l3_cache[]={
+   { .uname  = "READ_BLOCK_EXCLUSIVE",
+     .udesc  = "Read Block Exclusive (Data cache read)",
+     .ucode = 0x1,
+     .grpid = 0,
+   },
+   { .uname  = "READ_BLOCK_SHARED",
+     .udesc  = "Read Block Shared (Instruction cache read)",
+     .ucode = 0x2,
+     .grpid = 0,
+   },
+   { .uname  = "READ_BLOCK_MODIFY",
+     .udesc  = "Read Block Modify",
+     .ucode = 0x4,
+     .grpid = 0,
+   },
+   { .uname  = "ANY_READ",
+     .udesc  = "Any read modes (exclusive, shared, modify)",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+     .grpid = 0,
+   },
+   { .uname  = "ALL_CORES",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf0,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+     .grpid = 1,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_l3_cache_misses[]={
+   { .uname  = "READ_BLOCK_EXCLUSIVE",
+     .udesc  = "Read Block Exclusive (Data cache read)",
+     .ucode = 0x1,
+     .grpid = 0,
+   },
+   { .uname  = "READ_BLOCK_SHARED",
+     .udesc  = "Read Block Shared (Instruction cache read)",
+     .ucode = 0x2,
+     .grpid = 0,
+   },
+   { .uname  = "READ_BLOCK_MODIFY",
+     .udesc  = "Read Block Modify",
+     .ucode = 0x4,
+     .grpid = 0,
+   },
+   { .uname  = "ANY_READ",
+     .udesc  = "Any read modes (exclusive, shared, modify)",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+     .grpid = 0,
+   },
+   { .uname  = "ALL_CORES",
+     .udesc  = "All cores",
+     .ucode = 0xf0,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+     .grpid = 1,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_l3_fills_caused_by_l2_evictions[]={
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x1,
+     .grpid = 0,
+   },
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x2,
+     .grpid = 0,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x4,
+     .grpid = 0,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified",
+     .ucode = 0x8,
+     .grpid = 0,
+   },
+   { .uname  = "ANY_STATE",
+     .udesc  = "Any line state (shared, owned, exclusive, modified)",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+     .grpid = 0,
+   },
+   { .uname  = "ALL_CORES",
+     .udesc  = "All cores",
+     .ucode = 0xf0,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+     .grpid = 1,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_l3_evictions[]={
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x1,
+   },
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x2,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x4,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_page_size_mismatches[]={
+   { .uname  = "GUEST_LARGER",
+     .udesc  = "Guest page size is larger than the host page size.",
+     .ucode = 0x1,
+   },
+   { .uname  = "MTRR_MISMATCH",
+     .udesc  = "MTRR mismatch.",
+     .ucode = 0x2,
+   },
+   { .uname  = "HOST_LARGER",
+     .udesc  = "Host page size is larger than the guest page size.",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam10h_retired_x87_ops[]={
+   { .uname  = "ADD_SUB_OPS",
+     .udesc  = "Add/subtract ops",
+     .ucode = 0x1,
+   },
+   { .uname  = "MUL_OPS",
+     .udesc  = "Multiply ops",
+     .ucode = 0x2,
+   },
+   { .uname  = "DIV_OPS",
+     .udesc  = "Divide ops",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_entry_t amd64_fam10h_pe[]={
+{ .name    = "DISPATCHED_FPU",
+  .desc    = "Dispatched FPU Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_dispatched_fpu),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_dispatched_fpu,
+},
+{ .name    = "CYCLES_NO_FPU_OPS_RETIRED",
+  .desc    = "Cycles in which the FPU is Empty",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1,
+},
+{ .name    = "DISPATCHED_FPU_OPS_FAST_FLAG",
+  .desc    = "Dispatched Fast Flag FPU Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x2,
+},
+{ .name    = "RETIRED_SSE_OPERATIONS",
+  .desc    = "Retired SSE Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x3,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_retired_sse_operations),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_retired_sse_operations,
+},
+{ .name    = "RETIRED_MOVE_OPS",
+  .desc    = "Retired Move Ops",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_retired_move_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_retired_move_ops,
+},
+{ .name    = "RETIRED_SERIALIZING_OPS",
+  .desc    = "Retired Serializing Ops",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x5,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_retired_serializing_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_retired_serializing_ops,
+},
+{ .name    = "FP_SCHEDULER_CYCLES",
+  .desc    = "Number of Cycles that a Serializing uop is in the FP Scheduler",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x6,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_fp_scheduler_cycles),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_fp_scheduler_cycles,
+},
+{ .name    = "SEGMENT_REGISTER_LOADS",
+  .desc    = "Segment Register Loads",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x20,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_segment_register_loads),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_segment_register_loads,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE",
+  .desc    = "Pipeline Restart Due to Self-Modifying Code",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x21,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_PROBE_HIT",
+  .desc    = "Pipeline Restart Due to Probe Hit",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x22,
+},
+{ .name    = "LS_BUFFER_2_FULL_CYCLES",
+  .desc    = "LS Buffer 2 Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x23,
+},
+{ .name    = "LOCKED_OPS",
+  .desc    = "Locked Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x24,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_locked_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_locked_ops,
+},
+{ .name    = "RETIRED_CLFLUSH_INSTRUCTIONS",
+  .desc    = "Retired CLFLUSH Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x26,
+},
+{ .name    = "RETIRED_CPUID_INSTRUCTIONS",
+  .desc    = "Retired CPUID Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x27,
+},
+{ .name    = "CANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONS",
+  .desc    = "Cancelled Store to Load Forward Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x2a,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cancelled_store_to_load_forward_operations),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_cancelled_store_to_load_forward_operations,
+},
+{ .name    = "SMIS_RECEIVED",
+  .desc    = "SMIs Received",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x2b,
+},
+{ .name    = "DATA_CACHE_ACCESSES",
+  .desc    = "Data Cache Accesses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x40,
+},
+{ .name    = "DATA_CACHE_MISSES",
+  .desc    = "Data Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x41,
+},
+{ .name    = "DATA_CACHE_REFILLS",
+  .desc    = "Data Cache Refills from L2 or Northbridge",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x42,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_data_cache_refills),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_data_cache_refills,
+},
+{ .name    = "DATA_CACHE_REFILLS_FROM_SYSTEM",
+  .desc    = "Data Cache Refills from the Northbridge",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x43,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_data_cache_refills_from_system),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_data_cache_refills_from_system,
+},
+{ .name    = "DATA_CACHE_LINES_EVICTED",
+  .desc    = "Data Cache Lines Evicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x44,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_data_cache_lines_evicted),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_data_cache_lines_evicted,
+},
+{ .name    = "L1_DTLB_MISS_AND_L2_DTLB_HIT",
+  .desc    = "L1 DTLB Miss and L2 DTLB Hit",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x45,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l1_dtlb_miss_and_l2_dtlb_hit),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_l1_dtlb_miss_and_l2_dtlb_hit,
+},
+{ .name    = "L1_DTLB_AND_L2_DTLB_MISS",
+  .desc    = "L1 DTLB and L2 DTLB Miss",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x46,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l1_dtlb_and_l2_dtlb_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_l1_dtlb_and_l2_dtlb_miss,
+},
+{ .name    = "MISALIGNED_ACCESSES",
+  .desc    = "Misaligned Accesses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x47,
+},
+{ .name    = "MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS",
+  .desc    = "Microarchitectural Late Cancel of an Access",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x48,
+},
+{ .name    = "MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS",
+  .desc    = "Microarchitectural Early Cancel of an Access",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x49,
+},
+{ .name    = "SCRUBBER_SINGLE_BIT_ECC_ERRORS",
+  .desc    = "Single-bit ECC Errors Recorded by Scrubber",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4a,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_scrubber_single_bit_ecc_errors),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_scrubber_single_bit_ecc_errors,
+},
+{ .name    = "PREFETCH_INSTRUCTIONS_DISPATCHED",
+  .desc    = "Prefetch Instructions Dispatched",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4b,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_prefetch_instructions_dispatched),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_prefetch_instructions_dispatched,
+},
+{ .name    = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS",
+  .desc    = "DCACHE Misses by Locked Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4c,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_dcache_misses_by_locked_instructions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_dcache_misses_by_locked_instructions,
+},
+{ .name    = "L1_DTLB_HIT",
+  .desc    = "L1 DTLB Hit",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4d,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l1_dtlb_hit),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_l1_dtlb_hit,
+},
+{ .name    = "INEFFECTIVE_SW_PREFETCHES",
+  .desc    = "Ineffective Software Prefetches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x52,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_ineffective_sw_prefetches),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_ineffective_sw_prefetches,
+},
+{ .name    = "GLOBAL_TLB_FLUSHES",
+  .desc    = "Global TLB Flushes",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x54,
+},
+{ .name    = "MEMORY_REQUESTS",
+  .desc    = "Memory Requests by Type",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x65,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_memory_requests),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_memory_requests,
+},
+{ .name    = "DATA_PREFETCHES",
+  .desc    = "Data Prefetcher",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x67,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_data_prefetches),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_data_prefetches,
+},
+{ .name    = "MAB_REQUESTS",
+  .desc    = "Average L1 refill latency for Icache and Dcache misses (request count for cache refills)",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x68,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_mab_requests),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_mab_requests,
+},
+{ .name    = "MAB_WAIT_CYCLES",
+  .desc    = "Average L1 refill latency for Icache and Dcache misses (cycles that requests spent waiting for the refills)",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x69,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_mab_requests),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_mab_requests, /* identical to actual umasks list for this event */
+},
+{ .name    = "SYSTEM_READ_RESPONSES",
+  .desc    = "Northbridge Read Responses by Coherency State",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x6c,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_system_read_responses),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_system_read_responses,
+},
+{ .name    = "QUADWORDS_WRITTEN_TO_SYSTEM",
+  .desc    = "Octwords Written to System",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x6d,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_quadwords_written_to_system),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_quadwords_written_to_system,
+},
+{ .name    = "CPU_CLK_UNHALTED",
+  .desc    = "CPU Clocks not Halted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x76,
+},
+{ .name    = "REQUESTS_TO_L2",
+  .desc    = "Requests to L2 Cache",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x7d,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_requests_to_l2),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_requests_to_l2,
+},
+{ .name    = "L2_CACHE_MISS",
+  .desc    = "L2 Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x7e,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l2_cache_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_l2_cache_miss,
+},
+{ .name    = "L2_FILL_WRITEBACK",
+  .desc    = "L2 Fill/Writeback",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x7f,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l2_fill_writeback),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_l2_fill_writeback,
+},
+{ .name    = "INSTRUCTION_CACHE_FETCHES",
+  .desc    = "Instruction Cache Fetches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x80,
+},
+{ .name    = "INSTRUCTION_CACHE_MISSES",
+  .desc    = "Instruction Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x81,
+},
+{ .name    = "INSTRUCTION_CACHE_REFILLS_FROM_L2",
+  .desc    = "Instruction Cache Refills from L2",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x82,
+},
+{ .name    = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM",
+  .desc    = "Instruction Cache Refills from System",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x83,
+},
+{ .name    = "L1_ITLB_MISS_AND_L2_ITLB_HIT",
+  .desc    = "L1 ITLB Miss and L2 ITLB Hit",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x84,
+},
+{ .name    = "L1_ITLB_MISS_AND_L2_ITLB_MISS",
+  .desc    = "L1 ITLB Miss and L2 ITLB Miss",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x85,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l1_itlb_miss_and_l2_itlb_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_l1_itlb_miss_and_l2_itlb_miss,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE",
+  .desc    = "Pipeline Restart Due to Instruction Stream Probe",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x86,
+},
+{ .name    = "INSTRUCTION_FETCH_STALL",
+  .desc    = "Instruction Fetch Stall",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x87,
+},
+{ .name    = "RETURN_STACK_HITS",
+  .desc    = "Return Stack Hits",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x88,
+},
+{ .name    = "RETURN_STACK_OVERFLOWS",
+  .desc    = "Return Stack Overflows",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x89,
+},
+{ .name    = "INSTRUCTION_CACHE_VICTIMS",
+  .desc    = "Instruction Cache Victims",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x8b,
+},
+{ .name    = "INSTRUCTION_CACHE_LINES_INVALIDATED",
+  .desc    = "Instruction Cache Lines Invalidated",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x8c,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_instruction_cache_lines_invalidated),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_instruction_cache_lines_invalidated,
+},
+{ .name    = "ITLB_RELOADS",
+  .desc    = "ITLB Reloads",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x99,
+},
+{ .name    = "ITLB_RELOADS_ABORTED",
+  .desc    = "ITLB Reloads Aborted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x9a,
+},
+{ .name    = "RETIRED_INSTRUCTIONS",
+  .desc    = "Retired Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc0,
+},
+{ .name    = "RETIRED_UOPS",
+  .desc    = "Retired uops",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc1,
+},
+{ .name    = "RETIRED_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Branch Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc2,
+},
+{ .name    = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Mispredicted Branch Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc3,
+},
+{ .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Taken Branch Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc4,
+},
+{ .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED",
+  .desc    = "Retired Taken Branch Instructions Mispredicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc5,
+},
+{ .name    = "RETIRED_FAR_CONTROL_TRANSFERS",
+  .desc    = "Retired Far Control Transfers",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc6,
+},
+{ .name    = "RETIRED_BRANCH_RESYNCS",
+  .desc    = "Retired Branch Resyncs",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc7,
+},
+{ .name    = "RETIRED_NEAR_RETURNS",
+  .desc    = "Retired Near Returns",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc8,
+},
+{ .name    = "RETIRED_NEAR_RETURNS_MISPREDICTED",
+  .desc    = "Retired Near Returns Mispredicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc9,
+},
+{ .name    = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED",
+  .desc    = "Retired Indirect Branches Mispredicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xca,
+},
+{ .name    = "RETIRED_MMX_AND_FP_INSTRUCTIONS",
+  .desc    = "Retired MMX/FP Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_retired_mmx_and_fp_instructions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_retired_mmx_and_fp_instructions,
+},
+{ .name    = "RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS",
+  .desc    = "Retired Fastpath Double Op Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcc,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_retired_fastpath_double_op_instructions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_retired_fastpath_double_op_instructions,
+},
+{ .name    = "INTERRUPTS_MASKED_CYCLES",
+  .desc    = "Interrupts-Masked Cycles",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcd,
+},
+{ .name    = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING",
+  .desc    = "Interrupts-Masked Cycles with Interrupt Pending",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xce,
+},
+{ .name    = "INTERRUPTS_TAKEN",
+  .desc    = "Interrupts Taken",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcf,
+},
+{ .name    = "DECODER_EMPTY",
+  .desc    = "Decoder Empty",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd0,
+},
+{ .name    = "DISPATCH_STALLS",
+  .desc    = "Dispatch Stalls",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd1,
+},
+{ .name    = "DISPATCH_STALL_FOR_BRANCH_ABORT",
+  .desc    = "Dispatch Stall for Branch Abort to Retire",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd2,
+},
+{ .name    = "DISPATCH_STALL_FOR_SERIALIZATION",
+  .desc    = "Dispatch Stall for Serialization",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd3,
+},
+{ .name    = "DISPATCH_STALL_FOR_SEGMENT_LOAD",
+  .desc    = "Dispatch Stall for Segment Load",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd4,
+},
+{ .name    = "DISPATCH_STALL_FOR_REORDER_BUFFER_FULL",
+  .desc    = "Dispatch Stall for Reorder Buffer Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd5,
+},
+{ .name    = "DISPATCH_STALL_FOR_RESERVATION_STATION_FULL",
+  .desc    = "Dispatch Stall for Reservation Station Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd6,
+},
+{ .name    = "DISPATCH_STALL_FOR_FPU_FULL",
+  .desc    = "Dispatch Stall for FPU Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd7,
+},
+{ .name    = "DISPATCH_STALL_FOR_LS_FULL",
+  .desc    = "Dispatch Stall for LS Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd8,
+},
+{ .name    = "DISPATCH_STALL_WAITING_FOR_ALL_QUIET",
+  .desc    = "Dispatch Stall Waiting for All Quiet",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd9,
+},
+{ .name    = "DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNC",
+  .desc    = "Dispatch Stall for Far Transfer or Resync to Retire",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xda,
+},
+{ .name    = "FPU_EXCEPTIONS",
+  .desc    = "FPU Exceptions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_fpu_exceptions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_fpu_exceptions,
+},
+{ .name    = "DR0_BREAKPOINT_MATCHES",
+  .desc    = "DR0 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdc,
+},
+{ .name    = "DR1_BREAKPOINT_MATCHES",
+  .desc    = "DR1 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdd,
+},
+{ .name    = "DR2_BREAKPOINT_MATCHES",
+  .desc    = "DR2 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xde,
+},
+{ .name    = "DR3_BREAKPOINT_MATCHES",
+  .desc    = "DR3 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdf,
+},
+{ .name    = "DRAM_ACCESSES_PAGE",
+  .desc    = "DRAM Accesses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_dram_accesses_page),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_dram_accesses_page,
+},
+{ .name    = "MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS",
+  .desc    = "DRAM Controller Page Table Overflows",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe1,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_memory_controller_page_table_overflows),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_memory_controller_page_table_overflows,
+},
+{ .name    = "MEMORY_CONTROLLER_SLOT_MISSES",
+  .desc    = "Memory Controller DRAM Command Slots Missed",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe2,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_memory_controller_slot_misses),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_memory_controller_slot_misses,
+},
+{ .name    = "MEMORY_CONTROLLER_TURNAROUNDS",
+  .desc    = "Memory Controller Turnarounds",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe3,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_memory_controller_turnarounds),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_memory_controller_turnarounds,
+},
+{ .name    = "MEMORY_CONTROLLER_BYPASS",
+  .desc    = "Memory Controller Bypass Counter Saturation",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe4,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_memory_controller_bypass),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_memory_controller_bypass,
+},
+{ .name    = "THERMAL_STATUS_AND_ECC_ERRORS",
+  .desc    = "Thermal Status",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe8,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_thermal_status_and_ecc_errors),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_thermal_status_and_ecc_errors,
+},
+{ .name    = "CPU_IO_REQUESTS_TO_MEMORY_IO",
+  .desc    = "CPU/IO Requests to Memory/IO",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe9,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_io_requests_to_memory_io),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_cpu_io_requests_to_memory_io,
+},
+{ .name    = "CACHE_BLOCK",
+  .desc    = "Cache Block Commands",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xea,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cache_block),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_cache_block,
+},
+{ .name    = "SIZED_COMMANDS",
+  .desc    = "Sized Commands",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xeb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_sized_commands),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_sized_commands,
+},
+{ .name    = "PROBE",
+  .desc    = "Probe Responses and Upstream Requests",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xec,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_probe),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_probe,
+},
+{ .name    = "GART",
+  .desc    = "GART Events",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xee,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_gart),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_gart,
+},
+{ .name    = "MEMORY_CONTROLLER_REQUESTS",
+  .desc    = "Memory Controller Requests",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1f0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_memory_controller_requests),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_memory_controller_requests,
+},
+{ .name    = "CPU_TO_DRAM_REQUESTS_TO_TARGET_NODE",
+  .desc    = "CPU to DRAM Requests to Target Node",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1e0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_to_dram_requests_to_target_node),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_cpu_to_dram_requests_to_target_node,
+},
+{ .name    = "IO_TO_DRAM_REQUESTS_TO_TARGET_NODE",
+  .desc    = "IO to DRAM Requests to Target Node",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1e1,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_to_dram_requests_to_target_node),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_cpu_to_dram_requests_to_target_node, /* identical to actual umasks list for this event */
+},
+{ .name    = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_0_3",
+  .desc    = "CPU Read Command Latency to Target Node 0-3",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1e2,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_read_command_latency_to_target_node_0_3),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_cpu_read_command_latency_to_target_node_0_3,
+},
+{ .name    = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_0_3",
+  .desc    = "CPU Read Command Requests to Target Node 0-3",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1e3,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_read_command_latency_to_target_node_0_3),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_cpu_read_command_latency_to_target_node_0_3, /* identical to actual umasks list for this event */
+},
+{ .name    = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_4_7",
+  .desc    = "CPU Read Command Latency to Target Node 4-7",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1e4,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_read_command_latency_to_target_node_4_7),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_cpu_read_command_latency_to_target_node_4_7,
+},
+{ .name    = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_4_7",
+  .desc    = "CPU Read Command Requests to Target Node 4-7",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1e5,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_read_command_latency_to_target_node_4_7),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_cpu_read_command_latency_to_target_node_4_7, /* identical to actual umasks list for this event */
+},
+{ .name    = "CPU_COMMAND_LATENCY_TO_TARGET_NODE_0_3_4_7",
+  .desc    = "CPU Command Latency to Target Node 0-3/4-7",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1e6,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_command_latency_to_target_node_0_3_4_7),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_cpu_command_latency_to_target_node_0_3_4_7,
+},
+{ .name    = "CPU_REQUESTS_TO_TARGET_NODE_0_3_4_7",
+  .desc    = "CPU Requests to Target Node 0-3/4-7",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1e7,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_cpu_command_latency_to_target_node_0_3_4_7),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_cpu_command_latency_to_target_node_0_3_4_7, /* identical to actual umasks list for this event */
+},
+{ .name    = "HYPERTRANSPORT_LINK0",
+  .desc    = "HyperTransport Link 0 Transmit Bandwidth",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xf6,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_hypertransport_link0),
+  .ngrp    = 2,
+  .umasks  = amd64_fam10h_hypertransport_link0,
+},
+{ .name    = "HYPERTRANSPORT_LINK1",
+  .desc    = "HyperTransport Link 1 Transmit Bandwidth",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xf7,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_hypertransport_link0),
+  .ngrp    = 2,
+  .umasks  = amd64_fam10h_hypertransport_link0, /* identical to actual umasks list for this event */
+},
+{ .name    = "HYPERTRANSPORT_LINK2",
+  .desc    = "HyperTransport Link 2 Transmit Bandwidth",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xf8,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_hypertransport_link0),
+  .ngrp    = 2,
+  .umasks  = amd64_fam10h_hypertransport_link0, /* identical to actual umasks list for this event */
+},
+{ .name    = "HYPERTRANSPORT_LINK3",
+  .desc    = "HyperTransport Link 3 Transmit Bandwidth",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1f9,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_hypertransport_link3),
+  .ngrp    = 2,
+  .umasks  = amd64_fam10h_hypertransport_link3,
+},
+{ .name    = "READ_REQUEST_TO_L3_CACHE",
+  .desc    = "Read Request to L3 Cache",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4e0,
+  .flags   = AMD64_FL_TILL_FAM10H_REV_C,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_read_request_to_l3_cache),
+  .ngrp    = 2,
+  .umasks  = amd64_fam10h_read_request_to_l3_cache,
+},
+{ .name    = "L3_CACHE_MISSES",
+  .desc    = "L3 Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4e1,
+  .flags   = AMD64_FL_TILL_FAM10H_REV_C,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_cache_misses),
+  .ngrp    = 2,
+  .umasks  = amd64_fam10h_l3_cache_misses,
+},
+{ .name    = "L3_FILLS_CAUSED_BY_L2_EVICTIONS",
+  .desc    = "L3 Fills caused by L2 Evictions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4e2,
+  .flags   = AMD64_FL_TILL_FAM10H_REV_C,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_fills_caused_by_l2_evictions),
+  .ngrp    = 2,
+  .umasks  = amd64_fam10h_l3_fills_caused_by_l2_evictions,
+},
+{ .name    = "L3_EVICTIONS",
+  .desc    = "L3 Evictions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4e3,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_evictions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_l3_evictions,
+},
+{ .name    = "PAGE_SIZE_MISMATCHES",
+  .desc    = "Page Size Mismatches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x165,
+  .flags   = AMD64_FL_FAM10H_REV_C,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_page_size_mismatches),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_page_size_mismatches,
+},
+{ .name    = "RETIRED_X87_OPS",
+  .desc    = "Retired x87 Floating Point Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1c0,
+  .flags   = AMD64_FL_FAM10H_REV_C,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_retired_x87_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam10h_retired_x87_ops,
+},
+{ .name    = "IBS_OPS_TAGGED",
+  .desc    = "IBS Ops Tagged",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1cf,
+  .flags   = AMD64_FL_FAM10H_REV_C,
+},
+{ .name    = "LFENCE_INST_RETIRED",
+  .desc    = "LFENCE Instructions Retired",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1d3,
+  .flags   = AMD64_FL_FAM10H_REV_C,
+},
+{ .name    = "SFENCE_INST_RETIRED",
+  .desc    = "SFENCE Instructions Retired",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1d4,
+  .flags   = AMD64_FL_FAM10H_REV_C,
+},
+{ .name    = "MFENCE_INST_RETIRED",
+  .desc    = "MFENCE Instructions Retired",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1d5,
+  .flags   = AMD64_FL_FAM10H_REV_C,
+},
+{ .name    = "READ_REQUEST_TO_L3_CACHE",
+  .desc    = "Read Request to L3 Cache",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4e0,
+  .flags   = AMD64_FL_FAM10H_REV_D,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_cache_misses),
+  .ngrp    = 2,
+  .umasks  = amd64_fam10h_l3_cache_misses, /* identical to actual umasks list for this event */
+},
+{ .name    = "L3_CACHE_MISSES",
+  .desc    = "L3 Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4e1,
+  .flags   = AMD64_FL_FAM10H_REV_D,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_cache_misses),
+  .ngrp    = 2,
+  .umasks  = amd64_fam10h_l3_cache_misses, /* identical to actual umasks list for this event */
+},
+{ .name    = "L3_FILLS_CAUSED_BY_L2_EVICTIONS",
+  .desc    = "L3 Fills caused by L2 Evictions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4e2,
+  .flags   = AMD64_FL_FAM10H_REV_D,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_fills_caused_by_l2_evictions),
+  .ngrp    = 2,
+  .umasks  = amd64_fam10h_l3_fills_caused_by_l2_evictions, /* identical to actual umasks list for this event */
+},
+{ .name    = "NON_CANCELLED_L3_READ_REQUESTS",
+  .desc    = "Non-cancelled L3 Read Requests",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4ed,
+  .flags   = AMD64_FL_FAM10H_REV_D,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam10h_l3_cache_misses),
+  .ngrp    = 2,
+  .umasks  = amd64_fam10h_l3_cache_misses, /* identical to actual umasks list for this event */
+},
+};
diff --git a/user/perfmon/events/amd64_events_fam11h.h b/user/perfmon/events/amd64_events_fam11h.h
new file mode 100644 (file)
index 0000000..b53e7f6
--- /dev/null
@@ -0,0 +1,1403 @@
+/*
+ * Copyright (c) 2012 University of Tennessee
+ * Contributed by Vince Weaver <vweaver1@utk.edu>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * This file is part of libpfm, a performance monitoring support library for
+ * applications on Linux.
+ *
+ * PMU: amd64_fam11h (AMD64 Fam11h)
+ */
+
+static const amd64_umask_t amd64_fam11h_dispatched_fpu[]={
+   { .uname  = "OPS_ADD",
+     .udesc  = "Add pipe ops excluding load ops and SSE move ops",
+     .ucode = 0x1,
+   },
+   { .uname  = "OPS_MULTIPLY",
+     .udesc  = "Multiply pipe ops excluding load ops and SSE move ops",
+     .ucode = 0x2,
+   },
+   { .uname  = "OPS_STORE",
+     .udesc  = "Store pipe ops excluding load ops and SSE move ops",
+     .ucode = 0x4,
+   },
+   { .uname  = "OPS_ADD_PIPE_LOAD_OPS",
+     .udesc  = "Add pipe load ops and SSE move ops",
+     .ucode = 0x8,
+   },
+   { .uname  = "OPS_MULTIPLY_PIPE_LOAD_OPS",
+     .udesc  = "Multiply pipe load ops and SSE move ops",
+     .ucode = 0x10,
+   },
+   { .uname  = "OPS_STORE_PIPE_LOAD_OPS",
+     .udesc  = "Store pipe load ops and SSE move ops",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_segment_register_loads[]={
+   { .uname  = "ES",
+     .udesc  = "ES",
+     .ucode = 0x1,
+   },
+   { .uname  = "CS",
+     .udesc  = "CS",
+     .ucode = 0x2,
+   },
+   { .uname  = "SS",
+     .udesc  = "SS",
+     .ucode = 0x4,
+   },
+   { .uname  = "DS",
+     .udesc  = "DS",
+     .ucode = 0x8,
+   },
+   { .uname  = "FS",
+     .udesc  = "FS",
+     .ucode = 0x10,
+   },
+   { .uname  = "GS",
+     .udesc  = "GS",
+     .ucode = 0x20,
+   },
+   { .uname  = "HS",
+     .udesc  = "HS",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_locked_ops[]={
+   { .uname  = "EXECUTED",
+     .udesc  = "The number of locked instructions executed",
+     .ucode = 0x1,
+   },
+   { .uname  = "CYCLES_SPECULATIVE_PHASE",
+     .udesc  = "The number of cycles spent in speculative phase",
+     .ucode = 0x2,
+   },
+   { .uname  = "CYCLES_NON_SPECULATIVE_PHASE",
+     .udesc  = "The number of cycles spent in non-speculative phase (including cache miss penalty)",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_data_cache_refills[]={
+   { .uname  = "SYSTEM",
+     .udesc  = "Refill from the Northbridge",
+     .ucode = 0x1,
+   },
+   { .uname  = "L2_SHARED",
+     .udesc  = "Shared-state line from L2",
+     .ucode = 0x2,
+   },
+   { .uname  = "L2_EXCLUSIVE",
+     .udesc  = "Exclusive-state line from L2",
+     .ucode = 0x4,
+   },
+   { .uname  = "L2_OWNED",
+     .udesc  = "Owned-state line from L2",
+     .ucode = 0x8,
+   },
+   { .uname  = "L2_MODIFIED",
+     .udesc  = "Modified-state line from L2",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_data_cache_refills_from_system[]={
+   { .uname  = "INVALID",
+     .udesc  = "Invalid",
+     .ucode = 0x1,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x2,
+   },
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x8,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_data_cache_lines_evicted[]={
+   { .uname  = "INVALID",
+     .udesc  = "Invalid",
+     .ucode = 0x1,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x2,
+   },
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x8,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_scrubber_single_bit_ecc_errors[]={
+  { .uname  = "SCRUBBER_ERROR",
+    .udesc  = "Scrubber error",
+    .ucode = 0x1,
+  },
+  { .uname  = "PIGGYBACK_ERROR",
+    .udesc  = "Piggyback scrubber errors",
+    .ucode = 0x2,
+  },
+  { .uname  = "ALL",
+    .udesc  = "All sub-events selected",
+    .ucode = 0x3,
+    .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+  },
+};
+
+static const amd64_umask_t amd64_fam11h_prefetch_instructions_dispatched[]={
+   { .uname  = "LOAD",
+     .udesc  = "Load (Prefetch, PrefetchT0/T1/T2)",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORE",
+     .udesc  = "Store (PrefetchW)",
+     .ucode = 0x2,
+   },
+   { .uname  = "NTA",
+     .udesc  = "NTA (PrefetchNTA)",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_dcache_misses_by_locked_instructions[]={
+   { .uname  = "DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONS",
+     .udesc  = "Data cache misses by locked instructions",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x2,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_memory_requests[]={
+   { .uname  = "NON_CACHEABLE",
+     .udesc  = "Requests to non-cacheable (UC) memory",
+     .ucode = 0x1,
+   },
+   { .uname  = "WRITE_COMBINING",
+     .udesc  = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory",
+     .ucode = 0x2,
+   },
+   { .uname  = "STREAMING_STORE",
+     .udesc  = "Streaming store (SS) requests",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x83,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_data_prefetches[]={
+   { .uname  = "CANCELLED",
+     .udesc  = "Cancelled prefetches",
+     .ucode = 0x1,
+   },
+   { .uname  = "ATTEMPTED",
+     .udesc  = "Prefetch attempts",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_system_read_responses[]={
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x1,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified",
+     .ucode = 0x2,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x4,
+   },
+   { .uname  = "DATA_ERROR",
+     .udesc  = "Data Error",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x17,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_quadwords_written_to_system[]={
+   { .uname  = "QUADWORD_WRITE_TRANSFER",
+     .udesc  = "Quadword write transfer",
+     .ucode = 0x1,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_requests_to_l2[]={
+   { .uname  = "INSTRUCTIONS",
+     .udesc  = "IC fill",
+     .ucode = 0x1,
+   },
+   { .uname  = "DATA",
+     .udesc  = "DC fill",
+     .ucode = 0x2,
+   },
+   { .uname  = "TLB_WALK",
+     .udesc  = "TLB fill (page table walks)",
+     .ucode = 0x4,
+   },
+   { .uname  = "SNOOP",
+     .udesc  = "Tag snoop request",
+     .ucode = 0x8,
+   },
+   { .uname  = "CANCELLED",
+     .udesc  = "Cancelled request",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_l2_cache_miss[]={
+   { .uname  = "INSTRUCTIONS",
+     .udesc  = "IC fill",
+     .ucode = 0x1,
+   },
+   { .uname  = "DATA",
+     .udesc  = "DC fill (includes possible replays, whereas EventSelect 041h does not)",
+     .ucode = 0x2,
+   },
+   { .uname  = "TLB_WALK",
+     .udesc  = "TLB page table walk",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_l2_fill_writeback[]={
+   { .uname  = "L2_FILLS",
+     .udesc  = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)",
+     .ucode = 0x1,
+   },
+   { .uname  = "L2_WRITEBACKS",
+     .udesc  = "L2 Writebacks to system.",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_retired_mmx_and_fp_instructions[]={
+   { .uname  = "X87",
+     .udesc  = "X87 instructions",
+     .ucode = 0x1,
+   },
+   { .uname  = "MMX_AND_3DNOW",
+     .udesc  = "MMX and 3DNow! instructions",
+     .ucode = 0x2,
+   },
+   { .uname  = "PACKED_SSE_AND_SSE2",
+     .udesc  = "Packed SSE and SSE2 instructions",
+     .ucode = 0x4,
+   },
+   { .uname  = "SCALAR_SSE_AND_SSE2",
+     .udesc  = "Scalar SSE and SSE2 instructions",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_retired_fastpath_double_op_instructions[]={
+  { .uname  = "POSITION_0",
+    .udesc  = "With low op in position 0",
+    .ucode = 0x1,
+  },
+  { .uname  = "POSITION_1",
+    .udesc  = "With low op in position 1",
+    .ucode = 0x2,
+  },
+  { .uname  = "POSITION_2",
+    .udesc  = "With low op in position 2",
+    .ucode = 0x4,
+  },
+  { .uname  = "ALL",
+    .udesc  = "All sub-events selected",
+    .ucode = 0x7,
+    .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+  },
+};
+
+static const amd64_umask_t amd64_fam11h_interrupt_events[]={
+   { .uname  = "FIXED_AND_LPA",
+     .udesc  = "Fixed and LPA",
+     .ucode = 0x1,
+   },
+   { .uname  = "LPA",
+     .udesc  = "LPA",
+     .ucode = 0x2,
+   },
+   { .uname  = "SMI",
+     .udesc  = "SMI",
+     .ucode = 0x4,
+   },
+   { .uname  = "NMI",
+     .udesc  = "NMI",
+     .ucode = 0x8,
+   },
+   { .uname  = "INIT",
+     .udesc  = "INIT",
+     .ucode = 0x10,
+   },
+   { .uname  = "STARTUP",
+     .udesc  = "STARTUP",
+     .ucode = 0x20,
+   },
+   { .uname  = "INT",
+     .udesc  = "INT",
+     .ucode = 0x40,
+   },
+   { .uname  = "EOI",
+     .udesc  = "EOI",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_sideband_signals[]={
+   { .uname  = "HALT",
+     .udesc  = "HALT",
+     .ucode = 0x1,
+   },
+   { .uname  = "STOPGRANT",
+     .udesc  = "STOPGRANT",
+     .ucode = 0x2,
+   },
+   { .uname  = "SHUTDOWN",
+     .udesc  = "SHUTDOWN",
+     .ucode = 0x4,
+   },
+   { .uname  = "WBINVD",
+     .udesc  = "WBINVD",
+     .ucode = 0x8,
+   },
+   { .uname  = "INVD",
+     .udesc  = "INVD",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_fpu_exceptions[]={
+   { .uname  = "X87_RECLASS_MICROFAULTS",
+     .udesc  = "X87 reclass microfaults",
+     .ucode = 0x1,
+   },
+   { .uname  = "SSE_RETYPE_MICROFAULTS",
+     .udesc  = "SSE retype microfaults",
+     .ucode = 0x2,
+   },
+   { .uname  = "SSE_RECLASS_MICROFAULTS",
+     .udesc  = "SSE reclass microfaults",
+     .ucode = 0x4,
+   },
+   { .uname  = "SSE_AND_X87_MICROTRAPS",
+     .udesc  = "SSE and x87 microtraps",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_dram_accesses[]={
+   { .uname  = "DCT0_PAGE_HIT",
+     .udesc  = "DCT0 Page hit",
+     .ucode = 0x1,
+   },
+   { .uname  = "DCT0_PAGE_MISS",
+     .udesc  = "DCT0 Page Miss",
+     .ucode = 0x2,
+   },
+   { .uname  = "DCT0_PAGE_CONFLICT",
+     .udesc  = "DCT0 Page Conflict",
+     .ucode = 0x4,
+   },
+   { .uname  = "DCT1_PAGE_HIT",
+     .udesc  = "DCT1 Page hit",
+     .ucode = 0x8,
+   },
+   { .uname  = "DCT1_PAGE_MISS",
+     .udesc  = "DCT1 Page Miss",
+     .ucode = 0x10,
+   },
+   { .uname  = "DCT1_PAGE_CONFLICT",
+     .udesc  = "DCT1 Page Conflict",
+     .ucode = 0x20,
+   },
+   { .uname  = "WRITE_REQUEST",
+     .udesc  = "Write request.",
+     .ucode = 0x40,
+   },
+   { .uname  = "READ_REQUEST",
+     .udesc  = "Read request.",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_dram_controller_page_table_events[]={
+   { .uname  = "DCT_PAGE_TABLE_OVERFLOW",
+     .udesc  = "DCT Page Table Overflow",
+     .ucode = 0x1,
+   },
+   { .uname  = "STALE_TABLE_ENTRY_HITS",
+     .udesc  = "Number of stale table entry hits. (hit on a page closed too soon).",
+     .ucode = 0x2,
+   },
+   { .uname  = "PAGE_TABLE_IDLE_CYCLE_LIMIT_INCREMENTED",
+     .udesc  = "Page table idle cycle limit incremented.",
+     .ucode = 0x4,
+   },
+   { .uname  = "PAGE_TABLE_IDLE_CYCLE_LIMIT_DECREMENTED",
+     .udesc  = "Page table idle cycle limit decremented.",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_memory_controller_turnarounds[]={
+   { .uname  = "DCT0_READ_TO_WRITE",
+     .udesc  = "DCT0 read-to-write turnaround.",
+     .ucode = 0x1,
+   },
+   { .uname  = "DCT0_WRITE_TO_READ",
+     .udesc  = "DCT0 write-to-read turnaround",
+     .ucode = 0x2,
+   },
+   { .uname  = "DCT0_DIMM",
+     .udesc  = "DCT0 DIMM (chip select) turnaround",
+     .ucode = 0x4,
+   },
+   { .uname  = "DCT1_READ_TO_WRITE",
+     .udesc  = "DCT1 read-to-write turnaround.",
+     .ucode = 0x8,
+   },
+   { .uname  = "DCT1_WRITE_TO_READ",
+     .udesc  = "DCT1 write-to-read turnaround",
+     .ucode = 0x10,
+   },
+   { .uname  = "DCT1_DIMM",
+     .udesc  = "DCT1 DIMM (chip select) turnaround",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_memory_rbd_queue[]={
+   { .uname  = "COUNTER_REACHED",
+     .udesc  = "F2x[1,0]94[DcqBypassMax] counter reached.",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x4,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_thermal_status[]={
+   { .uname  = "MEMHOT_L_ASSERTIONS",
+     .udesc  = "Number of clocks MEMHOT_L is asserted.",
+     .ucode = 0x1,
+   },
+   { .uname  = "HTC_TRANSITIONS",
+     .udesc  = "Number of times the HTC transitions from inactive to active.",
+     .ucode = 0x4,
+   },
+   { .uname  = "CLOCKS_HTC_P_STATE_INACTIVE",
+     .udesc  = "Number of clocks HTC P-state is inactive.",
+     .ucode = 0x20,
+   },
+   { .uname  = "CLOCKS_HTC_P_STATE_ACTIVE",
+     .udesc  = "Number of clocks HTC P-state is active",
+     .ucode = 0x40,
+   },
+   { .uname  = "PROCHOT_L_ASSERTIONS",
+     .udesc  = "PROCHOT_L asserted by an external source and the assertion causes a P-state change.",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xe5,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_cpu_io_requests_to_memory_io[]={
+   { .uname  = "I_O_TO_I_O",
+     .udesc  = "IO to IO",
+     .ucode = 0xa1,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "I_O_TO_MEM",
+     .udesc  = "IO to Mem",
+     .ucode = 0xa2,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "CPU_TO_I_O",
+     .udesc  = "CPU to IO",
+     .ucode = 0xa4,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "CPU_TO_MEM",
+     .udesc  = "CPU to Mem",
+     .ucode = 0xa8,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xaf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_cache_block[]={
+   { .uname  = "VICTIM_WRITEBACK",
+     .udesc  = "Victim Block (Writeback)",
+     .ucode = 0x1,
+   },
+   { .uname  = "DCACHE_LOAD_MISS",
+     .udesc  = "Read Block (Dcache load miss refill)",
+     .ucode = 0x4,
+   },
+   { .uname  = "SHARED_ICACHE_REFILL",
+     .udesc  = "Read Block Shared (Icache refill)",
+     .ucode = 0x8,
+   },
+   { .uname  = "READ_BLOCK_MODIFIED",
+     .udesc  = "Read Block Modified (Dcache store miss refill)",
+     .ucode = 0x10,
+   },
+   { .uname  = "READ_TO_DIRTY",
+     .udesc  = "Change-to-Dirty (first store to clean block already in cache)",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3d,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_sized_commands[]={
+   { .uname  = "NON_POSTED_WRITE_BYTE",
+     .udesc  = "Non-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytes",
+     .ucode = 0x1,
+   },
+   { .uname  = "NON_POSTED_WRITE_DWORD",
+     .udesc  = "Non-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORD",
+     .ucode = 0x2,
+   },
+   { .uname  = "POSTED_WRITE_BYTE",
+     .udesc  = "Posted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer",
+     .ucode = 0x4,
+   },
+   { .uname  = "POSTED_WRITE_DWORD",
+     .udesc  = "Posted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes",
+     .ucode = 0x8,
+   },
+   { .uname  = "READ_BYTE_4_BYTES",
+     .udesc  = "SzRd Byte (4 bytes) Legacy or mapped IO",
+     .ucode = 0x10,
+   },
+   { .uname  = "READ_DWORD_1_16_DWORDS",
+     .udesc  = "SzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_probe[]={
+   { .uname  = "MISS",
+     .udesc  = "Probe miss",
+     .ucode = 0x1,
+   },
+   { .uname  = "HIT_CLEAN",
+     .udesc  = "Probe hit clean",
+     .ucode = 0x2,
+   },
+   { .uname  = "HIT_DIRTY_NO_MEMORY_CANCEL",
+     .udesc  = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)",
+     .ucode = 0x4,
+   },
+   { .uname  = "HIT_DIRTY_WITH_MEMORY_CANCEL",
+     .udesc  = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)",
+     .ucode = 0x8,
+   },
+   { .uname  = "UPSTREAM_DISPLAY_REFRESH_READS",
+     .udesc  = "Upstream display refresh/ISOC reads.",
+     .ucode = 0x10,
+   },
+   { .uname  = "UPSTREAM_NON_DISPLAY_REFRESH_READS",
+     .udesc  = "Upstream non-display refresh reads.",
+     .ucode = 0x20,
+   },
+   { .uname  = "UPSTREAM_ISOC_WRITES",
+     .udesc  = "Upstream ISOC writes.",
+     .ucode = 0x40,
+   },
+   { .uname  = "UPSTREAM_NON_ISOC_WRITES",
+     .udesc  = "Upstream non-ISOC writes.",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_dev[]={
+   { .uname  = "DEV_HIT",
+     .udesc  = "DEV hit",
+     .ucode = 0x10,
+   },
+   { .uname  = "DEV_MISS",
+     .udesc  = "DEV miss",
+     .ucode = 0x20,
+   },
+   { .uname  = "DEV_ERROR",
+     .udesc  = "DEV error",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x70,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_memory_controller_requests[]={
+   { .uname  = "32_BYTES_WRITES",
+     .udesc  = "32 Bytes Sized Writes",
+     .ucode = 0x8,
+   },
+   { .uname  = "64_BYTES_WRITES",
+     .udesc  = "64 Bytes Sized Writes",
+     .ucode = 0x10,
+   },
+   { .uname  = "32_BYTES_READS",
+     .udesc  = "32 Bytes Sized Reads",
+     .ucode = 0x20,
+   },
+   { .uname  = "64_BYTES_READS",
+     .udesc  = "64 Byte Sized Reads",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x78,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam11h_hypertransport_link0[]={
+  { .uname  = "COMMAND_DWORD_SENT",
+    .udesc  = "Command DWORD sent",
+    .ucode = 0x1,
+    .grpid = 0,
+  },
+  { .uname  = "ADDRESS_DWORD_SENT",
+    .udesc  = "Address DWORD sent",
+    .ucode = 0x2,
+    .grpid = 0,
+  },
+  { .uname  = "DATA_DWORD_SENT",
+    .udesc  = "Data DWORD sent",
+    .ucode = 0x4,
+    .grpid = 0,
+  },
+  { .uname  = "BUFFER_RELEASE_DWORD_SENT",
+    .udesc  = "Buffer release DWORD sent",
+    .ucode = 0x8,
+    .grpid = 0,
+  },
+  { .uname  = "NOP_DWORD_SENT",
+    .udesc  = "Nop DW sent (idle)",
+    .ucode = 0x10,
+    .grpid = 0,
+  },
+  { .uname  = "PER_PACKET_CRC_SENT",
+    .udesc  = "Per packet CRC sent",
+    .ucode = 0x20,
+    .grpid = 0,
+  },
+  { .uname  = "ALL",
+    .udesc  = "All sub-events selected",
+    .ucode = 0x3f,
+    .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+    .grpid = 0,
+  },
+};
+
+
+static const amd64_entry_t amd64_fam11h_pe[]={
+{ .name    = "DISPATCHED_FPU",
+  .desc    = "Dispatched FPU Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_dispatched_fpu),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_dispatched_fpu,
+},
+{ .name    = "CYCLES_NO_FPU_OPS_RETIRED",
+  .desc    = "Cycles in which the FPU is Empty",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1,
+},
+{ .name    = "DISPATCHED_FPU_OPS_FAST_FLAG",
+  .desc    = "Dispatched Fast Flag FPU Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x2,
+},
+{ .name    = "SEGMENT_REGISTER_LOADS",
+  .desc    = "Segment Register Loads",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x20,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_segment_register_loads),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_segment_register_loads,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE",
+  .desc    = "Pipeline Restart Due to Self-Modifying Code",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x21,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_PROBE_HIT",
+  .desc    = "Pipeline Restart Due to Probe Hit",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x22,
+},
+{ .name    = "LS_BUFFER_2_FULL_CYCLES",
+  .desc    = "LS Buffer 2 Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x23,
+},
+{ .name    = "LOCKED_OPS",
+  .desc    = "Locked Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x24,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_locked_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_locked_ops,
+},
+{ .name    = "RETIRED_CLFLUSH_INSTRUCTIONS",
+  .desc    = "Retired CLFLUSH Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x26,
+},
+{ .name    = "RETIRED_CPUID_INSTRUCTIONS",
+  .desc    = "Retired CPUID Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x27,
+},
+{ .name    = "DATA_CACHE_ACCESSES",
+  .desc    = "Data Cache Accesses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x40,
+},
+{ .name    = "DATA_CACHE_MISSES",
+  .desc    = "Data Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x41,
+},
+{ .name    = "DATA_CACHE_REFILLS",
+  .desc    = "Data Cache Refills from L2 or System",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x42,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_data_cache_refills),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_data_cache_refills,
+},
+{ .name    = "DATA_CACHE_REFILLS_FROM_SYSTEM",
+  .desc    = "Data Cache Refills from the System",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x43,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_data_cache_refills_from_system),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_data_cache_refills_from_system,
+},
+{ .name    = "DATA_CACHE_LINES_EVICTED",
+  .desc    = "Data Cache Lines Evicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x44,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_data_cache_lines_evicted),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_data_cache_lines_evicted,
+},
+{ .name    = "L1_DTLB_MISS_AND_L2_DTLB_HIT",
+  .desc    = "Number of data cache accesses that miss in L1 DTLB and hit in L2 DTLB",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x45,
+},
+{ .name    = "L1_DTLB_AND_L2_DTLB_MISS",
+  .desc    = "Number of data cache accesses that miss both the L1 and L2 DTLBs",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x46,
+},
+{ .name    = "MISALIGNED_ACCESSES",
+  .desc    = "Misaligned Accesses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x47,
+},
+{ .name    = "MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS",
+  .desc    = "Microarchitectural Late Cancel of an Access",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x48,
+},
+{ .name    = "MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS",
+  .desc    = "Microarchitectural Early Cancel of an Access",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x49,
+},
+{ .name    = "SCRUBBER_SINGLE_BIT_ECC_ERRORS",
+  .desc    = "Single-bit ECC Errors Recorded by Scrubber",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4a,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_scrubber_single_bit_ecc_errors),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_scrubber_single_bit_ecc_errors,
+},
+{ .name    = "PREFETCH_INSTRUCTIONS_DISPATCHED",
+  .desc    = "Prefetch Instructions Dispatched",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4b,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_prefetch_instructions_dispatched),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_prefetch_instructions_dispatched,
+},
+{ .name    = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS",
+  .desc    = "DCACHE Misses by Locked Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4c,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_dcache_misses_by_locked_instructions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_dcache_misses_by_locked_instructions,
+},
+{ .name    = "MEMORY_REQUESTS",
+  .desc    = "Memory Requests by Type",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x65,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_memory_requests),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_memory_requests,
+},
+{ .name    = "DATA_PREFETCHES",
+  .desc    = "Data Prefetcher",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x67,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_data_prefetches),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_data_prefetches,
+},
+{ .name    = "SYSTEM_READ_RESPONSES",
+  .desc    = "System Read Responses by Coherency State",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x6c,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_system_read_responses),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_system_read_responses,
+},
+{ .name    = "QUADWORDS_WRITTEN_TO_SYSTEM",
+  .desc    = "Quadwords Written to System",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x6d,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_quadwords_written_to_system),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_quadwords_written_to_system,
+},
+{ .name    = "CPU_CLK_UNHALTED",
+  .desc    = "CPU Clocks not Halted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x76,
+},
+{ .name    = "REQUESTS_TO_L2",
+  .desc    = "Requests to L2 Cache",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x7d,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_requests_to_l2),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_requests_to_l2,
+},
+{ .name    = "L2_CACHE_MISS",
+  .desc    = "L2 Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x7e,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_l2_cache_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_l2_cache_miss,
+},
+{ .name    = "L2_FILL_WRITEBACK",
+  .desc    = "L2 Fill/Writeback",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x7f,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_l2_fill_writeback),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_l2_fill_writeback,
+},
+{ .name    = "INSTRUCTION_CACHE_FETCHES",
+  .desc    = "Instruction Cache Fetches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x80,
+},
+{ .name    = "INSTRUCTION_CACHE_MISSES",
+  .desc    = "Instruction Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x81,
+},
+{ .name    = "INSTRUCTION_CACHE_REFILLS_FROM_L2",
+  .desc    = "Instruction Cache Refills from L2",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x82,
+},
+{ .name    = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM",
+  .desc    = "Instruction Cache Refills from System",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x83,
+},
+{ .name    = "L1_ITLB_MISS_AND_L2_ITLB_HIT",
+  .desc    = "L1 ITLB Miss and L2 ITLB Hit",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x84,
+},
+{ .name    = "L1_ITLB_MISS_AND_L2_ITLB_MISS",
+  .desc    = "L1 ITLB Miss and L2 ITLB Miss",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x85,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE",
+  .desc    = "Pipeline Restart Due to Instruction Stream Probe",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x86,
+},
+{ .name    = "INSTRUCTION_FETCH_STALL",
+  .desc    = "Instruction Fetch Stall",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x87,
+},
+{ .name    = "RETURN_STACK_HITS",
+  .desc    = "Return Stack Hits",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x88,
+},
+{ .name    = "RETURN_STACK_OVERFLOWS",
+  .desc    = "Return Stack Overflows",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x89,
+},
+{ .name    = "RETIRED_INSTRUCTIONS",
+  .desc    = "Retired Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc0,
+},
+{ .name    = "RETIRED_UOPS",
+  .desc    = "Retired uops",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc1,
+},
+{ .name    = "RETIRED_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Branch Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc2,
+},
+{ .name    = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Mispredicted Branch Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc3,
+},
+{ .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Taken Branch Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc4,
+},
+{ .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED",
+  .desc    = "Retired Taken Branch Instructions Mispredicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc5,
+},
+{ .name    = "RETIRED_FAR_CONTROL_TRANSFERS",
+  .desc    = "Retired Far Control Transfers",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc6,
+},
+{ .name    = "RETIRED_BRANCH_RESYNCS",
+  .desc    = "Retired Branch Resyncs",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc7,
+},
+{ .name    = "RETIRED_NEAR_RETURNS",
+  .desc    = "Retired Near Returns",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc8,
+},
+{ .name    = "RETIRED_NEAR_RETURNS_MISPREDICTED",
+  .desc    = "Retired Near Returns Mispredicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc9,
+},
+{ .name    = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED",
+  .desc    = "Retired Indirect Branches Mispredicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xca,
+},
+{ .name    = "RETIRED_MMX_AND_FP_INSTRUCTIONS",
+  .desc    = "Retired MMX/FP Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_retired_mmx_and_fp_instructions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_retired_mmx_and_fp_instructions,
+},
+{ .name    = "RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS",
+  .desc    = "Retired Fastpath Double Op Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcc,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_retired_fastpath_double_op_instructions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_retired_fastpath_double_op_instructions,
+},
+{ .name    = "INTERRUPTS_MASKED_CYCLES",
+  .desc    = "Interrupts-Masked Cycles",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcd,
+},
+{ .name    = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING",
+  .desc    = "Interrupts-Masked Cycles with Interrupt Pending",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xce,
+},
+{ .name    = "INTERRUPTS_TAKEN",
+  .desc    = "Interrupts Taken",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcf,
+},
+{ .name    = "DECODER_EMPTY",
+  .desc    = "Decoder Empty",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd0,
+},
+{ .name    = "DISPATCH_STALLS",
+  .desc    = "Dispatch Stalls",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd1,
+},
+{ .name    = "DISPATCH_STALL_FOR_BRANCH_ABORT",
+  .desc    = "Dispatch Stall for Branch Abort to Retire",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd2,
+},
+{ .name    = "DISPATCH_STALL_FOR_SERIALIZATION",
+  .desc    = "Dispatch Stall for Serialization",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd3,
+},
+{ .name    = "DISPATCH_STALL_FOR_SEGMENT_LOAD",
+  .desc    = "Dispatch Stall for Segment Load",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd4,
+},
+{ .name    = "DISPATCH_STALL_FOR_REORDER_BUFFER_FULL",
+  .desc    = "Dispatch Stall for Reorder Buffer Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd5,
+},
+{ .name    = "DISPATCH_STALL_FOR_RESERVATION_STATION_FULL",
+  .desc    = "Dispatch Stall for Reservation Station Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd6,
+},
+{ .name    = "DISPATCH_STALL_FOR_FPU_FULL",
+  .desc    = "Dispatch Stall for FPU Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd7,
+},
+{ .name    = "DISPATCH_STALL_FOR_LS_FULL",
+  .desc    = "Dispatch Stall for LS Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd8,
+},
+{ .name    = "DISPATCH_STALL_WAITING_FOR_ALL_QUIET",
+  .desc    = "Dispatch Stall Waiting for All Quiet",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd9,
+},
+{ .name    = "DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNC",
+  .desc    = "Dispatch Stall for Far Transfer or Resync to Retire",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xda,
+},
+{ .name    = "FPU_EXCEPTIONS",
+  .desc    = "FPU Exceptions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_fpu_exceptions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_fpu_exceptions,
+},
+{ .name    = "DR0_BREAKPOINT_MATCHES",
+  .desc    = "DR0 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdc,
+},
+{ .name    = "DR1_BREAKPOINT_MATCHES",
+  .desc    = "DR1 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdd,
+},
+{ .name    = "DR2_BREAKPOINT_MATCHES",
+  .desc    = "DR2 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xde,
+},
+{ .name    = "DR3_BREAKPOINT_MATCHES",
+  .desc    = "DR3 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdf,
+},
+{ .name    = "DRAM_ACCESSES",
+  .desc    = "DRAM Accesses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_dram_accesses),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_dram_accesses,
+},
+{ .name    = "DRAM_CONTROLLER_PAGE_TABLE_EVENTS",
+  .desc    = "DRAM Controller Page Table Events",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe1,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_dram_controller_page_table_events),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_dram_controller_page_table_events,
+},
+{ .name    = "MEMORY_CONTROLLER_TURNAROUNDS",
+  .desc    = "Memory Controller Turnarounds",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe3,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_memory_controller_turnarounds),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_memory_controller_turnarounds,
+},
+{ .name    = "MEMORY_CONTROLLER_RBD_QUEUE",
+  .desc    = "Memory Controller RBD Queue Events",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe4,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_memory_rbd_queue),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_memory_rbd_queue,
+},
+{ .name    = "THERMAL_STATUS",
+  .desc    = "Thermal Status",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe8,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_thermal_status),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_thermal_status,
+},
+{ .name    = "CPU_IO_REQUESTS_TO_MEMORY_IO",
+  .desc    = "CPU/IO Requests to Memory/IO",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe9,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_cpu_io_requests_to_memory_io),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_cpu_io_requests_to_memory_io,
+},
+{ .name    = "CACHE_BLOCK",
+  .desc    = "Cache Block Commands",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xea,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_cache_block),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_cache_block,
+},
+{ .name    = "SIZED_COMMANDS",
+  .desc    = "Sized Commands",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xeb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_sized_commands),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_sized_commands,
+},
+{ .name    = "PROBE",
+  .desc    = "Probe Responses and Upstream Requests",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xec,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_probe),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_probe,
+},
+{ .name    = "DEV",
+  .desc    = "DEV Events",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xee,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_dev),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_dev,
+},
+{ .name    = "HYPERTRANSPORT_LINK0",
+  .desc    = "HyperTransport Link 0 Transmit Bandwidth",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xf6,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_hypertransport_link0),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_hypertransport_link0,
+},
+{ .name    = "MEMORY_CONTROLLER_REQUESTS",
+  .desc    = "Memory Controller Requests",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1f0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_memory_controller_requests),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_memory_controller_requests,
+},
+{ .name    = "SIDEBAND_SIGNALS",
+  .desc    = "Sideband Signals and Special Cycles",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1e9,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_sideband_signals),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_sideband_signals,
+},
+{ .name    = "Interrupt Events",
+  .desc    = "Interrupt Events",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1ea,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam11h_interrupt_events),
+  .ngrp    = 1,
+  .umasks  = amd64_fam11h_interrupt_events,
+},
+};
diff --git a/user/perfmon/events/amd64_events_fam12h.h b/user/perfmon/events/amd64_events_fam12h.h
new file mode 100644 (file)
index 0000000..609f6d2
--- /dev/null
@@ -0,0 +1,1758 @@
+/*
+ * Copyright (c) 2011 University of Tennessee
+ * Contributed by Vince Weaver <vweaver1@utk.edu>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * This file is part of libpfm, a performance monitoring support library for
+ * applications on Linux.
+ *
+ * PMU: amd64_fam12h (AMD64 Fam12h)
+ */
+
+static const amd64_umask_t amd64_fam12h_dispatched_fpu[]={
+   { .uname  = "OPS_ADD",
+     .udesc  = "Add pipe ops excluding load ops and SSE move ops",
+     .ucode = 0x1,
+   },
+   { .uname  = "OPS_MULTIPLY",
+     .udesc  = "Multiply pipe ops excluding load ops and SSE move ops",
+     .ucode = 0x2,
+   },
+   { .uname  = "OPS_STORE",
+     .udesc  = "Store pipe ops excluding load ops and SSE move ops",
+     .ucode = 0x4,
+   },
+   { .uname  = "OPS_ADD_PIPE_LOAD_OPS",
+     .udesc  = "Add pipe load ops and SSE move ops",
+     .ucode = 0x8,
+   },
+   { .uname  = "OPS_MULTIPLY_PIPE_LOAD_OPS",
+     .udesc  = "Multiply pipe load ops and SSE move ops",
+     .ucode = 0x10,
+   },
+   { .uname  = "OPS_STORE_PIPE_LOAD_OPS",
+     .udesc  = "Store pipe load ops and SSE move ops",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_retired_sse_operations[]={
+   { .uname  = "SINGLE_ADD_SUB_OPS",
+     .udesc  = "Single precision add/subtract ops",
+     .ucode = 0x1,
+   },
+   { .uname  = "SINGLE_MUL_OPS",
+     .udesc  = "Single precision multiply ops",
+     .ucode = 0x2,
+   },
+   { .uname  = "SINGLE_DIV_OPS",
+     .udesc  = "Single precision divide/square root ops",
+     .ucode = 0x4,
+   },
+   { .uname  = "DOUBLE_ADD_SUB_OPS",
+     .udesc  = "Double precision add/subtract ops",
+     .ucode = 0x8,
+   },
+   { .uname  = "DOUBLE_MUL_OPS",
+     .udesc  = "Double precision multiply ops",
+     .ucode = 0x10,
+   },
+   { .uname  = "DOUBLE_DIV_OPS",
+     .udesc  = "Double precision divide/square root ops",
+     .ucode = 0x20,
+   },
+   { .uname  = "OP_TYPE",
+     .udesc  = "Op type: 0=uops. 1=FLOPS",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_retired_move_ops[]={
+   { .uname  = "LOW_QW_MOVE_UOPS",
+     .udesc  = "Merging low quadword move uops",
+     .ucode = 0x1,
+   },
+   { .uname  = "HIGH_QW_MOVE_UOPS",
+     .udesc  = "Merging high quadword move uops",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL_OTHER_MERGING_MOVE_UOPS",
+     .udesc  = "All other merging move uops",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL_OTHER_MOVE_UOPS",
+     .udesc  = "All other move uops",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_retired_serializing_ops[]={
+   { .uname  = "SSE_BOTTOM_EXECUTING_UOPS",
+     .udesc  = "SSE bottom-executing uops retired",
+     .ucode = 0x1,
+   },
+   { .uname  = "SSE_BOTTOM_SERIALIZING_UOPS",
+     .udesc  = "SSE bottom-serializing uops retired",
+     .ucode = 0x2,
+   },
+   { .uname  = "X87_BOTTOM_EXECUTING_UOPS",
+     .udesc  = "X87 bottom-executing uops retired",
+     .ucode = 0x4,
+   },
+   { .uname  = "X87_BOTTOM_SERIALIZING_UOPS",
+     .udesc  = "X87 bottom-serializing uops retired",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+static const amd64_umask_t amd64_fam12h_fp_scheduler_cycles[]={
+   { .uname  = "BOTTOM_EXECUTE_CYCLES",
+     .udesc  = "Number of cycles a bottom-execute uop is in the FP scheduler",
+     .ucode = 0x1,
+   },
+   { .uname  = "BOTTOM_SERIALIZING_CYCLES",
+     .udesc  = "Number of cycles a bottom-serializing uop is in the FP scheduler",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_segment_register_loads[]={
+   { .uname  = "ES",
+     .udesc  = "ES",
+     .ucode = 0x1,
+   },
+   { .uname  = "CS",
+     .udesc  = "CS",
+     .ucode = 0x2,
+   },
+   { .uname  = "SS",
+     .udesc  = "SS",
+     .ucode = 0x4,
+   },
+   { .uname  = "DS",
+     .udesc  = "DS",
+     .ucode = 0x8,
+   },
+   { .uname  = "FS",
+     .udesc  = "FS",
+     .ucode = 0x10,
+   },
+   { .uname  = "GS",
+     .udesc  = "GS",
+     .ucode = 0x20,
+   },
+   { .uname  = "HS",
+     .udesc  = "HS",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_locked_ops[]={
+   { .uname  = "EXECUTED",
+     .udesc  = "The number of locked instructions executed",
+     .ucode = 0x1,
+   },
+   { .uname  = "CYCLES_SPECULATIVE_PHASE",
+     .udesc  = "The number of cycles spent in speculative phase",
+     .ucode = 0x2,
+   },
+   { .uname  = "CYCLES_NON_SPECULATIVE_PHASE",
+     .udesc  = "The number of cycles spent in non-speculative phase (including cache miss penalty)",
+     .ucode = 0x4,
+   },
+   { .uname  = "CYCLES_WAITING",
+     .udesc  = "The number of cycles waiting for a cache hit (cache miss penalty).",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_cancelled_store_to_load_forward_operations[]={
+   { .uname  = "ADDRESS_MISMATCHES",
+     .udesc  = "Address mismatches (starting byte not the same).",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORE_IS_SMALLER_THAN_LOAD",
+     .udesc  = "Store is smaller than load.",
+     .ucode = 0x2,
+   },
+   { .uname  = "MISALIGNED",
+     .udesc  = "Misaligned.",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_data_cache_refills[]={
+   { .uname  = "SYSTEM",
+     .udesc  = "Refill from the Northbridge",
+     .ucode = 0x1,
+   },
+   { .uname  = "L2_SHARED",
+     .udesc  = "Shared-state line from L2",
+     .ucode = 0x2,
+   },
+   { .uname  = "L2_EXCLUSIVE",
+     .udesc  = "Exclusive-state line from L2",
+     .ucode = 0x4,
+   },
+   { .uname  = "L2_OWNED",
+     .udesc  = "Owned-state line from L2",
+     .ucode = 0x8,
+   },
+   { .uname  = "L2_MODIFIED",
+     .udesc  = "Modified-state line from L2",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_data_cache_refills_from_northbridge[]={
+   { .uname  = "INVALID",
+     .udesc  = "Invalid",
+     .ucode = 0x1,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x2,
+   },
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x8,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_data_cache_lines_evicted[]={
+   { .uname  = "INVALID",
+     .udesc  = "Invalid",
+     .ucode = 0x1,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x2,
+   },
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x8,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified",
+     .ucode = 0x10,
+   },
+   { .uname  = "BY_PREFETCHNTA",
+     .udesc  = "Cache line evicted was brought into the cache with by a PrefetchNTA instruction.",
+     .ucode = 0x20,
+   },
+   { .uname  = "NOT_BY_PREFETCHNTA",
+     .udesc  = "Cache line evicted was not brought into the cache with by a PrefetchNTA instruction.",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_l1_dtlb_miss_and_l2_dtlb_hit[]={
+   { .uname  = "L2_4K_TLB_HIT",
+     .udesc  = "L2 4K TLB hit",
+     .ucode = 0x1,
+   },
+   { .uname  = "L2_2M_TLB_HIT",
+     .udesc  = "L2 2M TLB hit",
+     .ucode = 0x2,
+   },
+   { .uname  = "L2_1G_TLB_HIT",
+     .udesc  = "L2 1G TLB hit",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, 
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_l1_dtlb_and_l2_dtlb_miss[]={
+   { .uname  = "4K_TLB_RELOAD",
+     .udesc  = "4K TLB reload",
+     .ucode = 0x1,
+   },
+   { .uname  = "2M_TLB_RELOAD",
+     .udesc  = "2M TLB reload",
+     .ucode = 0x2,
+   },
+   { .uname  = "1G_TLB_RELOAD",
+     .udesc  = "1G TLB reload",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_prefetch_instructions_dispatched[]={
+   { .uname  = "LOAD",
+     .udesc  = "Load (Prefetch, PrefetchT0/T1/T2)",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORE",
+     .udesc  = "Store (PrefetchW)",
+     .ucode = 0x2,
+   },
+   { .uname  = "NTA",
+     .udesc  = "NTA (PrefetchNTA)",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_dcache_misses_by_locked_instructions[]={
+   { .uname  = "DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONS",
+     .udesc  = "Data cache misses by locked instructions",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x2,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_l1_dtlb_hit[]={
+   { .uname  = "L1_4K_TLB_HIT",
+     .udesc  = "L1 4K TLB hit",
+     .ucode = 0x1,
+   },
+   { .uname  = "L1_2M_TLB_HIT",
+     .udesc  = "L1 2M TLB hit",
+     .ucode = 0x2,
+   },
+   { .uname  = "L1_1G_TLB_HIT",
+     .udesc  = "L1 1G TLB hit",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_ineffective_sw_prefetches[]={
+   { .uname  = "SW_PREFETCH_HIT_IN_L1",
+     .udesc  = "Software prefetch hit in the L1.",
+     .ucode = 0x1,
+   },
+   { .uname  = "SW_PREFETCH_HIT_IN_L2",
+     .udesc  = "Software prefetch hit in L2.",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x9,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_memory_requests[]={
+   { .uname  = "NON_CACHEABLE",
+     .udesc  = "Requests to non-cacheable (UC) memory",
+     .ucode = 0x1,
+   },
+   { .uname  = "WRITE_COMBINING",
+     .udesc  = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory",
+     .ucode = 0x2,
+   },
+   { .uname  = "CACHE_DISABLED",
+     .udesc  = "Requests to cache-disabled (CD) memory",
+     .ucode = 0x4,
+   },
+   { .uname  = "STREAMING_STORE",
+     .udesc  = "Streaming store (SS) requests",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x87,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_data_prefetches[]={
+   { .uname  = "CANCELLED",
+     .udesc  = "Cancelled prefetches",
+     .ucode = 0x1,
+   },
+   { .uname  = "ATTEMPTED",
+     .udesc  = "Prefetch attempts",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_northbridge_read_responses[]={
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x1,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified",
+     .ucode = 0x2,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x8,
+   },
+   { .uname  = "DATA_ERROR",
+     .udesc  = "Data Error",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_octwords_written_to_system[]={
+   { .uname  = "OCTWORD_WRITE_TRANSFER",
+     .udesc  = "Octword write transfer",
+     .ucode = 0x1,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_requests_to_l2[]={
+   { .uname  = "INSTRUCTIONS",
+     .udesc  = "IC fill",
+     .ucode = 0x1,
+   },
+   { .uname  = "DATA",
+     .udesc  = "DC fill",
+     .ucode = 0x2,
+   },
+   { .uname  = "TLB_WALK",
+     .udesc  = "TLB fill (page table walks)",
+     .ucode = 0x4,
+   },
+   { .uname  = "SNOOP",
+     .udesc  = "Tag snoop request",
+     .ucode = 0x8,
+   },
+   { .uname  = "CANCELLED",
+     .udesc  = "Cancelled request",
+     .ucode = 0x10,
+   },
+   { .uname  = "HW_PREFETCH_FROM_DC",
+     .udesc  = "Hardware prefetch from DC",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_l2_cache_miss[]={
+   { .uname  = "INSTRUCTIONS",
+     .udesc  = "IC fill",
+     .ucode = 0x1,
+   },
+   { .uname  = "DATA",
+     .udesc  = "DC fill (includes possible replays, whereas EventSelect 041h does not)",
+     .ucode = 0x2,
+   },
+   { .uname  = "TLB_WALK",
+     .udesc  = "TLB page table walk",
+     .ucode = 0x4,
+   },
+   { .uname  = "HW_PREFETCH_FROM_DC",
+     .udesc  = "Hardware prefetch from DC",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_l2_fill_writeback[]={
+   { .uname  = "L2_FILLS",
+     .udesc  = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)",
+     .ucode = 0x1,
+   },
+   { .uname  = "L2_WRITEBACKS",
+     .udesc  = "L2 Writebacks to system.",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_l1_itlb_miss_and_l2_itlb_miss[]={
+   { .uname  = "4K_PAGE_FETCHES",
+     .udesc  = "Instruction fetches to a 4K page.",
+     .ucode = 0x1,
+   },
+   { .uname  = "2M_PAGE_FETCHES",
+     .udesc  = "Instruction fetches to a 2M page.",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_instruction_cache_lines_invalidated[]={
+   { .uname  = "INVALIDATING_PROBE_NO_IN_FLIGHT",
+     .udesc  = "Invalidating probe that did not hit any in-flight instructions.",
+     .ucode = 0x1,
+   },
+   { .uname  = "INVALIDATING_PROBE_ONE_OR_MORE_IN_FLIGHT",
+     .udesc  = "Invalidating probe that hit one or more in-flight instructions.",
+     .ucode = 0x2,
+   },
+   { .uname  = "SMC_NO_INFLIGHT",
+     .udesc  = "SMC that did not hit any in-flight instructions.",
+     .ucode = 0x4,
+   },
+   { .uname  = "SMC_INFLIGHT",
+     .udesc  = "SMC that hit one or more in-flight instructions.",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_retired_mmx_and_fp_instructions[]={
+   { .uname  = "X87",
+     .udesc  = "X87 instructions",
+     .ucode = 0x1,
+   },
+   { .uname  = "MMX_AND_3DNOW",
+     .udesc  = "MMX and 3DNow! instructions",
+     .ucode = 0x2,
+   },
+   { .uname  = "SSE_AND_SSE2",
+     .udesc  = "SSE and SSE2 instructions",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_interrupt_events[]={
+   { .uname  = "FIXED_AND_LPA",
+     .udesc  = "Fixed and LPA",
+     .ucode = 0x1,
+   },
+   { .uname  = "LPA",
+     .udesc  = "LPA",
+     .ucode = 0x2,
+   },
+   { .uname  = "SMI",
+     .udesc  = "SMI",
+     .ucode = 0x4,
+   },
+   { .uname  = "NMI",
+     .udesc  = "NMI",
+     .ucode = 0x8,
+   },
+   { .uname  = "INIT",
+     .udesc  = "INIT",
+     .ucode = 0x10,
+   },
+   { .uname  = "STARTUP",
+     .udesc  = "STARTUP",
+     .ucode = 0x20,
+   },
+   { .uname  = "INT",
+     .udesc  = "INT",
+     .ucode = 0x40,
+   },
+   { .uname  = "EOI",
+     .udesc  = "EOI",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_sideband_signals[]={
+   { .uname  = "STOPGRANT",
+     .udesc  = "STOPGRANT",
+     .ucode = 0x2,
+   },
+   { .uname  = "SHUTDOWN",
+     .udesc  = "SHUTDOWN",
+     .ucode = 0x4,
+   },
+   { .uname  = "WBINVD",
+     .udesc  = "WBINVD",
+     .ucode = 0x8,
+   },
+   { .uname  = "INVD",
+     .udesc  = "INVD",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1e,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_fpu_exceptions[]={
+   { .uname  = "X87_RECLASS_MICROFAULTS",
+     .udesc  = "X87 reclass microfaults",
+     .ucode = 0x1,
+   },
+   { .uname  = "SSE_RETYPE_MICROFAULTS",
+     .udesc  = "SSE retype microfaults",
+     .ucode = 0x2,
+   },
+   { .uname  = "SSE_RECLASS_MICROFAULTS",
+     .udesc  = "SSE reclass microfaults",
+     .ucode = 0x4,
+   },
+   { .uname  = "SSE_AND_X87_MICROTRAPS",
+     .udesc  = "SSE and x87 microtraps",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_dram_accesses_page[]={
+   { .uname  = "DCT0_HIT",
+     .udesc  = "DCT0 Page hit",
+     .ucode = 0x1,
+   },
+   { .uname  = "DCT0_MISS",
+     .udesc  = "DCT0 Page Miss",
+     .ucode = 0x2,
+   },
+   { .uname  = "DCT0_CONFLICT",
+     .udesc  = "DCT0 Page Conflict",
+     .ucode = 0x4,
+   },
+   { .uname  = "DCT1_PAGE_HIT",
+     .udesc  = "DCT1 Page hit",
+     .ucode = 0x8,
+   },
+   { .uname  = "DCT1_PAGE_MISS",
+     .udesc  = "DCT1 Page Miss",
+     .ucode = 0x10,
+   },
+   { .uname  = "DCT1_PAGE_CONFLICT",
+     .udesc  = "DCT1 Page Conflict",
+     .ucode = 0x20,
+   },
+   { .uname  = "WRITE_REQUEST",
+     .udesc  = "Write request.",
+     .ucode = 0x40,
+   },
+   { .uname  = "READ_REQUEST",
+     .udesc  = "Read request.",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_memory_controller_page_table_events[]={
+   { .uname  = "PAGE_TABLE_OVERFLOW",
+     .udesc  = "Page Table Overflow",
+     .ucode = 0x1,
+   },
+   { .uname  = "STALE_TABLE_ENTRY_HITS",
+     .udesc  = "Number of stale table entry hits. (hit on a page closed too soon).",
+     .ucode = 0x2,
+   },
+   { .uname  = "PAGE_TABLE_IDLE_CYCLE_LIMIT_INCREMENTED",
+     .udesc  = "Page table idle cycle limit incremented.",
+     .ucode = 0x4,
+   },
+   { .uname  = "PAGE_TABLE_IDLE_CYCLE_LIMIT_DECREMENTED",
+     .udesc  = "Page table idle cycle limit decremented.",
+     .ucode = 0x8,
+   },
+   { .uname  = "PAGE_TABLE_CLOSED_INACTIVITY",
+     .udesc  = "Page table is closed due to row inactivity.",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_memory_controller_slot_misses[]={
+   { .uname  = "DCT0_RBD",
+     .udesc  = "DCT0 RBD.",
+     .ucode = 0x10,
+   },
+   { .uname  = "DCT1_RBD",
+     .udesc  = "DCT1 RBD.",
+     .ucode = 0x20,
+   },
+   { .uname  = "DCT0_PREFETCH",
+     .udesc  = "DCT0 Prefetch.",
+     .ucode = 0x40,
+   },
+   { .uname  = "DCT1_PREFETCH",
+     .udesc  = "DCT1 Prefetch.",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf0,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_memory_controller_turnarounds[]={
+   { .uname  = "DCT0_READ_TO_WRITE",
+     .udesc  = "DCT0 read-to-write turnaround.",
+     .ucode = 0x1,
+   },
+   { .uname  = "DCT0_WRITE_TO_READ",
+     .udesc  = "DCT0 write-to-read turnaround",
+     .ucode = 0x2,
+   },
+   { .uname  = "DCT1_READ_TO_WRITE",
+     .udesc  = "DCT1 read-to-write turnaround.",
+     .ucode = 0x8,
+   },
+   { .uname  = "DCT1_WRITE_TO_READ",
+     .udesc  = "DCT1 write-to-read turnaround",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1b,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_memory_rbd_queue[]={
+   { .uname  = "COUNTER_REACHED",
+     .udesc  = "D18F2x[1,0]94[DcqBypassMax] counter reached.",
+     .ucode = 0x4,
+   },
+   { .uname  = "BANK_CLOSED",
+     .udesc  = "Bank is closed due to bank conflict with an outstanding request in the RBD queue.",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xc,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_thermal_status[]={
+   { .uname  = "MEMHOT_L_ASSERTIONS",
+     .udesc  = "MEMHOT_L assertions.",
+     .ucode = 0x1,
+   },
+   { .uname  = "HTC_TRANSITIONS",
+     .udesc  = "Number of times the HTC transitions from inactive to active.",
+     .ucode = 0x4,
+   },
+   { .uname  = "CLOCKS_HTC_P_STATE_INACTIVE",
+     .udesc  = "Number of clocks HTC P-state is inactive.",
+     .ucode = 0x20,
+   },
+   { .uname  = "CLOCKS_HTC_P_STATE_ACTIVE",
+     .udesc  = "Number of clocks HTC P-state is active",
+     .ucode = 0x40,
+   },
+   { .uname  = "PROCHOT_L_ASSERTIONS",
+     .udesc  = "PROCHOT_L asserted by an external source and the assertion causes a P-state change.",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xe5,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_cpu_io_requests_to_memory_io[]={
+   { .uname  = "I_O_TO_I_O",
+     .udesc  = "IO to IO",
+     .ucode = 0x1,
+   },
+   { .uname  = "I_O_TO_MEM",
+     .udesc  = "IO to Mem",
+     .ucode = 0x2,
+   },
+   { .uname  = "CPU_TO_I_O",
+     .udesc  = "CPU to IO",
+     .ucode = 0x4,
+   },
+   { .uname  = "CPU_TO_MEM",
+     .udesc  = "CPU to Mem",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x0f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_cache_block[]={
+   { .uname  = "VICTIM_WRITEBACK",
+     .udesc  = "Victim Block (Writeback)",
+     .ucode = 0x1,
+   },
+   { .uname  = "DCACHE_LOAD_MISS",
+     .udesc  = "Read Block (Dcache load miss refill)",
+     .ucode = 0x4,
+   },
+   { .uname  = "SHARED_ICACHE_REFILL",
+     .udesc  = "Read Block Shared (Icache refill)",
+     .ucode = 0x8,
+   },
+   { .uname  = "READ_BLOCK_MODIFIED",
+     .udesc  = "Read Block Modified (Dcache store miss refill)",
+     .ucode = 0x10,
+   },
+   { .uname  = "READ_TO_DIRTY",
+     .udesc  = "Change-to-Dirty (first store to clean block already in cache)",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3d,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_sized_commands[]={
+   { .uname  = "NON_POSTED_WRITE_BYTE",
+     .udesc  = "Non-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytes",
+     .ucode = 0x1,
+   },
+   { .uname  = "NON_POSTED_WRITE_DWORD",
+     .udesc  = "Non-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORD",
+     .ucode = 0x2,
+   },
+   { .uname  = "POSTED_WRITE_BYTE",
+     .udesc  = "Posted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer",
+     .ucode = 0x4,
+   },
+   { .uname  = "POSTED_WRITE_DWORD",
+     .udesc  = "Posted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes",
+     .ucode = 0x8,
+   },
+   { .uname  = "READ_BYTE_4_BYTES",
+     .udesc  = "SzRd Byte (4 bytes) Legacy or mapped IO",
+     .ucode = 0x10,
+   },
+   { .uname  = "READ_DWORD_1_16_DWORDS",
+     .udesc  = "SzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_probe[]={
+   { .uname  = "MISS",
+     .udesc  = "Probe miss",
+     .ucode = 0x1,
+   },
+   { .uname  = "HIT_CLEAN",
+     .udesc  = "Probe hit clean",
+     .ucode = 0x2,
+   },
+   { .uname  = "HIT_DIRTY_NO_MEMORY_CANCEL",
+     .udesc  = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)",
+     .ucode = 0x4,
+   },
+   { .uname  = "HIT_DIRTY_WITH_MEMORY_CANCEL",
+     .udesc  = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)",
+     .ucode = 0x8,
+   },
+   { .uname  = "UPSTREAM_HIGH_PRIORITY_READS",
+     .udesc  = "Upstream high priority reads.",
+     .ucode = 0x10,
+   },
+   { .uname  = "UPSTREAM_LOW_PRIORITY_READS",
+     .udesc  = "Upstream low priority reads.",
+     .ucode = 0x20,
+   },
+   { .uname  = "UPSTREAM_LOW_PRIORITY_WRITES",
+     .udesc  = "Upstream low priority writes.",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xbf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_dev[]={
+   { .uname  = "DEV_HIT",
+     .udesc  = "DEV hit",
+     .ucode = 0x10,
+   },
+   { .uname  = "DEV_MISS",
+     .udesc  = "DEV miss",
+     .ucode = 0x20,
+   },
+   { .uname  = "DEV_ERROR",
+     .udesc  = "DEV error",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x70,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_memory_controller_requests[]={
+   { .uname  = "32_BYTES_WRITES",
+     .udesc  = "32 Bytes Sized Writes",
+     .ucode = 0x8,
+   },
+   { .uname  = "64_BYTES_WRITES",
+     .udesc  = "64 Bytes Sized Writes",
+     .ucode = 0x10,
+   },
+   { .uname  = "32_BYTES_READS",
+     .udesc  = "32 Bytes Sized Reads",
+     .ucode = 0x20,
+   },
+   { .uname  = "64_BYTES_READS",
+     .udesc  = "64 Byte Sized Reads",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x78,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam12h_page_size_mismatches[]={
+   { .uname  = "GUEST_LARGER",
+     .udesc  = "Guest page size is larger than the host page size.",
+     .ucode = 0x1,
+   },
+   { .uname  = "MTRR_MISMATCH",
+     .udesc  = "MTRR mismatch.",
+     .ucode = 0x2,
+   },
+   { .uname  = "HOST_LARGER",
+     .udesc  = "Host page size is larger than the guest page size.",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+static const amd64_umask_t amd64_fam12h_retired_x87_ops[]={
+   { .uname  = "ADD_SUB_OPS",
+     .udesc  = "Add/subtract ops",
+     .ucode = 0x1,
+   },
+   { .uname  = "MUL_OPS",
+     .udesc  = "Multiply ops",
+     .ucode = 0x2,
+   },
+   { .uname  = "DIV_OPS",
+     .udesc  = "Divide ops",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_entry_t amd64_fam12h_pe[]={
+{ .name    = "DISPATCHED_FPU",
+  .desc    = "Dispatched FPU Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_dispatched_fpu),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_dispatched_fpu,
+},
+{ .name    = "CYCLES_NO_FPU_OPS_RETIRED",
+  .desc    = "Cycles in which the FPU is Empty",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1,
+},
+{ .name    = "DISPATCHED_FPU_OPS_FAST_FLAG",
+  .desc    = "Dispatched Fast Flag FPU Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x2,
+},
+{ .name    = "RETIRED_SSE_OPERATIONS",
+  .desc    = "Retired SSE Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x3,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_sse_operations),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_retired_sse_operations,
+},
+{ .name    = "RETIRED_MOVE_OPS",
+  .desc    = "Retired Move Ops",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_move_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_retired_move_ops,
+},
+{ .name    = "RETIRED_SERIALIZING_OPS",
+  .desc    = "Retired Serializing Ops",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x5,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_serializing_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_retired_serializing_ops,
+},
+{ .name    = "FP_SCHEDULER_CYCLES",
+  .desc    = "Number of Cycles that a Serializing uop is in the FP Scheduler",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x6,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_fp_scheduler_cycles),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_fp_scheduler_cycles,
+},
+{ .name    = "SEGMENT_REGISTER_LOADS",
+  .desc    = "Segment Register Loads",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x20,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_segment_register_loads),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_segment_register_loads,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE",
+  .desc    = "Pipeline Restart Due to Self-Modifying Code",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x21,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_PROBE_HIT",
+  .desc    = "Pipeline Restart Due to Probe Hit",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x22,
+},
+{ .name    = "LS_BUFFER_2_FULL_CYCLES",
+  .desc    = "LS Buffer 2 Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x23,
+},
+{ .name    = "LOCKED_OPS",
+  .desc    = "Locked Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x24,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_locked_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_locked_ops,
+},
+{ .name    = "RETIRED_CLFLUSH_INSTRUCTIONS",
+  .desc    = "Retired CLFLUSH Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x26,
+},
+{ .name    = "RETIRED_CPUID_INSTRUCTIONS",
+  .desc    = "Retired CPUID Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x27,
+},
+{ .name    = "CANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONS",
+  .desc    = "Cancelled Store to Load Forward Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x2a,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_cancelled_store_to_load_forward_operations),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_cancelled_store_to_load_forward_operations,
+},
+{ .name    = "SMIS_RECEIVED",
+  .desc    = "SMIs Received",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x2b,
+},
+{ .name    = "DATA_CACHE_ACCESSES",
+  .desc    = "Data Cache Accesses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x40,
+},
+{ .name    = "DATA_CACHE_MISSES",
+  .desc    = "Data Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x41,
+},
+{ .name    = "DATA_CACHE_REFILLS",
+  .desc    = "Data Cache Refills from L2 or Northbridge",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x42,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_data_cache_refills),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_data_cache_refills,
+},
+{ .name    = "DATA_CACHE_REFILLS_FROM_SYSTEM",
+  .desc    = "Data Cache Refills from the Northbridge",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x43,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_data_cache_refills_from_northbridge),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_data_cache_refills_from_northbridge,
+},
+{ .name    = "DATA_CACHE_LINES_EVICTED",
+  .desc    = "Data Cache Lines Evicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x44,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_data_cache_lines_evicted),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_data_cache_lines_evicted,
+},
+{ .name    = "L1_DTLB_MISS_AND_L2_DTLB_HIT",
+  .desc    = "L1 DTLB Miss and L2 DTLB Hit",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x45,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l1_dtlb_miss_and_l2_dtlb_hit),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_l1_dtlb_miss_and_l2_dtlb_hit,
+},
+{ .name    = "L1_DTLB_AND_L2_DTLB_MISS",
+  .desc    = "L1 DTLB and L2 DTLB Miss",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x46,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l1_dtlb_and_l2_dtlb_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_l1_dtlb_and_l2_dtlb_miss,
+},
+{ .name    = "MISALIGNED_ACCESSES",
+  .desc    = "Misaligned Accesses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x47,
+},
+{ .name    = "MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS",
+  .desc    = "Microarchitectural Late Cancel of an Access",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x48,
+},
+{ .name    = "MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS",
+  .desc    = "Microarchitectural Early Cancel of an Access",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x49,
+},
+{ .name    = "PREFETCH_INSTRUCTIONS_DISPATCHED",
+  .desc    = "Prefetch Instructions Dispatched",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4b,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_prefetch_instructions_dispatched),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_prefetch_instructions_dispatched,
+},
+{ .name    = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS",
+  .desc    = "DCACHE Misses by Locked Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4c,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_dcache_misses_by_locked_instructions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_dcache_misses_by_locked_instructions,
+},
+{ .name    = "L1_DTLB_HIT",
+  .desc    = "L1 DTLB Hit",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4d,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l1_dtlb_hit),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_l1_dtlb_hit,
+},
+{ .name    = "INEFFECTIVE_SW_PREFETCHES",
+  .desc    = "Ineffective Software Prefetches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x52,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_ineffective_sw_prefetches),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_ineffective_sw_prefetches,
+},
+{ .name    = "GLOBAL_TLB_FLUSHES",
+  .desc    = "Global TLB Flushes",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x54,
+},
+{ .name    = "MEMORY_REQUESTS",
+  .desc    = "Memory Requests by Type",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x65,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_requests),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_memory_requests,
+},
+{ .name    = "DATA_PREFETCHES",
+  .desc    = "Data Prefetcher",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x67,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_data_prefetches),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_data_prefetches,
+},
+{ .name    = "NORTHBRIDGE_READ_RESPONSES",
+  .desc    = "Northbridge Read Responses by Coherency State",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x6c,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_northbridge_read_responses),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_northbridge_read_responses,
+},
+{ .name    = "OCTWORDS_WRITTEN_TO_SYSTEM",
+  .desc    = "Octwords Written to System",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x6d,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_octwords_written_to_system),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_octwords_written_to_system,
+},
+{ .name    = "CPU_CLK_UNHALTED",
+  .desc    = "CPU Clocks not Halted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x76,
+},
+{ .name    = "REQUESTS_TO_L2",
+  .desc    = "Requests to L2 Cache",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x7d,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_requests_to_l2),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_requests_to_l2,
+},
+{ .name    = "L2_CACHE_MISS",
+  .desc    = "L2 Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x7e,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l2_cache_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_l2_cache_miss,
+},
+{ .name    = "L2_FILL_WRITEBACK",
+  .desc    = "L2 Fill/Writeback",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x7f,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l2_fill_writeback),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_l2_fill_writeback,
+},
+{ .name    = "PAGE_SIZE_MISMATCHES",
+  .desc    = "Page Size Mismatches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x165,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_page_size_mismatches),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_page_size_mismatches,
+},
+{ .name    = "INSTRUCTION_CACHE_FETCHES",
+  .desc    = "Instruction Cache Fetches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x80,
+},
+{ .name    = "INSTRUCTION_CACHE_MISSES",
+  .desc    = "Instruction Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x81,
+},
+{ .name    = "INSTRUCTION_CACHE_REFILLS_FROM_L2",
+  .desc    = "Instruction Cache Refills from L2",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x82,
+},
+{ .name    = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM",
+  .desc    = "Instruction Cache Refills from System",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x83,
+},
+{ .name    = "L1_ITLB_MISS_AND_L2_ITLB_HIT",
+  .desc    = "L1 ITLB Miss and L2 ITLB Hit",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x84,
+},
+{ .name    = "L1_ITLB_MISS_AND_L2_ITLB_MISS",
+  .desc    = "L1 ITLB Miss and L2 ITLB Miss",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x85,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l1_itlb_miss_and_l2_itlb_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_l1_itlb_miss_and_l2_itlb_miss,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE",
+  .desc    = "Pipeline Restart Due to Instruction Stream Probe",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x86,
+},
+{ .name    = "INSTRUCTION_FETCH_STALL",
+  .desc    = "Instruction Fetch Stall",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x87,
+},
+{ .name    = "RETURN_STACK_HITS",
+  .desc    = "Return Stack Hits",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x88,
+},
+{ .name    = "RETURN_STACK_OVERFLOWS",
+  .desc    = "Return Stack Overflows",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x89,
+},
+{ .name    = "INSTRUCTION_CACHE_VICTIMS",
+  .desc    = "Instruction Cache Victims",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x8b,
+},
+{ .name    = "INSTRUCTION_CACHE_LINES_INVALIDATED",
+  .desc    = "Instruction Cache Lines Invalidated",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x8c,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_instruction_cache_lines_invalidated),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_instruction_cache_lines_invalidated,
+},
+{ .name    = "ITLB_RELOADS",
+  .desc    = "ITLB Reloads",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x99,
+},
+{ .name    = "ITLB_RELOADS_ABORTED",
+  .desc    = "ITLB Reloads Aborted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x9a,
+},
+{ .name    = "RETIRED_INSTRUCTIONS",
+  .desc    = "Retired Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc0,
+},
+{ .name    = "RETIRED_UOPS",
+  .desc    = "Retired uops",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc1,
+},
+{ .name    = "RETIRED_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Branch Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc2,
+},
+{ .name    = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Mispredicted Branch Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc3,
+},
+{ .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Taken Branch Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc4,
+},
+{ .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED",
+  .desc    = "Retired Taken Branch Instructions Mispredicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc5,
+},
+{ .name    = "RETIRED_FAR_CONTROL_TRANSFERS",
+  .desc    = "Retired Far Control Transfers",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc6,
+},
+{ .name    = "RETIRED_BRANCH_RESYNCS",
+  .desc    = "Retired Branch Resyncs",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc7,
+},
+{ .name    = "RETIRED_NEAR_RETURNS",
+  .desc    = "Retired Near Returns",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc8,
+},
+{ .name    = "RETIRED_NEAR_RETURNS_MISPREDICTED",
+  .desc    = "Retired Near Returns Mispredicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc9,
+},
+{ .name    = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED",
+  .desc    = "Retired Indirect Branches Mispredicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xca,
+},
+{ .name    = "RETIRED_MMX_AND_FP_INSTRUCTIONS",
+  .desc    = "Retired MMX/FP Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_mmx_and_fp_instructions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_retired_mmx_and_fp_instructions,
+},
+{ .name    = "INTERRUPTS_MASKED_CYCLES",
+  .desc    = "Interrupts-Masked Cycles",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcd,
+},
+{ .name    = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING",
+  .desc    = "Interrupts-Masked Cycles with Interrupt Pending",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xce,
+},
+{ .name    = "INTERRUPTS_TAKEN",
+  .desc    = "Interrupts Taken",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcf,
+},
+{ .name    = "DECODER_EMPTY",
+  .desc    = "Decoder Empty",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd0,
+},
+{ .name    = "DISPATCH_STALLS",
+  .desc    = "Dispatch Stalls",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd1,
+},
+{ .name    = "DISPATCH_STALL_FOR_BRANCH_ABORT",
+  .desc    = "Dispatch Stall for Branch Abort to Retire",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd2,
+},
+{ .name    = "DISPATCH_STALL_FOR_SERIALIZATION",
+  .desc    = "Dispatch Stall for Serialization",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd3,
+},
+{ .name    = "DISPATCH_STALL_FOR_SEGMENT_LOAD",
+  .desc    = "Dispatch Stall for Segment Load",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd4,
+},
+{ .name    = "DISPATCH_STALL_FOR_REORDER_BUFFER_FULL",
+  .desc    = "Dispatch Stall for Reorder Buffer Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd5,
+},
+{ .name    = "DISPATCH_STALL_FOR_RESERVATION_STATION_FULL",
+  .desc    = "Dispatch Stall for Reservation Station Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd6,
+},
+{ .name    = "DISPATCH_STALL_FOR_FPU_FULL",
+  .desc    = "Dispatch Stall for FPU Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd7,
+},
+{ .name    = "DISPATCH_STALL_FOR_LS_FULL",
+  .desc    = "Dispatch Stall for LS Full",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd8,
+},
+{ .name    = "DISPATCH_STALL_WAITING_FOR_ALL_QUIET",
+  .desc    = "Dispatch Stall Waiting for All Quiet",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xd9,
+},
+{ .name    = "DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNC",
+  .desc    = "Dispatch Stall for Far Transfer or Resync to Retire",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xda,
+},
+{ .name    = "FPU_EXCEPTIONS",
+  .desc    = "FPU Exceptions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_fpu_exceptions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_fpu_exceptions,
+},
+{ .name    = "DR0_BREAKPOINT_MATCHES",
+  .desc    = "DR0 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdc,
+},
+{ .name    = "DR1_BREAKPOINT_MATCHES",
+  .desc    = "DR1 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdd,
+},
+{ .name    = "DR2_BREAKPOINT_MATCHES",
+  .desc    = "DR2 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xde,
+},
+{ .name    = "DR3_BREAKPOINT_MATCHES",
+  .desc    = "DR3 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdf,
+},
+{ .name    = "RETIRED_X87_OPS",
+  .desc    = "Retired x87 Floating Point Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1c0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_x87_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_retired_x87_ops,
+},
+{ .name    = "LFENCE_INST_RETIRED",
+  .desc    = "LFENCE Instructions Retired",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1d3,
+},
+{ .name    = "SFENCE_INST_RETIRED",
+  .desc    = "SFENCE Instructions Retired",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1d4,
+},
+{ .name    = "MFENCE_INST_RETIRED",
+  .desc    = "MFENCE Instructions Retired",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1d5,
+},
+{ .name    = "DRAM_ACCESSES_PAGE",
+  .desc    = "DRAM Accesses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_dram_accesses_page),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_dram_accesses_page,
+},
+{ .name    = "MEMORY_CONTROLLER_0_PAGE",
+  .desc    = "DRAM Controller 0 Page Table Events",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe1,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_page_table_events),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_memory_controller_page_table_events,
+},
+{ .name    = "MEMORY_CONTROLLER_SLOT_MISSES",
+  .desc    = "Memory Controller DRAM Command Slots Missed",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe2,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_slot_misses),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_memory_controller_slot_misses,
+},
+{ .name    = "MEMORY_CONTROLLER_TURNAROUNDS",
+  .desc    = "Memory Controller Turnarounds",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe3,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_turnarounds),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_memory_controller_turnarounds,
+},
+{ .name    = "MEMORY_CONTROLLER_RBD_QUEUE",
+  .desc    = "Memory Controller RBD Queue Events",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe4,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_rbd_queue),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_memory_rbd_queue,
+},
+{ .name    = "MEMORY_CONTROLLER_1_PAGE",
+  .desc    = "DRAM Controller 1 Page Table Events",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe5,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_page_table_events),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_memory_controller_page_table_events,
+},
+{ .name    = "THERMAL_STATUS",
+  .desc    = "Thermal Status",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe8,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_thermal_status),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_thermal_status,
+},
+{ .name    = "CPU_IO_REQUESTS_TO_MEMORY_IO",
+  .desc    = "CPU/IO Requests to Memory/IO",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe9,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_cpu_io_requests_to_memory_io),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_cpu_io_requests_to_memory_io,
+},
+{ .name    = "CACHE_BLOCK",
+  .desc    = "Cache Block Commands",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xea,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_cache_block),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_cache_block,
+},
+{ .name    = "SIZED_COMMANDS",
+  .desc    = "Sized Commands",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xeb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_sized_commands),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_sized_commands,
+},
+{ .name    = "PROBE",
+  .desc    = "Probe Responses and Upstream Requests",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xec,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_probe),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_probe,
+},
+{ .name    = "DEV",
+  .desc    = "DEV Events",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xee,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_dev),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_dev,
+},
+{ .name    = "MEMORY_CONTROLLER_REQUESTS",
+  .desc    = "Memory Controller Requests",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1f0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_requests),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_memory_controller_requests,
+},
+{ .name    = "SIDEBAND_SIGNALS",
+  .desc    = "Sideband Signals and Special Cycles",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1e9,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_sideband_signals),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_sideband_signals,
+},
+{ .name    = "Interrupt Events",
+  .desc    = "Interrupt Events",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1ea,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_interrupt_events),
+  .ngrp    = 1,
+  .umasks  = amd64_fam12h_interrupt_events,
+},
+};
diff --git a/user/perfmon/events/amd64_events_fam14h.h b/user/perfmon/events/amd64_events_fam14h.h
new file mode 100644 (file)
index 0000000..905094a
--- /dev/null
@@ -0,0 +1,1540 @@
+/*
+ * Copyright (c) 2011 Google, Inc
+ * Contributed by Stephane Eranian <eranian@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * This file is part of libpfm, a performance monitoring support library for
+ * applications on Linux.
+ *
+ * This file has been automatically generated.
+ *
+ * PMU: amd64_fam14h (AMD64 Fam14h)
+ */
+
+static const amd64_umask_t amd64_fam14h_dispatched_fpu[]={
+   { .uname  = "PIPE0",
+     .udesc  = "Pipe 0 (fadd, imul, mmx) ops",
+     .ucode = 0x1,
+   },
+   { .uname  = "PIPE1",
+     .udesc  = "Pipe 1 (fmul, store, mmx) ops",
+     .ucode = 0x2,
+   },
+   { .uname  = "ANY",
+     .udesc  = "Pipe 1 and Pipe 0 ops",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_retired_sse_operations[]={
+   { .uname  = "SINGLE_ADD_SUB_OPS",
+     .udesc  = "Single precision add/subtract ops",
+     .ucode = 0x1,
+   },
+   { .uname  = "SINGLE_MUL_OPS",
+     .udesc  = "Single precision multiply ops",
+     .ucode = 0x2,
+   },
+   { .uname  = "SINGLE_DIV_OPS",
+     .udesc  = "Single precision divide/square root ops",
+     .ucode = 0x4,
+   },
+   { .uname  = "DOUBLE_ADD_SUB_OPS",
+     .udesc  = "Double precision add/subtract ops",
+     .ucode = 0x8,
+   },
+   { .uname  = "DOUBLE_MUL_OPS",
+     .udesc  = "Double precision multiply ops",
+     .ucode = 0x10,
+   },
+   { .uname  = "DOUBLE_DIV_OPS",
+     .udesc  = "Double precision divide/square root ops",
+     .ucode = 0x20,
+   },
+   { .uname  = "OP_TYPE",
+     .udesc  = "Op type: 0=uops. 1=FLOPS",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_retired_move_ops[]={
+   { .uname  = "ALL_OTHER_MERGING_MOVE_UOPS",
+     .udesc  = "All other merging move uops",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL_OTHER_MOVE_UOPS",
+     .udesc  = "All other move uops",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xc,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_retired_serializing_ops[]={
+   { .uname  = "SSE_BOTTOM_EXECUTING_UOPS",
+     .udesc  = "SSE bottom-executing uops retired",
+     .ucode = 0x1,
+   },
+   { .uname  = "SSE_BOTTOM_SERIALIZING_UOPS",
+     .udesc  = "SSE bottom-serializing uops retired",
+     .ucode = 0x2,
+   },
+   { .uname  = "X87_BOTTOM_EXECUTING_UOPS",
+     .udesc  = "X87 bottom-executing uops retired",
+     .ucode = 0x4,
+   },
+   { .uname  = "X87_BOTTOM_SERIALIZING_UOPS",
+     .udesc  = "X87 bottom-serializing uops retired",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_retired_x87_fpu_ops[]={
+   { .uname  = "ADD_SUB_OPS",
+     .udesc  = "Add/subtract ops",
+     .ucode = 0x1,
+   },
+   { .uname  = "MULT_OPS",
+     .udesc  = "Multiply ops",
+     .ucode = 0x2,
+   },
+   { .uname  = "DIV_FSQRT_OPS",
+     .udesc  = "Divide and fqsrt ops",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_segment_register_loads[]={
+   { .uname  = "ES",
+     .udesc  = "ES",
+     .ucode = 0x1,
+   },
+   { .uname  = "CS",
+     .udesc  = "CS",
+     .ucode = 0x2,
+   },
+   { .uname  = "SS",
+     .udesc  = "SS",
+     .ucode = 0x4,
+   },
+   { .uname  = "DS",
+     .udesc  = "DS",
+     .ucode = 0x8,
+   },
+   { .uname  = "FS",
+     .udesc  = "FS",
+     .ucode = 0x10,
+   },
+   { .uname  = "GS",
+     .udesc  = "GS",
+     .ucode = 0x20,
+   },
+   { .uname  = "HS",
+     .udesc  = "HS",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_locked_ops[]={
+   { .uname  = "EXECUTED",
+     .udesc  = "Number of locked instructions executed",
+     .ucode = 0x1,
+   },
+   { .uname  = "BUS_LOCK",
+     .udesc  = "Number of cycles to acquire bus lock",
+     .ucode = 0x2,
+   },
+   { .uname  = "UNLOCK_LINE",
+     .udesc  = "Number of cycles to unlock line (not including cache miss)",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_cancelled_store_to_load_forward_operations[]={
+   { .uname  = "ADDRESS_MISMATCHES",
+     .udesc  = "Address mismatches (starting byte not the same).",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORE_IS_SMALLER_THAN_LOAD",
+     .udesc  = "Store is smaller than load.",
+     .ucode = 0x2,
+   },
+   { .uname  = "MISALIGNED",
+     .udesc  = "Misaligned.",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_data_cache_refills[]={
+   { .uname  = "UNCACHEABLE",
+     .udesc  = "From non-cacheable data",
+     .ucode = 0x1,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "From shared lines",
+     .ucode = 0x2,
+   },
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "From exclusive lines",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "From owned lines",
+     .ucode = 0x8,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "From modified lines",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_data_cache_refills_from_nb[]={
+   { .uname  = "UNCACHEABLE",
+     .udesc  = "Uncacheable data",
+     .ucode = 0x1,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x2,
+   },
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x8,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_data_cache_lines_evicted[]={
+   { .uname  = "PROBE",
+     .udesc  = "Eviction from probe",
+     .ucode = 0x1,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared eviction",
+     .ucode = 0x2,
+   },
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive eviction",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned eviction",
+     .ucode = 0x8,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified eviction",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_dtlb_miss[]={
+   { .uname  = "STORES_L1TLB_MISS",
+     .udesc  = "Stores that miss L1TLB",
+     .ucode = 0x1,
+   },
+   { .uname  = "LOADS_L1TLB_MISS",
+     .udesc  = "Loads that miss L1TLB",
+     .ucode = 0x2,
+   },
+   { .uname  = "STORES_L2TLB_MISS",
+     .udesc  = "Stores that miss L2TLB",
+     .ucode = 0x4,
+   },
+   { .uname  = "LOADS_L2TLB_MISS",
+     .udesc  = "Loads that miss L2TLB",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_prefetch_instructions_dispatched[]={
+   { .uname  = "LOAD",
+     .udesc  = "Load (Prefetch, PrefetchT0/T1/T2)",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORE",
+     .udesc  = "Store (PrefetchW)",
+     .ucode = 0x2,
+   },
+   { .uname  = "NTA",
+     .udesc  = "NTA (PrefetchNTA)",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_l1_dtlb_hit[]={
+   { .uname  = "L1_4K_TLB_HIT",
+     .udesc  = "L1 4K TLB hit",
+     .ucode = 0x1,
+   },
+   { .uname  = "L1_2M_TLB_HIT",
+     .udesc  = "L1 2M TLB hit",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_dcache_sw_prefetches[]={
+   { .uname  = "HIT",
+     .udesc  = "SW prefetch hit in the data cache",
+     .ucode = 0x1,
+   },
+   { .uname  = "PENDING_FILL",
+     .udesc  = "SW prefetch hit a pending fill",
+     .ucode = 0x2,
+   },
+   { .uname  = "NO_MAB",
+     .udesc  = "SW prefetch does not get a MAB",
+     .ucode = 0x4,
+   },
+   { .uname  = "L2_HIT",
+     .udesc  = "SW prefetch hits L2",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_memory_requests[]={
+   { .uname  = "NON_CACHEABLE",
+     .udesc  = "Requests to non-cacheable (UC) memory",
+     .ucode = 0x1,
+   },
+   { .uname  = "WRITE_COMBINING",
+     .udesc  = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory",
+     .ucode = 0x2,
+   },
+   { .uname  = "STREAMING_STORE",
+     .udesc  = "Streaming store (SS) requests",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x83,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_mab_requests[]={
+   { .uname  = "DC_BUFFER_0",
+     .udesc  = "Data cache buffer 0",
+     .ucode = 0x0,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "DC_BUFFER_1",
+     .udesc  = "Data cache buffer 1",
+     .ucode = 0x1,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "DC_BUFFER_2",
+     .udesc  = "Data cache buffer 2",
+     .ucode = 0x2,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "DC_BUFFER_3",
+     .udesc  = "Data cache buffer 3",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "DC_BUFFER_4",
+     .udesc  = "Data cache buffer 4",
+     .ucode = 0x4,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "DC_BUFFER_5",
+     .udesc  = "Data cache buffer 5",
+     .ucode = 0x5,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "DC_BUFFER_6",
+     .udesc  = "Data cache buffer 6",
+     .ucode = 0x6,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "DC_BUFFER_7",
+     .udesc  = "Data cache buffer 7",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "IC_BUFFER_0",
+     .udesc  = "Instruction cache Buffer 1",
+     .ucode = 0x8,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "IC_BUFFER_1",
+     .udesc  = "Instructions cache buffer 1",
+     .ucode = 0x9,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "ANY_IC_BUFFER",
+     .udesc  = "Any instruction cache buffer",
+     .ucode = 0xa,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "ANY_DC_BUFFER",
+     .udesc  = "Any data cache buffer",
+     .ucode = 0xb,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_system_read_responses[]={
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x1,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified",
+     .ucode = 0x2,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x8,
+   },
+   { .uname  = "DATA_ERROR",
+     .udesc  = "Data Error",
+     .ucode = 0x10,
+   },
+   { .uname  = "DIRTY_SUCCESS",
+     .udesc  = "Change-to-dirty success",
+     .ucode = 0x20,
+   },
+   { .uname  = "UNCACHEABLE",
+     .udesc  = "Uncacheable",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_requests_to_l2[]={
+   { .uname  = "INSTRUCTIONS",
+     .udesc  = "IC fill",
+     .ucode = 0x1,
+   },
+   { .uname  = "DATA",
+     .udesc  = "DC fill",
+     .ucode = 0x2,
+   },
+   { .uname  = "SNOOP",
+     .udesc  = "Tag snoop request",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xb,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_l2_cache_miss[]={
+   { .uname  = "INSTRUCTIONS",
+     .udesc  = "IC fill",
+     .ucode = 0x1,
+   },
+   { .uname  = "DATA",
+     .udesc  = "DC fill (includes possible replays, whereas EventSelect 041h does not)",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_l2_fill_writeback[]={
+   { .uname  = "L2_FILLS",
+     .udesc  = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)",
+     .ucode = 0x1,
+   },
+   { .uname  = "L2_WRITEBACKS",
+     .udesc  = "L2 Writebacks to system.",
+     .ucode = 0x2,
+   },
+   { .uname  = "IC_ATTR_WRITES_L2_ACCESS",
+     .udesc  = "Ic attribute writes which access the L2",
+     .ucode = 0x4,
+   },
+   { .uname  = "IC_ATTR_WRITES_L2_WRITES",
+     .udesc  = "Ic attribute writes which store into the L2",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_l1_itlb_miss_and_l2_itlb_miss[]={
+   { .uname  = "4K_PAGE_FETCHES",
+     .udesc  = "Instruction fetches to a 4K page.",
+     .ucode = 0x1,
+   },
+   { .uname  = "2M_PAGE_FETCHES",
+     .udesc  = "Instruction fetches to a 2M page.",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_instruction_cache_lines_invalidated[]={
+   { .uname  = "INVALIDATING_LS_PROBE",
+     .udesc  = "IC invalidate due to an LS probe",
+     .ucode = 0x1,
+   },
+   { .uname  = "INVALIDATING_BU_PROBE",
+     .udesc  = "IC invalidate due to a BU probe",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_retired_floating_point_instructions[]={
+   { .uname  = "X87",
+     .udesc  = "X87 or MMX instructions",
+     .ucode = 0x1,
+   },
+   { .uname  = "SSE",
+     .udesc  = "SSE (SSE, SSE2, SSE3, MNI) instructions",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_fpu_exceptions[]={
+   { .uname  = "X87_RECLASS_MICROFAULTS",
+     .udesc  = "X87 reclass microfaults",
+     .ucode = 0x1,
+   },
+   { .uname  = "SSE_RETYPE_MICROFAULTS",
+     .udesc  = "SSE retype microfaults",
+     .ucode = 0x2,
+   },
+   { .uname  = "SSE_RECLASS_MICROFAULTS",
+     .udesc  = "SSE reclass microfaults",
+     .ucode = 0x4,
+   },
+   { .uname  = "SSE_AND_X87_MICROTRAPS",
+     .udesc  = "SSE and x87 microtraps",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_dram_accesses_page[]={
+   { .uname  = "HIT",
+     .udesc  = "DCT0 Page hit",
+     .ucode = 0x1,
+   },
+   { .uname  = "MISS",
+     .udesc  = "DCT0 Page Miss",
+     .ucode = 0x2,
+   },
+   { .uname  = "CONFLICT",
+     .udesc  = "DCT0 Page Conflict",
+     .ucode = 0x4,
+   },
+   { .uname  = "WRITE_REQUEST",
+     .udesc  = "Write request",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x47,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_memory_controller_page_table[]={
+   { .uname  = "DCT0_PAGE_TABLE_OVERFLOW",
+     .udesc  = "DCT0 Page Table Overflow",
+     .ucode = 0x1,
+   },
+   { .uname  = "DCT0_PAGE_TABLE_STALE_HIT",
+     .udesc  = "DCT0 number of stale table entry hits (hit on a page closed too soon)",
+     .ucode = 0x2,
+   },
+   { .uname  = "DCT0_PAGE_TABLE_IDLE_INC",
+     .udesc  = "DCT0 page table idle cycle limit incremented",
+     .ucode = 0x4,
+   },
+   { .uname  = "DCT0_PAGE_TABLE_IDLE_DEC",
+     .udesc  = "DCT0 page table idle cycle limit decremented",
+     .ucode = 0x8,
+   },
+   { .uname  = "DCT0_PAGE_TABLE_CLOSED",
+     .udesc  = "DCT0 page table is closed due to row inactivity",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_memory_controller_slot_misses[]={
+   { .uname  = "DCT0_RBD",
+     .udesc  = "DCT0 RBD",
+     .ucode = 0x10,
+   },
+   { .uname  = "DCT0_PREFETCH",
+     .udesc  = "DCT0 prefetch",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x50,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_memory_controller_rbd_queue_events[]={
+   { .uname  = "DCQ_BYPASS_MAX",
+     .udesc  = "DCQ_BYPASS_MAX counter reached",
+     .ucode = 0x4,
+   },
+   { .uname  = "BANK_CLOSED",
+     .udesc  = "Bank is closed due to bank conflict with an outstanding request in the RBD queue",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xc,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_thermal_status[]={
+   { .uname  = "MEMHOT_L",
+     .udesc  = "MEMHOT_L assertions",
+     .ucode = 0x1,
+   },
+   { .uname  = "HTC_TRANSITION",
+     .udesc  = "Number of times HTC transitions from inactive to active",
+     .ucode = 0x4,
+   },
+   { .uname  = "CLOCKS_HTC_P_STATE_INACTIVE",
+     .udesc  = "Number of clocks HTC P-state is inactive.",
+     .ucode = 0x20,
+   },
+   { .uname  = "CLOCKS_HTC_P_STATE_ACTIVE",
+     .udesc  = "Number of clocks HTC P-state is active",
+     .ucode = 0x40,
+   },
+   { .uname  = "PROCHOT_L",
+     .udesc  = "PROCHOT_L asserted by an external source and the assertion causes a P-state change",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xc5,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_cpu_io_requests_to_memory_io[]={
+   { .uname  = "I_O_TO_I_O",
+     .udesc  = "IO to IO",
+     .ucode = 0x1,
+   },
+   { .uname  = "I_O_TO_MEM",
+     .udesc  = "IO to Mem",
+     .ucode = 0x2,
+   },
+   { .uname  = "CPU_TO_I_O",
+     .udesc  = "CPU to IO",
+     .ucode = 0x4,
+   },
+   { .uname  = "CPU_TO_MEM",
+     .udesc  = "CPU to Mem",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_cache_block[]={
+   { .uname  = "VICTIM_WRITEBACK",
+     .udesc  = "Victim Block (Writeback)",
+     .ucode = 0x1,
+   },
+   { .uname  = "DCACHE_LOAD_MISS",
+     .udesc  = "Read Block (Dcache load miss refill)",
+     .ucode = 0x4,
+   },
+   { .uname  = "SHARED_ICACHE_REFILL",
+     .udesc  = "Read Block Shared (Icache refill)",
+     .ucode = 0x8,
+   },
+   { .uname  = "READ_BLOCK_MODIFIED",
+     .udesc  = "Read Block Modified (Dcache store miss refill)",
+     .ucode = 0x10,
+   },
+   { .uname  = "CHANGE_TO_DIRTY",
+     .udesc  = "Change-to-Dirty (first store to clean block already in cache)",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3d,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_sized_commands[]={
+   { .uname  = "NON_POSTED_WRITE_BYTE",
+     .udesc  = "Non-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytes",
+     .ucode = 0x1,
+   },
+   { .uname  = "NON_POSTED_WRITE_DWORD",
+     .udesc  = "Non-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORD",
+     .ucode = 0x2,
+   },
+   { .uname  = "POSTED_WRITE_BYTE",
+     .udesc  = "Posted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer",
+     .ucode = 0x4,
+   },
+   { .uname  = "POSTED_WRITE_DWORD",
+     .udesc  = "Posted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes",
+     .ucode = 0x8,
+   },
+   { .uname  = "READ_BYTE_4_BYTES",
+     .udesc  = "SzRd Byte (4 bytes) Legacy or mapped IO",
+     .ucode = 0x10,
+   },
+   { .uname  = "READ_DWORD_1_16_DWORDS",
+     .udesc  = "SzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_probe[]={
+   { .uname  = "MISS",
+     .udesc  = "Probe miss",
+     .ucode = 0x1,
+   },
+   { .uname  = "HIT_CLEAN",
+     .udesc  = "Probe hit clean",
+     .ucode = 0x2,
+   },
+   { .uname  = "HIT_DIRTY_NO_MEMORY_CANCEL",
+     .udesc  = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)",
+     .ucode = 0x4,
+   },
+   { .uname  = "HIT_DIRTY_WITH_MEMORY_CANCEL",
+     .udesc  = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)",
+     .ucode = 0x8,
+   },
+   { .uname  = "UPSTREAM_HIGH_PRIO_READS",
+     .udesc  = "Upstream high priority reads",
+     .ucode = 0x10,
+   },
+   { .uname  = "UPSTREAM_LOW_PRIO_READS",
+     .udesc  = "Upstream low priority reads",
+     .ucode = 0x20,
+   },
+   { .uname  = "UPSTREAM_LOW_PRIO_WRITES",
+     .udesc  = "Upstream non-ISOC writes",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xbf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_dev_events[]={
+   { .uname  = "HIT",
+     .udesc  = "DEV hit",
+     .ucode = 0x10,
+   },
+   { .uname  = "MISS",
+     .udesc  = "DEV miss",
+     .ucode = 0x20,
+   },
+   { .uname  = "ERROR",
+     .udesc  = "DEV error",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x70,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_memory_controller_requests[]={
+   { .uname  = "32_BYTES_WRITES",
+     .udesc  = "32 Bytes Sized Writes",
+     .ucode = 0x8,
+   },
+   { .uname  = "64_BYTES_WRITES",
+     .udesc  = "64 Bytes Sized Writes",
+     .ucode = 0x10,
+   },
+   { .uname  = "32_BYTES_READS",
+     .udesc  = "32 Bytes Sized Reads",
+     .ucode = 0x20,
+   },
+   { .uname  = "64_BYTES_READS",
+     .udesc  = "64 Byte Sized Reads",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x78,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_sideband_signals_special_signals[]={
+   { .uname  = "STOPGRANT",
+     .udesc  = "Stopgrant",
+     .ucode = 0x2,
+   },
+   { .uname  = "SHUTDOWN",
+     .udesc  = "Shutdown",
+     .ucode = 0x4,
+   },
+   { .uname  = "WBINVD",
+     .udesc  = "Wbinvd",
+     .ucode = 0x8,
+   },
+   { .uname  = "INVD",
+     .udesc  = "Invd",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1c,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_interrupt_events[]={
+   { .uname  = "FIXED_AND_LPA",
+     .udesc  = "Fixed and LPA",
+     .ucode = 0x1,
+   },
+   { .uname  = "LPA",
+     .udesc  = "LPA",
+     .ucode = 0x2,
+   },
+   { .uname  = "SMI",
+     .udesc  = "SMI",
+     .ucode = 0x4,
+   },
+   { .uname  = "NMI",
+     .udesc  = "NMI",
+     .ucode = 0x8,
+   },
+   { .uname  = "INIT",
+     .udesc  = "INIT",
+     .ucode = 0x10,
+   },
+   { .uname  = "STARTUP",
+     .udesc  = "STARTUP",
+     .ucode = 0x20,
+   },
+   { .uname  = "INT",
+     .udesc  = "INT",
+     .ucode = 0x40,
+   },
+   { .uname  = "EOI",
+     .udesc  = "EOI",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam14h_pdc_miss[]={
+   { .uname  = "HOST_PDE_LEVEL",
+     .udesc  = "Host PDE level",
+     .ucode = 0x1,
+   },
+   { .uname  = "HOST_PDPE_LEVEL",
+     .udesc  = "Host PDPE level",
+     .ucode = 0x2,
+   },
+   { .uname  = "HOST_PML4E_LEVEL",
+     .udesc  = "Host PML4E level",
+     .ucode = 0x4,
+   },
+   { .uname  = "GUEST_PDE_LEVEL",
+     .udesc  = "Guest PDE level",
+     .ucode = 0x10,
+   },
+   { .uname  = "GUEST_PDPE_LEVEL",
+     .udesc  = "Guest PDPE level",
+     .ucode = 0x20,
+   },
+   { .uname  = "GUEST_PML4E_LEVEL",
+     .udesc  = "Guest PML4E level",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x67,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_entry_t amd64_fam14h_pe[]={
+{ .name    = "DISPATCHED_FPU",
+  .desc    = "Number of uops dispatched to FPU execution pipelines",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_dispatched_fpu),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_dispatched_fpu,
+},
+{ .name    = "CYCLES_NO_FPU_OPS_RETIRED",
+  .desc    = "Cycles in which the FPU is Empty",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1,
+},
+{ .name    = "DISPATCHED_FPU_OPS_FAST_FLAG",
+  .desc    = "Dispatched Fast Flag FPU Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x2,
+},
+{ .name    = "RETIRED_SSE_OPERATIONS",
+  .desc    = "Retired SSE Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x3,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_retired_sse_operations),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_retired_sse_operations,
+},
+{ .name    = "RETIRED_MOVE_OPS",
+  .desc    = "Retired Move Ops",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_retired_move_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_retired_move_ops,
+},
+{ .name    = "RETIRED_SERIALIZING_OPS",
+  .desc    = "Retired Serializing Ops",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x5,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_retired_serializing_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_retired_serializing_ops,
+},
+{ .name    = "RETIRED_X87_FPU_OPS",
+  .desc    = "Number of x87 floating points ops that have retired",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x11,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_retired_x87_fpu_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_retired_x87_fpu_ops,
+},
+{ .name    = "SEGMENT_REGISTER_LOADS",
+  .desc    = "Segment Register Loads",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x20,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_segment_register_loads),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_segment_register_loads,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE",
+  .desc    = "Pipeline Restart Due to Self-Modifying Code",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x21,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_PROBE_HIT",
+  .desc    = "Pipeline Restart Due to Probe Hit",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x22,
+},
+{ .name    = "RSQ_FULL",
+  .desc    = "Number of cycles that the RSQ holds retired stores. This buffer holds the stores waiting to retired as well as requests that missed the data cache and waiting on a refill",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x23,
+},
+{ .name    = "LOCKED_OPS",
+  .desc    = "Locked Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x24,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_locked_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_locked_ops,
+},
+{ .name    = "RETIRED_CLFLUSH_INSTRUCTIONS",
+  .desc    = "Retired CLFLUSH Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x26,
+},
+{ .name    = "RETIRED_CPUID_INSTRUCTIONS",
+  .desc    = "Retired CPUID Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x27,
+},
+{ .name    = "CANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONS",
+  .desc    = "Cancelled Store to Load Forward Operations",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x2a,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_cancelled_store_to_load_forward_operations),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_cancelled_store_to_load_forward_operations,
+},
+{ .name    = "DATA_CACHE_ACCESSES",
+  .desc    = "Data Cache Accesses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x40,
+},
+{ .name    = "DATA_CACHE_MISSES",
+  .desc    = "Data Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x41,
+},
+{ .name    = "DATA_CACHE_REFILLS",
+  .desc    = "Data Cache Refills from L2 or Northbridge",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x42,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_data_cache_refills),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_data_cache_refills,
+},
+{ .name    = "DATA_CACHE_REFILLS_FROM_NB",
+  .desc    = "Data Cache Refills from the Northbridge",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x43,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_data_cache_refills_from_nb),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_data_cache_refills_from_nb,
+},
+{ .name    = "DATA_CACHE_LINES_EVICTED",
+  .desc    = "Data Cache Lines Evicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x44,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_data_cache_lines_evicted),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_data_cache_lines_evicted,
+},
+{ .name    = "L1_DTLB_MISS_AND_L2_DTLB_HIT",
+  .desc    = "Number of data cache accesses that miss in the L1 DTLB and hit the L2 DTLB. This is a speculative event",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x45,
+},
+{ .name    = "DTLB_MISS",
+  .desc    = "L1 DTLB and L2 DTLB Miss",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x46,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_dtlb_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_dtlb_miss,
+},
+{ .name    = "MISALIGNED_ACCESSES",
+  .desc    = "Misaligned Accesses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x47,
+},
+{ .name    = "PREFETCH_INSTRUCTIONS_DISPATCHED",
+  .desc    = "Prefetch Instructions Dispatched",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4b,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_prefetch_instructions_dispatched),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_prefetch_instructions_dispatched,
+},
+{ .name    = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS",
+  .desc    = "DCACHE Misses by Locked Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4c,
+},
+{ .name    = "L1_DTLB_HIT",
+  .desc    = "L1 DTLB Hit",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x4d,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_l1_dtlb_hit),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_l1_dtlb_hit,
+},
+{ .name    = "DCACHE_SW_PREFETCHES",
+  .desc    = "Number of software prefetches that do not cause an actual data cache refill",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x52,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_dcache_sw_prefetches),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_dcache_sw_prefetches,
+},
+{ .name    = "GLOBAL_TLB_FLUSHES",
+  .desc    = "Global TLB Flushes",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x54,
+},
+{ .name    = "MEMORY_REQUESTS",
+  .desc    = "Memory Requests by Type",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x65,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_memory_requests),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_memory_requests,
+},
+{ .name    = "MAB_REQUESTS",
+  .desc    = "Number of L1 I-cache and D-cache misses per buffer. Average latency by combining with MAB_WAIT_CYCLES.",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x68,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_mab_requests),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_mab_requests,
+},
+{ .name    = "MAB_WAIT_CYCLES",
+  .desc    = "Latency of L1 I-cache and D-cache misses per buffer. Average latency by combining with MAB_REQUESTS.",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x69,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_mab_requests),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_mab_requests, /* identical to actual umasks list for this event */
+},
+{ .name    = "SYSTEM_READ_RESPONSES",
+  .desc    = "Northbridge Read Responses by Coherency State",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x6c,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_system_read_responses),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_system_read_responses,
+},
+{ .name    = "CPU_CLK_UNHALTED",
+  .desc    = "CPU Clocks not Halted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x76,
+},
+{ .name    = "REQUESTS_TO_L2",
+  .desc    = "Requests to L2 Cache",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x7d,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_requests_to_l2),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_requests_to_l2,
+},
+{ .name    = "L2_CACHE_MISS",
+  .desc    = "L2 Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x7e,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_l2_cache_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_l2_cache_miss,
+},
+{ .name    = "L2_FILL_WRITEBACK",
+  .desc    = "L2 Fill/Writeback",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x7f,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_l2_fill_writeback),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_l2_fill_writeback,
+},
+{ .name    = "INSTRUCTION_CACHE_FETCHES",
+  .desc    = "Instruction Cache Fetches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x80,
+},
+{ .name    = "INSTRUCTION_CACHE_MISSES",
+  .desc    = "Instruction Cache Misses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x81,
+},
+{ .name    = "INSTRUCTION_CACHE_REFILLS_FROM_L2",
+  .desc    = "Instruction Cache Refills from L2",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x82,
+},
+{ .name    = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM",
+  .desc    = "Instruction Cache Refills from System",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x83,
+},
+{ .name    = "L1_ITLB_MISS_AND_L2_ITLB_MISS",
+  .desc    = "L1 ITLB Miss and L2 ITLB Miss",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x85,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_l1_itlb_miss_and_l2_itlb_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_l1_itlb_miss_and_l2_itlb_miss,
+},
+{ .name    = "INSTRUCTION_FETCH_STALL",
+  .desc    = "Instruction Fetch Stall",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x87,
+},
+{ .name    = "RETURN_STACK_HITS",
+  .desc    = "Return Stack Hits",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x88,
+},
+{ .name    = "RETURN_STACK_OVERFLOWS",
+  .desc    = "Return Stack Overflows",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x89,
+},
+{ .name    = "INSTRUCTION_CACHE_VICTIMS",
+  .desc    = "Instruction Cache Victims",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x8b,
+},
+{ .name    = "INSTRUCTION_CACHE_LINES_INVALIDATED",
+  .desc    = "Instruction Cache Lines Invalidated",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x8c,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_instruction_cache_lines_invalidated),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_instruction_cache_lines_invalidated,
+},
+{ .name    = "ITLB_RELOADS",
+  .desc    = "ITLB Reloads",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x99,
+},
+{ .name    = "ITLB_RELOADS_ABORTED",
+  .desc    = "ITLB Reloads Aborted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x9a,
+},
+{ .name    = "RETIRED_INSTRUCTIONS",
+  .desc    = "Retired Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc0,
+},
+{ .name    = "RETIRED_UOPS",
+  .desc    = "Retired uops",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc1,
+},
+{ .name    = "RETIRED_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Branch Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc2,
+},
+{ .name    = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Mispredicted Branch Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc3,
+},
+{ .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Taken Branch Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc4,
+},
+{ .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED",
+  .desc    = "Retired Taken Branch Instructions Mispredicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc5,
+},
+{ .name    = "RETIRED_FAR_CONTROL_TRANSFERS",
+  .desc    = "Retired Far Control Transfers",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc6,
+},
+{ .name    = "RETIRED_BRANCH_RESYNCS",
+  .desc    = "Retired Branch Resyncs",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc7,
+},
+{ .name    = "RETIRED_NEAR_RETURNS",
+  .desc    = "Retired Near Returns",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc8,
+},
+{ .name    = "RETIRED_NEAR_RETURNS_MISPREDICTED",
+  .desc    = "Retired Near Returns Mispredicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xc9,
+},
+{ .name    = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED",
+  .desc    = "Retired Indirect Branches Mispredicted",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xca,
+},
+{ .name    = "RETIRED_FLOATING_POINT_INSTRUCTIONS",
+  .desc    = "Retired SSE/MMX/FP Instructions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_retired_floating_point_instructions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_retired_floating_point_instructions,
+},
+{ .name    = "INTERRUPTS_MASKED_CYCLES",
+  .desc    = "Interrupts-Masked Cycles",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcd,
+},
+{ .name    = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING",
+  .desc    = "Interrupts-Masked Cycles with Interrupt Pending",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xce,
+},
+{ .name    = "INTERRUPTS_TAKEN",
+  .desc    = "Interrupts Taken",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xcf,
+},
+{ .name    = "FPU_EXCEPTIONS",
+  .desc    = "FPU Exceptions",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_fpu_exceptions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_fpu_exceptions,
+},
+{ .name    = "DR0_BREAKPOINT_MATCHES",
+  .desc    = "DR0 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdc,
+},
+{ .name    = "DR1_BREAKPOINT_MATCHES",
+  .desc    = "DR1 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdd,
+},
+{ .name    = "DR2_BREAKPOINT_MATCHES",
+  .desc    = "DR2 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xde,
+},
+{ .name    = "DR3_BREAKPOINT_MATCHES",
+  .desc    = "DR3 Breakpoint Matches",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xdf,
+},
+{ .name    = "DRAM_ACCESSES_PAGE",
+  .desc    = "DRAM Accesses",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_dram_accesses_page),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_dram_accesses_page,
+},
+{ .name    = "MEMORY_CONTROLLER_PAGE_TABLE",
+  .desc    = "Number of page table events in the local DRAM controller",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe1,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_memory_controller_page_table),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_memory_controller_page_table,
+},
+{ .name    = "MEMORY_CONTROLLER_SLOT_MISSES",
+  .desc    = "Memory Controller DRAM Command Slots Missed",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe2,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_memory_controller_slot_misses),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_memory_controller_slot_misses,
+},
+{ .name    = "MEMORY_CONTROLLER_RBD_QUEUE_EVENTS",
+  .desc    = "Memory Controller Bypass Counter Saturation",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe4,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_memory_controller_rbd_queue_events),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_memory_controller_rbd_queue_events,
+},
+{ .name    = "THERMAL_STATUS",
+  .desc    = "Thermal Status",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe8,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_thermal_status),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_thermal_status,
+},
+{ .name    = "CPU_IO_REQUESTS_TO_MEMORY_IO",
+  .desc    = "CPU/IO Requests to Memory/IO",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xe9,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_cpu_io_requests_to_memory_io),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_cpu_io_requests_to_memory_io,
+},
+{ .name    = "CACHE_BLOCK",
+  .desc    = "Cache Block Commands",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xea,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_cache_block),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_cache_block,
+},
+{ .name    = "SIZED_COMMANDS",
+  .desc    = "Sized Commands",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xeb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_sized_commands),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_sized_commands,
+},
+{ .name    = "PROBE",
+  .desc    = "Probe Responses and Upstream Requests",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xec,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_probe),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_probe,
+},
+{ .name    = "DEV_EVENTS",
+  .desc    = "DEV Events",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0xee,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_dev_events),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_dev_events,
+},
+{ .name    = "MEMORY_CONTROLLER_REQUESTS",
+  .desc    = "Memory Controller Requests",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1f0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_memory_controller_requests),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_memory_controller_requests,
+},
+{ .name    = "SIDEBAND_SIGNALS_SPECIAL_SIGNALS",
+  .desc    = "Sideband signals and special cycles",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1e9,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_sideband_signals_special_signals),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_sideband_signals_special_signals,
+},
+{ .name    = "INTERRUPT_EVENTS",
+  .desc    = "Interrupt events",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x1ea,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_interrupt_events),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_interrupt_events,
+},
+{ .name    = "PDC_MISS",
+  .desc    = "PDC miss",
+  .modmsk  = AMD64_FAM10H_ATTRS,
+  .code    = 0x162,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam14h_pdc_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam14h_pdc_miss,
+},
+};
diff --git a/user/perfmon/events/amd64_events_fam15h.h b/user/perfmon/events/amd64_events_fam15h.h
new file mode 100644 (file)
index 0000000..0b8c17b
--- /dev/null
@@ -0,0 +1,2298 @@
+/*
+ * Copyright (c) 2011 Google, Inc
+ * Contributed by Stephane Eranian <eranian@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * This file is part of libpfm, a performance monitoring support library for
+ * applications on Linux.
+ *
+ * This file has been automatically generated.
+ *
+ * PMU: amd64_fam15h (AMD64 Fam15h Interlagos)
+ *
+ * Based on libpfm patch by Robert Richter <robert.richter@amd.com>:
+ * Family 15h Microarchitecture performance monitor events
+ *
+ * History:
+ *
+ * Apr 29 2011 -- Robert Richter, robert.richter@amd.com:
+ * Source: BKDG for AMD Family 15h Models 00h-0Fh Processors,
+ * 42301, Rev 1.15, April 18, 2011
+ *
+ * Dec 09 2010 -- Robert Richter, robert.richter@amd.com:
+ * Source: BIOS and Kernel Developer's Guide for the AMD Family 15h
+ * Processors, Rev 0.90, May 18, 2010
+ */
+
+#define CORE_SELECT(b) \
+   { .uname  = "CORE_0",\
+     .udesc  = "Measure on Core0",\
+     .ucode = 0 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_1",\
+     .udesc  = "Measure on Core1",\
+     .ucode = 1 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_2",\
+     .udesc  = "Measure on Core2",\
+     .ucode = 2 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_3",\
+     .udesc  = "Measure on Core3",\
+     .ucode = 3 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_4",\
+     .udesc  = "Measure on Core4",\
+     .ucode = 4 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_5",\
+     .udesc  = "Measure on Core5",\
+     .ucode = 5 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_6",\
+     .udesc  = "Measure on Core6",\
+     .ucode = 6 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_7",\
+     .udesc  = "Measure on Core7",\
+     .ucode = 7 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "ANY_CORE",\
+     .udesc  = "Measure on any core",\
+     .ucode = 0xf << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,\
+   }
+
+static const amd64_umask_t amd64_fam15h_dispatched_fpu_ops[]={
+   { .uname  = "OPS_PIPE0",
+     .udesc  = "Total number uops assigned to Pipe 0",
+     .ucode = 0x1,
+   },
+   { .uname  = "OPS_PIPE1",
+     .udesc  = "Total number uops assigned to Pipe 1",
+     .ucode = 0x2,
+   },
+   { .uname  = "OPS_PIPE2",
+     .udesc  = "Total number uops assigned to Pipe 2",
+     .ucode = 0x4,
+   },
+   { .uname  = "OPS_PIPE3",
+     .udesc  = "Total number uops assigned to Pipe 3",
+     .ucode = 0x8,
+   },
+   { .uname  = "OPS_DUAL_PIPE0",
+     .udesc  = "Total number dual-pipe uops assigned to Pipe 0",
+     .ucode = 0x10,
+   },
+   { .uname  = "OPS_DUAL_PIPE1",
+     .udesc  = "Total number dual-pipe uops assigned to Pipe 1",
+     .ucode = 0x20,
+   },
+   { .uname  = "OPS_DUAL_PIPE2",
+     .udesc  = "Total number dual-pipe uops assigned to Pipe 2",
+     .ucode = 0x40,
+   },
+   { .uname  = "OPS_DUAL_PIPE3",
+     .udesc  = "Total number dual-pipe uops assigned to Pipe 3",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_retired_sse_ops[]={
+   { .uname  = "SINGLE_ADD_SUB_OPS",
+     .udesc  = "Single-precision add/subtract FLOPS",
+     .ucode = 0x1,
+   },
+   { .uname  = "SINGLE_MUL_OPS",
+     .udesc  = "Single-precision multiply FLOPS",
+     .ucode = 0x2,
+   },
+   { .uname  = "SINGLE_DIV_OPS",
+     .udesc  = "Single-precision divide/square root FLOPS",
+     .ucode = 0x4,
+   },
+   { .uname  = "SINGLE_MUL_ADD_OPS",
+     .udesc  = "Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS",
+     .ucode = 0x8,
+   },
+   { .uname  = "DOUBLE_ADD_SUB_OPS",
+     .udesc  = "Double precision add/subtract FLOPS",
+     .ucode = 0x10,
+   },
+   { .uname  = "DOUBLE_MUL_OPS",
+     .udesc  = "Double precision multiply FLOPS",
+     .ucode = 0x20,
+   },
+   { .uname  = "DOUBLE_DIV_OPS",
+     .udesc  = "Double precision divide/square root FLOPS",
+     .ucode = 0x40,
+   },
+   { .uname  = "DOUBLE_MUL_ADD_OPS",
+     .udesc  = "Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_move_scalar_optimization[]={
+   { .uname  = "SSE_MOVE_OPS",
+     .udesc  = "Number of SSE Move Ops",
+     .ucode = 0x1,
+   },
+   { .uname  = "SSE_MOVE_OPS_ELIM",
+     .udesc  = "Number of SSE Move Ops eliminated",
+     .ucode = 0x2,
+   },
+   { .uname  = "OPT_CAND",
+     .udesc  = "Number of Ops that are candidates for optimization (Z-bit set or pass)",
+     .ucode = 0x4,
+   },
+   { .uname  = "SCALAR_OPS_OPTIMIZED",
+     .udesc  = "Number of Scalar ops optimized",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_retired_serializing_ops[]={
+   { .uname  = "SSE_RETIRED",
+     .udesc  = "SSE bottom-executing uops retired",
+     .ucode = 0x1,
+   },
+   { .uname  = "SSE_MISPREDICTED",
+     .udesc  = "SSE control word mispredict traps due to mispredictions",
+     .ucode = 0x2,
+   },
+   { .uname  = "X87_RETIRED",
+     .udesc  = "X87 bottom-executing uops retired",
+     .ucode = 0x4,
+   },
+   { .uname  = "X87_MISPREDICTED",
+     .udesc  = "X87 control word mispredict traps due to mispredictions",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_segment_register_loads[]={
+   { .uname  = "ES",
+     .udesc  = "ES",
+     .ucode = 0x1,
+   },
+   { .uname  = "CS",
+     .udesc  = "CS",
+     .ucode = 0x2,
+   },
+   { .uname  = "SS",
+     .udesc  = "SS",
+     .ucode = 0x4,
+   },
+   { .uname  = "DS",
+     .udesc  = "DS",
+     .ucode = 0x8,
+   },
+   { .uname  = "FS",
+     .udesc  = "FS",
+     .ucode = 0x10,
+   },
+   { .uname  = "GS",
+     .udesc  = "GS",
+     .ucode = 0x20,
+   },
+   { .uname  = "HS",
+     .udesc  = "HS",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_load_q_store_q_full[]={
+   { .uname  = "LOAD_QUEUE",
+     .udesc  = "The number of cycles that the load buffer is full",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORE_QUEUE",
+     .udesc  = "The number of cycles that the store buffer is full",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_locked_ops[]={
+   { .uname  = "EXECUTED",
+     .udesc  = "Number of locked instructions executed",
+     .ucode = 0x1,
+   },
+   { .uname  = "CYCLES_NON_SPECULATIVE_PHASE",
+     .udesc  = "Number of cycles spent in non-speculative phase, excluding cache miss penalty",
+     .ucode = 0x4,
+   },
+   { .uname  = "CYCLES_WAITING",
+     .udesc  = "Number of cycles spent in non-speculative phase, including the cache miss penalty",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xd,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_cancelled_store_to_load[]={
+   { .uname  = "SIZE_ADDRESS_MISMATCHES",
+     .udesc  = "Store is smaller than load or different starting byte but partial overlap",
+     .ucode = 0x1,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_data_cache_misses[]={
+   { .uname  = "DC_MISS_STREAMING_STORE",
+     .udesc  = "First data cache miss or streaming store to a 64B cache line",
+     .ucode = 0x1,
+   },
+   { .uname  = "STREAMING_STORE",
+     .udesc  = "First streaming store to a 64B cache line",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_data_cache_refills_from_l2_or_northbridge[]={
+   { .uname  = "GOOD",
+     .udesc  = "Fill with good data. (Final valid status is valid)",
+     .ucode = 0x1,
+   },
+   { .uname  = "INVALID",
+     .udesc  = "Early valid status turned out to be invalid",
+     .ucode = 0x2,
+   },
+   { .uname  = "POISON",
+     .udesc  = "Fill with poison data",
+     .ucode = 0x4,
+   },
+   { .uname  = "READ_ERROR",
+     .udesc  = "Fill with read data error",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_unified_tlb_hit[]={
+   { .uname  = "4K_DATA",
+     .udesc  = "4 KB unified TLB hit for data",
+     .ucode = 0x1,
+   },
+   { .uname  = "2M_DATA",
+     .udesc  = "2 MB unified TLB hit for data",
+     .ucode = 0x2,
+   },
+   { .uname  = "1G_DATA",
+     .udesc  = "1 GB unified TLB hit for data",
+     .ucode = 0x4,
+   },
+   { .uname  = "4K_INST",
+     .udesc  = "4 KB unified TLB hit for instruction",
+     .ucode = 0x10,
+   },
+   { .uname  = "2M_INST",
+     .udesc  = "2 MB unified TLB hit for instruction",
+     .ucode = 0x20,
+   },
+   { .uname  = "1G_INST",
+     .udesc  = "1 GB unified TLB hit for instruction",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x77,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_unified_tlb_miss[]={
+   { .uname  = "4K_DATA",
+     .udesc  = "4 KB unified TLB miss for data",
+     .ucode = 0x1,
+   },
+   { .uname  = "2M_DATA",
+     .udesc  = "2 MB unified TLB miss for data",
+     .ucode = 0x2,
+   },
+   { .uname  = "1GB_DATA",
+     .udesc  = "1 GB unified TLB miss for data",
+     .ucode = 0x4,
+   },
+   { .uname  = "4K_INST",
+     .udesc  = "4 KB unified TLB miss for instruction",
+     .ucode = 0x10,
+   },
+   { .uname  = "2M_INST",
+     .udesc  = "2 MB unified TLB miss for instruction",
+     .ucode = 0x20,
+   },
+   { .uname  = "1G_INST",
+     .udesc  = "1 GB unified TLB miss for instruction",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x77,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_prefetch_instructions_dispatched[]={
+   { .uname  = "LOAD",
+     .udesc  = "Load (Prefetch, PrefetchT0/T1/T2)",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORE",
+     .udesc  = "Store (PrefetchW)",
+     .ucode = 0x2,
+   },
+   { .uname  = "NTA",
+     .udesc  = "NTA (PrefetchNTA)",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_ineffective_sw_prefetches[]={
+   { .uname  = "SW_PREFETCH_HIT_IN_L1",
+     .udesc  = "Software prefetch hit in the L1",
+     .ucode = 0x1,
+   },
+   { .uname  = "SW_PREFETCH_HIT_IN_L2",
+     .udesc  = "Software prefetch hit in the L2",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x9,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_memory_requests[]={
+   { .uname  = "NON_CACHEABLE",
+     .udesc  = "Requests to non-cacheable (UC) memory",
+     .ucode = 0x1,
+   },
+   { .uname  = "WRITE_COMBINING",
+     .udesc  = "Requests to non-cacheable (WC, but not WC+/SS) memory",
+     .ucode = 0x2,
+   },
+   { .uname  = "STREAMING_STORE",
+     .udesc  = "Requests to non-cacheable (WC+/SS, but not WC) memory",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x83,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_data_prefetcher[]={
+   { .uname  = "ATTEMPTED",
+     .udesc  = "Prefetch attempts",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x2,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_mab_reqs[]={
+   { .uname  = "BUFFER_BIT_0",
+     .udesc  = "Buffer entry index bit 0",
+     .ucode = 0x1,
+   },
+   { .uname  = "BUFFER_BIT_1",
+     .udesc  = "Buffer entry index bit 1",
+     .ucode = 0x2,
+   },
+   { .uname  = "BUFFER_BIT_2",
+     .udesc  = "Buffer entry index bit 2",
+     .ucode = 0x4,
+   },
+   { .uname  = "BUFFER_BIT_3",
+     .udesc  = "Buffer entry index bit 3",
+     .ucode = 0x8,
+   },
+   { .uname  = "BUFFER_BIT_4",
+     .udesc  = "Buffer entry index bit 4",
+     .ucode = 0x10,
+   },
+   { .uname  = "BUFFER_BIT_5",
+     .udesc  = "Buffer entry index bit 5",
+     .ucode = 0x20,
+   },
+   { .uname  = "BUFFER_BIT_6",
+     .udesc  = "Buffer entry index bit 6",
+     .ucode = 0x40,
+   },
+   { .uname  = "BUFFER_BIT_7",
+     .udesc  = "Buffer entry index bit 7",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_system_read_responses[]={
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x1,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified (D18F0x68[ATMModeEn]==0), Modified written (D18F0x68[ATMModeEn]==1)",
+     .ucode = 0x2,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x8,
+   },
+   { .uname  = "DATA_ERROR",
+     .udesc  = "Data Error",
+     .ucode = 0x10,
+   },
+   { .uname  = "MODIFIED_UNWRITTEN",
+     .udesc  = "Modified unwritten",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_octword_write_transfers[]={
+   { .uname  = "OCTWORD_WRITE_TRANSFER",
+     .udesc  = "OW write transfer",
+     .ucode = 0x1,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_requests_to_l2[]={
+   { .uname  = "INSTRUCTIONS",
+     .udesc  = "IC fill",
+     .ucode = 0x1,
+   },
+   { .uname  = "DATA",
+     .udesc  = "DC fill",
+     .ucode = 0x2,
+   },
+   { .uname  = "TLB_WALK",
+     .udesc  = "TLB fill (page table walks)",
+     .ucode = 0x4,
+   },
+   { .uname  = "SNOOP",
+     .udesc  = "NB probe request",
+     .ucode = 0x8,
+   },
+   { .uname  = "CANCELLED",
+     .udesc  = "Canceled request",
+     .ucode = 0x10,
+   },
+   { .uname  = "PREFETCHER",
+     .udesc  = "L2 cache prefetcher request",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x5f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_l2_cache_miss[]={
+   { .uname  = "INSTRUCTIONS",
+     .udesc  = "IC fill",
+     .ucode = 0x1,
+   },
+   { .uname  = "DATA",
+     .udesc  = "DC fill (includes possible replays, whereas PMCx041 does not)",
+     .ucode = 0x2,
+   },
+   { .uname  = "TLB_WALK",
+     .udesc  = "TLB page table walk",
+     .ucode = 0x4,
+   },
+   { .uname  = "PREFETCHER",
+     .udesc  = "L2 Cache Prefetcher request",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x17,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_l2_cache_fill_writeback[]={
+   { .uname  = "L2_FILLS",
+     .udesc  = "L2 fills from system",
+     .ucode = 0x1,
+   },
+   { .uname  = "L2_WRITEBACKS",
+     .udesc  = "L2 Writebacks to system (Clean and Dirty)",
+     .ucode = 0x2,
+   },
+   { .uname  = "L2_WRITEBACKS_CLEAN",
+     .udesc  = "L2 Clean Writebacks to system",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_page_splintering[]={
+   { .uname  = "GUEST_LARGER",
+     .udesc  = "Guest page size is larger than host page size when nested paging is enabled",
+     .ucode = 0x1,
+   },
+   { .uname  = "MTRR_MISMATCH",
+     .udesc  = "Splintering due to MTRRs, IORRs, APIC, TOMs or other special address region",
+     .ucode = 0x2,
+   },
+   { .uname  = "HOST_LARGER",
+     .udesc  = "Host page size is larger than the guest page size",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_l1_itlb_miss_and_l2_itlb_miss[]={
+   { .uname  = "4K_PAGE_FETCHES",
+     .udesc  = "Instruction fetches to a 4 KB page",
+     .ucode = 0x1,
+   },
+   { .uname  = "2M_PAGE_FETCHES",
+     .udesc  = "Instruction fetches to a 2 MB page",
+     .ucode = 0x2,
+   },
+   { .uname  = "1G_PAGE_FETCHES",
+     .udesc  = "Instruction fetches to a 1 GB page",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_instruction_cache_invalidated[]={
+   { .uname  = "NON_SMC_PROBE_MISS",
+     .udesc  = "Non-SMC invalidating probe that missed on in-flight instructions",
+     .ucode = 0x1,
+   },
+   { .uname  = "NON_SMC_PROBE_HIT",
+     .udesc  = "Non-SMC invalidating probe that hit on in-flight instructions",
+     .ucode = 0x2,
+   },
+   { .uname  = "SMC_PROBE_MISS",
+     .udesc  = "SMC invalidating probe that missed on in-flight instructions",
+     .ucode = 0x4,
+   },
+   { .uname  = "SMC_PROBE_HIT",
+     .udesc  = "SMC invalidating probe that hit on in-flight instructions",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_retired_mmx_fp_instructions[]={
+   { .uname  = "X87",
+     .udesc  = "X87 instructions",
+     .ucode = 0x1,
+   },
+   { .uname  = "MMX",
+     .udesc  = "MMX(tm) instructions",
+     .ucode = 0x2,
+   },
+   { .uname  = "SSE",
+     .udesc  = "SSE instructions (SSE,SSE2,SSE3,SSSE3,SSE4A,SSE4.1,SSE4.2,AVX,XOP,FMA4)",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_fpu_exceptions[]={
+   { .uname  = "TOTAL_FAULTS",
+     .udesc  = "Total microfaults",
+     .ucode = 0x1,
+   },
+   { .uname  = "TOTAL_TRAPS",
+     .udesc  = "Total microtraps",
+     .ucode = 0x2,
+   },
+   { .uname  = "INT2EXT_FAULTS",
+     .udesc  = "Int2Ext faults",
+     .ucode = 0x4,
+   },
+   { .uname  = "EXT2INT_FAULTS",
+     .udesc  = "Ext2Int faults",
+     .ucode = 0x8,
+   },
+   { .uname  = "BYPASS_FAULTS",
+     .udesc  = "Bypass faults",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_ibs_ops_tagged[]={
+   { .uname  = "TAGGED",
+     .udesc  = "Number of ops tagged by IBS",
+     .ucode = 0x1,
+   },
+   { .uname  = "RETIRED",
+     .udesc  = "Number of ops tagged by IBS that retired",
+     .ucode = 0x2,
+   },
+   { .uname  = "IGNORED",
+     .udesc  = "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_ls_dispatch[]={
+   { .uname  = "LOADS",
+     .udesc  = "Loads",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORES",
+     .udesc  = "Stores",
+     .ucode = 0x2,
+   },
+   { .uname  = "LOAD_OP_STORES",
+     .udesc  = "Load-op-Stores",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_l2_prefetcher_trigger_events[]={
+   { .uname  = "LOAD_L1_MISS_SEEN_BY_PREFETCHER",
+     .udesc  = "Load L1 miss seen by prefetcher",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORE_L1_MISS_SEEN_BY_PREFETCHER",
+     .udesc  = "Store L1 miss seen by prefetcher",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_dram_accesses[]={
+   { .uname = "DCT0_PAGE_HIT",
+     .udesc = "DCT0 Page hit",
+     .ucode = 0x1,
+   },
+   { .uname = "DCT0_PAGE_MISS",
+     .udesc = "DCT0 Page Miss",
+     .ucode = 0x2,
+   },
+   { .uname = "DCT0_PAGE_CONFLICT",
+     .udesc = "DCT0 Page Conflict",
+     .ucode = 0x4,
+   },
+   { .uname = "DCT1_PAGE_HIT",
+     .udesc = "DCT1 Page hit",
+     .ucode = 0x8,
+   },
+   { .uname = "DCT1_PAGE_MISS",
+     .udesc = "DCT1 Page Miss",
+     .ucode = 0x10,
+   },
+   { .uname = "DCT1_PAGE_CONFLICT",
+     .udesc = "DCT1 Page Conflict",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_dram_controller_page_table_overflows[]={
+   { .uname = "DCT0_PAGE_TABLE_OVERFLOW",
+     .udesc = "DCT0 Page Table Overflow",
+     .ucode = 0x1,
+   },
+   { .uname = "DCT1_PAGE_TABLE_OVERFLOW",
+     .udesc = "DCT1 Page Table Overflow",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode  = 0x3,
+     .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_memory_controller_dram_command_slots_missed[]={
+   { .uname = "DCT0_COMMAND_SLOTS_MISSED",
+     .udesc = "DCT0 Command Slots Missed (in MemClks)",
+     .ucode = 0x1,
+   },
+   { .uname = "DCT1_COMMAND_SLOTS_MISSED",
+     .udesc = "DCT1 Command Slots Missed (in MemClks)",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode  = 0x3,
+     .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_memory_controller_turnarounds[]={
+   { .uname = "DCT0_DIMM_TURNAROUND",
+     .udesc = "DCT0 DIMM (chip select) turnaround",
+     .ucode = 0x1,
+   },
+   { .uname = "DCT0_READ_WRITE_TURNAROUND",
+     .udesc = "DCT0 Read to write turnaround",
+     .ucode = 0x2,
+   },
+   { .uname = "DCT0_WRITE_READ_TURNAROUND",
+     .udesc = "DCT0 Write to read turnaround",
+     .ucode = 0x4,
+   },
+   { .uname = "DCT1_DIMM_TURNAROUND",
+     .udesc = "DCT1 DIMM (chip select) turnaround",
+     .ucode = 0x8,
+   },
+   { .uname = "DCT1_READ_WRITE_TURNAROUND",
+     .udesc = "DCT1 Read to write turnaround",
+     .ucode = 0x10,
+   },
+   { .uname = "DCT1_WRITE_READ_TURNAROUND",
+     .udesc = "DCT1 Write to read turnaround",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode  = 0x3f,
+     .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_memory_controller_bypass_counter_saturation[]={
+   { .uname = "MEMORY_CONTROLLER_HIGH_PRIORITY_BYPASS",
+     .udesc = "Memory controller high priority bypass",
+     .ucode = 0x1,
+   },
+   { .uname = "MEMORY_CONTROLLER_MEDIUM_PRIORITY_BYPASS",
+     .udesc = "Memory controller medium priority bypass",
+     .ucode = 0x2,
+   },
+   { .uname = "DCT0_DCQ_BYPASS",
+     .udesc = "DCT0 DCQ bypass",
+     .ucode = 0x4,
+   },
+   { .uname = "DCT1_DCQ_BYPASS",
+     .udesc = "DCT1 DCQ bypass",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode  = 0xf,
+     .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_thermal_status[]={
+   { .uname = "NUM_HTC_TRIP_POINT_CROSSED",
+     .udesc = "Number of times the HTC trip point is crossed",
+     .ucode = 0x4,
+   },
+   { .uname = "NUM_CLOCKS_HTC_PSTATE_INACTIVE",
+     .udesc = "Number of clocks HTC P-state is inactive",
+     .ucode = 0x20,
+   },
+   { .uname = "NUM_CLOCKS_HTC_PSTATE_ACTIVE",
+     .udesc = "Number of clocks HTC P-state is active",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x64,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_cpu_io_requests_to_memory_io[]={
+   { .uname = "REMOTE_IO_TO_LOCAL_IO",
+     .udesc = "Remote IO to Local IO",
+     .ucode = 0x61,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "REMOTE_CPU_TO_LOCAL_IO",
+     .udesc = "Remote CPU to Local IO",
+     .ucode = 0x64,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "LOCAL_IO_TO_REMOTE_IO",
+     .udesc = "Local IO to Remote IO",
+     .ucode = 0x91,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "LOCAL_IO_TO_REMOTE_MEM",
+     .udesc = "Local IO to Remote Mem",
+     .ucode = 0x92,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "LOCAL_CPU_TO_REMOTE_IO",
+     .udesc = "Local CPU to Remote IO",
+     .ucode = 0x94,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "LOCAL_CPU_TO_REMOTE_MEM",
+     .udesc = "Local CPU to Remote Mem",
+     .ucode = 0x98,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "LOCAL_IO_TO_LOCAL_IO",
+     .udesc = "Local IO to Local IO",
+     .ucode = 0xa1,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "LOCAL_IO_TO_LOCAL_MEM",
+     .udesc = "Local IO to Local Mem",
+     .ucode = 0xa2,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "LOCAL_CPU_TO_LOCAL_IO",
+     .udesc = "Local CPU to Local IO",
+     .ucode = 0xa4,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "LOCAL_CPU_TO_LOCAL_MEM",
+     .udesc = "Local CPU to Local Mem",
+     .ucode = 0xa8,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_cache_block_commands[]={
+   { .uname = "VICTIM_BLOCK",
+     .udesc = "Victim Block (Writeback)",
+     .ucode = 0x1,
+   },
+   { .uname = "READ_BLOCK",
+     .udesc = "Read Block (Dcache load miss refill)",
+     .ucode = 0x4,
+   },
+   { .uname = "READ_BLOCK_SHARED",
+     .udesc = "Read Block Shared (Icache refill)",
+     .ucode = 0x8,
+   },
+   { .uname = "READ_BLOCK_MODIFIED",
+     .udesc = "Read Block Modified (Dcache store miss refill)",
+     .ucode = 0x10,
+   },
+   { .uname = "CHANGE_TO_DIRTY",
+     .udesc = "Change-to-Dirty (first store to clean block already in cache)",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode  = 0x3d,
+     .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_sized_commands[]={
+   { .uname = "NON-POSTED_SZWR_BYTE",
+     .udesc = "Non-Posted SzWr Byte (1-32 bytes). Typical Usage: Legacy or mapped IO, typically 1-4 bytes.",
+     .ucode = 0x1,
+   },
+   { .uname = "NON-POSTED_SZWR_DW",
+     .udesc = "Non-Posted SzWr DW (1-16 dwords). Typical Usage: Legacy or mapped IO, typically 1",
+     .ucode = 0x2,
+   },
+   { .uname = "POSTED_SZWR_BYTE",
+     .udesc = "Posted SzWr Byte (1-32 bytes). Typical Usage: Subcache-line DMA writes, size varies; also",
+     .ucode = 0x4,
+   },
+   { .uname = "POSTED_SZWR_DW",
+     .udesc = "Posted SzWr DW (1-16 dwords). Typical Usage: Block-oriented DMA writes, often cache-line",
+     .ucode = 0x8,
+   },
+   { .uname = "SZRD_BYTE",
+     .udesc = "SzRd Byte (4 bytes). Typical Usage: Legacy or mapped IO.",
+     .ucode = 0x10,
+   },
+   { .uname = "SZRD_DW",
+     .udesc = "SzRd DW (1-16 dwords). Typical Usage: Block-oriented DMA reads, typically cache-line size.",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_probe_responses_and_upstream_requests[]={
+   { .uname = "PROBE_MISS",
+     .udesc = "Probe miss",
+     .ucode = 0x1,
+   },
+   { .uname = "PROBE_HIT_CLEAN",
+     .udesc = "Probe hit clean",
+     .ucode = 0x2,
+   },
+   { .uname = "PROBE_HIT_DIRTY_WITHOUT_MEMORY_CANCEL",
+     .udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)",
+     .ucode = 0x4,
+   },
+   { .uname = "PROBE_HIT_DIRTY_WITH_MEMORY_CANCEL",
+     .udesc = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)",
+     .ucode = 0x8,
+   },
+   { .uname = "UPSTREAM_DISPLAY_REFRESH_ISOC_READS",
+     .udesc = "Upstream display refresh/ISOC reads",
+     .ucode = 0x10,
+   },
+   { .uname = "UPSTREAM_NON-DISPLAY_REFRESH_READS",
+     .udesc = "Upstream non-display refresh reads",
+     .ucode = 0x20,
+   },
+   { .uname = "UPSTREAM_ISOC_WRITES",
+     .udesc = "Upstream ISOC writes",
+     .ucode = 0x40,
+   },
+   { .uname = "UPSTREAM_NON-ISOC_WRITES",
+     .udesc = "Upstream non-ISOC writes",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_gart_events[]={
+   { .uname = "GART_APERTURE_HIT_ON_ACCESS_FROM_CPU",
+     .udesc = "GART aperture hit on access from CPU",
+     .ucode = 0x1,
+   },
+   { .uname = "GART_APERTURE_HIT_ON_ACCESS_FROM_IO",
+     .udesc = "GART aperture hit on access from IO",
+     .ucode = 0x2,
+   },
+   { .uname = "GART_MISS",
+     .udesc = "GART miss",
+     .ucode = 0x4,
+   },
+   { .uname = "GART_REQUEST_HIT_TABLE_WALK_IN_PROGRESS",
+     .udesc = "GART Request hit table walk in progress",
+     .ucode = 0x8,
+   },
+   { .uname = "GART_MULTIPLE_TABLE_WALK_IN_PROGRESS",
+     .udesc = "GART multiple table walk in progress",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x8f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_link_transmit_bandwidth[]={
+   { .uname = "COMMAND_DW_SENT",
+     .udesc = "Command DW sent",
+     .ucode = 0x1,
+     .grpid = 0,
+   },
+   { .uname = "DATA_DW_SENT",
+     .udesc = "Data DW sent",
+     .ucode = 0x2,
+     .grpid = 0,
+   },
+   { .uname = "BUFFER_RELEASE_DW_SENT",
+     .udesc = "Buffer release DW sent",
+     .ucode = 0x4,
+     .grpid = 0,
+   },
+   { .uname = "NOP_DW_SENT",
+     .udesc = "NOP DW sent (idle)",
+     .ucode = 0x8,
+     .grpid = 0,
+   },
+   { .uname = "ADDRESS_DW_SENT",
+     .udesc = "Address (including extensions) DW sent",
+     .ucode = 0x10,
+     .grpid = 0,
+   },
+   { .uname = "PER_PACKET_CRC_SENT",
+     .udesc = "Per packet CRC sent",
+     .ucode = 0x20,
+     .grpid = 0,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+     .grpid = 0,
+   },
+   { .uname = "SUBLINK_1",
+     .udesc = "When links are unganged, enable this umask to select sublink 1",
+     .ucode = 0x80,
+     .grpid = 1,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "SUBLINK_0",
+     .udesc = "When links are unganged, enable this umask to select sublink 0 (default when links ganged)",
+     .ucode = 0x00,
+     .grpid = 1,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+
+
+};
+
+static const amd64_umask_t amd64_fam15h_cpu_to_dram_requests_to_target_node[]={
+   { .uname = "LOCAL_TO_NODE_0",
+     .udesc = "From Local node to Node 0",
+     .ucode = 0x1,
+   },
+   { .uname = "LOCAL_TO_NODE_1",
+     .udesc = "From Local node to Node 1",
+     .ucode = 0x2,
+   },
+   { .uname = "LOCAL_TO_NODE_2",
+     .udesc = "From Local node to Node 2",
+     .ucode = 0x4,
+   },
+   { .uname = "LOCAL_TO_NODE_3",
+     .udesc = "From Local node to Node 3",
+     .ucode = 0x8,
+   },
+   { .uname = "LOCAL_TO_NODE_4",
+     .udesc = "From Local node to Node 4",
+     .ucode = 0x10,
+   },
+   { .uname = "LOCAL_TO_NODE_5",
+     .udesc = "From Local node to Node 5",
+     .ucode = 0x20,
+   },
+   { .uname = "LOCAL_TO_NODE_6",
+     .udesc = "From Local node to Node 6",
+     .ucode = 0x40,
+   },
+   { .uname = "LOCAL_TO_NODE_7",
+     .udesc = "From Local node to Node 7",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_io_to_dram_requests_to_target_node[]={
+   { .uname = "LOCAL_TO_NODE_0",
+     .udesc = "From Local node to Node 0",
+     .ucode = 0x1,
+   },
+   { .uname = "LOCAL_TO_NODE_1",
+     .udesc = "From Local node to Node 1",
+     .ucode = 0x2,
+   },
+   { .uname = "LOCAL_TO_NODE_2",
+     .udesc = "From Local node to Node 2",
+     .ucode = 0x4,
+   },
+   { .uname = "LOCAL_TO_NODE_3",
+     .udesc = "From Local node to Node 3",
+     .ucode = 0x8,
+   },
+   { .uname = "LOCAL_TO_NODE_4",
+     .udesc = "From Local node to Node 4",
+     .ucode = 0x10,
+   },
+   { .uname = "LOCAL_TO_NODE_5",
+     .udesc = "From Local node to Node 5",
+     .ucode = 0x20,
+   },
+   { .uname = "LOCAL_TO_NODE_6",
+     .udesc = "From Local node to Node 6",
+     .ucode = 0x40,
+   },
+   { .uname = "LOCAL_TO_NODE_7",
+     .udesc = "From Local node to Node 7",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_cpu_read_command_requests_to_target_node_0_3[]={
+   { .uname = "READ_BLOCK_LOCAL_TO_NODE_0",
+     .udesc = "Read block From Local node to Node 0",
+     .ucode = 0x11,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_0",
+     .udesc = "Read block shared From Local node to Node 0",
+     .ucode = 0x12,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_0",
+     .udesc = "Read block modified From Local node to Node 0",
+     .ucode = 0x14,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_0",
+     .udesc = "Change-to-Dirty From Local node to Node 0",
+     .ucode = 0x18,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_LOCAL_TO_NODE_1",
+     .udesc = "Read block From Local node to Node 1",
+     .ucode = 0x21,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_1",
+     .udesc = "Read block shared From Local node to Node 1",
+     .ucode = 0x22,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_1",
+     .udesc = "Read block modified From Local node to Node 1",
+     .ucode = 0x24,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_1",
+     .udesc = "Change-to-Dirty From Local node to Node 1",
+     .ucode = 0x28,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_LOCAL_TO_NODE_2",
+     .udesc = "Read block From Local node to Node 2",
+     .ucode = 0x41,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_2",
+     .udesc = "Read block shared From Local node to Node 2",
+     .ucode = 0x42,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_2",
+     .udesc = "Read block modified From Local node to Node 2",
+     .ucode = 0x44,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_2",
+     .udesc = "Change-to-Dirty From Local node to Node 2",
+     .ucode = 0x48,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_LOCAL_TO_NODE_3",
+     .udesc = "Read block From Local node to Node 3",
+     .ucode = 0x81,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_3",
+     .udesc = "Read block shared From Local node to Node 3",
+     .ucode = 0x82,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_3",
+     .udesc = "Read block modified From Local node to Node 3",
+     .ucode = 0x84,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_3",
+     .udesc = "Change-to-Dirty From Local node to Node 3",
+     .ucode = 0x88,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_cpu_read_command_requests_to_target_node_4_7[]={
+   { .uname = "READ_BLOCK_LOCAL_TO_NODE_4",
+     .udesc = "Read block From Local node to Node 4",
+     .ucode = 0x11,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_4",
+     .udesc = "Read block shared From Local node to Node 4",
+     .ucode = 0x12,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_4",
+     .udesc = "Read block modified From Local node to Node 4",
+     .ucode = 0x14,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_4",
+     .udesc = "Change-to-Dirty From Local node to Node 4",
+     .ucode = 0x18,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_LOCAL_TO_NODE_5",
+     .udesc = "Read block From Local node to Node 5",
+     .ucode = 0x21,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_5",
+     .udesc = "Read block shared From Local node to Node 5",
+     .ucode = 0x22,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_5",
+     .udesc = "Read block modified From Local node to Node 5",
+     .ucode = 0x24,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_5",
+     .udesc = "Change-to-Dirty From Local node to Node 5",
+     .ucode = 0x28,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_LOCAL_TO_NODE_6",
+     .udesc = "Read block From Local node to Node 6",
+     .ucode = 0x41,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_6",
+     .udesc = "Read block shared From Local node to Node 6",
+     .ucode = 0x42,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_6",
+     .udesc = "Read block modified From Local node to Node 6",
+     .ucode = 0x44,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_6",
+     .udesc = "Change-to-Dirty From Local node to Node 6",
+     .ucode = 0x48,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_LOCAL_TO_NODE_7",
+     .udesc = "Read block From Local node to Node 7",
+     .ucode = 0x81,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_7",
+     .udesc = "Read block shared From Local node to Node 7",
+     .ucode = 0x82,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_7",
+     .udesc = "Read block modified From Local node to Node 7",
+     .ucode = 0x84,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_7",
+     .udesc = "Change-to-Dirty From Local node to Node 7",
+     .ucode = 0x88,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_cpu_command_requests_to_target_node[]={
+   { .uname = "READ_SIZED_LOCAL_TO_NODE_0",
+     .udesc = "Read Sized From Local node to Node 0",
+     .ucode = 0x11,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "WRITE_SIZED_LOCAL_TO_NODE_0",
+     .udesc = "Write Sized From Local node to Node 0",
+     .ucode = 0x12,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_0",
+     .udesc = "Victim Block From Local node to Node 0",
+     .ucode = 0x14,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_SIZED_LOCAL_TO_NODE_1",
+     .udesc = "Read Sized From Local node to Node 1",
+     .ucode = 0x21,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "WRITE_SIZED_LOCAL_TO_NODE_1",
+     .udesc = "Write Sized From Local node to Node 1",
+     .ucode = 0x22,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_1",
+     .udesc = "Victim Block From Local node to Node 1",
+     .ucode = 0x24,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_SIZED_LOCAL_TO_NODE_2",
+     .udesc = "Read Sized From Local node to Node 2",
+     .ucode = 0x41,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "WRITE_SIZED_LOCAL_TO_NODE_2",
+     .udesc = "Write Sized From Local node to Node 2",
+     .ucode = 0x42,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_2",
+     .udesc = "Victim Block From Local node to Node 2",
+     .ucode = 0x44,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_SIZED_LOCAL_TO_NODE_3",
+     .udesc = "Read Sized From Local node to Node 3",
+     .ucode = 0x81,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "WRITE_SIZED_LOCAL_TO_NODE_3",
+     .udesc = "Write Sized From Local node to Node 3",
+     .ucode = 0x82,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_3",
+     .udesc = "Victim Block From Local node to Node 3",
+     .ucode = 0x84,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_SIZED_LOCAL_TO_NODE_4",
+     .udesc = "Read Sized From Local node to Node 4",
+     .ucode = 0x19,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "WRITE_SIZED_LOCAL_TO_NODE_4",
+     .udesc = "Write Sized From Local node to Node 4",
+     .ucode = 0x1a,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_4",
+     .udesc = "Victim Block From Local node to Node 4",
+     .ucode = 0x1c,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_SIZED_LOCAL_TO_NODE_5",
+     .udesc = "Read Sized From Local node to Node 5",
+     .ucode = 0x29,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "WRITE_SIZED_LOCAL_TO_NODE_5",
+     .udesc = "Write Sized From Local node to Node 5",
+     .ucode = 0x2a,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_5",
+     .udesc = "Victim Block From Local node to Node 5",
+     .ucode = 0x2c,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_SIZED_LOCAL_TO_NODE_6",
+     .udesc = "Read Sized From Local node to Node 6",
+     .ucode = 0x49,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "WRITE_SIZED_LOCAL_TO_NODE_6",
+     .udesc = "Write Sized From Local node to Node 6",
+     .ucode = 0x4a,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_6",
+     .udesc = "Victim Block From Local node to Node 6",
+     .ucode = 0x4c,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "READ_SIZED_LOCAL_TO_NODE_7",
+     .udesc = "Read Sized From Local node to Node 7",
+     .ucode = 0x89,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "WRITE_SIZED_LOCAL_TO_NODE_7",
+     .udesc = "Write Sized From Local node to Node 7",
+     .ucode = 0x8a,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_7",
+     .udesc = "Victim Block From Local node to Node 7",
+     .ucode = 0x8c,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "ALL_LOCAL_TO_NODE_0_3",
+     .udesc  = "All From Local node to Node 0-3",
+     .ucode = 0xf7,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname  = "ALL_LOCAL_TO_NODE_4_7",
+     .udesc  = "All From Local node to Node 4-7",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_request_cache_status_0[]={
+   { .uname = "PROBE_HIT_S",
+     .udesc = "Probe Hit S",
+     .ucode = 0x1,
+   },
+   { .uname = "PROBE_HIT_E",
+     .udesc = "Probe Hit E",
+     .ucode = 0x2,
+   },
+   { .uname = "PROBE_HIT_MUW_OR_O",
+     .udesc = "Probe Hit MuW or O",
+     .ucode = 0x4,
+   },
+   { .uname = "PROBE_HIT_M",
+     .udesc = "Probe Hit M",
+     .ucode = 0x8,
+   },
+   { .uname = "PROBE_MISS",
+     .udesc = "Probe Miss",
+     .ucode = 0x10,
+   },
+   { .uname = "DIRECTED_PROBE",
+     .udesc = "Directed Probe",
+     .ucode = 0x20,
+   },
+   { .uname = "TRACK_CACHE_STAT_FOR_RDBLK",
+     .udesc = "Track Cache Stat for RdBlk",
+     .ucode = 0x40,
+   },
+   { .uname = "TRACK_CACHE_STAT_FOR_RDBLKS",
+     .udesc = "Track Cache Stat for RdBlkS",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_request_cache_status_1[]={
+   { .uname = "PROBE_HIT_S",
+     .udesc = "Probe Hit S",
+     .ucode = 0x1,
+   },
+   { .uname = "PROBE_HIT_E",
+     .udesc = "Probe Hit E",
+     .ucode = 0x2,
+   },
+   { .uname = "PROBE_HIT_MUW_OR_O",
+     .udesc = "Probe Hit MuW or O",
+     .ucode = 0x4,
+   },
+   { .uname = "PROBE_HIT_M",
+     .udesc = "Probe Hit M",
+     .ucode = 0x8,
+   },
+   { .uname = "PROBE_MISS",
+     .udesc = "Probe Miss",
+     .ucode = 0x10,
+   },
+   { .uname = "DIRECTED_PROBE",
+     .udesc = "Directed Probe",
+     .ucode = 0x20,
+   },
+   { .uname = "TRACK_CACHE_STAT_FOR_CHGTODIRTY",
+     .udesc = "Track Cache Stat for ChgToDirty",
+     .ucode = 0x40,
+   },
+   { .uname = "TRACK_CACHE_STAT_FOR_RDBLKM",
+     .udesc = "Track Cache Stat for RdBlkM",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_memory_controller_requests[]={
+   { .uname = "WRITE_REQUESTS_TO_DCT",
+     .udesc = "Write requests sent to the DCT",
+     .ucode = 0x1,
+   },
+   { .uname = "READ_REQUESTS_TO_DCT",
+     .udesc = "Read requests (including prefetch requests) sent to the DCT",
+     .ucode = 0x2,
+   },
+   { .uname = "PREFETCH_REQUESTS_TO_DCT",
+     .udesc = "Prefetch requests sent to the DCT",
+     .ucode = 0x4,
+   },
+   { .uname = "32_BYTES_SIZED_WRITES",
+     .udesc = "32 Bytes Sized Writes",
+     .ucode = 0x8,
+   },
+   { .uname = "64_BYTES_SIZED_WRITES",
+     .udesc = "64 Bytes Sized Writes",
+     .ucode = 0x10,
+   },
+   { .uname = "32_BYTES_SIZED_READS",
+     .udesc = "32 Bytes Sized Reads",
+     .ucode = 0x20,
+   },
+   { .uname = "64_BYTE_SIZED_READS",
+     .udesc = "64 Byte Sized Reads",
+     .ucode = 0x40,
+   },
+   { .uname = "READ_REQUESTS_TO_DCT_WHILE_WRITES_PENDING",
+     .udesc = "Read requests sent to the DCT while writes requests are pending in the DCT",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_read_request_to_l3_cache[]={
+   { .uname = "READ_BLOCK_EXCLUSIVE",
+     .udesc = "Read Block Exclusive (Data cache read)",
+     .ucode = 0x1,
+     .grpid = 0,
+   },
+   { .uname = "READ_BLOCK_SHARED",
+     .udesc = "Read Block Shared (Instruction cache read)",
+     .ucode = 0x2,
+     .grpid = 0,
+   },
+   { .uname = "READ_BLOCK_MODIFY",
+     .udesc = "Read Block Modify",
+     .ucode = 0x4,
+     .grpid = 0,
+   },
+   { .uname = "PREFETCH",
+     .udesc = "Count prefetches only",
+     .ucode = 0x8,
+     .grpid = 0,
+   },
+   { .uname  = "READ_BLOCK_ANY",
+     .udesc  = "Count any read request",
+     .ucode = 0x7,
+     .grpid = 0,
+     .uflags= AMD64_FL_DFL | AMD64_FL_NCOMBO,
+   },
+  CORE_SELECT(1),
+};
+
+static const amd64_umask_t amd64_fam15h_l3_fills_caused_by_l2_evictions[]={
+   { .uname = "SHARED",
+     .udesc = "Shared",
+     .ucode = 0x1,
+     .grpid = 0,
+   },
+   { .uname = "EXCLUSIVE",
+     .udesc = "Exclusive",
+     .ucode = 0x2,
+     .grpid = 0,
+   },
+   { .uname = "OWNED",
+     .udesc = "Owned",
+     .ucode = 0x4,
+     .grpid = 0,
+   },
+   { .uname = "MODIFIED",
+     .udesc = "Modified",
+     .ucode = 0x8,
+     .grpid = 0,
+   },
+  { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+     .grpid = 0,
+   },
+   CORE_SELECT(1),
+ };
+
+static const amd64_umask_t amd64_fam15h_l3_evictions[]={
+   { .uname = "SHARED",
+     .udesc = "Shared",
+     .ucode = 0x1,
+   },
+   { .uname = "EXCLUSIVE",
+     .udesc = "Exclusive",
+     .ucode = 0x2,
+   },
+   { .uname = "OWNED",
+     .udesc = "Owned",
+     .ucode = 0x4,
+   },
+   { .uname = "MODIFIED",
+     .udesc = "Modified",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_l3_latency[]={
+   { .uname = "L3_REQUEST_CYCLE",
+     .udesc = "L3 Request cycle count.",
+     .ucode = 0x1,
+   },
+   { .uname = "L3_REQUEST",
+     .udesc = "L3 request count.",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_entry_t amd64_fam15h_pe[]={
+{ .name    = "DISPATCHED_FPU_OPS",
+  .desc    = "FPU Pipe Assignment",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x0,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_dispatched_fpu_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_dispatched_fpu_ops,
+},
+{ .name    = "CYCLES_FPU_EMPTY",
+  .desc    = "FP Scheduler Empty",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x1,
+},
+{ .name    = "RETIRED_SSE_OPS",
+  .desc    = "Retired SSE/BNI Ops",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x3,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_retired_sse_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_retired_sse_ops,
+},
+{ .name    = "MOVE_SCALAR_OPTIMIZATION",
+  .desc    = "Number of Move Elimination and Scalar Op Optimization",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x4,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_move_scalar_optimization),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_move_scalar_optimization,
+},
+{ .name    = "RETIRED_SERIALIZING_OPS",
+  .desc    = "Retired Serializing Ops",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x5,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_retired_serializing_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_retired_serializing_ops,
+},
+{ .name    = "BOTTOM_EXECUTE_OP",
+  .desc    = "Number of Cycles that a Bottom-Execute uop is in the FP Scheduler",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x6,
+},
+{ .name    = "SEGMENT_REGISTER_LOADS",
+  .desc    = "Segment Register Loads",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x20,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_segment_register_loads),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_segment_register_loads,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE",
+  .desc    = "Pipeline Restart Due to Self-Modifying Code",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x21,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_PROBE_HIT",
+  .desc    = "Pipeline Restart Due to Probe Hit",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x22,
+},
+{ .name    = "LOAD_Q_STORE_Q_FULL",
+  .desc    = "Load Queue/Store Queue Full",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x23,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_load_q_store_q_full),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_load_q_store_q_full,
+},
+{ .name    = "LOCKED_OPS",
+  .desc    = "Locked Operations",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x24,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_locked_ops),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_locked_ops,
+},
+{ .name    = "RETIRED_CLFLUSH_INSTRUCTIONS",
+  .desc    = "Retired CLFLUSH Instructions",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x26,
+},
+{ .name    = "RETIRED_CPUID_INSTRUCTIONS",
+  .desc    = "Retired CPUID Instructions",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x27,
+},
+{ .name    = "CANCELLED_STORE_TO_LOAD",
+  .desc    = "Canceled Store to Load Forward Operations",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x2a,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_cancelled_store_to_load),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_cancelled_store_to_load,
+},
+{ .name    = "SMIS_RECEIVED",
+  .desc    = "SMIs Received",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x2b,
+},
+{ .name    = "DATA_CACHE_ACCESSES",
+  .desc    = "Data Cache Accesses",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x40,
+},
+{ .name    = "DATA_CACHE_MISSES",
+  .desc    = "Data Cache Misses",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x41,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_data_cache_misses),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_data_cache_misses,
+},
+{ .name    = "DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE",
+  .desc    = "Data Cache Refills from L2 or System",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x42,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_data_cache_refills_from_l2_or_northbridge),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_data_cache_refills_from_l2_or_northbridge,
+},
+{ .name    = "DATA_CACHE_REFILLS_FROM_NORTHBRIDGE",
+  .desc    = "Data Cache Refills from System",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x43,
+},
+{ .name    = "UNIFIED_TLB_HIT",
+  .desc    = "Unified TLB Hit",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x45,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_unified_tlb_hit),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_unified_tlb_hit,
+},
+{ .name    = "UNIFIED_TLB_MISS",
+  .desc    = "Unified TLB Miss",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x46,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_unified_tlb_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_unified_tlb_miss,
+},
+{ .name    = "MISALIGNED_ACCESSES",
+  .desc    = "Misaligned Accesses",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x47,
+},
+{ .name    = "PREFETCH_INSTRUCTIONS_DISPATCHED",
+  .desc    = "Prefetch Instructions Dispatched",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x4b,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_prefetch_instructions_dispatched),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_prefetch_instructions_dispatched,
+},
+{ .name    = "INEFFECTIVE_SW_PREFETCHES",
+  .desc    = "Ineffective Software Prefetches",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x52,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_ineffective_sw_prefetches),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_ineffective_sw_prefetches,
+},
+{ .name    = "MEMORY_REQUESTS",
+  .desc    = "Memory Requests by Type",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x65,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_memory_requests),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_memory_requests,
+},
+{ .name    = "DATA_PREFETCHER",
+  .desc    = "Data Prefetcher",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x67,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_data_prefetcher),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_data_prefetcher,
+},
+{ .name    = "MAB_REQS",
+  .desc    = "MAB Requests",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x68,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_mab_reqs),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_mab_reqs,
+},
+{ .name    = "MAB_WAIT",
+  .desc    = "MAB Wait Cycles",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x69,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_mab_reqs),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_mab_reqs, /* identical to actual umasks list for this event */
+},
+{ .name    = "SYSTEM_READ_RESPONSES",
+  .desc    = "Response From System on Cache Refills",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x6c,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_system_read_responses),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_system_read_responses,
+},
+{ .name    = "OCTWORD_WRITE_TRANSFERS",
+  .desc    = "Octwords Written to System",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x6d,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_octword_write_transfers),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_octword_write_transfers,
+},
+{ .name    = "CPU_CLK_UNHALTED",
+  .desc    = "CPU Clocks not Halted",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x76,
+},
+{ .name    = "REQUESTS_TO_L2",
+  .desc    = "Requests to L2 Cache",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x7d,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_requests_to_l2),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_requests_to_l2,
+},
+{ .name    = "L2_CACHE_MISS",
+  .desc    = "L2 Cache Misses",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x7e,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l2_cache_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_l2_cache_miss,
+},
+{ .name    = "L2_CACHE_FILL_WRITEBACK",
+  .desc    = "L2 Fill/Writeback",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x7f,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l2_cache_fill_writeback),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_l2_cache_fill_writeback,
+},
+{ .name    = "PAGE_SPLINTERING",
+  .desc    = "Page Splintering",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x165,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_page_splintering),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_page_splintering,
+},
+{ .name    = "INSTRUCTION_CACHE_FETCHES",
+  .desc    = "Instruction Cache Fetches",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x80,
+},
+{ .name    = "INSTRUCTION_CACHE_MISSES",
+  .desc    = "Instruction Cache Misses",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x81,
+},
+{ .name    = "INSTRUCTION_CACHE_REFILLS_FROM_L2",
+  .desc    = "Instruction Cache Refills from L2",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x82,
+},
+{ .name    = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM",
+  .desc    = "Instruction Cache Refills from System",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x83,
+},
+{ .name    = "L1_ITLB_MISS_AND_L2_ITLB_HIT",
+  .desc    = "L1 ITLB Miss, L2 ITLB Hit",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x84,
+},
+{ .name    = "L1_ITLB_MISS_AND_L2_ITLB_MISS",
+  .desc    = "L1 ITLB Miss, L2 ITLB Miss",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x85,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l1_itlb_miss_and_l2_itlb_miss),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_l1_itlb_miss_and_l2_itlb_miss,
+},
+{ .name    = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE",
+  .desc    = "Pipeline Restart Due to Instruction Stream Probe",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x86,
+},
+{ .name    = "INSTRUCTION_FETCH_STALL",
+  .desc    = "Instruction Fetch Stall",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x87,
+},
+{ .name    = "RETURN_STACK_HITS",
+  .desc    = "Return Stack Hits",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x88,
+},
+{ .name    = "RETURN_STACK_OVERFLOWS",
+  .desc    = "Return Stack Overflows",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x89,
+},
+{ .name    = "INSTRUCTION_CACHE_VICTIMS",
+  .desc    = "Instruction Cache Victims",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x8b,
+},
+{ .name    = "INSTRUCTION_CACHE_INVALIDATED",
+  .desc    = "Instruction Cache Lines Invalidated",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x8c,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_instruction_cache_invalidated),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_instruction_cache_invalidated,
+},
+{ .name    = "ITLB_RELOADS",
+  .desc    = "ITLB Reloads",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x99,
+},
+{ .name    = "ITLB_RELOADS_ABORTED",
+  .desc    = "ITLB Reloads Aborted",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x9a,
+},
+{ .name    = "RETIRED_INSTRUCTIONS",
+  .desc    = "Retired Instructions",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xc0,
+},
+{ .name    = "RETIRED_UOPS",
+  .desc    = "Retired uops",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xc1,
+},
+{ .name    = "RETIRED_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Branch Instructions",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xc2,
+},
+{ .name    = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Mispredicted Branch Instructions",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xc3,
+},
+{ .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS",
+  .desc    = "Retired Taken Branch Instructions",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xc4,
+},
+{ .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED",
+  .desc    = "Retired Taken Branch Instructions Mispredicted",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xc5,
+},
+{ .name    = "RETIRED_FAR_CONTROL_TRANSFERS",
+  .desc    = "Retired Far Control Transfers",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xc6,
+},
+{ .name    = "RETIRED_BRANCH_RESYNCS",
+  .desc    = "Retired Branch Resyncs",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xc7,
+},
+{ .name    = "RETIRED_NEAR_RETURNS",
+  .desc    = "Retired Near Returns",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xc8,
+},
+{ .name    = "RETIRED_NEAR_RETURNS_MISPREDICTED",
+  .desc    = "Retired Near Returns Mispredicted",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xc9,
+},
+{ .name    = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED",
+  .desc    = "Retired Indirect Branches Mispredicted",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xca,
+},
+{ .name    = "RETIRED_MMX_FP_INSTRUCTIONS",
+  .desc    = "Retired MMX/FP Instructions",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xcb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_retired_mmx_fp_instructions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_retired_mmx_fp_instructions,
+},
+{ .name    = "INTERRUPTS_MASKED_CYCLES",
+  .desc    = "Interrupts-Masked Cycles",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xcd,
+},
+{ .name    = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING",
+  .desc    = "Interrupts-Masked Cycles with Interrupt Pending",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xce,
+},
+{ .name    = "INTERRUPTS_TAKEN",
+  .desc    = "Interrupts Taken",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xcf,
+},
+{ .name    = "DECODER_EMPTY",
+  .desc    = "Decoder Empty",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xd0,
+},
+{ .name    = "DISPATCH_STALLS",
+  .desc    = "Dispatch Stalls",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xd1,
+},
+{ .name    = "DISPATCH_STALL_FOR_SERIALIZATION",
+  .desc    = "Microsequencer Stall due to Serialization",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xd3,
+},
+{ .name    = "DISPATCH_STALL_FOR_RETIRE_QUEUE_FULL",
+  .desc    = "Dispatch Stall for Instruction Retire Q Full",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xd5,
+},
+{ .name    = "DISPATCH_STALL_FOR_INT_SCHED_QUEUE_FULL",
+  .desc    = "Dispatch Stall for Integer Scheduler Queue Full",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xd6,
+},
+{ .name    = "DISPATCH_STALL_FOR_FPU_FULL",
+  .desc    = "Dispatch Stall for FP Scheduler Queue Full",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xd7,
+},
+{ .name    = "DISPATCH_STALL_FOR_LDQ_FULL",
+  .desc    = "Dispatch Stall for LDQ Full",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xd8,
+},
+{ .name    = "MICROSEQ_STALL_WAITING_FOR_ALL_QUIET",
+  .desc    = "Microsequencer Stall Waiting for All Quiet",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xd9,
+},
+{ .name    = "FPU_EXCEPTIONS",
+  .desc    = "FPU Exceptions",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xdb,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_fpu_exceptions),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_fpu_exceptions,
+},
+{ .name    = "DR0_BREAKPOINTS",
+  .desc    = "DR0 Breakpoint Match",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xdc,
+},
+{ .name    = "DR1_BREAKPOINTS",
+  .desc    = "DR1 Breakpoint Match",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xdd,
+},
+{ .name    = "DR2_BREAKPOINTS",
+  .desc    = "DR2 Breakpoint Match",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xde,
+},
+{ .name    = "DR3_BREAKPOINTS",
+  .desc    = "DR3 Breakpoint Match",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0xdf,
+},
+{ .name    = "IBS_OPS_TAGGED",
+  .desc    = "Tagged IBS Ops",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x1cf,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_ibs_ops_tagged),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_ibs_ops_tagged,
+},
+{ .name    = "LS_DISPATCH",
+  .desc    = "LS Dispatch",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x29,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_ls_dispatch),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_ls_dispatch,
+},
+{ .name    = "EXECUTED_CLFLUSH_INSTRUCTIONS",
+  .desc    = "Executed CLFLUSH Instructions",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x30,
+},
+{ .name    = "L2_PREFETCHER_TRIGGER_EVENTS",
+  .desc    = "L2 Prefetcher Trigger Events",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x16c,
+  .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l2_prefetcher_trigger_events),
+  .ngrp    = 1,
+  .umasks  = amd64_fam15h_l2_prefetcher_trigger_events,
+},
+{ .name    = "DISPATCH_STALL_FOR_STQ_FULL",
+  .desc    = "Dispatch Stall for STQ Full",
+  .modmsk  = AMD64_FAM15H_ATTRS,
+  .code    = 0x1d8,
+},
+};
diff --git a/user/perfmon/events/amd64_events_fam15h_nb.h b/user/perfmon/events/amd64_events_fam15h_nb.h
new file mode 100644 (file)
index 0000000..82799f0
--- /dev/null
@@ -0,0 +1,2022 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ * Contributed by Stephane Eranian <eranian@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * This file is part of libpfm, a performance monitoring support library for
+ * applications on Linux.
+ *
+ * This file has been automatically generated.
+ *
+ * PMU: amd64_fam15h_nb_nb (AMD64 Fam15h Interlagos NorthBridge)
+ *
+ * Based on libpfm patch by Robert Richter <robert.richter@amd.com>:
+ * Family 15h Microarchitecture performance monitor events
+ *
+ * History:
+ *
+ * Nov 30 2013 -- Stephane Eranian , eranian@gmail.com:
+ * Split core and Northbridge events as PMU is distinct
+ *
+ * Apr 29 2011 -- Robert Richter, robert.richter@amd.com:
+ * Source: BKDG for AMD Family 15h Models 00h-0Fh Processors,
+ * 42301, Rev 1.15, April 18, 2011
+ *
+ * Dec 09 2010 -- Robert Richter, robert.richter@amd.com:
+ * Source: BIOS and Kernel Developer's Guide for the AMD Family 15h
+ * Processors, Rev 0.90, May 18, 2010
+ */
+
+#define CORE_SELECT(b) \
+   { .uname  = "CORE_0",\
+     .udesc  = "Measure on Core0",\
+     .ucode = 0 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_1",\
+     .udesc  = "Measure on Core1",\
+     .ucode = 1 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_2",\
+     .udesc  = "Measure on Core2",\
+     .ucode = 2 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_3",\
+     .udesc  = "Measure on Core3",\
+     .ucode = 3 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_4",\
+     .udesc  = "Measure on Core4",\
+     .ucode = 4 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_5",\
+     .udesc  = "Measure on Core5",\
+     .ucode = 5 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_6",\
+     .udesc  = "Measure on Core6",\
+     .ucode = 6 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "CORE_7",\
+     .udesc  = "Measure on Core7",\
+     .ucode = 7 << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO,\
+   },\
+   { .uname  = "ANY_CORE",\
+     .udesc  = "Measure on any core",\
+     .ucode = 0xf << 4,\
+     .grpid = b,\
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,\
+   }
+
+static const amd64_umask_t amd64_fam15h_nb_dispatched_fpu_ops[]={
+   { .uname  = "OPS_PIPE0",
+     .udesc  = "Total number uops assigned to Pipe 0",
+     .ucode = 0x1,
+   },
+   { .uname  = "OPS_PIPE1",
+     .udesc  = "Total number uops assigned to Pipe 1",
+     .ucode = 0x2,
+   },
+   { .uname  = "OPS_PIPE2",
+     .udesc  = "Total number uops assigned to Pipe 2",
+     .ucode = 0x4,
+   },
+   { .uname  = "OPS_PIPE3",
+     .udesc  = "Total number uops assigned to Pipe 3",
+     .ucode = 0x8,
+   },
+   { .uname  = "OPS_DUAL_PIPE0",
+     .udesc  = "Total number dual-pipe uops assigned to Pipe 0",
+     .ucode = 0x10,
+   },
+   { .uname  = "OPS_DUAL_PIPE1",
+     .udesc  = "Total number dual-pipe uops assigned to Pipe 1",
+     .ucode = 0x20,
+   },
+   { .uname  = "OPS_DUAL_PIPE2",
+     .udesc  = "Total number dual-pipe uops assigned to Pipe 2",
+     .ucode = 0x40,
+   },
+   { .uname  = "OPS_DUAL_PIPE3",
+     .udesc  = "Total number dual-pipe uops assigned to Pipe 3",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_retired_sse_ops[]={
+   { .uname  = "SINGLE_ADD_SUB_OPS",
+     .udesc  = "Single-precision add/subtract FLOPS",
+     .ucode = 0x1,
+   },
+   { .uname  = "SINGLE_MUL_OPS",
+     .udesc  = "Single-precision multiply FLOPS",
+     .ucode = 0x2,
+   },
+   { .uname  = "SINGLE_DIV_OPS",
+     .udesc  = "Single-precision divide/square root FLOPS",
+     .ucode = 0x4,
+   },
+   { .uname  = "SINGLE_MUL_ADD_OPS",
+     .udesc  = "Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS",
+     .ucode = 0x8,
+   },
+   { .uname  = "DOUBLE_ADD_SUB_OPS",
+     .udesc  = "Double precision add/subtract FLOPS",
+     .ucode = 0x10,
+   },
+   { .uname  = "DOUBLE_MUL_OPS",
+     .udesc  = "Double precision multiply FLOPS",
+     .ucode = 0x20,
+   },
+   { .uname  = "DOUBLE_DIV_OPS",
+     .udesc  = "Double precision divide/square root FLOPS",
+     .ucode = 0x40,
+   },
+   { .uname  = "DOUBLE_MUL_ADD_OPS",
+     .udesc  = "Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_move_scalar_optimization[]={
+   { .uname  = "SSE_MOVE_OPS",
+     .udesc  = "Number of SSE Move Ops",
+     .ucode = 0x1,
+   },
+   { .uname  = "SSE_MOVE_OPS_ELIM",
+     .udesc  = "Number of SSE Move Ops eliminated",
+     .ucode = 0x2,
+   },
+   { .uname  = "OPT_CAND",
+     .udesc  = "Number of Ops that are candidates for optimization (Z-bit set or pass)",
+     .ucode = 0x4,
+   },
+   { .uname  = "SCALAR_OPS_OPTIMIZED",
+     .udesc  = "Number of Scalar ops optimized",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_retired_serializing_ops[]={
+   { .uname  = "SSE_RETIRED",
+     .udesc  = "SSE bottom-executing uops retired",
+     .ucode = 0x1,
+   },
+   { .uname  = "SSE_MISPREDICTED",
+     .udesc  = "SSE control word mispredict traps due to mispredictions",
+     .ucode = 0x2,
+   },
+   { .uname  = "X87_RETIRED",
+     .udesc  = "X87 bottom-executing uops retired",
+     .ucode = 0x4,
+   },
+   { .uname  = "X87_MISPREDICTED",
+     .udesc  = "X87 control word mispredict traps due to mispredictions",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_segment_register_loads[]={
+   { .uname  = "ES",
+     .udesc  = "ES",
+     .ucode = 0x1,
+   },
+   { .uname  = "CS",
+     .udesc  = "CS",
+     .ucode = 0x2,
+   },
+   { .uname  = "SS",
+     .udesc  = "SS",
+     .ucode = 0x4,
+   },
+   { .uname  = "DS",
+     .udesc  = "DS",
+     .ucode = 0x8,
+   },
+   { .uname  = "FS",
+     .udesc  = "FS",
+     .ucode = 0x10,
+   },
+   { .uname  = "GS",
+     .udesc  = "GS",
+     .ucode = 0x20,
+   },
+   { .uname  = "HS",
+     .udesc  = "HS",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_load_q_store_q_full[]={
+   { .uname  = "LOAD_QUEUE",
+     .udesc  = "The number of cycles that the load buffer is full",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORE_QUEUE",
+     .udesc  = "The number of cycles that the store buffer is full",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_locked_ops[]={
+   { .uname  = "EXECUTED",
+     .udesc  = "Number of locked instructions executed",
+     .ucode = 0x1,
+   },
+   { .uname  = "CYCLES_NON_SPECULATIVE_PHASE",
+     .udesc  = "Number of cycles spent in non-speculative phase, excluding cache miss penalty",
+     .ucode = 0x4,
+   },
+   { .uname  = "CYCLES_WAITING",
+     .udesc  = "Number of cycles spent in non-speculative phase, including the cache miss penalty",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xd,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_cancelled_store_to_load[]={
+   { .uname  = "SIZE_ADDRESS_MISMATCHES",
+     .udesc  = "Store is smaller than load or different starting byte but partial overlap",
+     .ucode = 0x1,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_data_cache_misses[]={
+   { .uname  = "DC_MISS_STREAMING_STORE",
+     .udesc  = "First data cache miss or streaming store to a 64B cache line",
+     .ucode = 0x1,
+   },
+   { .uname  = "STREAMING_STORE",
+     .udesc  = "First streaming store to a 64B cache line",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_data_cache_refills_from_l2_or_northbridge[]={
+   { .uname  = "GOOD",
+     .udesc  = "Fill with good data. (Final valid status is valid)",
+     .ucode = 0x1,
+   },
+   { .uname  = "INVALID",
+     .udesc  = "Early valid status turned out to be invalid",
+     .ucode = 0x2,
+   },
+   { .uname  = "POISON",
+     .udesc  = "Fill with poison data",
+     .ucode = 0x4,
+   },
+   { .uname  = "READ_ERROR",
+     .udesc  = "Fill with read data error",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_unified_tlb_hit[]={
+   { .uname  = "4K_DATA",
+     .udesc  = "4 KB unified TLB hit for data",
+     .ucode = 0x1,
+   },
+   { .uname  = "2M_DATA",
+     .udesc  = "2 MB unified TLB hit for data",
+     .ucode = 0x2,
+   },
+   { .uname  = "1G_DATA",
+     .udesc  = "1 GB unified TLB hit for data",
+     .ucode = 0x4,
+   },
+   { .uname  = "4K_INST",
+     .udesc  = "4 KB unified TLB hit for instruction",
+     .ucode = 0x10,
+   },
+   { .uname  = "2M_INST",
+     .udesc  = "2 MB unified TLB hit for instruction",
+     .ucode = 0x20,
+   },
+   { .uname  = "1G_INST",
+     .udesc  = "1 GB unified TLB hit for instruction",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x77,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_unified_tlb_miss[]={
+   { .uname  = "4K_DATA",
+     .udesc  = "4 KB unified TLB miss for data",
+     .ucode = 0x1,
+   },
+   { .uname  = "2M_DATA",
+     .udesc  = "2 MB unified TLB miss for data",
+     .ucode = 0x2,
+   },
+   { .uname  = "1GB_DATA",
+     .udesc  = "1 GB unified TLB miss for data",
+     .ucode = 0x4,
+   },
+   { .uname  = "4K_INST",
+     .udesc  = "4 KB unified TLB miss for instruction",
+     .ucode = 0x10,
+   },
+   { .uname  = "2M_INST",
+     .udesc  = "2 MB unified TLB miss for instruction",
+     .ucode = 0x20,
+   },
+   { .uname  = "1G_INST",
+     .udesc  = "1 GB unified TLB miss for instruction",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x77,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_prefetch_instructions_dispatched[]={
+   { .uname  = "LOAD",
+     .udesc  = "Load (Prefetch, PrefetchT0/T1/T2)",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORE",
+     .udesc  = "Store (PrefetchW)",
+     .ucode = 0x2,
+   },
+   { .uname  = "NTA",
+     .udesc  = "NTA (PrefetchNTA)",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_ineffective_sw_prefetches[]={
+   { .uname  = "SW_PREFETCH_HIT_IN_L1",
+     .udesc  = "Software prefetch hit in the L1",
+     .ucode = 0x1,
+   },
+   { .uname  = "SW_PREFETCH_HIT_IN_L2",
+     .udesc  = "Software prefetch hit in the L2",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x9,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_memory_requests[]={
+   { .uname  = "NON_CACHEABLE",
+     .udesc  = "Requests to non-cacheable (UC) memory",
+     .ucode = 0x1,
+   },
+   { .uname  = "WRITE_COMBINING",
+     .udesc  = "Requests to non-cacheable (WC, but not WC+/SS) memory",
+     .ucode = 0x2,
+   },
+   { .uname  = "STREAMING_STORE",
+     .udesc  = "Requests to non-cacheable (WC+/SS, but not WC) memory",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x83,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_data_prefetcher[]={
+   { .uname  = "ATTEMPTED",
+     .udesc  = "Prefetch attempts",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x2,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_mab_reqs[]={
+   { .uname  = "BUFFER_BIT_0",
+     .udesc  = "Buffer entry index bit 0",
+     .ucode = 0x1,
+   },
+   { .uname  = "BUFFER_BIT_1",
+     .udesc  = "Buffer entry index bit 1",
+     .ucode = 0x2,
+   },
+   { .uname  = "BUFFER_BIT_2",
+     .udesc  = "Buffer entry index bit 2",
+     .ucode = 0x4,
+   },
+   { .uname  = "BUFFER_BIT_3",
+     .udesc  = "Buffer entry index bit 3",
+     .ucode = 0x8,
+   },
+   { .uname  = "BUFFER_BIT_4",
+     .udesc  = "Buffer entry index bit 4",
+     .ucode = 0x10,
+   },
+   { .uname  = "BUFFER_BIT_5",
+     .udesc  = "Buffer entry index bit 5",
+     .ucode = 0x20,
+   },
+   { .uname  = "BUFFER_BIT_6",
+     .udesc  = "Buffer entry index bit 6",
+     .ucode = 0x40,
+   },
+   { .uname  = "BUFFER_BIT_7",
+     .udesc  = "Buffer entry index bit 7",
+     .ucode = 0x80,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xff,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_system_read_responses[]={
+   { .uname  = "EXCLUSIVE",
+     .udesc  = "Exclusive",
+     .ucode = 0x1,
+   },
+   { .uname  = "MODIFIED",
+     .udesc  = "Modified (D18F0x68[ATMModeEn]==0), Modified written (D18F0x68[ATMModeEn]==1)",
+     .ucode = 0x2,
+   },
+   { .uname  = "SHARED",
+     .udesc  = "Shared",
+     .ucode = 0x4,
+   },
+   { .uname  = "OWNED",
+     .udesc  = "Owned",
+     .ucode = 0x8,
+   },
+   { .uname  = "DATA_ERROR",
+     .udesc  = "Data Error",
+     .ucode = 0x10,
+   },
+   { .uname  = "MODIFIED_UNWRITTEN",
+     .udesc  = "Modified unwritten",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_octword_write_transfers[]={
+   { .uname  = "OCTWORD_WRITE_TRANSFER",
+     .udesc  = "OW write transfer",
+     .ucode = 0x1,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_requests_to_l2[]={
+   { .uname  = "INSTRUCTIONS",
+     .udesc  = "IC fill",
+     .ucode = 0x1,
+   },
+   { .uname  = "DATA",
+     .udesc  = "DC fill",
+     .ucode = 0x2,
+   },
+   { .uname  = "TLB_WALK",
+     .udesc  = "TLB fill (page table walks)",
+     .ucode = 0x4,
+   },
+   { .uname  = "SNOOP",
+     .udesc  = "NB probe request",
+     .ucode = 0x8,
+   },
+   { .uname  = "CANCELLED",
+     .udesc  = "Canceled request",
+     .ucode = 0x10,
+   },
+   { .uname  = "PREFETCHER",
+     .udesc  = "L2 cache prefetcher request",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x5f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_l2_cache_miss[]={
+   { .uname  = "INSTRUCTIONS",
+     .udesc  = "IC fill",
+     .ucode = 0x1,
+   },
+   { .uname  = "DATA",
+     .udesc  = "DC fill (includes possible replays, whereas PMCx041 does not)",
+     .ucode = 0x2,
+   },
+   { .uname  = "TLB_WALK",
+     .udesc  = "TLB page table walk",
+     .ucode = 0x4,
+   },
+   { .uname  = "PREFETCHER",
+     .udesc  = "L2 Cache Prefetcher request",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x17,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_l2_cache_fill_writeback[]={
+   { .uname  = "L2_FILLS",
+     .udesc  = "L2 fills from system",
+     .ucode = 0x1,
+   },
+   { .uname  = "L2_WRITEBACKS",
+     .udesc  = "L2 Writebacks to system (Clean and Dirty)",
+     .ucode = 0x2,
+   },
+   { .uname  = "L2_WRITEBACKS_CLEAN",
+     .udesc  = "L2 Clean Writebacks to system",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_page_splintering[]={
+   { .uname  = "GUEST_LARGER",
+     .udesc  = "Guest page size is larger than host page size when nested paging is enabled",
+     .ucode = 0x1,
+   },
+   { .uname  = "MTRR_MISMATCH",
+     .udesc  = "Splintering due to MTRRs, IORRs, APIC, TOMs or other special address region",
+     .ucode = 0x2,
+   },
+   { .uname  = "HOST_LARGER",
+     .udesc  = "Host page size is larger than the guest page size",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_l1_itlb_miss_and_l2_itlb_miss[]={
+   { .uname  = "4K_PAGE_FETCHES",
+     .udesc  = "Instruction fetches to a 4 KB page",
+     .ucode = 0x1,
+   },
+   { .uname  = "2M_PAGE_FETCHES",
+     .udesc  = "Instruction fetches to a 2 MB page",
+     .ucode = 0x2,
+   },
+   { .uname  = "1G_PAGE_FETCHES",
+     .udesc  = "Instruction fetches to a 1 GB page",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_instruction_cache_invalidated[]={
+   { .uname  = "NON_SMC_PROBE_MISS",
+     .udesc  = "Non-SMC invalidating probe that missed on in-flight instructions",
+     .ucode = 0x1,
+   },
+   { .uname  = "NON_SMC_PROBE_HIT",
+     .udesc  = "Non-SMC invalidating probe that hit on in-flight instructions",
+     .ucode = 0x2,
+   },
+   { .uname  = "SMC_PROBE_MISS",
+     .udesc  = "SMC invalidating probe that missed on in-flight instructions",
+     .ucode = 0x4,
+   },
+   { .uname  = "SMC_PROBE_HIT",
+     .udesc  = "SMC invalidating probe that hit on in-flight instructions",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0xf,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_retired_mmx_fp_instructions[]={
+   { .uname  = "X87",
+     .udesc  = "X87 instructions",
+     .ucode = 0x1,
+   },
+   { .uname  = "MMX",
+     .udesc  = "MMX(tm) instructions",
+     .ucode = 0x2,
+   },
+   { .uname  = "SSE",
+     .udesc  = "SSE instructions (SSE,SSE2,SSE3,SSSE3,SSE4A,SSE4.1,SSE4.2,AVX,XOP,FMA4)",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_fpu_exceptions[]={
+   { .uname  = "TOTAL_FAULTS",
+     .udesc  = "Total microfaults",
+     .ucode = 0x1,
+   },
+   { .uname  = "TOTAL_TRAPS",
+     .udesc  = "Total microtraps",
+     .ucode = 0x2,
+   },
+   { .uname  = "INT2EXT_FAULTS",
+     .udesc  = "Int2Ext faults",
+     .ucode = 0x4,
+   },
+   { .uname  = "EXT2INT_FAULTS",
+     .udesc  = "Ext2Int faults",
+     .ucode = 0x8,
+   },
+   { .uname  = "BYPASS_FAULTS",
+     .udesc  = "Bypass faults",
+     .ucode = 0x10,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x1f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_ibs_ops_tagged[]={
+   { .uname  = "TAGGED",
+     .udesc  = "Number of ops tagged by IBS",
+     .ucode = 0x1,
+   },
+   { .uname  = "RETIRED",
+     .udesc  = "Number of ops tagged by IBS that retired",
+     .ucode = 0x2,
+   },
+   { .uname  = "IGNORED",
+     .udesc  = "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_ls_dispatch[]={
+   { .uname  = "LOADS",
+     .udesc  = "Loads",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORES",
+     .udesc  = "Stores",
+     .ucode = 0x2,
+   },
+   { .uname  = "LOAD_OP_STORES",
+     .udesc  = "Load-op-Stores",
+     .ucode = 0x4,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x7,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_l2_prefetcher_trigger_events[]={
+   { .uname  = "LOAD_L1_MISS_SEEN_BY_PREFETCHER",
+     .udesc  = "Load L1 miss seen by prefetcher",
+     .ucode = 0x1,
+   },
+   { .uname  = "STORE_L1_MISS_SEEN_BY_PREFETCHER",
+     .udesc  = "Store L1 miss seen by prefetcher",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_dram_accesses[]={
+   { .uname = "DCT0_PAGE_HIT",
+     .udesc = "DCT0 Page hit",
+     .ucode = 0x1,
+   },
+   { .uname = "DCT0_PAGE_MISS",
+     .udesc = "DCT0 Page Miss",
+     .ucode = 0x2,
+   },
+   { .uname = "DCT0_PAGE_CONFLICT",
+     .udesc = "DCT0 Page Conflict",
+     .ucode = 0x4,
+   },
+   { .uname = "DCT1_PAGE_HIT",
+     .udesc = "DCT1 Page hit",
+     .ucode = 0x8,
+   },
+   { .uname = "DCT1_PAGE_MISS",
+     .udesc = "DCT1 Page Miss",
+     .ucode = 0x10,
+   },
+   { .uname = "DCT1_PAGE_CONFLICT",
+     .udesc = "DCT1 Page Conflict",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x3f,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_dram_controller_page_table_overflows[]={
+   { .uname = "DCT0_PAGE_TABLE_OVERFLOW",
+     .udesc = "DCT0 Page Table Overflow",
+     .ucode = 0x1,
+   },
+   { .uname = "DCT1_PAGE_TABLE_OVERFLOW",
+     .udesc = "DCT1 Page Table Overflow",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode  = 0x3,
+     .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_memory_controller_dram_command_slots_missed[]={
+   { .uname = "DCT0_COMMAND_SLOTS_MISSED",
+     .udesc = "DCT0 Command Slots Missed (in MemClks)",
+     .ucode = 0x1,
+   },
+   { .uname = "DCT1_COMMAND_SLOTS_MISSED",
+     .udesc = "DCT1 Command Slots Missed (in MemClks)",
+     .ucode = 0x2,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode  = 0x3,
+     .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_memory_controller_turnarounds[]={
+   { .uname = "DCT0_DIMM_TURNAROUND",
+     .udesc = "DCT0 DIMM (chip select) turnaround",
+     .ucode = 0x1,
+   },
+   { .uname = "DCT0_READ_WRITE_TURNAROUND",
+     .udesc = "DCT0 Read to write turnaround",
+     .ucode = 0x2,
+   },
+   { .uname = "DCT0_WRITE_READ_TURNAROUND",
+     .udesc = "DCT0 Write to read turnaround",
+     .ucode = 0x4,
+   },
+   { .uname = "DCT1_DIMM_TURNAROUND",
+     .udesc = "DCT1 DIMM (chip select) turnaround",
+     .ucode = 0x8,
+   },
+   { .uname = "DCT1_READ_WRITE_TURNAROUND",
+     .udesc = "DCT1 Read to write turnaround",
+     .ucode = 0x10,
+   },
+   { .uname = "DCT1_WRITE_READ_TURNAROUND",
+     .udesc = "DCT1 Write to read turnaround",
+     .ucode = 0x20,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode  = 0x3f,
+     .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_memory_controller_bypass_counter_saturation[]={
+   { .uname = "MEMORY_CONTROLLER_HIGH_PRIORITY_BYPASS",
+     .udesc = "Memory controller high priority bypass",
+     .ucode = 0x1,
+   },
+   { .uname = "MEMORY_CONTROLLER_MEDIUM_PRIORITY_BYPASS",
+     .udesc = "Memory controller medium priority bypass",
+     .ucode = 0x2,
+   },
+   { .uname = "DCT0_DCQ_BYPASS",
+     .udesc = "DCT0 DCQ bypass",
+     .ucode = 0x4,
+   },
+   { .uname = "DCT1_DCQ_BYPASS",
+     .udesc = "DCT1 DCQ bypass",
+     .ucode = 0x8,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode  = 0xf,
+     .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_thermal_status[]={
+   { .uname = "NUM_HTC_TRIP_POINT_CROSSED",
+     .udesc = "Number of times the HTC trip point is crossed",
+     .ucode = 0x4,
+   },
+   { .uname = "NUM_CLOCKS_HTC_PSTATE_INACTIVE",
+     .udesc = "Number of clocks HTC P-state is inactive",
+     .ucode = 0x20,
+   },
+   { .uname = "NUM_CLOCKS_HTC_PSTATE_ACTIVE",
+     .udesc = "Number of clocks HTC P-state is active",
+     .ucode = 0x40,
+   },
+   { .uname  = "ALL",
+     .udesc  = "All sub-events selected",
+     .ucode = 0x64,
+     .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
+   },
+};
+
+static const amd64_umask_t amd64_fam15h_nb_cpu_io_requests_to_memory_io[]={
+   { .uname = "REMOTE_IO_TO_LOCAL_IO",
+     .udesc = "Remote IO to Local IO",
+     .ucode = 0x61,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "REMOTE_CPU_TO_LOCAL_IO",
+     .udesc = "Remote CPU to Local IO",
+     .ucode = 0x64,
+     .uflags= AMD64_FL_NCOMBO,
+   },
+   { .uname = "LOCAL_I