Exposed per-core timer interrupts on SPARC
authorAndrew Waterman <waterman@ros-dev.(none)>
Tue, 20 Apr 2010 21:19:12 +0000 (14:19 -0700)
committerKevin Klues <klueska@cs.berkeley.edu>
Thu, 3 Nov 2011 00:35:43 +0000 (17:35 -0700)
timer_interrupt() will be called on a timer interrupt.  set_timer(usec) arms
a core's timer.  Beware that, internally, we only support a power-of-2 number
of cycles as the timer period, so the usec value will be rounded up to the
next power-of-2 cycle count.  Also, the max period is 2^24 cycles (~60 HZ for
a 1 GHz target clock).

kern/arch/sparc/arch.h
kern/arch/sparc/sparc.h
kern/arch/sparc/timer.c
kern/arch/sparc/timer.h
kern/arch/sparc/trap_table.S

index 74f56a9..6a124b3 100644 (file)
@@ -81,13 +81,13 @@ read_tsc_serialized(void)
 static __inline void
 enable_irq(void)
 {
-       write_psr(read_psr() & ~0xF00);
+       write_psr(read_psr() & ~PSR_PIL);
 }
 
 static __inline void
 disable_irq(void)
 {
-       write_psr(read_psr() | 0xF00);
+       write_psr(read_psr() | PSR_PIL);
 }
 
 static __inline void
index d8c8212..95b5602 100644 (file)
@@ -23,6 +23,7 @@
 #define XSTR(arg) STR(arg)
 
 #include <ros/common.h>
+#include <arch/timer.h>
 
 static __inline uint32_t read_psr(void) __attribute__((always_inline));
 static __inline uint32_t read_wim(void) __attribute__((always_inline));
@@ -186,7 +187,7 @@ send_ipi(uint32_t dst)
 static __inline void
 sparc_set_timer(uint32_t clocks, uint32_t enable)
 {
-       store_iobus(1,0,enable << 24 | (clocks-1));
+       store_iobus(1,0,enable << TIMER_PERIOD_BITS | (clocks-1));
 }
 
 #endif /* !__ASSEMBLER__ */
index 820333a..71cf85e 100644 (file)
 #endif
 
 system_timing_t system_timing = {0};
-volatile uint32_t timer_ticks = 0;
 
-asm (
-".global handle_timer_interrupt                \n\t"
-"handle_timer_interrupt:               \n\t"
-"      mov     " XSTR(CORE_ID_REG) ",%l3       \n\t"
-"      mov     %psr,%l4                        \n\t"
-"      cmp     %l3,0                           \n\t"
-"      bne     1f                              \n\t"
-"       mov    %l4,%psr                        \n\t"
-"      sethi   %hi(timer_ticks),%l4            \n\t"
-"      ld      [%l4+%lo(timer_ticks)],%l5      \n\t"
-"      inc     %l5                             \n\t"
-"      st      %l5,[%l4+%lo(timer_ticks)]      \n\t"
-"1:    jmp     %l1                             \n\t"
-"       rett   %l2                             \n\t" );
+void
+timer_interrupt(void)
+{
+}
 
 void
 timer_init(void)
@@ -39,11 +28,8 @@ set_timer(uint32_t usec)
 {
        uint32_t clocks =  (uint64_t)usec*TSC_HZ/1000000;
        if(clocks & (clocks-1))
-       {
                clocks = ROUNDUPPWR2(clocks);
-               warn("set_timer: rounding up to %d usec",
-                    (uint64_t)clocks*1000000/TSC_HZ);
-       }
+
        if(clocks > TIMER_MAX_PERIOD)
        {
                clocks = TIMER_MAX_PERIOD;
index 7d0e030..55ac719 100644 (file)
@@ -1,8 +1,9 @@
 #ifndef ROS_ARCH_TIMER_H
 #define ROS_ARCH_TIMER_H
 
-#define TSC_HZ 1000000 // really, this is the core clock frequency
-#define TIMER_MAX_PERIOD (1 << 24) // in cycles
+#define TSC_HZ 1000000000 // really, this is the core clock frequency
+#define TIMER_PERIOD_BITS 24
+#define TIMER_MAX_PERIOD (1 << TIMER_PERIOD_BITS) // in cycles
 
 #include <ros/common.h>
 
index a3cc060..845e3d6 100644 (file)
@@ -38,7 +38,7 @@ trap_table_pagefault:
        UNHANDLED_TRAP                          ! 0x17
        UNHANDLED_TRAP                          ! 0x18
        UNHANDLED_TRAP                          ! 0x19
-       JMP(handle_timer_interrupt)             ! 0x1A
+       TRAP_TABLE_ENTRY(timer_interrupt)               ! 0x1A
        UNHANDLED_TRAP                          ! 0x1B
        UNHANDLED_TRAP                          ! 0x1C
        UNHANDLED_TRAP                          ! 0x1D