Use correct memory barrier on x86
authorAndrew Waterman <waterman@s143.Millennium.Berkeley.EDU>
Sun, 2 May 2010 20:56:54 +0000 (13:56 -0700)
committerKevin Klues <klueska@cs.berkeley.edu>
Thu, 3 Nov 2011 00:35:46 +0000 (17:35 -0700)
commitec2d36521917f6b6b9c896db2db5e1778a310f3d
tree63f0f7ac96fa38f6c6022b09f012ab4306d7d1e6
parentf9638859c4fb4d865cde8135c1ca3eee96375404
Use correct memory barrier on x86

On Intel implementations of x86, SFENCE seems to only have any effect on
programs that use the write-combining buffers (e.g., those that use the
SSE instruction MOVNTPS).  Its semantics seem to NOT guarantee load-to-store
ordering.

LFENCE and SFENCE do not prevent older stores from bypassing younger
loads to different addresses, which is something a full memory barrier
should most definitely do.  So, mb() should call MFENCE, which does
have this property, not LFENCE+SFENCE.  If the latter two worked, it
may be because they happened to interlock the pipeline just enough that
the desired ordering serendipitously was enforced.
kern/arch/i686/ros/membar.h