perf: Fix GPF when writing fixed trigger counters
authorBarret Rhoden <brho@cs.berkeley.edu>
Fri, 20 May 2016 15:34:02 +0000 (11:34 -0400)
committerBarret Rhoden <brho@cs.berkeley.edu>
Thu, 16 Jun 2016 15:48:37 +0000 (11:48 -0400)
commitb54b815425d2c37d630f4475921ec6dcb82706b2
treec859837994cfe78542a9f414eb82b6b307be6573
parente4c3cc214849421a1ff584112b982b65f65d1d49
perf: Fix GPF when writing fixed trigger counters

There are a bunch of bits reserved in fixed counters.  We must set the
upper ones to 0.  We'll still overflow properly; the register is just
smaller.

The unfixed perf counters also have a width, but I didn't get a GPF when
setting the upper bits.  Still - we should do the right thing and not set
those upper bits.

Signed-off-by: Barret Rhoden <brho@cs.berkeley.edu>
kern/arch/x86/perfmon.c