Add RISC-V CAS via load-reserved/store conditional
authorAndrew Waterman <waterman@cs.berkeley.edu>
Wed, 27 Mar 2013 09:59:49 +0000 (02:59 -0700)
committerAndrew Waterman <waterman@cs.berkeley.edu>
Wed, 27 Mar 2013 10:05:50 +0000 (03:05 -0700)
commit7f12842dcadeef2e5412e9a84280732deb283e9a
tree4f1fa7c101168fef16df6ffa16015db124f9f1ac
parente317184b861e76a8712fe8d2eaa6a484d0a9fc8a
Add RISC-V CAS via load-reserved/store conditional
kern/arch/riscv/Makefrag
kern/arch/riscv/atomic.c [deleted file]
kern/arch/riscv/atomic.h
tools/compilers/gcc-glibc/binutils-2.21.1-riscv.patch
tools/compilers/gcc-glibc/gcc-4.6.1-riscv.patch
tools/compilers/gcc-glibc/glibc-2.14.1-riscv.patch
user/parlib/include/riscv/atomic.h
user/parlib/riscv/vcore.S