Improve RISC-V cpu_relax
authorAndrew Waterman <waterman@cs.berkeley.edu>
Tue, 23 Apr 2013 12:20:54 +0000 (05:20 -0700)
committerAndrew Waterman <waterman@cs.berkeley.edu>
Tue, 23 Apr 2013 12:20:54 +0000 (05:20 -0700)
commit7958bc79707a451c43af4da798a7fb9fe64c562e
tree7db86709dae4e8b9a98bbf533bcc3d12ff3fb77a
parent108bfcf3791472e048cb43d3d39dc32bbac99958
Improve RISC-V cpu_relax

Before, it executed a tight loop, which isn't energy efficient.  Now,
it divides 0 by 0 and "uses" the result, which, on our in-order
microarchitectures, results in a long-latency stall that doesn't burn too
much energy.
kern/arch/riscv/arch.h