VM regions: management functions and structs
[akaros.git] / kern / src / init.c
index 3a6c6a8..523a52c 100644 (file)
@@ -1,19 +1,19 @@
 /* See COPYRIGHT for copyright information. */
 
-#ifdef __DEPUTY__
-#pragma nodeputy
+#ifdef __SHARC__
+#pragma nosharc
 #endif
 
-#ifdef __BSD_ON_CORE_0__
-#include Everything For Free -- It just works!!
+#ifdef __CONFIG_BSD_ON_CORE0__
+#error "Yeah, it's not possible to build ROS with BSD on Core 0, sorry......"
 #else
 
-#include <arch/x86.h>
-#include <arch/apic.h>
+#include <ros/timer.h>
+#include <arch/arch.h>
 #include <arch/console.h>
-#include <arch/multiboot.h>
-#include <arch/stab.h>
-#include <arch/smp.h>
+#include <multiboot.h>
+#include <stab.h>
+#include <smp.h>
 
 #include <atomic.h>
 #include <stdio.h>
 #include <assert.h>
 #include <monitor.h>
 #include <pmap.h>
-#include <env.h>
+#include <process.h>
 #include <trap.h>
-#include <testing.h>
 #include <syscall.h>
 #include <kclock.h>
 #include <manager.h>
+#include <testing.h>
+#include <kmalloc.h>
+#include <hashtable.h>
+#include <mm.h>
+#include <frontend.h>
 
-static void print_cpuinfo(void);
+#include <arch/init.h>
+#include <arch/bitmask.h>
+#include <slab.h>
+#include <kfs.h>
+#include <vfs.h>
+
+// zra: flag for Ivy
+int booting = 1;
 
 void kernel_init(multiboot_info_t *mboot_info)
 {
-       extern char (BND(__this, end) edata)[], (SNT end)[];
+       extern char (RO BND(__this, end) edata)[], (RO SNT end)[];
 
        // Before doing anything else, complete the ELF loading process.
        // Clear the uninitialized global data (BSS) section of our program.
@@ -45,27 +56,45 @@ void kernel_init(multiboot_info_t *mboot_info)
 
        print_cpuinfo();
 
-       i386_detect_memory((multiboot_info_t*)((uint32_t)mboot_info + KERNBASE));
-       i386_print_memory_map((multiboot_info_t*)((uint32_t)mboot_info + KERNBASE));
-       i386_vm_init();
-       page_init();
+       // Old way, pre Zach's Ivy annotations
+       //multiboot_detect_memory((multiboot_info_t*)((uint32_t)mboot_info + KERNBASE));
+       //multiboot_print_memory_map((multiboot_info_t*)((uint32_t)mboot_info + KERNBASE));
+       
+       // Paul: Can't use KADDR as arg to multiboot_detect_memory
+       //  since multiboot_detect_memory is what sets npages. 
+       //  Must simulate KADDR macro (ugly).
+       multiboot_detect_memory((multiboot_info_t*CT(1))TC((physaddr_t)mboot_info + KERNBASE));
+
+       multiboot_print_memory_map((multiboot_info_t*CT(1))KADDR((physaddr_t)mboot_info));
+
+       vm_init();                      // Sets up pages tables, turns on paging
+       cache_init();                                   // Determine systems's cache properties
+       page_init();                                    // Initializes free page list, etc
+       kmem_cache_init();              // Sets up slab allocator
+       kmalloc_init();
+       hashtable_init();
+       cache_color_alloc_init();       // Inits data structs
+       colored_page_alloc_init();      // Allocates colors for agnostic processes
+       vmr_init();
+       file_init();
        page_check();
-
-       env_init();
+       vfs_init();
        idt_init();
+       kernel_msg_init();
        sysenter_init();
        timer_init();
-       // this returns when all other cores are done and ready to receive IPIs
-       smp_boot();
-       /*
-       test_smp_call_functions();
-       test_checklists();
-       test_barrier();
-       test_print_info();
-       test_lapic_status_bit();
-       test_ipi_sending();
-       test_pit();
-       */
+       train_timing();
+       
+       // At this point our boot paths diverge based on arch. 
+       arch_init();
+               
+//     printk("Starting tests....\n");
+//     test_color_alloc();
+//     printk("Testing complete....\n");
+
+       // zra: let's Ivy know we're done booting
+       booting = 0;
+
        manager();
 }
 
@@ -78,19 +107,14 @@ void _panic(const char *file, int line, const char *fmt,...)
        va_list ap;
 
        va_start(ap, fmt);
-       cprintf("kernel panic at %s:%d, from core %d: ", file, line, lapic_get_id());
+       cprintf("kernel panic at %s:%d, from core %d: ", file, line, core_id());
        vcprintf(fmt, ap);
        cprintf("\n");
        va_end(ap);
 
 dead:
-       /* break into the kernel monitor, if we're core 0 */
-       if (lapic_get_id()) {
-               smp_idle();
-               panic("should never see me");
-       }
-       while (1)
-               monitor(NULL);
+       monitor(NULL);
+       smp_idle();
 }
 
 /* like panic, but don't */
@@ -99,79 +123,10 @@ void _warn(const char *file, int line, const char *fmt,...)
        va_list ap;
 
        va_start(ap, fmt);
-       cprintf("kernel warning at %s:%d, from core %d: ", file, line, lapic_get_id());
+       cprintf("kernel warning at %s:%d, from core %d: ", file, line, core_id());
        vcprintf(fmt, ap);
        cprintf("\n");
        va_end(ap);
 }
 
-static void print_cpuinfo(void) {
-       uint32_t eax, ebx, ecx, edx;
-       uint32_t model, family;
-       uint64_t msr_val;
-       char vendor_id[13];
-
-       asm volatile ("cpuid;"
-                  "movl    %%ebx, (%2);"
-                  "movl    %%edx, 4(%2);"
-                  "movl    %%ecx, 8(%2);"
-                     : "=a"(eax)
-                                 : "a"(0), "D"(vendor_id)
-                     : "%ebx", "%ecx", "%edx");
-
-       vendor_id[12] = '\0';
-       cprintf("Vendor ID: %s\n", vendor_id);
-       cprintf("Largest Standard Function Number Supported: %d\n", eax);
-       cpuid(0x80000000, &eax, 0, 0, 0);
-       cprintf("Largest Extended Function Number Supported: 0x%08x\n", eax);
-       cpuid(1, &eax, &ebx, &ecx, &edx);
-       family = ((eax & 0x0FF00000) >> 20) + ((eax & 0x00000F00) >> 8);
-       model = ((eax & 0x000F0000) >> 12) + ((eax & 0x000000F0) >> 4);
-       cprintf("Family: %d\n", family);
-       cprintf("Model: %d\n", model);
-       cprintf("Stepping: %d\n", eax & 0x0000000F);
-       // eventually can fill this out with SDM Vol3B App B info, or
-       // better yet with stepping info.  or cpuid 8000_000{2,3,4}
-       switch ( family << 8 | model ) {
-               case(0x061a):
-                       cprintf("Processor: Core i7\n");
-                       break;
-               case(0x060f):
-                       cprintf("Processor: Core 2 Duo or Similar\n");
-                       break;
-               default:
-                       cprintf("Unknown or non-Intel CPU\n");
-       }
-       if (!(edx & 0x00000020))
-               panic("MSRs not supported!");
-       if (!(edx & 0x00001000))
-               panic("MTRRs not supported!");
-       if (!(edx & 0x00002000))
-               panic("Global Pages not supported!");
-       if (!(edx & 0x00000200))
-               panic("Local APIC Not Detected!");
-       if (ecx & 0x00200000)
-               cprintf("x2APIC Detected\n");
-       else
-               cprintf("x2APIC Not Detected\n");
-       cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
-       cprintf("Physical Address Bits: %d\n", eax & 0x000000FF);
-       cprintf("Cores per Die: %d\n", (ecx & 0x000000FF) + 1);
-    cprintf("This core's Default APIC ID: 0x%08x\n", lapic_get_default_id());
-       msr_val = read_msr(IA32_APIC_BASE);
-       if (msr_val & MSR_APIC_ENABLE)
-               cprintf("Local APIC Enabled\n");
-       else
-               cprintf("Local APIC Disabled\n");
-       if (msr_val & 0x00000100)
-               cprintf("I am the Boot Strap Processor\n");
-       else
-               cprintf("I am an Application Processor\n");
-       cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
-       if (edx & 0x00000100)
-               printk("Invariant TSC present\n");
-       else
-               printk("Invariant TSC not present\n");
-}
-
 #endif //Everything For Free