#include <arch/mmu.h>
/* Model Specific Registers */
+// TODO: figure out which are intel specific, and name them accordingly
#define IA32_APIC_BASE 0x1b
+/* These two are intel-only */
#define IA32_FEATURE_CONTROL 0x3a
#define IA32_MISC_ENABLE 0x1a0
#define MSR_APIC_ENABLE 0x00000800
#define MSR_APIC_BASE_ADDRESS 0x0000000FFFFFF000
+#define IA32_EFER_MSR 0xc0000080
+# define IA32_EFER_SYSCALL (1 << 0)
+# define IA32_EFER_IA32E_EN (1 << 8)
+# define IA32_EFER_IA32E_ACT (1 << 10)
+# define IA32_EFER_EXE_DIS_BIT (1 << 11)
+
+#define MSR_TSC_AUX 0xc0000103
+
+#define MSR_FS_BASE 0xc0000100
+#define MSR_GS_BASE 0xc0000101
+#define MSR_KERN_GS_BASE 0xc0000102
+
+#define MSR_STAR 0xc0000081
+#define MSR_LSTAR 0xc0000082
+#define MSR_CSTAR 0xc0000083
+#define MSR_SFMASK 0xc0000084
+
/* CPUID */
#define CPUID_PSE_SUPPORT 0x00000008
#endif /* 64bit / 32bit */
+/* Various flags defined: can be included from assembler. */
+
+/*
+ * EFLAGS bits
+ */
+#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
+#define X86_EFLAGS_BIT1 0x00000002 /* Bit 1 - always on */
+#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
+#define X86_EFLAGS_AF 0x00000010 /* Auxiliary carry Flag */
+#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
+#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
+#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
+#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
+#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
+#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
+#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
+#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
+#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
+#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
+#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
+#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
+#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
+#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
+
+/*
+ * Basic CPU control in CR0
+ */
+#define X86_CR0_PE 0x00000001 /* Protection Enable */
+#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */
+#define X86_CR0_EM 0x00000004 /* Emulation */
+#define X86_CR0_TS 0x00000008 /* Task Switched */
+#define X86_CR0_ET 0x00000010 /* Extension Type */
+#define X86_CR0_NE 0x00000020 /* Numeric Error */
+#define X86_CR0_WP 0x00010000 /* Write Protect */
+#define X86_CR0_AM 0x00040000 /* Alignment Mask */
+#define X86_CR0_NW 0x20000000 /* Not Write-through */
+#define X86_CR0_CD 0x40000000 /* Cache Disable */
+#define X86_CR0_PG 0x80000000 /* Paging */
+
+/*
+ * Paging options in CR3
+ */
+#define X86_CR3_PWT 0x00000008 /* Page Write Through */
+#define X86_CR3_PCD 0x00000010 /* Page Cache Disable */
+#define X86_CR3_PCID_MASK 0x00000fff /* PCID Mask */
+
+/*
+ * Intel CPU features in CR4
+ */
+#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */
+#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */
+#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */
+#define X86_CR4_DE 0x00000008 /* enable debugging extensions */
+#define X86_CR4_PSE 0x00000010 /* enable page size extensions */
+#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */
+#define X86_CR4_MCE 0x00000040 /* Machine check enable */
+#define X86_CR4_PGE 0x00000080 /* enable global pages */
+#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */
+#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */
+#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
+#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */
+#define X86_CR4_RDWRGSFS 0x00010000 /* enable RDWRGSFS support */
+#define X86_CR4_PCIDE 0x00020000 /* enable PCID support */
+#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
+#define X86_CR4_SMEP 0x00100000 /* enable SMEP support */
+#define X86_CR4_SMAP 0x00200000 /* enable SMAP support */
+
+/*
+ * x86-64 Task Priority Register, CR8
+ */
+#define X86_CR8_TPR 0x0000000F /* task priority register */
+
+#ifndef __ASSEMBLER__
static inline uint8_t inb(int port) __attribute__((always_inline));
static inline void insb(int port, void *addr, int cnt)
__attribute__((always_inline));
static inline void write_eflags(unsigned long eflags)
__attribute__((always_inline));
static inline unsigned long read_bp(void) __attribute__((always_inline));
-static inline unsigned long read_ip(void) __attribute__((always_inline));
+static inline unsigned long read_pc(void) __attribute__((always_inline));
static inline unsigned long read_sp(void) __attribute__((always_inline));
static inline void cpuid(uint32_t info1, uint32_t info2, uint32_t *eaxp,
uint32_t *ebxp, uint32_t *ecxp, uint32_t *edxp)
__attribute__((always_inline));
+static inline uint32_t cpuid_ecx(int op) __attribute__((always_inline));
static inline uint64_t read_msr(uint32_t reg) __attribute__((always_inline));
static inline void write_msr(uint32_t reg, uint64_t val)
__attribute__((always_inline));
return bp;
}
-static inline unsigned long read_ip(void)
+static inline unsigned long read_pc(void)
{
unsigned long ip;
asm volatile("call 1f; 1: pop %0" : "=r"(ip));
*edxp = edx;
}
+static inline uint32_t cpuid_ecx(int opcode)
+{
+ uint32_t ecx;
+ cpuid(1, 0, NULL, NULL, &ecx, NULL);
+ return ecx;
+}
+
// Might need to mfence rdmsr. supposedly wrmsr serializes, but not for x2APIC
static inline uint64_t read_msr(uint32_t reg)
{
#ifndef UNUSED_ARG
#define UNUSED_ARG(x) (void)x
#endif /* This prevents compiler warnings for UNUSED_ARG */
+#endif /* !__ASSEMBLER__ */
#endif /* !ROS_INC_X86_H */
projects / akaros.git / blobdiff