Begin work on true virtio mmio Kill tests/vmrunkernel.c Our makefiles, plus emacs...
[akaros.git] / kern / arch / x86 / vmm / intel / vmx.c
index 8efa0b2..e4198fc 100644 (file)
@@ -1,3 +1,4 @@
+//#define DEBUG
 /**
  *  vmx.c - The Intel VT-x driver for Dune
  *
@@ -92,8 +93,8 @@
  * We divide this into two things: vmm_proc_init and vm_run.
  * Currently, on Intel, vmm_proc_init does nothing.
  *
- * vm_run is really complicated. It is called with a coreid, rip, rsp,
- * cr3, and flags.  On intel, it calls vmx_launch. vmx_launch is set
+ * vm_run is really complicated. It is called with a coreid, and
+ * vmctl struct. On intel, it calls vmx_launch. vmx_launch is set
  * up for a few test cases. If rip is 1, it sets the guest rip to
  * a function which will deref 0 and should exit with failure 2. If rip is 0,
  * it calls an infinite loop in the guest.
 #include <bitops.h>
 #include <arch/types.h>
 #include <syscall.h>
+#include <arch/io.h>
 
 #include "vmx.h"
 #include "../vmm.h"
+#include <ros/vmm.h>
 
-#include "compat.h"
 #include "cpufeature.h"
 
 #define currentcpu (&per_cpu_info[core_id()])
 
-/*
- * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
- * away by decrementing the array size.
- */
-static const uint32_t vmx_msr_index[] = {
-#ifdef CONFIG_X86_64
-       MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
-#endif
-       MSR_EFER, MSR_TSC_AUX, MSR_STAR,
-};
-#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
-
 static unsigned long *msr_bitmap;
+#define VMX_IO_BITMAP_ORDER            4       /* 64 KB */
+#define VMX_IO_BITMAP_SZ               (1 << (VMX_IO_BITMAP_ORDER + PGSHIFT))
+static unsigned long *io_bitmap;
 
-static struct vmcs_config {
-       int size;
-       int order;
-       uint32_t revision_id;
-       uint32_t pin_based_exec_ctrl;
-       uint32_t cpu_based_exec_ctrl;
-       uint32_t cpu_based_2nd_exec_ctrl;
-       uint32_t vmexit_ctrl;
-       uint32_t vmentry_ctrl;
-} vmcs_config;
+int x86_ept_pte_fix_ups = 0;
 
 struct vmx_capability vmx_capability;
+struct vmcs_config vmcs_config;
 
-static inline bool cpu_has_secondary_exec_ctrls(void)
-{
-       return vmcs_config.cpu_based_exec_ctrl &
-               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
-}
-
-static inline bool cpu_has_vmx_vpid(void)
-{
-       return vmcs_config.cpu_based_2nd_exec_ctrl &
-               SECONDARY_EXEC_ENABLE_VPID;
-}
-
-static inline bool cpu_has_vmx_invpcid(void)
-{
-       return vmcs_config.cpu_based_2nd_exec_ctrl &
-               SECONDARY_EXEC_ENABLE_INVPCID;
-}
-
-static inline bool cpu_has_vmx_invvpid_single(void)
-{
-       return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
-}
-
-static inline bool cpu_has_vmx_invvpid_global(void)
-{
-       return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
-}
-
-static inline bool cpu_has_vmx_ept(void)
-{
-       return vmcs_config.cpu_based_2nd_exec_ctrl &
-               SECONDARY_EXEC_ENABLE_EPT;
-}
-
-static inline bool cpu_has_vmx_invept(void)
-{
-       return vmx_capability.ept & VMX_EPT_INVEPT_BIT;
-}
-
-/* the SDM (2015-01) doesn't mention this ability (still?) */
-static inline bool cpu_has_vmx_invept_individual_addr(void)
-{
-       return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
-}
-
-static inline bool cpu_has_vmx_invept_context(void)
-{
-       return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
-}
-
-static inline bool cpu_has_vmx_invept_global(void)
-{
-       return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
-}
-
-static inline bool cpu_has_vmx_ept_ad_bits(void)
-{
-       return vmx_capability.ept & VMX_EPT_AD_BIT;
-}
-
-static inline bool cpu_has_vmx_ept_execute_only(void)
-{
-       return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
-}
-
-static inline bool cpu_has_vmx_eptp_uncacheable(void)
-{
-       return vmx_capability.ept & VMX_EPTP_UC_BIT;
-}
-
-static inline bool cpu_has_vmx_eptp_writeback(void)
-{
-       return vmx_capability.ept & VMX_EPTP_WB_BIT;
-}
-
-static inline bool cpu_has_vmx_ept_2m_page(void)
-{
-       return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
-}
-
-static inline bool cpu_has_vmx_ept_1g_page(void)
-{
-       return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
-}
-
-static inline bool cpu_has_vmx_ept_4levels(void)
-{
-       return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
-}
-
-static inline void __invept(int ext, uint64_t eptp, gpa_t gpa)
-{
-       struct {
-               uint64_t eptp, gpa;
-       } operand = {eptp, gpa};
-
-       asm volatile (ASM_VMX_INVEPT
-                       /* CF==1 or ZF==1 --> rc = -1 */
-                       "; ja 1f ; ud2 ; 1:\n"
-                       : : "a" (&operand), "c" (ext) : "cc", "memory");
-}
-
-/* We assert support for the global flush during ept_init() */
-static inline void ept_sync_global(void)
-{
-       __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
-}
-
-static inline void ept_sync_context(uint64_t eptp)
-{
-       if (cpu_has_vmx_invept_context())
-               __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
-       else
-               ept_sync_global();
-}
-
-void ept_flush(uint64_t eptp)
-{
-       ept_sync_context(eptp);
-}
-
-static inline void ept_sync_individual_addr(uint64_t eptp, gpa_t gpa)
-{
-       if (cpu_has_vmx_invept_individual_addr())
-               __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
-                               eptp, gpa);
-       else
-               ept_sync_context(eptp);
-}
+static int autoloaded_msrs[] = {
+       MSR_KERNEL_GS_BASE,
+       MSR_LSTAR,
+       MSR_STAR,
+       MSR_SFMASK,
+};
 
-static inline void __vmxon(uint64_t addr)
-{
-       asm volatile (ASM_VMX_VMXON_RAX
-                       : : "a"(&addr), "m"(addr)
-                       : "memory", "cc");
-}
+static char *cr_access_type[] = {
+       "move to cr",
+       "move from cr",
+       "clts",
+       "lmsw"
+};
 
-static inline void __vmxoff(void)
-{
-       asm volatile (ASM_VMX_VMXOFF : : : "cc");
-}
+static char *cr_gpr[] = {
+       "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
+       "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
+};
 
-static inline void __invvpid(int ext, uint16_t vpid, gva_t gva)
-{
-    struct {
-       uint64_t vpid : 16;
-       uint64_t rsvd : 48;
-       uint64_t gva;
-    } operand = { vpid, 0, gva };
-
-    asm volatile (ASM_VMX_INVVPID
-                 /* CF==1 or ZF==1 --> rc = -1 */
-                 "; ja 1f ; ud2 ; 1:"
-                 : : "a"(&operand), "c"(ext) : "cc", "memory");
-}
+static int guest_cr_num[16] = {
+       GUEST_CR0,
+       -1,
+       -1,
+       GUEST_CR3,
+       GUEST_CR4,
+       -1,
+       -1,
+       -1,
+       -1,     /* 8? */
+       -1, -1, -1, -1, -1, -1, -1
+};
 
-static inline void vpid_sync_vcpu_single(uint16_t vpid)
-{
-       if (vpid == 0) {
-               return;
+__always_inline unsigned long vmcs_readl(unsigned long field);
+/* See section 24-3 of The Good Book */
+void
+show_cr_access(uint64_t val)
+{
+       int crnr = val & 0xf;
+       int type = (val >> 4) & 3;
+       int reg = (val >> 11) & 0xf;
+       printk("%s: %d: ", cr_access_type[type], crnr);
+       if (type < 2) {
+               printk("%s", cr_gpr[reg]);
+               if (guest_cr_num[crnr] > -1) {
+                       printk(": 0x%x", vmcs_readl(guest_cr_num[crnr]));
+               }
        }
-
-       if (cpu_has_vmx_invvpid_single())
-               __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
-}
-
-static inline void vpid_sync_vcpu_global(void)
-{
-       if (cpu_has_vmx_invvpid_global())
-               __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
+       printk("\n");
 }
 
-static inline void vpid_sync_context(uint16_t vpid)
+void
+ept_flush(uint64_t eptp)
 {
-       if (cpu_has_vmx_invvpid_single())
-               vpid_sync_vcpu_single(vpid);
-       else
-               vpid_sync_vcpu_global();
-}
-
-static inline uint64_t vcpu_get_eptp(struct vmx_vcpu *vcpu)
-{
-       return vcpu->proc->env_pgdir.eptp;
+       ept_sync_context(eptp);
 }
 
-static void vmcs_clear(struct vmcs *vmcs)
+static void
+vmcs_clear(struct vmcs *vmcs)
 {
        uint64_t phys_addr = PADDR(vmcs);
        uint8_t error;
 
-       asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
-                     : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
-                     "cc", "memory");
+       asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0":"=qm"(error):"a"(&phys_addr),
+                                 "m"(phys_addr)
+                                 :"cc", "memory");
        if (error)
-               printk("vmclear fail: %p/%llx\n",
-                      vmcs, phys_addr);
+               printk("vmclear fail: %p/%llx\n", vmcs, phys_addr);
 }
 
-static void vmcs_load(struct vmcs *vmcs)
+static void
+vmcs_load(struct vmcs *vmcs)
 {
        uint64_t phys_addr = PADDR(vmcs);
        uint8_t error;
 
-       asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
-                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
-                       "cc", "memory");
+       asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0":"=qm"(error):"a"(&phys_addr),
+                                 "m"(phys_addr)
+                                 :"cc", "memory");
        if (error)
-               printk("vmptrld %p/%llx failed\n",
-                      vmcs, phys_addr);
+               printk("vmptrld %p/%llx failed\n", vmcs, phys_addr);
 }
 
 /* Returns the paddr pointer of the current CPU's VMCS region, or -1 if none. */
-static physaddr_t vmcs_get_current(void)
+static physaddr_t
+vmcs_get_current(void)
 {
        physaddr_t vmcs_paddr;
        /* RAX contains the addr of the location to store the VMCS pointer.  The
         * compiler doesn't know the ASM will deref that pointer, hence the =m */
-       asm volatile (ASM_VMX_VMPTRST_RAX : "=m"(vmcs_paddr) : "a"(&vmcs_paddr));
+       asm volatile (ASM_VMX_VMPTRST_RAX:"=m"(vmcs_paddr):"a"(&vmcs_paddr));
        return vmcs_paddr;
 }
 
-__always_inline unsigned long vmcs_readl(unsigned long field)
+__always_inline unsigned long
+vmcs_readl(unsigned long field)
 {
        unsigned long value;
 
-       asm volatile (ASM_VMX_VMREAD_RDX_RAX
-                     : "=a"(value) : "d"(field) : "cc");
+       asm volatile (ASM_VMX_VMREAD_RDX_RAX:"=a"(value):"d"(field):"cc");
        return value;
 }
 
-__always_inline uint16_t vmcs_read16(unsigned long field)
+__always_inline uint16_t
+vmcs_read16(unsigned long field)
 {
        return vmcs_readl(field);
 }
 
-static __always_inline uint32_t vmcs_read32(unsigned long field)
+static __always_inline uint32_t
+vmcs_read32(unsigned long field)
 {
        return vmcs_readl(field);
 }
 
-static __always_inline uint64_t vmcs_read64(unsigned long field)
+static __always_inline uint64_t
+vmcs_read64(unsigned long field)
 {
-#ifdef CONFIG_X86_64
        return vmcs_readl(field);
-#else
-       return vmcs_readl(field) | ((uint64_t)vmcs_readl(field+1) << 32);
-#endif
 }
 
-void vmwrite_error(unsigned long field, unsigned long value)
+void
+vmwrite_error(unsigned long field, unsigned long value)
 {
        printk("vmwrite error: reg %lx value %lx (err %d)\n",
-              field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
+                  field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 }
 
-void vmcs_writel(unsigned long field, unsigned long value)
+void
+vmcs_writel(unsigned long field, unsigned long value)
 {
        uint8_t error;
 
-       asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
-                      : "=q"(error) : "a"(value), "d"(field) : "cc");
+       asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0":"=q"(error):"a"(value),
+                                 "d"(field):"cc");
        if (error)
                vmwrite_error(field, value);
 }
 
-static void vmcs_write16(unsigned long field, uint16_t value)
+static void
+vmcs_write16(unsigned long field, uint16_t value)
 {
        vmcs_writel(field, value);
 }
 
-static void vmcs_write32(unsigned long field, uint32_t value)
+static void
+vmcs_write32(unsigned long field, uint32_t value)
 {
        vmcs_writel(field, value);
 }
 
-static void vmcs_write64(unsigned long field, uint64_t value)
+static void
+vmcs_write64(unsigned long field, uint64_t value)
 {
        vmcs_writel(field, value);
 }
 
-static int adjust_vmx_controls(uint32_t ctl_min, uint32_t ctl_opt,
-                                     uint32_t msr, uint32_t *result)
+/*
+ * A note on Things You Can't Make Up.
+ * or
+ * "George, you can type this shit, but you can't say it" -- Harrison Ford
+ *
+ * There are 5 VMCS 32-bit words that control guest permissions. If
+ * you set these correctly, you've got a guest that will behave. If
+ * you get even one bit wrong, you've got a guest that will chew your
+ * leg off. Some bits must be 1, some must be 0, and some can be set
+ * either way. To add to the fun, the docs are sort of a docudrama or,
+ * as the quote goes, "interesting if true."
+ *
+ * To determine what bit can be set in what VMCS 32-bit control word,
+ * there are 5 corresponding 64-bit MSRs.  And, to make it even more
+ * fun, the standard set of MSRs have errors in them, i.e. report
+ * incorrect values, for legacy reasons, and so you are supposed to
+ * "look around" to another set, which have correct bits in
+ * them. There are four such 'correct' registers, and they have _TRUE_
+ * in the names as you can see below. We test for the value of VMCS
+ * control bits in the _TRUE_ registers if possible. The fifth
+ * register, CPU Secondary Exec Controls, which came later, needs no
+ * _TRUE_ variant.
+ *
+ * For each MSR, the high 32 bits tell you what bits can be "1" by a
+ * "1" in that position; the low 32 bits tell you what bit can be "0"
+ * by a "0" in that position. So, for each of 32 bits in a given VMCS
+ * control word, there is a pair of bits in an MSR that tells you what
+ * values it can take. The two bits, of which there are *four*
+ * combinations, describe the *three* possible operations on a
+ * bit. The two bits, taken together, form an untruth table: There are
+ * three possibilities: The VMCS bit can be set to 0 or 1, or it can
+ * only be 0, or only 1. The fourth combination is not supposed to
+ * happen.
+ *
+ * So: there is the 1 bit from the upper 32 bits of the msr.
+ * If this bit is set, then the bit can be 1. If clear, it can not be 1.
+ *
+ * Then there is the 0 bit, from low 32 bits. If clear, the VMCS bit
+ * can be 0. If 1, the VMCS bit can not be 0.
+ *
+ * SO, let's call the 1 bit R1, and the 0 bit R0, we have:
+ *  R1 R0
+ *  0 0 -> must be 0
+ *  1 0 -> can be 1, can be 0
+ *  0 1 -> can not be 1, can not be 0. --> JACKPOT! Not seen yet.
+ *  1 1 -> must be one.
+ *
+ * It's also pretty hard to know what you can and can't set, and
+ * that's led to inadvertant opening of permissions at times.  Because
+ * of this complexity we've decided on the following: the driver must
+ * define EVERY bit, UNIQUELY, for each of the 5 registers, that it wants
+ * set. Further, for any bit that's settable, the driver must specify
+ * a setting; for any bit that's reserved, the driver settings must
+ * match that bit. If there are reserved bits we don't specify, that's
+ * ok; we'll take them as is.
+ *
+ * We use a set-means-set, and set-means-clear model, i.e. we use a
+ * 32-bit word to contain the bits we want to be 1, indicated by one;
+ * and another 32-bit word in which a bit we want to be 0 is indicated
+ * by a 1. This allows us to easily create masks of all bits we're
+ * going to set, for example.
+ *
+ * We have two 32-bit numbers for each 32-bit VMCS field: bits we want
+ * set and bits we want clear.  If you read the MSR for that field,
+ * compute the reserved 0 and 1 settings, and | them together, they
+ * need to result in 0xffffffff. You can see that we can create other
+ * tests for conflicts (i.e. overlap).
+ *
+ * At this point, I've tested check_vmx_controls in every way
+ * possible, beause I kept screwing the bitfields up. You'll get a nice
+ * error it won't work at all, which is what we want: a
+ * failure-prone setup, where even errors that might result in correct
+ * values are caught -- "right answer, wrong method, zero credit." If there's
+ * weirdness in the bits, we don't want to run.
+ */
+
+static bool
+check_vmxec_controls(struct vmxec const *v, bool have_true_msr,
+                                        uint32_t * result)
 {
+       bool err = false;
        uint32_t vmx_msr_low, vmx_msr_high;
-       uint32_t ctl = ctl_min | ctl_opt;
-       uint64_t vmx_msr = read_msr(msr);
-       vmx_msr_low = vmx_msr;
-       vmx_msr_high = vmx_msr>>32;
+       uint32_t reserved_0, reserved_1, changeable_bits;
 
-       ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
-       ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
+       if (have_true_msr)
+               rdmsr(v->truemsr, vmx_msr_low, vmx_msr_high);
+       else
+               rdmsr(v->msr, vmx_msr_low, vmx_msr_high);
 
-       /* Ensure minimum (required) set of control bits are supported. */
-       if (ctl_min & ~ctl) {
-               return -EIO;
-       }
+       if (vmx_msr_low & ~vmx_msr_high)
+               warn("JACKPOT: Conflicting VMX ec ctls for %s, high 0x%08x low 0x%08x",
+                        v->name, vmx_msr_high, vmx_msr_low);
 
-       *result = ctl;
-       return 0;
-}
+       reserved_0 = (~vmx_msr_low) & (~vmx_msr_high);
+       reserved_1 = vmx_msr_low & vmx_msr_high;
+       changeable_bits = ~(reserved_0 | reserved_1);
 
-static  bool allow_1_setting(uint32_t msr, uint32_t ctl)
-{
-       uint32_t vmx_msr_low, vmx_msr_high;
+       /*
+        * this is very much as follows:
+        * accept the things I cannot change,
+        * change the things I can,
+        * know the difference.
+        */
 
-       rdmsr(msr, vmx_msr_low, vmx_msr_high);
-       return vmx_msr_high & ctl;
-}
+       /* Conflict. Don't try to both set and reset bits. */
+       if (v->set_to_0 & v->set_to_1) {
+               printk("%s: set to 0 (0x%x) and set to 1 (0x%x) overlap: 0x%x\n",
+                          v->name, v->set_to_0, v->set_to_1, v->set_to_0 & v->set_to_1);
+               err = true;
+       }
 
-static  void setup_vmcs_config(void *p)
-{
-       int *ret = p;
-       struct vmcs_config *vmcs_conf = &vmcs_config;
-       uint32_t vmx_msr_low, vmx_msr_high;
-       uint32_t min, opt, min2, opt2;
-       uint32_t _pin_based_exec_control = 0;
-       uint32_t _cpu_based_exec_control = 0;
-       uint32_t _cpu_based_2nd_exec_control = 0;
-       uint32_t _vmexit_control = 0;
-       uint32_t _vmentry_control = 0;
+       /* coverage */
+       if (((v->set_to_0 | v->set_to_1) & changeable_bits) != changeable_bits) {
+               printk("%s: Need to cover 0x%x and have 0x%x,0x%x\n",
+                          v->name, changeable_bits, v->set_to_0, v->set_to_1);
+               err = true;
+       }
 
-       *ret = -EIO;
-       min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
-       opt = PIN_BASED_VIRTUAL_NMIS;
-       if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
-                               &_pin_based_exec_control) < 0) {
-               return;
+       if ((v->set_to_0 | v->set_to_1 | reserved_0 | reserved_1) != 0xffffffff) {
+               printk("%s: incomplete coverage: have 0x%x, want 0x%x\n",
+                          v->name, v->set_to_0 | v->set_to_1 |
+                          reserved_0 | reserved_1, 0xffffffff);
+               err = true;
        }
 
-       min =
-             CPU_BASED_CR8_LOAD_EXITING |
-             CPU_BASED_CR8_STORE_EXITING |
-             CPU_BASED_CR3_LOAD_EXITING |
-             CPU_BASED_CR3_STORE_EXITING |
-             CPU_BASED_MOV_DR_EXITING |
-             CPU_BASED_USE_TSC_OFFSETING |
-             CPU_BASED_MWAIT_EXITING |
-             CPU_BASED_MONITOR_EXITING |
-             CPU_BASED_INVLPG_EXITING;
-
-       min |= CPU_BASED_HLT_EXITING;
-
-       opt = CPU_BASED_TPR_SHADOW |
-             CPU_BASED_USE_MSR_BITMAPS |
-             CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
-       if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
-                               &_cpu_based_exec_control) < 0) {
-               return;
+       /* Don't try to change bits that can't be changed. */
+       if ((v->set_to_0 & (reserved_0 | changeable_bits)) != v->set_to_0) {
+               printk("%s: set to 0 (0x%x) can't be done\n", v->name, v->set_to_0);
+               err = true;
        }
 
-       if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
-               _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
-                                          ~CPU_BASED_CR8_STORE_EXITING;
-
-       if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
-               min2 = 
-                       SECONDARY_EXEC_ENABLE_EPT |
-                       SECONDARY_EXEC_UNRESTRICTED_GUEST;
-               opt2 =  SECONDARY_EXEC_WBINVD_EXITING |
-                       SECONDARY_EXEC_RDTSCP |
-                       SECONDARY_EXEC_ENABLE_INVPCID;
-               if (adjust_vmx_controls(min2, opt2,
-                                       MSR_IA32_VMX_PROCBASED_CTLS2,
-                                       &_cpu_based_2nd_exec_control) < 0) {
-                                               return;
-                                       }
+       if ((v->set_to_1 & (reserved_1 | changeable_bits)) != v->set_to_1) {
+               printk("%s: set to 1 (0x%x) can't be done\n", v->name, v->set_to_1);
+               err = true;
        }
 
-       if (!(_cpu_based_2nd_exec_control &
-                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
-               _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
-
-       if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
-               /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
-                  enabled */
-               _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
-                                            CPU_BASED_CR3_STORE_EXITING |
-                                            CPU_BASED_INVLPG_EXITING);
-               rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
-                     vmx_capability.ept, vmx_capability.vpid);
+       /* If there's been any error at all, spill our guts and return. */
+       if (err) {
+               printk("%s: vmx_msr_high 0x%x, vmx_msr_low 0x%x, ",
+                          v->name, vmx_msr_high, vmx_msr_low);
+               printk("set_to_1 0x%x,set_to_0 0x%x,reserved_1 0x%x",
+                          v->set_to_1, v->set_to_0, reserved_1);
+               printk(" reserved_0 0x%x", reserved_0);
+               printk(" changeable_bits 0x%x\n", changeable_bits);
+               return false;
        }
 
-       min = 0;
+       *result = v->set_to_1 | reserved_1;
 
-       min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
+       printd("%s: check_vmxec_controls succeeds with result 0x%x\n",
+                  v->name, *result);
+       return true;
+}
 
-//     opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
-       opt = 0;
-       if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
-                               &_vmexit_control) < 0) {
-               return;
+/*
+ * We're trying to make this as readable as possible. Realistically, it will
+ * rarely if ever change, if the past is any guide.
+ */
+static const struct vmxec pbec = {
+       .name = "Pin Based Execution Controls",
+       .msr = MSR_IA32_VMX_PINBASED_CTLS,
+       .truemsr = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
+
+       .set_to_1 = (PIN_BASED_EXT_INTR_MASK |
+                    PIN_BASED_NMI_EXITING |
+                    PIN_BASED_VIRTUAL_NMIS),
+
+       .set_to_0 = (PIN_BASED_VMX_PREEMPTION_TIMER |
+                    PIN_BASED_POSTED_INTR),
+};
+
+static const struct vmxec cbec = {
+       .name = "CPU Based Execution Controls",
+       .msr = MSR_IA32_VMX_PROCBASED_CTLS,
+       .truemsr = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
+
+       .set_to_1 = (CPU_BASED_HLT_EXITING |
+                    CPU_BASED_MWAIT_EXITING |
+                    CPU_BASED_RDPMC_EXITING |
+                    CPU_BASED_CR8_LOAD_EXITING |
+                    CPU_BASED_CR8_STORE_EXITING |
+                    CPU_BASED_USE_MSR_BITMAPS |
+                    CPU_BASED_MONITOR_EXITING |
+                    CPU_BASED_USE_IO_BITMAPS |
+                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS),
+
+       .set_to_0 = (CPU_BASED_VIRTUAL_INTR_PENDING |
+                    CPU_BASED_INVLPG_EXITING |
+                    CPU_BASED_USE_TSC_OFFSETING |
+                    CPU_BASED_RDTSC_EXITING |
+                    CPU_BASED_CR3_LOAD_EXITING |
+                    CPU_BASED_CR3_STORE_EXITING |
+                    CPU_BASED_TPR_SHADOW |
+                    CPU_BASED_MOV_DR_EXITING |
+                    CPU_BASED_VIRTUAL_NMI_PENDING |
+                    CPU_BASED_MONITOR_TRAP |
+                    CPU_BASED_PAUSE_EXITING |
+                    CPU_BASED_UNCOND_IO_EXITING),
+};
+
+static const struct vmxec cb2ec = {
+       .name = "CPU Based 2nd Execution Controls",
+       .msr = MSR_IA32_VMX_PROCBASED_CTLS2,
+       .truemsr = MSR_IA32_VMX_PROCBASED_CTLS2,
+
+       .set_to_1 = (SECONDARY_EXEC_ENABLE_EPT |
+                    SECONDARY_EXEC_WBINVD_EXITING),
+
+       .set_to_0 = (SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+                    SECONDARY_EXEC_DESCRIPTOR_EXITING |
+                    SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
+                    SECONDARY_EXEC_ENABLE_VPID |
+                    SECONDARY_EXEC_UNRESTRICTED_GUEST |
+                    SECONDARY_EXEC_APIC_REGISTER_VIRT |
+                    SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
+                    SECONDARY_EXEC_PAUSE_LOOP_EXITING |
+                    SECONDARY_EXEC_RDRAND_EXITING |
+                    SECONDARY_EXEC_ENABLE_INVPCID |
+                    SECONDARY_EXEC_ENABLE_VMFUNC |
+                    SECONDARY_EXEC_SHADOW_VMCS |
+                    SECONDARY_EXEC_RDSEED_EXITING |
+                    SECONDARY_EPT_VE |
+                    /* TODO: re enable this via a "Want" struct
+                       member at some point */
+                    SECONDARY_EXEC_RDTSCP |
+                    SECONDARY_ENABLE_XSAV_RESTORE)
+};
+
+static const struct vmxec vmentry = {
+       .name = "VMENTRY controls",
+       .msr = MSR_IA32_VMX_ENTRY_CTLS,
+       .truemsr = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
+       /* exact order from vmx.h; only the first two are enabled. */
+
+       .set_to_1 =  (VM_ENTRY_LOAD_DEBUG_CONTROLS | /* can't set to 0 */
+                     VM_ENTRY_LOAD_IA32_EFER |
+                     VM_ENTRY_IA32E_MODE),
+
+       .set_to_0 = (VM_ENTRY_SMM |
+                    VM_ENTRY_DEACT_DUAL_MONITOR |
+                    VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
+                    VM_ENTRY_LOAD_IA32_PAT),
+};
+
+static const struct vmxec vmexit = {
+       .name = "VMEXIT controls",
+       .msr = MSR_IA32_VMX_EXIT_CTLS,
+       .truemsr = MSR_IA32_VMX_TRUE_EXIT_CTLS,
+
+       .set_to_1 = (VM_EXIT_SAVE_DEBUG_CONTROLS |      /* can't set to 0 */
+                                VM_EXIT_SAVE_IA32_EFER | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_HOST_ADDR_SPACE_SIZE),       /* 64 bit */
+
+       .set_to_0 = (VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
+                                VM_EXIT_ACK_INTR_ON_EXIT |
+                                VM_EXIT_SAVE_IA32_PAT |
+                                VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER),
+};
+
+static void
+setup_vmcs_config(void *p)
+{
+       int *ret = p;
+       struct vmcs_config *vmcs_conf = &vmcs_config;
+       uint32_t vmx_msr_high;
+       uint64_t vmx_msr;
+       bool have_true_msrs = false;
+       bool ok;
+
+       *ret = -EIO;
+
+       vmx_msr = read_msr(MSR_IA32_VMX_BASIC);
+       vmx_msr_high = vmx_msr >> 32;
+
+       /*
+        * If bit 55 (VMX_BASIC_HAVE_TRUE_MSRS) is set, then we
+        * can go for the true MSRs.  Else, we ask you to get a better CPU.
+        */
+       if (vmx_msr & VMX_BASIC_TRUE_CTLS) {
+               have_true_msrs = true;
+               printd("Running with TRUE MSRs\n");
+       } else {
+               printk("Running with non-TRUE MSRs, this is old hardware\n");
        }
 
-       min = 0;
-//     opt = VM_ENTRY_LOAD_IA32_PAT;
-       opt = 0;
-       if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
-                               &_vmentry_control) < 0) {
+       /*
+        * Don't worry that one or more of these might fail and leave
+        * the VMCS in some kind of incomplete state. If one of these
+        * fails, the caller is going to discard the VMCS.
+        * It is written this way to ensure we get results of all tests and avoid
+        * BMAFR behavior.
+        */
+       ok = check_vmxec_controls(&pbec, have_true_msrs,
+                                 &vmcs_conf->pin_based_exec_ctrl);
+       ok = check_vmxec_controls(&cbec, have_true_msrs,
+                                 &vmcs_conf->cpu_based_exec_ctrl) && ok;
+       /* Only check cb2ec if we're still ok, o/w we may GPF */
+       ok = ok && check_vmxec_controls(&cb2ec, have_true_msrs,
+                                       &vmcs_conf->cpu_based_2nd_exec_ctrl);
+       ok = check_vmxec_controls(&vmentry, have_true_msrs,
+                                 &vmcs_conf->vmentry_ctrl) && ok;
+       ok = check_vmxec_controls(&vmexit, have_true_msrs,
+                                 &vmcs_conf->vmexit_ctrl) && ok;
+       if (! ok) {
+               printk("vmxexec controls is no good.\n");
                return;
        }
 
-       rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
-
        /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
-       if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) {
+       if ((vmx_msr_high & 0x1fff) > PGSIZE) {
+               printk("vmx_msr_high & 0x1fff) is 0x%x, > PAGE_SIZE 0x%x\n",
+                          vmx_msr_high & 0x1fff, PGSIZE);
                return;
        }
 
        /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
-       if (vmx_msr_high & (1u<<16)) {
-               printk("64-bit CPUs always have VMX_BASIC_MSR[48]==0. FAILS!\n");
+       if (vmx_msr & VMX_BASIC_64) {
+               printk("VMX doesn't support 64 bit width!\n");
                return;
        }
 
-       /* Require Write-Back (WB) memory type for VMCS accesses. */
-       if (((vmx_msr_high >> 18) & 15) != 6) {
-               printk("NO WB!\n");
+       if (((vmx_msr & VMX_BASIC_MEM_TYPE_MASK) >> VMX_BASIC_MEM_TYPE_SHIFT)
+               != VMX_BASIC_MEM_TYPE_WB) {
+               printk("VMX doesn't support WB memory for VMCS accesses!\n");
                return;
        }
 
        vmcs_conf->size = vmx_msr_high & 0x1fff;
        vmcs_conf->order = LOG2_UP(nr_pages(vmcs_config.size));
-       vmcs_conf->revision_id = vmx_msr_low;
-       printk("vmcs_conf size %d order %d rev %d\n",
-              vmcs_conf->size, vmcs_conf->order,
-              vmcs_conf->revision_id);
-
-       vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
-       vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
-       vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
-       vmcs_conf->vmexit_ctrl         = _vmexit_control;
-       vmcs_conf->vmentry_ctrl        = _vmentry_control;
-
-       vmx_capability.has_load_efer =
-               allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
-                               VM_ENTRY_LOAD_IA32_EFER)
-               && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
-                                  VM_EXIT_LOAD_IA32_EFER);
-
-       /* Now that we've done all the setup we can do, verify
-        * that we have all the capabilities we need. These tests
-        * are done last presumably because all the work done above
-        * affects some of them.
-        */
+       vmcs_conf->revision_id = (uint32_t) vmx_msr;
 
-       if (!vmx_capability.has_load_efer) {
-               printk("CPU lacks ability to load EFER register\n");
-               return;
-       }
+       /* Read in the caps for runtime checks.  This MSR is only available if
+        * secondary controls and ept or vpid is on, which we check earlier */
+       rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, vmx_capability.ept, vmx_capability.vpid);
 
        *ret = 0;
 }
 
-static struct vmcs *__vmx_alloc_vmcs(int node)
+static struct vmcs *
+__vmx_alloc_vmcs(int node)
 {
        struct vmcs *vmcs;
 
@@ -660,17 +686,19 @@ static struct vmcs *__vmx_alloc_vmcs(int node)
  *
  * Returns a valid VMCS region.
  */
-static struct vmcs *vmx_alloc_vmcs(void)
+static struct vmcs *
+vmx_alloc_vmcs(void)
 {
-       return __vmx_alloc_vmcs(node_id());
+       return __vmx_alloc_vmcs(numa_id());
 }
 
 /**
  * vmx_free_vmcs - frees a VMCS region
  */
-static void vmx_free_vmcs(struct vmcs *vmcs)
+static void
+vmx_free_vmcs(struct vmcs *vmcs)
 {
-  //free_pages((unsigned long)vmcs, vmcs_config.order);
+       //free_pages((unsigned long)vmcs, vmcs_config.order);
 }
 
 /*
@@ -679,32 +707,33 @@ static void vmx_free_vmcs(struct vmcs *vmcs)
  * Note that host-state that does change is set elsewhere. E.g., host-state
  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
  */
-static void vmx_setup_constant_host_state(void)
+static void
+vmx_setup_constant_host_state(void)
 {
        uint32_t low32, high32;
        unsigned long tmpl;
        pseudodesc_t dt;
 
-       vmcs_writel(HOST_CR0, rcr0() & ~X86_CR0_TS);  /* 22.2.3 */
-       vmcs_writel(HOST_CR4, rcr4());  /* 22.2.3, 22.2.5 */
-       vmcs_writel(HOST_CR3, rcr3());  /* 22.2.3 */
+       vmcs_writel(HOST_CR0, rcr0() & ~X86_CR0_TS);    /* 22.2.3 */
+       vmcs_writel(HOST_CR4, rcr4());  /* 22.2.3, 22.2.5 */
+       vmcs_writel(HOST_CR3, rcr3());  /* 22.2.3 */
 
-       vmcs_write16(HOST_CS_SELECTOR, GD_KT);  /* 22.2.4 */
-       vmcs_write16(HOST_DS_SELECTOR, GD_KD);  /* 22.2.4 */
-       vmcs_write16(HOST_ES_SELECTOR, GD_KD);  /* 22.2.4 */
-       vmcs_write16(HOST_SS_SELECTOR, GD_KD);  /* 22.2.4 */
-       vmcs_write16(HOST_TR_SELECTOR, GD_TSS);  /* 22.2.4 */
+       vmcs_write16(HOST_CS_SELECTOR, GD_KT);  /* 22.2.4 */
+       vmcs_write16(HOST_DS_SELECTOR, GD_KD);  /* 22.2.4 */
+       vmcs_write16(HOST_ES_SELECTOR, GD_KD);  /* 22.2.4 */
+       vmcs_write16(HOST_SS_SELECTOR, GD_KD);  /* 22.2.4 */
+       vmcs_write16(HOST_TR_SELECTOR, GD_TSS); /* 22.2.4 */
 
        native_store_idt(&dt);
-       vmcs_writel(HOST_IDTR_BASE, dt.pd_base);   /* 22.2.4 */
+       vmcs_writel(HOST_IDTR_BASE, dt.pd_base);        /* 22.2.4 */
 
-       asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
-       vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
+       asm("mov $.Lkvm_vmx_return, %0":"=r"(tmpl));
+       vmcs_writel(HOST_RIP, tmpl);    /* 22.2.5 */
 
        rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
        vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
        rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
-       vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
+       vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);      /* 22.2.3 */
 
        rdmsr(MSR_EFER, low32, high32);
        vmcs_write32(HOST_IA32_EFER, low32);
@@ -714,24 +743,26 @@ static void vmx_setup_constant_host_state(void)
                vmcs_write64(HOST_IA32_PAT, low32 | ((uint64_t) high32 << 32));
        }
 
-       vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
-       vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
+       vmcs_write16(HOST_FS_SELECTOR, 0);      /* 22.2.4 */
+       vmcs_write16(HOST_GS_SELECTOR, 0);      /* 22.2.4 */
 
        /* TODO: This (at least gs) is per cpu */
        rdmsrl(MSR_FS_BASE, tmpl);
-       vmcs_writel(HOST_FS_BASE, tmpl); /* 22.2.4 */
+       vmcs_writel(HOST_FS_BASE, tmpl);        /* 22.2.4 */
        rdmsrl(MSR_GS_BASE, tmpl);
-       vmcs_writel(HOST_GS_BASE, tmpl); /* 22.2.4 */
+       vmcs_writel(HOST_GS_BASE, tmpl);        /* 22.2.4 */
 }
 
-static inline uint16_t vmx_read_ldt(void)
+static inline uint16_t
+vmx_read_ldt(void)
 {
        uint16_t ldt;
-       asm("sldt %0" : "=g"(ldt));
+asm("sldt %0":"=g"(ldt));
        return ldt;
 }
 
-static unsigned long segment_base(uint16_t selector)
+static unsigned long
+segment_base(uint16_t selector)
 {
        pseudodesc_t *gdt = &currentcpu->host_gdt;
        struct desc_struct *d;
@@ -744,7 +775,7 @@ static unsigned long segment_base(uint16_t selector)
 
        table_base = gdt->pd_base;
 
-       if (selector & 4) {           /* from ldt */
+       if (selector & 4) {     /* from ldt */
                uint16_t ldt_selector = vmx_read_ldt();
 
                if (!(ldt_selector & ~3)) {
@@ -755,21 +786,21 @@ static unsigned long segment_base(uint16_t selector)
        }
        d = (struct desc_struct *)(table_base + (selector & ~7));
        v = get_desc_base(d);
-#ifdef CONFIG_X86_64
-       if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
-               v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
-#endif
+       if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
+               v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
        return v;
 }
 
-static inline unsigned long vmx_read_tr_base(void)
+static inline unsigned long
+vmx_read_tr_base(void)
 {
        uint16_t tr;
-       asm("str %0" : "=g"(tr));
+asm("str %0":"=g"(tr));
        return segment_base(tr);
 }
 
-static void __vmx_setup_cpu(void)
+static void
+__vmx_setup_cpu(void)
 {
        pseudodesc_t *gdt = &currentcpu->host_gdt;
        unsigned long sysenter_esp;
@@ -779,16 +810,16 @@ static void __vmx_setup_cpu(void)
         * Linux uses per-cpu TSS and GDT, so set these when switching
         * processors.
         */
-       vmcs_writel(HOST_TR_BASE, vmx_read_tr_base()); /* 22.2.4 */
-       vmcs_writel(HOST_GDTR_BASE, gdt->pd_base);   /* 22.2.4 */
+       vmcs_writel(HOST_TR_BASE, vmx_read_tr_base());  /* 22.2.4 */
+       vmcs_writel(HOST_GDTR_BASE, gdt->pd_base);      /* 22.2.4 */
 
        rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
-       vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
+       vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp);      /* 22.2.3 */
 
        rdmsrl(MSR_FS_BASE, tmpl);
-       vmcs_writel(HOST_FS_BASE, tmpl); /* 22.2.4 */
+       vmcs_writel(HOST_FS_BASE, tmpl);        /* 22.2.4 */
        rdmsrl(MSR_GS_BASE, tmpl);
-       vmcs_writel(HOST_GS_BASE, tmpl); /* 22.2.4 */
+       vmcs_writel(HOST_GS_BASE, tmpl);        /* 22.2.4 */
 }
 
 /**
@@ -797,7 +828,8 @@ static void __vmx_setup_cpu(void)
  *
  * Disables preemption. Call vmx_put_cpu() when finished.
  */
-static void vmx_get_cpu(struct vmx_vcpu *vcpu)
+static void
+vmx_get_cpu(struct vmx_vcpu *vcpu)
 {
        int cur_cpu = core_id();
        handler_wrapper_t *w;
@@ -829,11 +861,12 @@ static void vmx_get_cpu(struct vmx_vcpu *vcpu)
  * vmx_put_cpu - called after using a cpu
  * @vcpu: VCPU that was loaded.
  */
-static void vmx_put_cpu(struct vmx_vcpu *vcpu)
+static void
+vmx_put_cpu(struct vmx_vcpu *vcpu)
 {
        if (core_id() != vcpu->cpu)
                panic("%s: core_id() %d != vcpu->cpu %d\n",
-                     __func__, core_id(), vcpu->cpu);
+                         __func__, core_id(), vcpu->cpu);
 
        if (currentcpu->local_vcpu != vcpu)
                panic("vmx_put_cpu: asked to clear something not ours");
@@ -845,72 +878,12 @@ static void vmx_put_cpu(struct vmx_vcpu *vcpu)
        //put_cpu();
 }
 
-static void __vmx_sync_helper(struct hw_trapframe *hw_tf, void *ptr)
-{
-       struct vmx_vcpu *vcpu = ptr;
-
-       ept_sync_context(vcpu_get_eptp(vcpu));
-}
-
-struct sync_addr_args {
-       struct vmx_vcpu *vcpu;
-       gpa_t gpa;
-};
-
-static void __vmx_sync_individual_addr_helper(struct hw_trapframe *hw_tf, void *ptr)
-{
-       struct sync_addr_args *args = ptr;
-
-//     ept_sync_individual_addr(
-
-}
-
-/**
- * vmx_ept_sync_global - used to evict everything in the EPT
- * @vcpu: the vcpu
- */
-void vmx_ept_sync_vcpu(struct vmx_vcpu *vcpu)
-{
-       handler_wrapper_t *w;
-
-       smp_call_function_single(vcpu->cpu,
-               __vmx_sync_helper, (void *) vcpu, &w);
-
-       if (smp_call_wait(w)) {
-               printk("litevm_init. smp_call_wait failed. Expect a panic.\n");
-       }
-
-
-}
-
-/**
- * vmx_ept_sync_individual_addr - used to evict an individual address
- * @vcpu: the vcpu
- * @gpa: the guest-physical address
- */
-void vmx_ept_sync_individual_addr(struct vmx_vcpu *vcpu, gpa_t gpa)
-{
-       struct sync_addr_args args;
-       args.vcpu = vcpu;
-       args.gpa = gpa;
-
-       handler_wrapper_t *w;
-
-
-       smp_call_function_single(vcpu->cpu,
-                                __vmx_sync_individual_addr_helper, (void *) &args, &w);
-
-       if (smp_call_wait(w)) {
-               printk("litevm_init. smp_call_wait failed. Expect a panic.\n");
-       }
-
-}
-
 /**
  * vmx_dump_cpu - prints the CPU state
  * @vcpu: VCPU to print
  */
-static void vmx_dump_cpu(struct vmx_vcpu *vcpu)
+static void
+vmx_dump_cpu(struct vmx_vcpu *vcpu)
 {
 
        unsigned long flags;
@@ -923,35 +896,26 @@ static void vmx_dump_cpu(struct vmx_vcpu *vcpu)
 
        printk("--- Begin VCPU Dump ---\n");
        printk("CPU %d VPID %d\n", vcpu->cpu, 0);
-       printk("RIP 0x%016lx RFLAGS 0x%08lx\n",
-              vcpu->regs.tf_rip, flags);
-       printk("RAX 0x%016lx RCX 0x%016lx\n",
-               vcpu->regs.tf_rax, vcpu->regs.tf_rcx);
-       printk("RDX 0x%016lx RBX 0x%016lx\n",
-               vcpu->regs.tf_rdx, vcpu->regs.tf_rbx);
-       printk("RSP 0x%016lx RBP 0x%016lx\n",
-               vcpu->regs.tf_rsp, vcpu->regs.tf_rbp);
-       printk("RSI 0x%016lx RDI 0x%016lx\n",
-               vcpu->regs.tf_rsi, vcpu->regs.tf_rdi);
-       printk("R8  0x%016lx R9  0x%016lx\n",
-               vcpu->regs.tf_r8, vcpu->regs.tf_r9);
-       printk("R10 0x%016lx R11 0x%016lx\n",
-               vcpu->regs.tf_r10, vcpu->regs.tf_r11);
-       printk("R12 0x%016lx R13 0x%016lx\n",
-               vcpu->regs.tf_r12, vcpu->regs.tf_r13);
-       printk("R14 0x%016lx R15 0x%016lx\n",
-               vcpu->regs.tf_r14, vcpu->regs.tf_r15);
+       printk("RIP 0x%016lx RFLAGS 0x%08lx\n", vcpu->regs.tf_rip, flags);
+       printk("RAX 0x%016lx RCX 0x%016lx\n", vcpu->regs.tf_rax, vcpu->regs.tf_rcx);
+       printk("RDX 0x%016lx RBX 0x%016lx\n", vcpu->regs.tf_rdx, vcpu->regs.tf_rbx);
+       printk("RSP 0x%016lx RBP 0x%016lx\n", vcpu->regs.tf_rsp, vcpu->regs.tf_rbp);
+       printk("RSI 0x%016lx RDI 0x%016lx\n", vcpu->regs.tf_rsi, vcpu->regs.tf_rdi);
+       printk("R8  0x%016lx R9  0x%016lx\n", vcpu->regs.tf_r8, vcpu->regs.tf_r9);
+       printk("R10 0x%016lx R11 0x%016lx\n", vcpu->regs.tf_r10, vcpu->regs.tf_r11);
+       printk("R12 0x%016lx R13 0x%016lx\n", vcpu->regs.tf_r12, vcpu->regs.tf_r13);
+       printk("R14 0x%016lx R15 0x%016lx\n", vcpu->regs.tf_r14, vcpu->regs.tf_r15);
        printk("--- End VCPU Dump ---\n");
 
 }
 
-uint64_t construct_eptp(physaddr_t root_hpa)
+uint64_t
+construct_eptp(physaddr_t root_hpa)
 {
        uint64_t eptp;
 
        /* set WB memory and 4 levels of walk.  we checked these in ept_init */
-       eptp = VMX_EPT_MEM_TYPE_WB |
-              (VMX_EPT_GAW_4_LVL << VMX_EPT_GAW_EPTP_SHIFT);
+       eptp = VMX_EPT_MEM_TYPE_WB | (VMX_EPT_GAW_4_LVL << VMX_EPT_GAW_EPTP_SHIFT);
        if (cpu_has_vmx_ept_ad_bits())
                eptp |= VMX_EPT_AD_ENABLE_BIT;
        eptp |= (root_hpa & PAGE_MASK);
@@ -962,34 +926,35 @@ uint64_t construct_eptp(physaddr_t root_hpa)
 /**
  * vmx_setup_initial_guest_state - configures the initial state of guest registers
  */
-static void vmx_setup_initial_guest_state(void)
+static void
+vmx_setup_initial_guest_state(void)
 {
        unsigned long tmpl;
        unsigned long cr4 = X86_CR4_PAE | X86_CR4_VMXE | X86_CR4_OSXMMEXCPT |
-                           X86_CR4_PGE | X86_CR4_OSFXSR;
+               X86_CR4_PGE | X86_CR4_OSFXSR;
        uint32_t protected_mode = X86_CR0_PG | X86_CR0_PE;
 #if 0
-       do we need it
-       if (boot_cpu_has(X86_FEATURE_PCID))
-               cr4 |= X86_CR4_PCIDE;
+       do
+               we need it if (boot_cpu_has(X86_FEATURE_PCID))
+                       cr4 |= X86_CR4_PCIDE;
        if (boot_cpu_has(X86_FEATURE_OSXSAVE))
                cr4 |= X86_CR4_OSXSAVE;
 #endif
        /* we almost certainly have this */
        /* we'll go sour if we don't. */
-       if (1) //boot_cpu_has(X86_FEATURE_FSGSBASE))
+       if (1)  //boot_cpu_has(X86_FEATURE_FSGSBASE))
                cr4 |= X86_CR4_RDWRGSFS;
 
        /* configure control and data registers */
        vmcs_writel(GUEST_CR0, protected_mode | X86_CR0_WP |
-                              X86_CR0_MP | X86_CR0_ET | X86_CR0_NE);
+                               X86_CR0_MP | X86_CR0_ET | X86_CR0_NE);
        vmcs_writel(CR0_READ_SHADOW, protected_mode | X86_CR0_WP |
-                                    X86_CR0_MP | X86_CR0_ET | X86_CR0_NE);
+                               X86_CR0_MP | X86_CR0_ET | X86_CR0_NE);
        vmcs_writel(GUEST_CR3, rcr3());
        vmcs_writel(GUEST_CR4, cr4);
        vmcs_writel(CR4_READ_SHADOW, cr4);
        vmcs_writel(GUEST_IA32_EFER, EFER_LME | EFER_LMA |
-                                    EFER_SCE | EFER_FFXSR);
+                               EFER_SCE /*| EFER_FFXSR */ );
        vmcs_writel(GUEST_GDTR_BASE, 0);
        vmcs_writel(GUEST_GDTR_LIMIT, 0);
        vmcs_writel(GUEST_IDTR_BASE, 0);
@@ -1054,11 +1019,11 @@ static void vmx_setup_initial_guest_state(void)
        vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
        vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
        vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
-       vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
-}
+       vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);      /* 22.2.1 */
+       }
 
-static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, uint32_t msr)
-{
+static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
+                                           uint32_t msr) {
        int f = sizeof(unsigned long);
        /*
         * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
@@ -1066,29 +1031,288 @@ static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, uint32_t
         * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
         */
        if (msr <= 0x1fff) {
-               __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
-               __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
+               __clear_bit(msr, msr_bitmap + 0x000 / f);       /* read-low */
+               __clear_bit(msr, msr_bitmap + 0x800 / f);       /* write-low */
        } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
                msr &= 0x1fff;
-               __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
-               __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
+               __clear_bit(msr, msr_bitmap + 0x400 / f);       /* read-high */
+               __clear_bit(msr, msr_bitmap + 0xc00 / f);       /* write-high */
        }
 }
 
-static void setup_msr(struct vmx_vcpu *vcpu)
+/* note the io_bitmap is big enough for the 64K port space. */
+static void __vmx_disable_intercept_for_io(unsigned long *io_bitmap,
+                                          uint16_t port) {
+       __clear_bit(port, io_bitmap);
+}
+
+static void vcpu_print_autoloads(struct vmx_vcpu *vcpu) {
+       struct vmx_msr_entry *e;
+       int sz = sizeof(autoloaded_msrs) / sizeof(*autoloaded_msrs);
+       printk("Host Autoloads:\n-------------------\n");
+       for (int i = 0; i < sz; i++) {
+               e = &vcpu->msr_autoload.host[i];
+               printk("\tMSR 0x%08x: %p\n", e->index, e->value);
+       }
+       printk("Guest Autoloads:\n-------------------\n");
+       for (int i = 0; i < sz; i++) {
+               e = &vcpu->msr_autoload.guest[i];
+               printk("\tMSR 0x%08x %p\n", e->index, e->value);
+       }
+}
+
+static void dumpmsrs(void) {
+       int i;
+       int set[] = {
+               MSR_LSTAR,
+               MSR_FS_BASE,
+               MSR_GS_BASE,
+               MSR_KERNEL_GS_BASE,
+               MSR_SFMASK,
+               MSR_IA32_PEBS_ENABLE
+       };
+       for (i = 0; i < ARRAY_SIZE(set); i++) {
+               printk("%p: %p\n", set[i], read_msr(set[i]));
+       }
+       printk("core id %d\n", core_id());
+}
+
+/* emulated msr. For now, an msr value and a pointer to a helper that
+ * performs the requested operation.
+ */
+struct emmsr {
+       uint32_t reg;
+       char *name;
+       int (*f) (struct vmx_vcpu * vcpu, struct emmsr *, uint32_t, uint32_t);
+       bool written;
+       uint32_t edx, eax;
+};
+
+int emsr_miscenable(struct vmx_vcpu *vcpu, struct emmsr *, uint32_t,
+                   uint32_t);
+int emsr_mustmatch(struct vmx_vcpu *vcpu, struct emmsr *, uint32_t,
+                  uint32_t);
+int emsr_readonly(struct vmx_vcpu *vcpu, struct emmsr *, uint32_t,
+                 uint32_t);
+int emsr_readzero(struct vmx_vcpu *vcpu, struct emmsr *, uint32_t,
+                 uint32_t);
+int emsr_fakewrite(struct vmx_vcpu *vcpu, struct emmsr *, uint32_t,
+                  uint32_t);
+int emsr_ok(struct vmx_vcpu *vcpu, struct emmsr *, uint32_t, uint32_t);
+
+struct emmsr emmsrs[] = {
+       {MSR_IA32_MISC_ENABLE, "MSR_IA32_MISC_ENABLE", emsr_miscenable},
+       {MSR_IA32_SYSENTER_CS, "MSR_IA32_SYSENTER_CS", emsr_ok},
+       {MSR_IA32_SYSENTER_EIP, "MSR_IA32_SYSENTER_EIP", emsr_ok},
+       {MSR_IA32_SYSENTER_ESP, "MSR_IA32_SYSENTER_ESP", emsr_ok},
+       {MSR_IA32_UCODE_REV, "MSR_IA32_UCODE_REV", emsr_fakewrite},
+       {MSR_CSTAR, "MSR_CSTAR", emsr_fakewrite},
+       {MSR_IA32_VMX_BASIC_MSR, "MSR_IA32_VMX_BASIC_MSR", emsr_fakewrite},
+       {MSR_IA32_VMX_PINBASED_CTLS_MSR, "MSR_IA32_VMX_PINBASED_CTLS_MSR",
+        emsr_fakewrite},
+       {MSR_IA32_VMX_PROCBASED_CTLS_MSR, "MSR_IA32_VMX_PROCBASED_CTLS_MSR",
+        emsr_fakewrite},
+       {MSR_IA32_VMX_PROCBASED_CTLS2, "MSR_IA32_VMX_PROCBASED_CTLS2",
+        emsr_fakewrite},
+       {MSR_IA32_VMX_EXIT_CTLS_MSR, "MSR_IA32_VMX_EXIT_CTLS_MSR",
+        emsr_fakewrite},
+       {MSR_IA32_VMX_ENTRY_CTLS_MSR, "MSR_IA32_VMX_ENTRY_CTLS_MSR",
+        emsr_fakewrite},
+       {MSR_IA32_ENERGY_PERF_BIAS, "MSR_IA32_ENERGY_PERF_BIAS",
+        emsr_fakewrite},
+       {MSR_LBR_SELECT, "MSR_LBR_SELECT", emsr_ok},
+       {MSR_LBR_TOS, "MSR_LBR_TOS", emsr_ok},
+       {MSR_LBR_NHM_FROM, "MSR_LBR_NHM_FROM", emsr_ok},
+       {MSR_LBR_NHM_TO, "MSR_LBR_NHM_TO", emsr_ok},
+       {MSR_LBR_CORE_FROM, "MSR_LBR_CORE_FROM", emsr_ok},
+       {MSR_LBR_CORE_TO, "MSR_LBR_CORE_TO", emsr_ok},
+
+       // grumble. 
+       {MSR_OFFCORE_RSP_0, "MSR_OFFCORE_RSP_0", emsr_ok},
+       {MSR_OFFCORE_RSP_1, "MSR_OFFCORE_RSP_1", emsr_ok},
+       // louder.
+       {MSR_PEBS_LD_LAT_THRESHOLD, "MSR_PEBS_LD_LAT_THRESHOLD", emsr_ok},
+       // aaaaaahhhhhhhhhhhhhhhhhhhhh
+       {MSR_ARCH_PERFMON_EVENTSEL0, "MSR_ARCH_PERFMON_EVENTSEL0", emsr_ok},
+       {MSR_ARCH_PERFMON_EVENTSEL1, "MSR_ARCH_PERFMON_EVENTSEL0", emsr_ok},
+       // unsafe.
+       {MSR_IA32_APICBASE, "MSR_IA32_APICBASE", emsr_fakewrite},
+
+       // mostly harmless.
+       {MSR_TSC_AUX, "MSR_TSC_AUX", emsr_fakewrite},
+       {MSR_RAPL_POWER_UNIT, "MSR_RAPL_POWER_UNIT", emsr_readzero},
+};
+
+static uint64_t set_low32(uint64_t hi, uint32_t lo)
+{
+       return (hi & 0xffffffff00000000ULL) | lo;
+}
+
+static uint64_t set_low16(uint64_t hi, uint16_t lo)
+{
+       return (hi & 0xffffffffffff0000ULL) | lo;
+}
+
+static uint64_t set_low8(uint64_t hi, uint8_t lo)
 {
-       int set[] = { MSR_LSTAR };
+       return (hi & 0xffffffffffffff00ULL) | lo;
+}
+
+/* this may be the only register that needs special handling.
+ * If there others then we might want to extend teh emmsr struct.
+ */
+int emsr_miscenable(struct vmx_vcpu *vcpu, struct emmsr *msr,
+                   uint32_t opcode, uint32_t qual) {
+       uint32_t eax, edx;
+       rdmsr(msr->reg, eax, edx);
+       /* we just let them read the misc msr for now. */
+       if (opcode == EXIT_REASON_MSR_READ) {
+               vcpu->regs.tf_rax = set_low32(vcpu->regs.tf_rax, eax);
+               vcpu->regs.tf_rax |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
+               vcpu->regs.tf_rdx = set_low32(vcpu->regs.tf_rdx, edx);
+               return 0;
+       } else {
+               /* if they are writing what is already written, that's ok. */
+               if (((uint32_t) vcpu->regs.tf_rax == eax)
+                   && ((uint32_t) vcpu->regs.tf_rdx == edx))
+                       return 0;
+       }
+       printk
+               ("%s: Wanted to write 0x%x:0x%x, but could not; value was 0x%x:0x%x\n",
+                msr->name, (uint32_t) vcpu->regs.tf_rdx,
+                (uint32_t) vcpu->regs.tf_rax, edx, eax);
+       return SHUTDOWN_UNHANDLED_EXIT_REASON;
+}
+
+int emsr_mustmatch(struct vmx_vcpu *vcpu, struct emmsr *msr,
+                  uint32_t opcode, uint32_t qual) {
+       uint32_t eax, edx;
+       rdmsr(msr->reg, eax, edx);
+       /* we just let them read the misc msr for now. */
+       if (opcode == EXIT_REASON_MSR_READ) {
+               vcpu->regs.tf_rax = set_low32(vcpu->regs.tf_rax, eax);
+               vcpu->regs.tf_rdx = set_low32(vcpu->regs.tf_rdx, edx);
+               return 0;
+       } else {
+               /* if they are writing what is already written, that's ok. */
+               if (((uint32_t) vcpu->regs.tf_rax == eax)
+                   && ((uint32_t) vcpu->regs.tf_rdx == edx))
+                       return 0;
+       }
+       printk
+               ("%s: Wanted to write 0x%x:0x%x, but could not; value was 0x%x:0x%x\n",
+                msr->name, (uint32_t) vcpu->regs.tf_rdx,
+                (uint32_t) vcpu->regs.tf_rax, edx, eax);
+       return SHUTDOWN_UNHANDLED_EXIT_REASON;
+}
+
+int emsr_ok(struct vmx_vcpu *vcpu, struct emmsr *msr, uint32_t opcode,
+           uint32_t qual) {
+       if (opcode == EXIT_REASON_MSR_READ) {
+               rdmsr(msr->reg, vcpu->regs.tf_rdx, vcpu->regs.tf_rax);
+       } else {
+               uint64_t val =
+                       (uint64_t) vcpu->regs.tf_rdx << 32 | vcpu->regs.tf_rax;
+               write_msr(msr->reg, val);
+       }
+       return 0;
+}
+
+int emsr_readonly(struct vmx_vcpu *vcpu, struct emmsr *msr, uint32_t opcode,
+                 uint32_t qual) {
+       uint32_t eax, edx;
+       rdmsr((uint32_t) vcpu->regs.tf_rcx, eax, edx);
+       /* we just let them read the misc msr for now. */
+       if (opcode == EXIT_REASON_MSR_READ) {
+               vcpu->regs.tf_rax = set_low32(vcpu->regs.tf_rax, eax);
+               vcpu->regs.tf_rdx = set_low32(vcpu->regs.tf_rdx, edx);
+               return 0;
+       }
+
+       printk("%s: Tried to write a readonly register\n", msr->name);
+       return SHUTDOWN_UNHANDLED_EXIT_REASON;
+}
+
+int emsr_readzero(struct vmx_vcpu *vcpu, struct emmsr *msr, uint32_t opcode,
+                 uint32_t qual) {
+       if (opcode == EXIT_REASON_MSR_READ) {
+               vcpu->regs.tf_rax = 0;
+               vcpu->regs.tf_rdx = 0;
+               return 0;
+       }
+
+       printk("%s: Tried to write a readonly register\n", msr->name);
+       return SHUTDOWN_UNHANDLED_EXIT_REASON;
+}
+
+/* pretend to write it, but don't write it. */
+int emsr_fakewrite(struct vmx_vcpu *vcpu, struct emmsr *msr,
+                  uint32_t opcode, uint32_t qual) {
+       uint32_t eax, edx;
+       if (!msr->written) {
+               rdmsr(msr->reg, eax, edx);
+       } else {
+               edx = msr->edx;
+               eax = msr->eax;
+       }
+       /* we just let them read the misc msr for now. */
+       if (opcode == EXIT_REASON_MSR_READ) {
+               vcpu->regs.tf_rax = set_low32(vcpu->regs.tf_rax, eax);
+               vcpu->regs.tf_rdx = set_low32(vcpu->regs.tf_rdx, edx);
+               return 0;
+       } else {
+               /* if they are writing what is already written, that's ok. */
+               if (((uint32_t) vcpu->regs.tf_rax == eax)
+                   && ((uint32_t) vcpu->regs.tf_rdx == edx))
+                       return 0;
+               msr->edx = vcpu->regs.tf_rdx;
+               msr->eax = vcpu->regs.tf_rax;
+               msr->written = true;
+       }
+       return 0;
+}
+
+static int
+msrio(struct vmx_vcpu *vcpu, uint32_t opcode, uint32_t qual) {
+       int i;
+       for (i = 0; i < ARRAY_SIZE(emmsrs); i++) {
+               if (emmsrs[i].reg != vcpu->regs.tf_rcx)
+                       continue;
+               return emmsrs[i].f(vcpu, &emmsrs[i], opcode, qual);
+       }
+       printk("msrio for 0x%lx failed\n", vcpu->regs.tf_rcx);
+       return SHUTDOWN_UNHANDLED_EXIT_REASON;
+}
+
+/* Notes on autoloading.  We can't autoload FS_BASE or GS_BASE, according to the
+ * manual, but that's because they are automatically saved and restored when all
+ * of the other architectural registers are saved and restored, such as cs, ds,
+ * es, and other fun things. (See 24.4.1).  We need to make sure we don't
+ * accidentally intercept them too, since they are magically autloaded..
+ *
+ * We'll need to be careful of any MSR we neither autoload nor intercept
+ * whenever we vmenter/vmexit, and we intercept by default.
+ *
+ * Other MSRs, such as MSR_IA32_PEBS_ENABLE only work on certain architectures
+ * only work on certain architectures. */
+static void setup_msr(struct vmx_vcpu *vcpu) {
        struct vmx_msr_entry *e;
-       int sz = sizeof(set) / sizeof(*set);
+       int sz = sizeof(autoloaded_msrs) / sizeof(*autoloaded_msrs);
        int i;
 
-       //BUILD_BUG_ON(sz > NR_AUTOLOAD_MSRS);
+       static_assert((sizeof(autoloaded_msrs) / sizeof(*autoloaded_msrs)) <=
+                     NR_AUTOLOAD_MSRS);
 
        vcpu->msr_autoload.nr = sz;
 
-       /* XXX enable only MSRs in set */
+       /* Since PADDR(msr_bitmap) is non-zero, and the bitmap is all 0xff, we now
+        * intercept all MSRs */
        vmcs_write64(MSR_BITMAP, PADDR(msr_bitmap));
 
+       vmcs_write64(IO_BITMAP_A, PADDR(io_bitmap));
+       vmcs_write64(IO_BITMAP_B, PADDR((uintptr_t)io_bitmap +
+                                       (VMX_IO_BITMAP_SZ / 2)));
+
        vmcs_write32(VM_EXIT_MSR_STORE_COUNT, vcpu->msr_autoload.nr);
        vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vcpu->msr_autoload.nr);
        vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vcpu->msr_autoload.nr);
@@ -1101,31 +1325,32 @@ static void setup_msr(struct vmx_vcpu *vcpu)
                uint64_t val;
 
                e = &vcpu->msr_autoload.host[i];
-               e->index = set[i];
+               e->index = autoloaded_msrs[i];
                __vmx_disable_intercept_for_msr(msr_bitmap, e->index);
                rdmsrl(e->index, val);
                e->value = val;
+               printk("host index %p val %p\n", e->index, e->value);
 
                e = &vcpu->msr_autoload.guest[i];
-               e->index = set[i];
+               e->index = autoloaded_msrs[i];
                e->value = 0xDEADBEEF;
+               printk("guest index %p val %p\n", e->index, e->value);
        }
 }
 
 /**
  *  vmx_setup_vmcs - configures the vmcs with starting parameters
  */
-static void vmx_setup_vmcs(struct vmx_vcpu *vcpu)
-{
+static void vmx_setup_vmcs(struct vmx_vcpu *vcpu) {
        vmcs_write16(VIRTUAL_PROCESSOR_ID, 0);
-       vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
+       vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
 
        /* Control */
        vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
-               vmcs_config.pin_based_exec_ctrl);
+                    vmcs_config.pin_based_exec_ctrl);
 
        vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
-               vmcs_config.cpu_based_exec_ctrl);
+                    vmcs_config.cpu_based_exec_ctrl);
 
        if (cpu_has_secondary_exec_ctrls()) {
                vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
@@ -1136,47 +1361,17 @@ static void vmx_setup_vmcs(struct vmx_vcpu *vcpu)
 
        vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
        vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
-       vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
+       vmcs_write32(CR3_TARGET_COUNT, 0);      /* 22.2.1 */
 
        setup_msr(vcpu);
-#if 0
-       if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
-               uint32_t msr_low, msr_high;
-               uint64_t host_pat;
-               rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
-               host_pat = msr_low | ((uint64_t) msr_high << 32);
-               /* Write the default value follow host pat */
-               vmcs_write64(GUEST_IA32_PAT, host_pat);
-               /* Keep arch.pat sync with GUEST_IA32_PAT */
-               vmx->vcpu.arch.pat = host_pat;
-       }
-#endif
-#if 0
-       for (int i = 0; i < NR_VMX_MSR; ++i) {
-               uint32_t index = vmx_msr_index[i];
-               uint32_t data_low, data_high;
-               int j = vmx->nmsrs;
-               // TODO we should have read/writemsr_safe
-#if 0
-               if (rdmsr_safe(index, &data_low, &data_high) < 0)
-                       continue;
-               if (wrmsr_safe(index, data_low, data_high) < 0)
-                       continue;
-#endif
-               vmx->guest_msrs[j].index = i;
-               vmx->guest_msrs[j].data = 0;
-               vmx->guest_msrs[j].mask = -1ull;
-               ++vmx->nmsrs;
-       }
-#endif
 
        vmcs_config.vmentry_ctrl |= VM_ENTRY_IA32E_MODE;
 
        vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
        vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
 
-       vmcs_writel(CR0_GUEST_HOST_MASK, ~0ul);
-       vmcs_writel(CR4_GUEST_HOST_MASK, ~0ul);
+       vmcs_writel(CR0_GUEST_HOST_MASK, 0);    // ~0ul);
+       vmcs_writel(CR4_GUEST_HOST_MASK, 0);    // ~0ul);
 
        //kvm_write_tsc(&vmx->vcpu, 0);
        vmcs_writel(TSC_OFFSET, 0);
@@ -1189,8 +1384,7 @@ static void vmx_setup_vmcs(struct vmx_vcpu *vcpu)
  *
  * Returns: A new VCPU structure
  */
-struct vmx_vcpu *vmx_create_vcpu(struct proc *p)
-{
+struct vmx_vcpu *vmx_create_vcpu(struct proc *p) {
        struct vmx_vcpu *vcpu = kmalloc(sizeof(struct vmx_vcpu), KMALLOC_WAIT);
        if (!vcpu) {
                return NULL;
@@ -1222,36 +1416,23 @@ fail_vmcs:
  * vmx_destroy_vcpu - destroys and frees an existing virtual cpu
  * @vcpu: the VCPU to destroy
  */
-void vmx_destroy_vcpu(struct vmx_vcpu *vcpu)
-{
+void vmx_destroy_vcpu(struct vmx_vcpu *vcpu) {
        vmx_free_vmcs(vcpu->vmcs);
        kfree(vcpu);
 }
 
 /**
- * vmx_task_vcpu - returns a pointer to the task's vcpu or NULL.
- * @task: the task
- */
-static inline struct vmx_vcpu *vmx_task_vcpu(struct proc *p)
-{
-       struct dune_struct *dune = current->virtinfo;
-       return dune ? dune->vcpu : NULL;
-}
-
-/**
  * vmx_current_vcpu - returns a pointer to the vcpu for the current task.
  *
  * In the contexts where this is used the vcpu pointer should never be NULL.
  */
-static inline struct vmx_vcpu *vmx_current_vcpu(void)
-{
-       struct vmx_vcpu *vcpu = vmx_task_vcpu(current);
-       if (! vcpu)
-               panic("%s: core_id %d: no vcpu", __func__, core_id());
+static inline struct vmx_vcpu *vmx_current_vcpu(void) {
+       struct vmx_vcpu *vcpu = currentcpu->local_vcpu;
+       if (!vcpu)
+               panic("Core has no vcpu!");
        return vcpu;
 }
 
-
 /**
  * vmx_run_vcpu - launches the CPU into non-root mode
  * We ONLY support 64-bit guests.
@@ -1358,11 +1539,11 @@ static int vmx_run_vcpu(struct vmx_vcpu *vcpu)
 
        vcpu->regs.tf_rip = vmcs_readl(GUEST_RIP);
        vcpu->regs.tf_rsp = vmcs_readl(GUEST_RSP);
-       printk("RETURN. ip %016lx sp %016lx cr2 %016lx\n",
+       printd("RETURN. ip %016lx sp %016lx cr2 %016lx\n",
               vcpu->regs.tf_rip, vcpu->regs.tf_rsp, vcpu->cr2);
        /* FIXME: do we need to set up other flags? */
        vcpu->regs.tf_rflags = (vmcs_readl(GUEST_RFLAGS) & 0xFF) |
-                     X86_EFLAGS_IF | 0x2;
+               X86_EFLAGS_IF | 0x2;
 
        vcpu->regs.tf_cs = GD_UT;
        vcpu->regs.tf_ss = GD_UD;
@@ -1385,14 +1566,12 @@ static int vmx_run_vcpu(struct vmx_vcpu *vcpu)
 #endif
 }
 
-static void vmx_step_instruction(void)
-{
+static void vmx_step_instruction(void) {
        vmcs_writel(GUEST_RIP, vmcs_readl(GUEST_RIP) +
-                              vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
+                   vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
 }
 
-static int vmx_handle_ept_violation(struct vmx_vcpu *vcpu)
-{
+static int vmx_handle_ept_violation(struct vmx_vcpu *vcpu, struct vmctl *v) {
        unsigned long gva, gpa;
        int exit_qual, ret = -1;
        page_t *page;
@@ -1401,48 +1580,43 @@ static int vmx_handle_ept_violation(struct vmx_vcpu *vcpu)
        exit_qual = vmcs_read32(EXIT_QUALIFICATION);
        gva = vmcs_readl(GUEST_LINEAR_ADDRESS);
        gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
-       printk("ept: gva %016lx, gpa %016lx\n", gva, gpa);
-
+       v->gpa = gpa;
+       v->gva = gva;
+       v->exit_qual = exit_qual;
        vmx_put_cpu(vcpu);
 
-       // this is a total hack, for testing things.
-       // note that we only care about the gpa, and the
-       // gpa is our process virtual address. 
-       // Confused yet?
-       page = page_lookup(current->env_pgdir, (void *)gpa, NULL);
-       printk("Lookup %p returns %p\n", gpa, page);
-       if (page) {
-               uint64_t hpa = page2pa(page);
-               printk("hpa for %p is %p\n", gpa, hpa);
-               ret = vmx_do_ept_fault(vcpu->proc->env_pgdir.epte, gpa, hpa, exit_qual);
-               printk("vmx_do_ept_fault returns %d\n", ret);
-       }
+       int prot = 0;
+       prot |= exit_qual & VMX_EPT_FAULT_READ ? PROT_READ : 0;
+       prot |= exit_qual & VMX_EPT_FAULT_WRITE ? PROT_WRITE : 0;
+       prot |= exit_qual & VMX_EPT_FAULT_INS ? PROT_EXEC : 0;
+       ret = handle_page_fault(current, gpa, prot);
 
-       if (ret) {
-               printk("page fault failure "
-                      "GPA: 0x%lx, GVA: 0x%lx\n",
-                      gpa, gva);
+       // Some of these get fixed in the vmm; be less chatty now.
+       if (0 && ret) {
+               printk("EPT page fault failure %d, GPA: %p, GVA: %p\n", ret, gpa,
+                      gva);
                vmx_dump_cpu(vcpu);
        }
 
-       return ret;
+       /* we let the vmm handle the failure cases. So return
+        * the VMX exit violation, not what handle_page_fault returned.
+        */
+       return EXIT_REASON_EPT_VIOLATION;
 }
 
-static void vmx_handle_cpuid(struct vmx_vcpu *vcpu)
-{
+static void vmx_handle_cpuid(struct vmx_vcpu *vcpu) {
        unsigned int eax, ebx, ecx, edx;
 
        eax = vcpu->regs.tf_rax;
        ecx = vcpu->regs.tf_rcx;
-       cpuid(0, 2, &eax, &ebx, &ecx, &edx);
+       cpuid(eax, ecx, &eax, &ebx, &ecx, &edx);
        vcpu->regs.tf_rax = eax;
        vcpu->regs.tf_rbx = ebx;
        vcpu->regs.tf_rcx = ecx;
        vcpu->regs.tf_rdx = edx;
 }
 
-static int vmx_handle_nmi_exception(struct vmx_vcpu *vcpu)
-{
+static int vmx_handle_nmi_exception(struct vmx_vcpu *vcpu) {
        uint32_t intr_info;
 
        vmx_get_cpu(vcpu);
@@ -1459,66 +1633,17 @@ static int vmx_handle_nmi_exception(struct vmx_vcpu *vcpu)
        return -EIO;
 }
 
-
-static void noop(void) {
-       __asm__ __volatile__ ("1: jmp 1b");
-}
-
-static void fail(void) {
-       __asm__ __volatile__ ("movq $0xdeadbeef, %rbx; movq 0, %rax");
-}
-
-static unsigned long stack[512];
 /**
  * vmx_launch - the main loop for a VMX Dune process
  * @conf: the launch configuration
  */
-int vmx_launch(struct dune_config *conf)
-{
+int vmx_launch(struct vmctl *v) {
        int ret;
-       struct dune_struct dune;
        struct vmx_vcpu *vcpu;
-       int i = 0;
-       unsigned long rip = conf->rip;
-       unsigned long rsp = conf->rsp;
-       unsigned long cr3 = conf->cr3;
        int errors = 0;
+       int advance;
 
-       if (conf->rip < 4096 ) {
-               // testing.
-               switch(conf->rip) {
-               default:
-                       rip = (uint64_t)noop + 4;
-                       break;
-               case 1:
-                       rip = (uint64_t)fail + 4;
-                       break;
-               }
-       }
-
-       if (conf->cr3 == 0) {
-               cr3 = rcr3();
-       }
-
-       /* sanity checking.  -- later
-       ret = ept_check_page(ept, rip);
-       if (ret) {
-               printk("0x%x is not mapped in the ept!\n", rip);
-               errors++;
-       }
-       ret = ept_check_page(ept, rsp);
-       if (ret) {
-               printk("0x%x is not mapped in the ept!\n", rsp);
-               errors++;
-       }
-       */
-       if (errors) {
-               return -EINVAL;
-       }
-
-
-       printk("RUNNING: %s: rip %p rsp %p cr3 %p \n",
-              __func__, rip, rsp, cr3);
+       printd("RUNNING: %s: rip %p rsp %p cr3 %p \n", __func__, rip, rsp, cr3);
        /* TODO: dirty hack til we have VMM contexts */
        vcpu = current->vmm.guest_pcores[0];
        if (!vcpu) {
@@ -1526,64 +1651,129 @@ int vmx_launch(struct dune_config *conf)
                return -ENOMEM;
        }
 
+       /* We need to prep the host's autoload region for our current core.  Right
+        * now, the only autoloaded MSR that varies at runtime (in this case per
+        * core is the KERN_GS_BASE). */
+       rdmsrl(MSR_KERNEL_GS_BASE, vcpu->msr_autoload.host[0].value);
+       /* if cr3 is set, means 'set everything', else means 'start where you left off' */
        vmx_get_cpu(vcpu);
-       vmcs_writel(GUEST_RIP, rip);
-       vmcs_writel(GUEST_RSP, rsp);
-       vmcs_writel(GUEST_CR3, cr3);
+       switch(v->command) {
+       case REG_ALL:
+               printk("REG_ALL\n");
+               // fallthrough
+               vcpu->regs = v->regs;
+               vmcs_writel(GUEST_RSP, v->regs.tf_rsp);
+               vmcs_writel(GUEST_RIP, v->regs.tf_rip);
+               break;
+       case REG_RSP_RIP_CR3:
+               printk("REG_RSP_RIP_CR3\n");
+               vmcs_writel(GUEST_RSP, v->regs.tf_rsp);
+               vmcs_writel(GUEST_CR3, v->cr3);
+               // fallthrough
+       case REG_RIP:
+               printk("REG_RIP %p\n", v->regs.tf_rip);
+               vmcs_writel(GUEST_RIP, v->regs.tf_rip);
+               break;
+       case RESUME:
+               printk("RESUME\n");
+               break;
+       default: 
+               error(EINVAL, "Bad command in vmx_launch");
+       }
+       vcpu->shutdown = 0;
        vmx_put_cpu(vcpu);
-
        vcpu->ret_code = -1;
 
-       if (current->virtinfo)
-               printk("vmx_launch: current->virtinfo is NOT NULL (%p)\n", current->virtinfo);
-       //WARN_ON(current->virtinfo != NULL);
-       dune.vcpu = vcpu;
-
-       current->virtinfo = &dune;
-
        while (1) {
+               advance = 0;
                vmx_get_cpu(vcpu);
 
                // TODO: manage the fpu when we restart.
 
                // TODO: see if we need to exit before we go much further.
                disable_irq();
+               //dumpmsrs();
                ret = vmx_run_vcpu(vcpu);
+               //dumpmsrs();
                enable_irq();
                vmx_put_cpu(vcpu);
 
                if (ret == EXIT_REASON_VMCALL) {
+                       if (current->vmm.flags & VMM_VMCALL_PRINTF) {
+                               uint8_t byte = vcpu->regs.tf_rdi;
+                               printd("System call\n");
+#ifdef DEBUG
+                               vmx_dump_cpu(vcpu);
+#endif
+                               advance = 3;
+                               printk("%c", byte);
+                               // adjust the RIP
+                       } else {
+                               vcpu->shutdown = SHUTDOWN_UNHANDLED_EXIT_REASON;
+                               uint8_t byte = vcpu->regs.tf_rdi;
+                               printk("%p %c\n", byte, vcpu->regs.tf_rdi);
+                               vmx_dump_cpu(vcpu);
+                               printd("system call! WTF\n");
+                       }
+               } else if (ret == EXIT_REASON_CR_ACCESS) {
+                       show_cr_access(vmcs_read32(EXIT_QUALIFICATION));
+                       vmx_dump_cpu(vcpu);
                        vcpu->shutdown = SHUTDOWN_UNHANDLED_EXIT_REASON;
-                       printk("system call! WTF\n");
-               } else if (ret == EXIT_REASON_CPUID)
+               } else if (ret == EXIT_REASON_CPUID) {
                        vmx_handle_cpuid(vcpu);
-               else if (ret == EXIT_REASON_EPT_VIOLATION) {
-                       if (vmx_handle_ept_violation(vcpu))
+                       vmx_get_cpu(vcpu);
+                       vmcs_writel(GUEST_RIP, vcpu->regs.tf_rip + 2);
+                       vmx_put_cpu(vcpu);
+               } else if (ret == EXIT_REASON_EPT_VIOLATION) {
+                       if (vmx_handle_ept_violation(vcpu, v))
                                vcpu->shutdown = SHUTDOWN_EPT_VIOLATION;
                } else if (ret == EXIT_REASON_EXCEPTION_NMI) {
-                       if (vmx_handle_nmi_exception(vcpu))
+                       if (vmx_handle_nmi_exception(vcpu)) 
                                vcpu->shutdown = SHUTDOWN_NMI_EXCEPTION;
                } else if (ret == EXIT_REASON_EXTERNAL_INTERRUPT) {
-                       printk("External interrupt\n");
+                       printd("External interrupt\n");
+                       vcpu->shutdown = SHUTDOWN_UNHANDLED_EXIT_REASON;
+               } else if (ret == EXIT_REASON_MSR_READ) {
+                       printd("msr read\n");
+                       vmx_dump_cpu(vcpu);
+                       vcpu->shutdown =
+                               msrio(vcpu, ret, vmcs_read32(EXIT_QUALIFICATION));
+                       advance = 2;
+               } else if (ret == EXIT_REASON_MSR_WRITE) {
+                       printd("msr write\n");
+                       vmx_dump_cpu(vcpu);
+                       vcpu->shutdown =
+                               msrio(vcpu, ret, vmcs_read32(EXIT_QUALIFICATION));
+                       advance = 2;
+               } else if (ret == EXIT_REASON_IO_INSTRUCTION) {
+                       /* the VMM does this now. */
+                       vcpu->shutdown = ret; 
                } else {
-                       printk("unhandled exit: reason %x, exit qualification %x\n",
+                       printk("unhandled exit: reason 0x%x, exit qualification 0x%x\n",
                               ret, vmcs_read32(EXIT_QUALIFICATION));
-                       vmx_dump_cpu(vcpu);
+                       //vmx_dump_cpu(vcpu);
                        vcpu->shutdown = SHUTDOWN_UNHANDLED_EXIT_REASON;
                }
 
                /* TODO: we can't just return and relaunch the VMCS, in case we blocked.
                 * similar to how proc_restartcore/smp_idle only restart the pcpui
                 * cur_ctx, we need to do the same, via the VMCS resume business. */
-
                if (vcpu->shutdown)
                        break;
-       }
 
-       printk("RETURN. ip %016lx sp %016lx\n",
-               vcpu->regs.tf_rip, vcpu->regs.tf_rsp);
-       current->virtinfo = NULL;
+               if (advance) {
+                       vmx_get_cpu(vcpu);
+                       vmcs_writel(GUEST_RIP, vcpu->regs.tf_rip + advance);
+                       vmx_put_cpu(vcpu);
+               }
+       }
 
+       printk("RETURN. ip %016lx sp %016lx, shutdown 0x%lx ret 0x%lx\n",
+              vcpu->regs.tf_rip, vcpu->regs.tf_rsp, vcpu->shutdown, vcpu->shutdown);
+       v->regs = vcpu->regs;
+       v->shutdown = vcpu->shutdown;
+       v->ret_code = ret;
+//  hexdump((void *)vcpu->regs.tf_rsp, 128 * 8);
        /*
         * Return both the reason for the shutdown and a status value.
         * The exit() and exit_group() system calls only need 8 bits for
@@ -1599,8 +1789,7 @@ int vmx_launch(struct dune_config *conf)
  * __vmx_enable - low-level enable of VMX mode on the current CPU
  * @vmxon_buf: an opaque buffer for use as the VMXON region
  */
-static  int __vmx_enable(struct vmcs *vmxon_buf)
-{
+static int __vmx_enable(struct vmcs *vmxon_buf) {
        uint64_t phys_addr = PADDR(vmxon_buf);
        uint64_t old, test_bits;
 
@@ -1614,7 +1803,7 @@ static  int __vmx_enable(struct vmcs *vmxon_buf)
        test_bits = FEATURE_CONTROL_LOCKED;
        test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
 
-       if (0) // tboot_enabled())
+       if (0)  // tboot_enabled())
                test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
 
        if ((old & test_bits) != test_bits) {
@@ -1644,8 +1833,7 @@ static  int __vmx_enable(struct vmcs *vmxon_buf)
  *
  * Sets up necessary state for enable (e.g. a scratchpad for VMXON.)
  */
-static void vmx_enable(void)
-{
+static void vmx_enable(void) {
        struct vmcs *vmxon_buf = currentcpu->vmxarea;
        int ret;
 
@@ -1667,8 +1855,7 @@ failed:
 /**
  * vmx_disable - disables VMX mode on the current CPU
  */
-static void vmx_disable(void *unused)
-{
+static void vmx_disable(void *unused) {
        if (currentcpu->vmx_enabled) {
                __vmxoff();
                lcr4(rcr4() & ~X86_CR4_VMXE);
@@ -1679,8 +1866,7 @@ static void vmx_disable(void *unused)
 /* Probe the cpus to see which ones can do vmx.
  * Return -errno if it fails, and 1 if it succeeds.
  */
-static bool probe_cpu_vmx(void)
-{
+static bool probe_cpu_vmx(void) {
        /* The best way to test this code is:
         * wrmsr -p <cpu> 0x3a 1
         * This will lock vmx off; then modprobe dune.
@@ -1699,20 +1885,18 @@ static bool probe_cpu_vmx(void)
        }
 }
 
-static void setup_vmxarea(void)
-{
-               struct vmcs *vmxon_buf;
-               printd("Set up vmxarea for cpu %d\n", core_id());
-               vmxon_buf = __vmx_alloc_vmcs(node_id());
-               if (!vmxon_buf) {
-                       printk("setup_vmxarea failed on node %d\n", core_id());
-                       return;
-               }
-               currentcpu->vmxarea = vmxon_buf;
+static void setup_vmxarea(void) {
+       struct vmcs *vmxon_buf;
+       printd("Set up vmxarea for cpu %d\n", core_id());
+       vmxon_buf = __vmx_alloc_vmcs(core_id());
+       if (!vmxon_buf) {
+               printk("setup_vmxarea failed on node %d\n", core_id());
+               return;
+       }
+       currentcpu->vmxarea = vmxon_buf;
 }
 
-static int ept_init(void)
-{
+static int ept_init(void) {
        if (!cpu_has_vmx_ept()) {
                printk("VMX doesn't support EPT!\n");
                return -1;
@@ -1726,26 +1910,26 @@ static int ept_init(void)
                return -1;
        }
        switch (arch_max_jumbo_page_shift()) {
-               case PML3_SHIFT:
-                       if (!cpu_has_vmx_ept_1g_page()) {
-                               printk("VMX EPT doesn't support 1 GB pages!\n");
-                               return -1;
-                       }
-                       break;
-               case PML2_SHIFT:
-                       if (!cpu_has_vmx_ept_2m_page()) {
-                               printk("VMX EPT doesn't support 2 MB pages!\n");
-                               return -1;
-                       }
-                       break;
-               default:
-                       printk("Unexpected jumbo page size %d\n",
-                              arch_max_jumbo_page_shift());
+       case PML3_SHIFT:
+               if (!cpu_has_vmx_ept_1g_page()) {
+                       printk("VMX EPT doesn't support 1 GB pages!\n");
                        return -1;
+               }
+               break;
+       case PML2_SHIFT:
+               if (!cpu_has_vmx_ept_2m_page()) {
+                       printk("VMX EPT doesn't support 2 MB pages!\n");
+                       return -1;
+               }
+               break;
+       default:
+               printk("Unexpected jumbo page size %d\n",
+                      arch_max_jumbo_page_shift());
+               return -1;
        }
        if (!cpu_has_vmx_ept_ad_bits()) {
                printk("VMX EPT doesn't support accessed/dirty!\n");
-               /* TODO: set the pmap_ops accordingly */
+               x86_ept_pte_fix_ups |= EPTE_A | EPTE_D;
        }
        if (!cpu_has_vmx_invept() || !cpu_has_vmx_invept_global()) {
                printk("VMX EPT can't invalidate PTEs/TLBs!\n");
@@ -1761,11 +1945,10 @@ static int ept_init(void)
  * they are in some sense externalizing what would other wise be a very large ball of
  * state that would be inside the CPU.
  */
-int intel_vmm_init(void)
-{
+int intel_vmm_init(void) {
        int r, cpu, ret;
 
-       if (! probe_cpu_vmx()) {
+       if (!probe_cpu_vmx()) {
                return -EOPNOTSUPP;
        }
 
@@ -1781,11 +1964,27 @@ int intel_vmm_init(void)
                printk("Could not allocate msr_bitmap\n");
                return -ENOMEM;
        }
+       io_bitmap = (unsigned long *)get_cont_pages(VMX_IO_BITMAP_ORDER,
+                                                   KMALLOC_WAIT);
+       if (!io_bitmap) {
+               printk("Could not allocate msr_bitmap\n");
+               kfree(msr_bitmap);
+               return -ENOMEM;
+       }
        /* FIXME: do we need APIC virtualization (flexpriority?) */
 
        memset(msr_bitmap, 0xff, PAGE_SIZE);
+       memset(io_bitmap, 0xff, VMX_IO_BITMAP_SZ);
+
+       /* These are the only MSRs that are not autoloaded and not intercepted */
        __vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE);
        __vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE);
+       __vmx_disable_intercept_for_msr(msr_bitmap, MSR_EFER);
+
+       /* TODO: this might be dangerous, since they can do more than just read the
+        * CMOS */
+       __vmx_disable_intercept_for_io(io_bitmap, CMOS_RAM_IDX);
+       __vmx_disable_intercept_for_io(io_bitmap, CMOS_RAM_DATA);
 
        if ((ret = ept_init())) {
                printk("EPT init failed, %d\n", ret);
@@ -1795,8 +1994,7 @@ int intel_vmm_init(void)
        return 0;
 }
 
-int intel_vmm_pcpu_init(void)
-{
+int intel_vmm_pcpu_init(void) {
        setup_vmxarea();
        vmx_enable();
        return 0;