VMM: Use the I_POKE_CORE IRQ for posted IRQs
[akaros.git] / kern / arch / x86 / time.c
index 9762787..ddea6c6 100644 (file)
@@ -9,6 +9,7 @@
 #include <arch/pic.h>
 #include <arch/apic.h>
 #include <time.h>
+#include <trap.h>
 #include <assert.h>
 #include <stdio.h>
 
@@ -17,7 +18,7 @@ system_timing_t system_timing = {0, 0, 0xffff, 0};
 // timer init calibrates both tsc timer and lapic timer using PIT
 void timer_init(void){
        /* some boards have this unmasked early on. */
-       pic_mask_irq(0 + PIC1_OFFSET);
+       pic_mask_irq(0, 0 + PIC1_OFFSET);
        uint64_t tscval[2];
        long timercount[2];
        pit_set_timer(0xffff, TIMER_RATEGEN);
@@ -25,9 +26,9 @@ void timer_init(void){
        tscval[0] = read_tsc();
        udelay_pit(1000000);
        tscval[1] = read_tsc();
-       system_timing.tsc_freq = SINIT(tscval[1] - tscval[0]);
+       system_timing.tsc_freq = tscval[1] - tscval[0];
        cprintf("TSC Frequency: %llu\n", system_timing.tsc_freq);
-       __lapic_set_timer(0xffffffff, LAPIC_TIMER_DEFAULT_VECTOR, FALSE,
+       __lapic_set_timer(0xffffffff, IdtLAPIC_TIMER, FALSE,
                          LAPIC_TIMER_DIVISOR_BITS);
        // Mask the LAPIC Timer, so we never receive this interrupt (minor race)
        mask_lapic_lvt(LAPIC_LVT_TIMER);
@@ -51,8 +52,8 @@ void pit_set_timer(uint32_t divisor, uint32_t mode)
        outb(TIMER_MODE, mode); 
        outb(TIMER_CNTR0, divisor & 0xff);
        outb(TIMER_CNTR0, (divisor >> 8) );
-       system_timing.pit_mode = SINIT(mode);
-       system_timing.pit_divisor = SINIT(divisor);
+       system_timing.pit_mode = mode;
+       system_timing.pit_divisor = divisor;
        // cprintf("timer mode set to %d, divisor %d\n",mode, divisor);
 }