Enabling X2APIC
[akaros.git] / kern / arch / x86 / ros / msr-index.h
index d7be860..5ae4835 100644 (file)
 #define MSR_IA32_LASTINTFROMIP         0x000001dd
 #define MSR_IA32_LASTINTTOIP           0x000001de
 
+/* X86 X2APIC registers */
+#define MSR_LAPIC_ID                                   0x00000802
+#define MSR_LAPIC_VERSION                              0x00000803
+#define MSR_LAPIC_TPR                                  0x00000808
+#define MSR_LAPIC_PPR                                  0x0000080a
+#define MSR_LAPIC_EOI                                  0x0000080b
+#define MSR_LAPIC_LDR                                  0x0000080d
+#define MSR_LAPIC_SPURIOUS                             0x0000080f
+
+#define MSR_LAPIC_ISR_31_0                             0x00000810
+#define MSR_LAPIC_ISR_63_32                            0x00000811
+#define MSR_LAPIC_ISR_95_64                            0x00000812
+#define MSR_LAPIC_ISR_127_96                   0x00000813
+#define MSR_LAPIC_ISR_159_128                  0x00000814
+#define MSR_LAPIC_ISR_191_160                  0x00000815
+#define MSR_LAPIC_ISR_223_192                  0x00000816
+#define MSR_LAPIC_ISR_255_224                  0x00000817
+// For easier looping
+#define MSR_LAPIC_ISR_START                            MSR_LAPIC_ISR_31_0
+#define MSR_LAPIC_ISR_END                              (MSR_LAPIC_ISR_255_224 + 1)
+
+#define MSR_LAPIC_TMR_31_0                             0x00000818
+#define MSR_LAPIC_TMR_63_32                            0x00000819
+#define MSR_LAPIC_TMR_95_64                            0x0000081a
+#define MSR_LAPIC_TMR_127_96                   0x0000081b
+#define MSR_LAPIC_TMR_159_128                  0x0000081c
+#define MSR_LAPIC_TMR_191_160                  0x0000081d
+#define MSR_LAPIC_TMR_223_192                  0x0000081e
+#define MSR_LAPIC_TMR_255_224                  0x0000081f
+// For easier looping
+#define MSR_LAPIC_TMR_START                            MSR_LAPIC_TMR_31_0
+#define MSR_LAPIC_TMR_END                              (MSR_LAPIC_TMR_255_224 + 1)
+
+#define MSR_LAPIC_IRR_31_0                             0x00000820
+#define MSR_LAPIC_IRR_63_32                            0x00000821
+#define MSR_LAPIC_IRR_95_64                            0x00000822
+#define MSR_LAPIC_IRR_127_96                   0x00000823
+#define MSR_LAPIC_IRR_159_128                  0x00000824
+#define MSR_LAPIC_IRR_191_160                  0x00000825
+#define MSR_LAPIC_IRR_223_192                  0x00000826
+#define MSR_LAPIC_IRR_255_224                  0x00000827
+// For easier looping
+#define MSR_LAPIC_IRR_START                            MSR_LAPIC_IRR_31_0
+#define MSR_LAPIC_IRR_END                              (MSR_LAPIC_IRR_255_224 + 1)
+
+#define MSR_LAPIC_ESR                                  0x00000828
+#define MSR_LAPIC_LVT_CMCI                             0x0000082f
+#define MSR_LAPIC_ICR                                  0x00000830
+#define MSR_LAPIC_LVT_TIMER                            0x00000832
+#define MSR_LAPIC_LVT_THERMAL                  0x00000833
+#define MSR_LAPIC_LVT_PERFMON                  0x00000834
+#define MSR_LAPIC_LVT_LINT0                            0x00000835
+#define MSR_LAPIC_LVT_LINT1                            0x00000836
+#define MSR_LAPIC_LVT_ERROR_REG                        0x00000837
+#define MSR_LAPIC_INITIAL_COUNT                        0x00000838
+#define MSR_LAPIC_CURRENT_COUNT                        0x00000839
+#define MSR_LAPIC_DIVIDE_CONFIG_REG            0x0000083e
+#define MSR_LAPIC_SELF_IPI                             0x0000083f
+
+#define MSR_LAPIC_END                                  (MSR_LAPIC_SELF_IPI + 1)
+
 /* DEBUGCTLMSR bits (others vary by model): */
 #define DEBUGCTLMSR_LBR                        (1UL <<  0)     /* last branch recording */
 #define DEBUGCTLMSR_BTF                        (1UL <<  1)     /* single-step on branches */