Remove the BUILD_INFO_FILE variable
[akaros.git] / kern / arch / x86 / apic.h
index 813a373..fc0fd97 100644 (file)
@@ -6,7 +6,7 @@
 
 #pragma once
 
-/* 
+/*
  * Functions and definitions for dealing with the APIC and PIC, specific to
  * Intel.  Does not handle an x2APIC.
  */
@@ -15,6 +15,7 @@
 #include <ros/trapframe.h>
 #include <atomic.h>
 #include <endian.h>
+#include <arch/ros/msr-index.h>
 
 // Local APIC
 /* PBASE is the physical address.  It is mapped in at the VADDR LAPIC_BASE.
  * memory.  We can move the PBASE, but we're limited to 32 bit (physical)
  * addresses. */
 #define LAPIC_PBASE                                    0xfee00000      /* default *physical* address */
-#define LAPIC_EOI                                      (LAPIC_BASE + 0x0b0)
-#define LAPIC_SPURIOUS                         (LAPIC_BASE + 0x0f0)
-#define LAPIC_VERSION                          (LAPIC_BASE + 0x030)
-#define LAPIC_ERROR                                    (LAPIC_BASE + 0x280)
-#define LAPIC_ID                                       (LAPIC_BASE + 0x020)
-#define LAPIC_LOGICAL_ID                       (LAPIC_BASE + 0x0d0)
-// LAPIC Local Vector Table
-#define LAPIC_LVT_TIMER                                (LAPIC_BASE + 0x320)
-#define LAPIC_LVT_THERMAL                      (LAPIC_BASE + 0x330)
-#define LAPIC_LVT_PERFMON                      (LAPIC_BASE + 0x340)
-#define LAPIC_LVT_LINT0                                (LAPIC_BASE + 0x350)
-#define LAPIC_LVT_LINT1                                (LAPIC_BASE + 0x360)
-#define LAPIC_LVT_ERROR                                (LAPIC_BASE + 0x370)
-#define LAPIC_LVT_MASK                         0x00010000
-// LAPIC Timer
-#define LAPIC_TIMER_INIT                       (LAPIC_BASE + 0x380)
-#define LAPIC_TIMER_CURRENT                    (LAPIC_BASE + 0x390)
-#define LAPIC_TIMER_DIVIDE                     (LAPIC_BASE + 0x3e0)
+#define LAPIC_LVT_MASK                                 0x00010000
+
 /* Quick note on the divisor.  The LAPIC timer ticks once per divisor-bus ticks
  * (system bus or APIC bus, depending on the model).  Ex: A divisor of 128 means
  * 128 bus ticks results in 1 timer tick.  The divisor increases the time range
 #define LAPIC_TIMER_DIVISOR_BITS       0x8     /* Div = 32 */
 
 // IPI Interrupt Command Register
-#define LAPIC_IPI_ICR_LOWER                    (LAPIC_BASE + 0x300)
-#define LAPIC_IPI_ICR_UPPER                    (LAPIC_BASE + 0x310)
+#define LAPIC_IPI_ICR_LOWER                            0x30
+#define LAPIC_IPI_ICR_UPPER                            0x31
 /* Interrupts being serviced (in-service) and pending (interrupt request reg).
  * Note these registers are not normal bitmaps, but instead are 8 separate
  * 32-bit registers, spaced/aligned on 16 byte boundaries in the LAPIC address
  * space. */
-#define LAPIC_ISR                                      (LAPIC_BASE + 0x100)
-#define LAPIC_IRR                                      (LAPIC_BASE + 0x200)
+#define LAPIC_ISR                                      0x10
+#define LAPIC_IRR                                      0x20
+#define LAPIC_DFR                                      0x0e
 
 struct irq_handler;    /* include loops */
 
@@ -77,6 +63,11 @@ void lapic_set_timer(uint32_t usec, bool periodic);
 uint32_t lapic_get_default_id(void);
 int apiconline(void);
 void handle_lapic_error(struct hw_trapframe *hw_tf, void *data);
+uint32_t apicrget(uint64_t r);
+void apicrput(uint64_t r, uint32_t data);
+void apicsendipi(uint64_t data);
+void apic_isr_dump(void);
+void apic_irr_dump(void);
 
 static inline void lapic_send_eoi(int unused);
 static inline uint32_t lapic_get_version(void);
@@ -86,7 +77,6 @@ static inline uint8_t lapic_get_logid(void);
 static inline void lapic_disable_timer(void);
 static inline void lapic_disable(void);
 static inline void lapic_enable(void);
-static inline void lapic_wait_to_send(void);
 static inline void send_init_ipi(void);
 static inline void send_startup_ipi(uint8_t vector);
 static inline void send_self_ipi(uint8_t vector);
@@ -98,39 +88,39 @@ static inline void __send_nmi(uint8_t hw_coreid);
 
 /* XXX: remove these */
 #define mask_lapic_lvt(entry) \
-       write_mmreg32(entry, read_mmreg32(entry) | LAPIC_LVT_MASK)
+       apicrput(entry, apicrget(entry) | LAPIC_LVT_MASK)
 #define unmask_lapic_lvt(entry) \
-       write_mmreg32(entry, read_mmreg32(entry) & ~LAPIC_LVT_MASK)
+       apicrput(entry, apicrget(entry) & ~LAPIC_LVT_MASK)
 
 static inline void lapic_send_eoi(int unused)
 {
-       write_mmreg32(LAPIC_EOI, 0);
+       apicrput(MSR_LAPIC_EOI, 0);
 }
 
 static inline uint32_t lapic_get_version(void)
 {
-       return read_mmreg32(LAPIC_VERSION);
+       return apicrget(MSR_LAPIC_VERSION);
 }
 
 static inline uint32_t lapic_get_error(void)
 {
-       write_mmreg32(LAPIC_ERROR, 0xdeadbeef);
-       return read_mmreg32(LAPIC_ERROR);
+       apicrput(MSR_LAPIC_ESR, 0xdeadbeef);
+       return apicrget(MSR_LAPIC_ESR);
 }
 
 static inline uint32_t lapic_get_id(void)
 {
-       return read_mmreg32(LAPIC_ID) >> 24;
+       return apicrget(MSR_LAPIC_ID);
 }
 
 static inline uint8_t lapic_get_logid(void)
 {
-       return read_mmreg32(LAPIC_LOGICAL_ID) >> 24;
+       return apicrget(MSR_LAPIC_LDR);
 }
 
 static inline void lapic_disable_timer(void)
 {
-       write_mmreg32(LAPIC_LVT_TIMER, 0);
+       apicrput(MSR_LAPIC_LVT_TIMER, 0);
 }
 
 /* There are a couple ways to do it.  The MSR route doesn't seem to work
@@ -138,75 +128,55 @@ static inline void lapic_disable_timer(void)
  */
 static inline void lapic_disable(void)
 {
-       write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) & 0xffffefff);
+       apicrput(MSR_LAPIC_SPURIOUS, apicrget(MSR_LAPIC_SPURIOUS) & 0xffffefff);
        //write_msr(IA32_APIC_BASE, read_msr(IA32_APIC_BASE) & ~MSR_APIC_ENABLE);
 }
 
-/* Spins until previous IPIs are delivered.  Not sure if we want it inlined
- * Also not sure when we really need to do this. 
- */
-static inline void lapic_wait_to_send(void)
-{
-       while (read_mmreg32(LAPIC_IPI_ICR_LOWER) & 0x1000)
-               __cpu_relax();
-}
-
 static inline void lapic_enable(void)
 {
-       write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) | 0x00000100);
+       apicrput(MSR_LAPIC_SPURIOUS, apicrget(MSR_LAPIC_SPURIOUS) | 0x00000100);
 }
 
 static inline void send_init_ipi(void)
 {
-       write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4500);
-       lapic_wait_to_send();
+       apicsendipi(0xFFFFFFFF000c4500);
 }
 
 static inline void send_startup_ipi(uint8_t vector)
 {
-       write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4600 | vector);
-       lapic_wait_to_send();
+       apicsendipi(0xFFFFFFFF000c4600ULL | vector);
 }
 
 static inline void send_self_ipi(uint8_t vector)
 {
-       write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00044000 | vector);
-       lapic_wait_to_send();
+       apicrput(MSR_LAPIC_SELF_IPI, 0x00000000 | vector);
 }
 
 static inline void send_broadcast_ipi(uint8_t vector)
 {
-       write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00084000 | vector);
-       lapic_wait_to_send();
+       apicsendipi(0xFFFFFFFF00084000ULL | vector);
 }
 
 static inline void send_all_others_ipi(uint8_t vector)
 {
-       write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4000 | vector);
-       lapic_wait_to_send();
+       apicsendipi(0xFFFFFFFF000c4000ULL | vector);
 }
 
 static inline void __send_ipi(uint8_t hw_coreid, uint8_t vector)
 {
-       write_mmreg32(LAPIC_IPI_ICR_UPPER, hw_coreid << 24);
-       write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00004000 | vector);
-       lapic_wait_to_send();
+       apicsendipi(((uint64_t)hw_coreid << 32) | 0x00004000 | vector);
 }
 
 static inline void send_group_ipi(uint8_t hw_groupid, uint8_t vector)
 {
-       write_mmreg32(LAPIC_IPI_ICR_UPPER, hw_groupid << 24);
-       write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00004800 | vector);
-       lapic_wait_to_send();
+       apicsendipi(((uint64_t)hw_groupid << 32) | 0x00004800 | vector);
 }
 
 static inline void __send_nmi(uint8_t hw_coreid)
 {
        if (hw_coreid == 255)
                return;
-       write_mmreg32(LAPIC_IPI_ICR_UPPER, hw_coreid << 24);
-       write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00004400);
-       lapic_wait_to_send();
+       apicsendipi(((uint64_t)hw_coreid << 32) | 0x00004400);
 }
 
 /* To change the LAPIC Base (not recommended):
@@ -215,7 +185,7 @@ static inline void __send_nmi(uint8_t hw_coreid)
        write_msr(IA32_APIC_BASE, msr_val);
 */
 
-/* 
+/*
  * This file is part of the UCB release of Plan 9. It is subject to the license
  * terms in the LICENSE file found in the top-level directory of this
  * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No