Changes to RISC-V supervisor mode
[akaros.git] / kern / arch / riscv / smp.c
index c8769e0..d3279ef 100644 (file)
@@ -6,32 +6,31 @@
 #include <error.h>
 #include <assert.h>
 #include <atomic.h>
+#include <pmap.h>
 
-volatile uint32_t num_cpus;
+static volatile uint32_t num_cpus_booted = 1;
 
 void
 smp_boot(void)
 {
-       num_cpus = 1;
-       printd("Cores, report in!\n");
-
        smp_percpu_init();
 
-       //while(*(volatile uint32_t*)&num_cpus < num_cores());
+       printd("Cores, report in!\n");
+
+       for(uint32_t i = 1; i < num_cpus; i++)
+               send_ipi(i);
+       
+       while(num_cpus_booted < num_cpus);
 
-       printd("%d cores reporting!\n",num_cpus);
+       printd("%d cores reporting!\n", num_cpus);
 }
 
 void
 smp_init(void)
 {
-       static spinlock_t report_in_lock = SPINLOCK_INITIALIZER;
-
        smp_percpu_init();
-       spin_lock(&report_in_lock);
-       num_cpus++;
-       spin_unlock(&report_in_lock);
 
+       __sync_fetch_and_add(&num_cpus_booted, 1);
        printd("Good morning, Vietnam! (core id = %d)\n",core_id());
 
        smp_idle();
@@ -52,24 +51,24 @@ smp_make_wrapper()
 
 void
 smp_call_wrapper(trapframe_t* tf, uint32_t src, isr_t handler,
-                 handler_wrapper_t* wrapper,void* data)
+                 handler_wrapper_t* wrapper, void* data)
 {
        if(wrapper)
                wrapper->wait_list[core_id()] = 0;
-       handler(tf,data);
+       handler(tf, data);
 }
 
 int smp_call_function_self(isr_t handler, void* data,
                            handler_wrapper_t** wait_wrapper)
 {
-       return smp_call_function_single(core_id(),handler,data,wait_wrapper);
+       return smp_call_function_single(core_id(), handler, data, wait_wrapper);
 }
 
 int smp_call_function_all(isr_t handler, void* data,
                           handler_wrapper_t** wait_wrapper)
 {
        int8_t state = 0;
-       int i;
+       int i, me;
        handler_wrapper_t* wrapper = 0;
        if(wait_wrapper)
        {
@@ -84,18 +83,18 @@ int smp_call_function_all(isr_t handler, void* data,
        enable_irqsave(&state);
 
        // send to others
-       for(i = 0; i < num_cpus; i++)
+       for(i = 0, me = core_id(); i < num_cpus; i++)
        {
-               if(i == core_id())
+               if(i == me)
                        continue;
 
-               send_kernel_message(i,(amr_t)smp_call_wrapper,
-                                         handler, wrapper, data, KMSG_IMMEDIATE);
+               send_kernel_message(i, (amr_t)smp_call_wrapper, (long)handler,
+                                   (long)wrapper, (long)data, KMSG_IMMEDIATE);
        }
 
        // send to me
-       send_kernel_message(core_id(),(amr_t)smp_call_wrapper,
-                                 handler,wrapper,data, KMSG_IMMEDIATE);
+       send_kernel_message(me, (amr_t)smp_call_wrapper, (long)handler,
+                           (long)wrapper, (long)data, KMSG_IMMEDIATE);
 
        cpu_relax(); // wait to get the interrupt
 
@@ -119,8 +118,8 @@ int smp_call_function_single(uint32_t dest, isr_t handler, void* data,
 
        enable_irqsave(&state);
 
-       send_kernel_message(dest,(amr_t)smp_call_wrapper,
-                                 handler,wrapper,data, KMSG_IMMEDIATE);
+       send_kernel_message(dest, (amr_t)smp_call_wrapper, (long)handler,
+                           (long)wrapper, (long)data, KMSG_IMMEDIATE);
 
        cpu_relax(); // wait to get the interrupt, if it's to this core
 
@@ -144,4 +143,8 @@ int smp_call_wait(handler_wrapper_t* wrapper)
  * core calls this at some point in the smp_boot process. */
 void __arch_pcpu_init(uint32_t coreid)
 {
+       // Switch to the real L1 page table, rather than the boot page table which
+       // has the [0,KERNSIZE-1] identity mapping.
+       extern pte_t l1pt[NPTENTRIES];
+       lcr3(PADDR(l1pt));
 }