Add RISC-V CAS via load-reserved/store conditional
[akaros.git] / kern / arch / riscv / Makefrag
index 9b636a9..ce1f49f 100644 (file)
@@ -11,6 +11,20 @@ OBJDIRS += $(KERN_ARCH_SRC_DIR)
 #
 # We also snatch the use of a couple handy source files
 # from the lib directory, to avoid gratuitous code duplication.
-KERN_ARCH_SRCFILES := $(KERN_ARCH_SRC_DIR)/entry.S \
+KERN_ARCH_SRCFILES := $(KERN_ARCH_SRC_DIR)/boot.S \
+                      $(KERN_ARCH_SRC_DIR)/entry.S \
+                      $(KERN_ARCH_SRC_DIR)/cboot.c \
+                      $(KERN_ARCH_SRC_DIR)/trap.c \
                       $(KERN_ARCH_SRC_DIR)/cpuinfo.c \
                       $(KERN_ARCH_SRC_DIR)/console.c \
+                      $(KERN_ARCH_SRC_DIR)/pmap.c \
+                      $(KERN_ARCH_SRC_DIR)/time.c \
+                      $(KERN_ARCH_SRC_DIR)/smp.c \
+                      $(KERN_ARCH_SRC_DIR)/colored_caches.c \
+                      $(KERN_ARCH_SRC_DIR)/page_alloc.c \
+                      $(KERN_ARCH_SRC_DIR)/process.c \
+                      $(KERN_ARCH_SRC_DIR)/env.c \
+                      $(KERN_ARCH_SRC_DIR)/init.c \
+                      $(KERN_ARCH_SRC_DIR)/kdebug.c \
+                      $(KERN_ARCH_SRC_DIR)/fpu.c \
+                      $(KERN_ARCH_SRC_DIR)/softfloat.c \