user/perfmon/pfmlib_intel_snbep_unc_priv.h

   1 /*
   2  * pfmlib_intel_snbep_unc_priv.c : Intel SandyBridge/IvyBridge-EP common definitions
   3  *
   4  * Copyright (c) 2012 Google, Inc
   5  * Contributed by Stephane Eranian <eranian@gmail.com>
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  11  * of the Software, and to permit persons to whom the Software is furnished to do so,
  12  * subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in all
  15  * copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
  18  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
  19  * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  20  * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
  21  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  22  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 #ifndef __PFMLIB_INTEL_SNBEP_UNC_PRIV_H__
  25 #define __PFMLIB_INTEL_SNBEP_UNC_PRIV_H__
  26
  27 /*
  28  * Intel x86 specific pmu flags (pmu->flags 16 MSB)
  29  */
  30 #define INTEL_PMU_FL_UNC_OCC 0x10000    /* PMU has occupancy counter filters */
  31 #define INTEL_PMU_FL_UNC_CBO 0x20000    /* PMU is Cbox */
  32
  33
  34 #define SNBEP_UNC_ATTR_E                0
  35 #define SNBEP_UNC_ATTR_I                1
  36 #define SNBEP_UNC_ATTR_T8               2
  37 #define SNBEP_UNC_ATTR_T5               3
  38 #define SNBEP_UNC_ATTR_TF               4
  39 #define SNBEP_UNC_ATTR_CF               5
  40 #define SNBEP_UNC_ATTR_NF               6 /* for filter0 */
  41 #define SNBEP_UNC_ATTR_FF               7
  42 #define SNBEP_UNC_ATTR_A                8
  43 #define SNBEP_UNC_ATTR_NF1              9 /* for filter1 */
  44 #define SNBEP_UNC_ATTR_ISOC            10 /* isochronous */
  45 #define SNBEP_UNC_ATTR_NC              11 /* non-coherent */
  46
  47 #define _SNBEP_UNC_ATTR_I       (1 << SNBEP_UNC_ATTR_I)
  48 #define _SNBEP_UNC_ATTR_E       (1 << SNBEP_UNC_ATTR_E)
  49 #define _SNBEP_UNC_ATTR_T8      (1 << SNBEP_UNC_ATTR_T8)
  50 #define _SNBEP_UNC_ATTR_T5      (1 << SNBEP_UNC_ATTR_T5)
  51 #define _SNBEP_UNC_ATTR_TF      (1 << SNBEP_UNC_ATTR_TF)
  52 #define _SNBEP_UNC_ATTR_CF      (1 << SNBEP_UNC_ATTR_CF)
  53 #define _SNBEP_UNC_ATTR_NF      (1 << SNBEP_UNC_ATTR_NF)
  54 #define _SNBEP_UNC_ATTR_FF      (1 << SNBEP_UNC_ATTR_FF)
  55 #define _SNBEP_UNC_ATTR_A       (1 << SNBEP_UNC_ATTR_A)
  56 #define _SNBEP_UNC_ATTR_NF1     (1 << SNBEP_UNC_ATTR_NF1)
  57 #define _SNBEP_UNC_ATTR_ISOC    (1 << SNBEP_UNC_ATTR_ISOC)
  58 #define _SNBEP_UNC_ATTR_NC      (1 << SNBEP_UNC_ATTR_NC)
  59
  60 #define SNBEP_UNC_IRP_ATTRS \
  61         (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
  62
  63 #define SNBEP_UNC_R3QPI_ATTRS \
  64         (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
  65
  66 #define IVBEP_UNC_R3QPI_ATTRS \
  67         (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
  68
  69 #define SNBEP_UNC_R2PCIE_ATTRS \
  70         (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
  71
  72 #define IVBEP_UNC_R2PCIE_ATTRS \
  73         (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
  74
  75 #define SNBEP_UNC_QPI_ATTRS \
  76         (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
  77
  78 #define IVBEP_UNC_QPI_ATTRS \
  79         (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
  80
  81 #define SNBEP_UNC_UBO_ATTRS \
  82         (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
  83
  84 #define IVBEP_UNC_UBO_ATTRS \
  85         (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
  86
  87
  88 #define SNBEP_UNC_PCU_ATTRS \
  89         (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T5)
  90
  91 #define IVBEP_UNC_PCU_ATTRS \
  92         (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T5)
  93
  94 #define SNBEP_UNC_PCU_BAND_ATTRS \
  95         (SNBEP_UNC_PCU_ATTRS | _SNBEP_UNC_ATTR_FF)
  96
  97 #define IVBEP_UNC_PCU_BAND_ATTRS \
  98         (IVBEP_UNC_PCU_ATTRS | _SNBEP_UNC_ATTR_FF)
  99
 100 #define SNBEP_UNC_IMC_ATTRS \
 101         (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
 102
 103 #define IVBEP_UNC_IMC_ATTRS \
 104         (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
 105
 106 #define SNBEP_UNC_CBO_ATTRS   \
 107         (_SNBEP_UNC_ATTR_I   |\
 108          _SNBEP_UNC_ATTR_E   |\
 109          _SNBEP_UNC_ATTR_T8  |\
 110          _SNBEP_UNC_ATTR_CF  |\
 111          _SNBEP_UNC_ATTR_TF)
 112
 113 #define IVBEP_UNC_CBO_ATTRS   \
 114         (_SNBEP_UNC_ATTR_E   |\
 115          _SNBEP_UNC_ATTR_T8  |\
 116          _SNBEP_UNC_ATTR_CF  |\
 117          _SNBEP_UNC_ATTR_TF)
 118
 119 #define SNBEP_UNC_CBO_NID_ATTRS \
 120         (SNBEP_UNC_CBO_ATTRS|_SNBEP_UNC_ATTR_NF)
 121
 122 #define IVBEP_UNC_CBO_NID_ATTRS \
 123         (IVBEP_UNC_CBO_ATTRS|_SNBEP_UNC_ATTR_NF1)
 124
 125 #define SNBEP_UNC_HA_ATTRS \
 126         (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
 127
 128 #define IVBEP_UNC_HA_ATTRS \
 129         (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8)
 130
 131 #define SNBEP_UNC_HA_OPC_ATTRS \
 132         (SNBEP_UNC_HA_ATTRS|_SNBEP_UNC_ATTR_A)
 133
 134 typedef union {
 135         uint64_t val;
 136         struct {
 137                 unsigned long unc_event:8;      /* event code */
 138                 unsigned long unc_umask:8;      /* unit mask */
 139                 unsigned long unc_res1:1;       /* reserved */
 140                 unsigned long unc_rst:1;        /* reset */
 141                 unsigned long unc_edge:1;       /* edge detec */
 142                 unsigned long unc_res2:3;       /* reserved */
 143                 unsigned long unc_en:1;         /* enable */
 144                 unsigned long unc_inv:1;        /* invert counter mask */
 145                 unsigned long unc_thres:8;      /* counter mask */
 146                 unsigned long unc_res3:32;      /* reserved */
 147         } com; /* covers common fields for cbox, ha, imc, ubox, r2pcie, r3qpi */
 148         struct {
 149                 unsigned long unc_event:8;      /* event code */
 150                 unsigned long unc_umask:8;      /* unit mask */
 151                 unsigned long unc_res1:1;       /* reserved */
 152                 unsigned long unc_rst:1;        /* reset */
 153                 unsigned long unc_edge:1;       /* edge detect */
 154                 unsigned long unc_tid:1;        /* tid filter enable */
 155                 unsigned long unc_res2:2;       /* reserved */
 156                 unsigned long unc_en:1;         /* enable */
 157                 unsigned long unc_inv:1;        /* invert counter mask */
 158                 unsigned long unc_thres:8;      /* counter mask */
 159                 unsigned long unc_res3:32;      /* reserved */
 160         } cbo; /* covers c-box */
 161         struct {
 162                 unsigned long unc_event:8;      /* event code */
 163                 unsigned long unc_res1:6;       /* reserved */
 164                 unsigned long unc_occ:2;        /* occ select */
 165                 unsigned long unc_res2:1;       /* reserved */
 166                 unsigned long unc_rst:1;        /* reset */
 167                 unsigned long unc_edge:1;       /* edge detec */
 168                 unsigned long unc_res3:1;       /* reserved */
 169                 unsigned long unc_res4:2;       /* reserved */
 170                 unsigned long unc_en:1;         /* enable */
 171                 unsigned long unc_inv:1;        /* invert counter mask */
 172                 unsigned long unc_thres:5;      /* threshold */
 173                 unsigned long unc_res5:1;       /* reserved */
 174                 unsigned long unc_occ_inv:1;    /* occupancy invert */
 175                 unsigned long unc_occ_edge:1;   /* occupancy edge detect */
 176                 unsigned long unc_res6:32;      /* reserved */
 177         } pcu; /* covers pcu */
 178         struct {
 179                 unsigned long unc_event:8;      /* event code */
 180                 unsigned long unc_res1:6;       /* reserved */
 181                 unsigned long unc_occ:2;        /* occ select */
 182                 unsigned long unc_res2:1;       /* reserved */
 183                 unsigned long unc_rst:1;        /* reset */
 184                 unsigned long unc_edge:1;       /* edge detec */
 185                 unsigned long unc_res3:1;       /* reserved */
 186                 unsigned long unc_ov_en:1;      /* overflow enable */
 187                 unsigned long unc_sel_ext:1;    /* event_sel extension */
 188                 unsigned long unc_en:1;         /* enable */
 189                 unsigned long unc_res4:1;       /* reserved */
 190                 unsigned long unc_thres:5;      /* threshold */
 191                 unsigned long unc_res5:1;       /* reserved */
 192                 unsigned long unc_occ_inv:1;    /* occupancy invert */
 193                 unsigned long unc_occ_edge:1;   /* occupancy edge detect */
 194                 unsigned long unc_res6:32;      /* reserved */
 195         } ivbep_pcu; /* covers ivb-ep pcu */
 196         struct {
 197                 unsigned long unc_event:8;      /* event code */
 198                 unsigned long unc_umask:8;      /* unit maks */
 199                 unsigned long unc_res1:1;       /* reserved */
 200                 unsigned long unc_rst:1;        /* reset */
 201                 unsigned long unc_edge:1;       /* edge detec */
 202                 unsigned long unc_res2:1;       /* reserved */
 203                 unsigned long unc_res3:1;       /* reserved */
 204                 unsigned long unc_event_ext:1;  /* event code extension */
 205                 unsigned long unc_en:1;         /* enable */
 206                 unsigned long unc_inv:1;        /* invert counter mask */
 207                 unsigned long unc_thres:8;      /* threshold */
 208                 unsigned long unc_res4:32;      /* reserved */
 209         } qpi; /* covers qpi */
 210         struct {
 211                 unsigned long tid:1;
 212                 unsigned long cid:3;
 213                 unsigned long res0:1;
 214                 unsigned long res1:3;
 215                 unsigned long res2:2;
 216                 unsigned long nid:8;
 217                 unsigned long state:5;
 218                 unsigned long opc:9;
 219                 unsigned long res3:1;
 220                 unsigned long res4:32;
 221         } cbo_filt; /* cbox filter */
 222         struct {
 223                 unsigned long tid:1;
 224                 unsigned long cid:4;
 225                 unsigned long res0:12;
 226                 unsigned long state:6;
 227                 unsigned long res1:9;
 228                 unsigned long res2:32;
 229         } ivbep_cbo_filt0; /* ivbep cbox filter0 */
 230         struct {
 231                 unsigned long nid:16;
 232                 unsigned long res0:4;
 233                 unsigned long opc:9;
 234                 unsigned long res1:1;
 235                 unsigned long nc:1;
 236                 unsigned long isoc:1;
 237                 unsigned long res2:32;
 238         } ivbep_cbo_filt1; /* ivbep cbox filter1 */
 239         struct {
 240                 unsigned long filt0:8; /* band0 freq filter */
 241                 unsigned long filt1:8; /* band1 freq filter */
 242                 unsigned long filt2:8; /* band2 freq filter */
 243                 unsigned long filt3:8; /* band3 freq filter */
 244                 unsigned long res1:32; /* reserved */
 245         } pcu_filt;
 246         struct {
 247                 unsigned long res1:6;
 248                 unsigned long lo_addr:26; /* lo order 26b */
 249                 unsigned long hi_addr:14; /* hi order 14b */
 250                 unsigned long res2:18; /* reserved */
 251         } ha_addr;
 252         struct {
 253                 unsigned long opc:6; /* opcode match */
 254                 unsigned long res1:26; /* reserved */
 255                 unsigned long res2:32; /* reserved */
 256         } ha_opc;
 257         struct {
 258                 unsigned long unc_event:8;      /* event code */
 259                 unsigned long unc_umask:8;      /* unit mask */
 260                 unsigned long unc_res1:1;       /* reserved */
 261                 unsigned long unc_rst:1;        /* reset */
 262                 unsigned long unc_edge:1;       /* edge detec */
 263                 unsigned long unc_res2:3;       /* reserved */
 264                 unsigned long unc_en:1;         /* enable */
 265                 unsigned long unc_res3:1;       /* reserved */
 266                 unsigned long unc_thres:8;      /* counter mask */
 267                 unsigned long unc_res4:32;      /* reserved */
 268         } irp; /* covers irp */
 269 } pfm_snbep_unc_reg_t;
 270
 271 extern void pfm_intel_snbep_unc_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e);
 272 extern int  pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e);
 273 extern const pfmlib_attr_desc_t snbep_unc_mods[];
 274 extern int  pfm_intel_snbep_unc_detect(void *this);
 275 extern int  pfm_intel_ivbep_unc_detect(void *this);
 276 extern int  pfm_intel_snbep_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e);
 277 extern int  pfm_intel_snbep_unc_can_auto_encode(void *this, int pidx, int uidx);
 278 extern int pfm_intel_snbep_unc_get_event_attr_info(void *this, int pidx, int attr_idx, pfm_event_attr_info_t *info);
 279
 280 static inline int
 281 is_cbo_filt_event(void *this, pfm_intel_x86_reg_t reg)
 282 {
 283         pfmlib_pmu_t *pmu = this;
 284         uint64_t sel = reg.sel_event_select;
 285         /*
 286          * umask bit 0 must be 1 (OPCODE)
 287          * TOR_INSERT: event code 0x35
 288          * TOR_OCCUPANCY: event code 0x36
 289          * LLC_LOOKUP : event code 0x34
 290          */
 291         return (pmu->flags & INTEL_PMU_FL_UNC_CBO)
 292                 && (reg.sel_unit_mask & 0x1)
 293                 && (sel == 0x35 || sel == 0x36 || sel == 0x34);
 294 }
 295
 296 #endif /* __PFMLIB_INTEL_SNBEP_UNC_PRIV_H__ */