user/perfmon/events/perf_events.h

   1 /*
   2  * Copyright (c) 2009 Google, Inc
   3  * Contributed by Stephane Eranian <eranian@google.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is furnished to do so,
  10  * subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
  16  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
  17  * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  18  * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
  19  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  20  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * This file is part of libpfm, a performance monitoring support library for
  23  * applications on Linux.
  24  */
  25
  26 #define CACHE_ST_ACCESS(n, d, e) \
  27        {\
  28         .name = #n"-STORES",\
  29         .desc = d" store accesses",\
  30         .id   = PERF_COUNT_HW_CACHE_##e,\
  31         .type = PERF_TYPE_HW_CACHE,\
  32         .modmsk = PERF_ATTR_HW,\
  33         .umask_ovfl_idx = -1,\
  34         .equiv = "PERF_COUNT_HW_CACHE_"#e":WRITE:ACCESS"\
  35        },\
  36        {\
  37         .name = #n"-STORE-MISSES",\
  38         .desc = d" store misses",\
  39         .id   = PERF_COUNT_HW_CACHE_##e,\
  40         .type = PERF_TYPE_HW_CACHE,\
  41         .modmsk = PERF_ATTR_HW,\
  42         .umask_ovfl_idx = -1,\
  43         .equiv = "PERF_COUNT_HW_CACHE_"#e":WRITE:MISS"\
  44        }
  45
  46 #define CACHE_PF_ACCESS(n, d, e) \
  47        {\
  48         .name = #n"-PREFETCHES",\
  49         .desc = d" prefetch accesses",\
  50         .id   = PERF_COUNT_HW_CACHE_##e,\
  51         .type = PERF_TYPE_HW_CACHE,\
  52         .modmsk = PERF_ATTR_HW,\
  53         .umask_ovfl_idx = -1,\
  54         .equiv = "PERF_COUNT_HW_CACHE_"#e":PREFETCH:ACCESS"\
  55        },\
  56        {\
  57         .name = #n"-PREFETCH-MISSES",\
  58         .desc = d" prefetch misses",\
  59         .id   = PERF_COUNT_HW_CACHE_##e,\
  60         .type = PERF_TYPE_HW_CACHE,\
  61         .modmsk = PERF_ATTR_HW,\
  62         .umask_ovfl_idx = -1,\
  63         .equiv = "PERF_COUNT_HW_CACHE_"#e":PREFETCH:MISS"\
  64        }
  65
  66
  67 #define CACHE_LD_ACCESS(n, d, e) \
  68        {\
  69         .name = #n"-LOADS",\
  70         .desc = d" load accesses",\
  71         .id   = PERF_COUNT_HW_CACHE_##e,\
  72         .type = PERF_TYPE_HW_CACHE,\
  73         .modmsk = PERF_ATTR_HW,\
  74         .umask_ovfl_idx = -1,\
  75         .equiv = "PERF_COUNT_HW_CACHE_"#e":READ:ACCESS"\
  76        },\
  77        {\
  78         .name = #n"-LOAD-MISSES",\
  79         .desc = d" load misses",\
  80         .id   = PERF_COUNT_HW_CACHE_##e,\
  81         .type = PERF_TYPE_HW_CACHE,\
  82         .modmsk = PERF_ATTR_HW,\
  83         .umask_ovfl_idx = -1,\
  84         .equiv = "PERF_COUNT_HW_CACHE_"#e":READ:MISS"\
  85        }
  86
  87 #define CACHE_ACCESS(n, d, e) \
  88         CACHE_LD_ACCESS(n, d, e), \
  89         CACHE_ST_ACCESS(n, d, e), \
  90         CACHE_PF_ACCESS(n, d, e)
  91
  92 #define ICACHE_ACCESS(n, d, e) \
  93         CACHE_LD_ACCESS(n, d, e), \
  94         CACHE_PF_ACCESS(n, d, e)
  95
  96 static perf_event_t perf_static_events[]={
  97         PCL_EVT_HW(CPU_CYCLES),
  98         PCL_EVT_AHW(CYCLES, CPU_CYCLES),
  99         PCL_EVT_AHW(CPU-CYCLES, CPU_CYCLES),
 100
 101         PCL_EVT_HW(INSTRUCTIONS),
 102         PCL_EVT_AHW(INSTRUCTIONS, INSTRUCTIONS),
 103
 104         PCL_EVT_HW(CACHE_REFERENCES),
 105         PCL_EVT_AHW(CACHE-REFERENCES, CACHE_REFERENCES),
 106
 107         PCL_EVT_HW(CACHE_MISSES),
 108         PCL_EVT_AHW(CACHE-MISSES,CACHE_MISSES),
 109
 110         PCL_EVT_HW(BRANCH_INSTRUCTIONS),
 111         PCL_EVT_AHW(BRANCH-INSTRUCTIONS, BRANCH_INSTRUCTIONS),
 112         PCL_EVT_AHW(BRANCHES, BRANCH_INSTRUCTIONS),
 113
 114         PCL_EVT_HW(BRANCH_MISSES),
 115         PCL_EVT_AHW(BRANCH-MISSES, BRANCH_MISSES),
 116
 117         PCL_EVT_HW(BUS_CYCLES),
 118         PCL_EVT_AHW(BUS-CYCLES, BUS_CYCLES),
 119
 120         PCL_EVT_HW(STALLED_CYCLES_FRONTEND),
 121         PCL_EVT_AHW(STALLED-CYCLES-FRONTEND, STALLED_CYCLES_FRONTEND),
 122         PCL_EVT_AHW(IDLE-CYCLES-FRONTEND, STALLED_CYCLES_FRONTEND),
 123
 124         PCL_EVT_HW(STALLED_CYCLES_BACKEND),
 125         PCL_EVT_AHW(STALLED-CYCLES-BACKEND, STALLED_CYCLES_BACKEND),
 126         PCL_EVT_AHW(IDLE-CYCLES-BACKEND, STALLED_CYCLES_BACKEND),
 127
 128         PCL_EVT_HW(REF_CPU_CYCLES),
 129         PCL_EVT_AHW(REF-CYCLES,REF_CPU_CYCLES),
 130
 131         PCL_EVT_SW(CPU_CLOCK),
 132         PCL_EVT_ASW(CPU-CLOCK, CPU_CLOCK),
 133
 134         PCL_EVT_SW(TASK_CLOCK),
 135         PCL_EVT_ASW(TASK-CLOCK, TASK_CLOCK),
 136
 137         PCL_EVT_SW(PAGE_FAULTS),
 138         PCL_EVT_ASW(PAGE-FAULTS, PAGE_FAULTS),
 139         PCL_EVT_ASW(FAULTS, PAGE_FAULTS),
 140
 141         PCL_EVT_SW(CONTEXT_SWITCHES),
 142         PCL_EVT_ASW(CONTEXT-SWITCHES, CONTEXT_SWITCHES),
 143         PCL_EVT_ASW(CS, CONTEXT_SWITCHES),
 144
 145         PCL_EVT_SW(CPU_MIGRATIONS),
 146         PCL_EVT_ASW(CPU-MIGRATIONS, CPU_MIGRATIONS),
 147         PCL_EVT_ASW(MIGRATIONS, CPU_MIGRATIONS),
 148
 149         PCL_EVT_SW(PAGE_FAULTS_MIN),
 150         PCL_EVT_ASW(MINOR-FAULTS, PAGE_FAULTS_MIN),
 151
 152         PCL_EVT_SW(PAGE_FAULTS_MAJ),
 153         PCL_EVT_ASW(MAJOR-FAULTS, PAGE_FAULTS_MAJ),
 154         {
 155         .name = "PERF_COUNT_HW_CACHE_L1D",
 156         .desc = "L1 data cache",
 157         .id   = PERF_COUNT_HW_CACHE_L1D,
 158         .type = PERF_TYPE_HW_CACHE,
 159         .numasks = 5,
 160         .modmsk = PERF_ATTR_HW,
 161         .umask_ovfl_idx = -1,
 162         .ngrp = 2,
 163         .umasks = {
 164                 { .uname = "READ",
 165                   .udesc = "read access",
 166                   .uid   = PERF_COUNT_HW_CACHE_OP_READ << 8,
 167                   .uflags= PERF_FL_DEFAULT,
 168                   .grpid = 0,
 169                 },
 170                 { .uname = "WRITE",
 171                   .udesc = "write access",
 172                   .uid   = PERF_COUNT_HW_CACHE_OP_WRITE << 8,
 173                   .grpid = 0,
 174                 },
 175                 { .uname = "PREFETCH",
 176                   .udesc = "prefetch access",
 177                   .uid   = PERF_COUNT_HW_CACHE_OP_PREFETCH << 8,
 178                   .grpid = 0,
 179                 },
 180                 { .uname = "ACCESS",
 181                   .udesc = "hit access",
 182                   .uid   = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16,
 183                   .grpid = 1,
 184                 },
 185                 { .uname = "MISS",
 186                   .udesc = "miss access",
 187                   .uid   = PERF_COUNT_HW_CACHE_RESULT_MISS << 16,
 188                   .uflags= PERF_FL_DEFAULT,
 189                   .grpid = 1,
 190                 }
 191         }
 192        },
 193        CACHE_ACCESS(L1-DCACHE, "L1 cache", L1D),
 194        {
 195         .name = "PERF_COUNT_HW_CACHE_L1I",
 196         .desc = "L1 instruction cache",
 197         .id   = PERF_COUNT_HW_CACHE_L1I,
 198         .type = PERF_TYPE_HW_CACHE,
 199         .numasks = 4,
 200         .modmsk = PERF_ATTR_HW,
 201         .umask_ovfl_idx = -1,
 202         .ngrp = 2,
 203         .umasks = {
 204                 { .uname = "READ",
 205                   .udesc = "read access",
 206                   .uid   = PERF_COUNT_HW_CACHE_OP_READ << 8,
 207                   .uflags= PERF_FL_DEFAULT,
 208                   .grpid = 0,
 209                 },
 210                 { .uname = "PREFETCH",
 211                   .udesc = "prefetch access",
 212                   .uid   = PERF_COUNT_HW_CACHE_OP_PREFETCH << 8,
 213                   .grpid = 0,
 214                 },
 215                 { .uname = "ACCESS",
 216                   .udesc = "hit access",
 217                   .uid   = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16,
 218                   .grpid = 1,
 219                 },
 220                 { .uname = "MISS",
 221                   .udesc = "miss access",
 222                   .uid   = PERF_COUNT_HW_CACHE_RESULT_MISS << 16,
 223                   .uflags= PERF_FL_DEFAULT,
 224                   .grpid = 1,
 225                 }
 226         }
 227        },
 228        ICACHE_ACCESS(L1-ICACHE, "L1I cache", L1I),
 229        {
 230         .name = "PERF_COUNT_HW_CACHE_LL",
 231         .desc = "Last level cache",
 232         .id   = PERF_COUNT_HW_CACHE_LL,
 233         .type = PERF_TYPE_HW_CACHE,
 234         .numasks = 5,
 235         .modmsk = PERF_ATTR_HW,
 236         .umask_ovfl_idx = -1,
 237         .ngrp = 2,
 238         .umasks = {
 239                 { .uname = "READ",
 240                   .udesc = "read access",
 241                   .uid   = PERF_COUNT_HW_CACHE_OP_READ << 8,
 242                   .uflags= PERF_FL_DEFAULT,
 243                   .grpid = 0,
 244                 },
 245                 { .uname = "WRITE",
 246                   .udesc = "write access",
 247                   .uid   = PERF_COUNT_HW_CACHE_OP_WRITE << 8,
 248                   .grpid = 0,
 249                 },
 250                 { .uname = "PREFETCH",
 251                   .udesc = "prefetch access",
 252                   .uid   = PERF_COUNT_HW_CACHE_OP_PREFETCH << 8,
 253                   .grpid = 0,
 254                 },
 255                 { .uname = "ACCESS",
 256                   .udesc = "hit access",
 257                   .uid   = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16,
 258                   .grpid = 1,
 259                 },
 260                 { .uname = "MISS",
 261                   .udesc = "miss access",
 262                   .uid   = PERF_COUNT_HW_CACHE_RESULT_MISS << 16,
 263                   .uflags= PERF_FL_DEFAULT,
 264                   .grpid = 1,
 265                 }
 266         }
 267        },
 268        CACHE_ACCESS(LLC, "Last level cache", LL),
 269        {
 270         .name = "PERF_COUNT_HW_CACHE_DTLB",
 271         .desc = "Data Translation Lookaside Buffer",
 272         .id   = PERF_COUNT_HW_CACHE_DTLB,
 273         .type = PERF_TYPE_HW_CACHE,
 274         .numasks = 5,
 275         .modmsk = PERF_ATTR_HW,
 276         .umask_ovfl_idx = -1,
 277         .ngrp = 2,
 278         .umasks = {
 279                 { .uname = "READ",
 280                   .udesc = "read access",
 281                   .uid   = PERF_COUNT_HW_CACHE_OP_READ << 8,
 282                   .uflags= PERF_FL_DEFAULT,
 283                   .grpid = 0,
 284                 },
 285                 { .uname = "WRITE",
 286                   .udesc = "write access",
 287                   .uid   = PERF_COUNT_HW_CACHE_OP_WRITE << 8,
 288                   .grpid = 0,
 289                 },
 290                 { .uname = "PREFETCH",
 291                   .udesc = "prefetch access",
 292                   .uid   = PERF_COUNT_HW_CACHE_OP_PREFETCH << 8,
 293                   .grpid = 0,
 294                 },
 295                 { .uname = "ACCESS",
 296                   .udesc = "hit access",
 297                   .uid   = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16,
 298                   .grpid = 1,
 299                 },
 300                 { .uname = "MISS",
 301                   .udesc = "miss access",
 302                   .uid   = PERF_COUNT_HW_CACHE_RESULT_MISS << 16,
 303                   .uflags= PERF_FL_DEFAULT,
 304                   .grpid = 1,
 305                 }
 306         }
 307        },
 308        CACHE_ACCESS(DTLB, "Data TLB", DTLB),
 309        {
 310         .name = "PERF_COUNT_HW_CACHE_ITLB",
 311         .desc = "Instruction Translation Lookaside Buffer",
 312         .id   = PERF_COUNT_HW_CACHE_ITLB,
 313         .type = PERF_TYPE_HW_CACHE,
 314         .numasks = 3,
 315         .modmsk = PERF_ATTR_HW,
 316         .umask_ovfl_idx = -1,
 317         .ngrp = 2,
 318         .umasks = {
 319                 { .uname = "READ",
 320                   .udesc = "read access",
 321                   .uid   = PERF_COUNT_HW_CACHE_OP_READ << 8,
 322                   .uflags= PERF_FL_DEFAULT,
 323                   .grpid = 0,
 324                 },
 325                 { .uname = "ACCESS",
 326                   .udesc = "hit access",
 327                   .uid   = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16,
 328                   .grpid = 1,
 329                 },
 330                 { .uname = "MISS",
 331                   .udesc = "miss access",
 332                   .uid   = PERF_COUNT_HW_CACHE_RESULT_MISS << 16,
 333                   .uflags= PERF_FL_DEFAULT,
 334                   .grpid = 1,
 335                 }
 336         }
 337        },
 338        CACHE_LD_ACCESS(ITLB, "Instruction TLB", ITLB),
 339        {
 340         .name = "PERF_COUNT_HW_CACHE_BPU",
 341         .desc = "Branch Prediction Unit",
 342         .id   = PERF_COUNT_HW_CACHE_BPU,
 343         .type = PERF_TYPE_HW_CACHE,
 344         .numasks = 3,
 345         .modmsk = PERF_ATTR_HW,
 346         .umask_ovfl_idx = -1,
 347         .ngrp = 2,
 348         .umasks = {
 349                 { .uname = "READ",
 350                   .udesc = "read access",
 351                   .uid   = PERF_COUNT_HW_CACHE_OP_READ << 8,
 352                   .uflags= PERF_FL_DEFAULT,
 353                   .grpid = 0,
 354                 },
 355                 { .uname = "ACCESS",
 356                   .udesc = "hit access",
 357                   .uid   = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16,
 358                   .grpid = 1,
 359                 },
 360                 { .uname = "MISS",
 361                   .udesc = "miss access",
 362                   .uid   = PERF_COUNT_HW_CACHE_RESULT_MISS << 16,
 363                   .uflags= PERF_FL_DEFAULT,
 364                   .grpid = 1,
 365                 }
 366         }
 367        },
 368        CACHE_LD_ACCESS(BRANCH, "Branch ", BPU),
 369        {
 370         .name = "PERF_COUNT_HW_CACHE_NODE",
 371         .desc = "Node memory access",
 372         .id   = PERF_COUNT_HW_CACHE_NODE,
 373         .type = PERF_TYPE_HW_CACHE,
 374         .numasks = 5,
 375         .modmsk = PERF_ATTR_HW,
 376         .umask_ovfl_idx = -1,
 377         .ngrp = 2,
 378         .umasks = {
 379                 { .uname = "READ",
 380                   .udesc = "read access",
 381                   .uid   = PERF_COUNT_HW_CACHE_OP_READ << 8,
 382                   .uflags= PERF_FL_DEFAULT,
 383                   .grpid = 0,
 384                 },
 385                 { .uname = "WRITE",
 386                   .udesc = "write access",
 387                   .uid   = PERF_COUNT_HW_CACHE_OP_WRITE << 8,
 388                   .grpid = 0,
 389                 },
 390                 { .uname = "PREFETCH",
 391                   .udesc = "prefetch access",
 392                   .uid   = PERF_COUNT_HW_CACHE_OP_PREFETCH << 8,
 393                   .grpid = 0,
 394                 },
 395                 { .uname = "ACCESS",
 396                   .udesc = "hit access",
 397                   .uid   = PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16,
 398                   .grpid = 1,
 399                 },
 400                 { .uname = "MISS",
 401                   .udesc = "miss access",
 402                   .uid   = PERF_COUNT_HW_CACHE_RESULT_MISS << 16,
 403                   .uflags= PERF_FL_DEFAULT,
 404                   .grpid = 1,
 405                 }
 406         },
 407        },
 408        CACHE_ACCESS(NODE, "Node ", NODE)
 409 };
 410 #define PME_PERF_EVENT_COUNT (sizeof(perf_static_events)/sizeof(perf_event_t))