vmm: Fix use-after-free in load_elf()
[akaros.git] / user / perfmon / events / intel_netburst_events.h
1 /*
2  * Copyright (c) 2006 IBM Corp.
3  * Contributed by Kevin Corry <kevcorry@us.ibm.com>
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * This header contains arrays to describe the Event-Selection-Control
24  * Registers (ESCRs), Counter-Configuration-Control Registers (CCCRs),
25  * and countable events on Pentium4/Xeon/EM64T systems.
26  *
27  * For more details, see:
28  * - IA-32 Intel Architecture Software Developer's Manual,
29  *   Volume 3B: System Programming Guide, Part 2
30  *   (available at: http://www.intel.com/design/Pentium4/manuals/253669.htm)
31  *   - Chapter 18.10: Performance Monitoring Overview
32  *   - Chapter 18.13: Performance Monitoring - Pentium4 and Xeon Processors
33  *   - Chapter 18.14: Performance Monitoring and Hyper-Threading Technology
34  *   - Appendix A.1: Pentium4 and Xeon Processor Performance-Monitoring Events
35  *
36  * This header also contains an array to describe how the Perfmon PMCs map to
37  * the ESCRs and CCCRs.
38  */
39
40 #ifndef _NETBURST_EVENTS_H_
41 #define _NETBURST_EVENTS_H_
42 /**
43  * netburst_events
44  *
45  * Array of events that can be counted on Pentium4.
46  **/
47 static const netburst_entry_t netburst_events[] = {
48
49         /* 0 */
50         {.name = "TC_deliver_mode",
51          .desc = "The duration (in clock cycles) of the operating modes of "
52                  "the trace cache and decode engine in the processor package",
53          .event_select = 0x1,
54          .escr_select = 0x1,
55          .allowed_escrs = { 9, 32 },
56          .perf_code = P4_EVENT_TC_DELIVER_MODE,
57          .event_masks = {
58                 {.name = "DD",
59                  .desc = "Both logical CPUs in deliver mode",
60                  .bit = 0,
61                 },
62                 {.name = "DB",
63                  .desc = "Logical CPU 0 in deliver mode and "
64                          "logical CPU 1 in build mode",
65                  .bit = 1,
66                 },
67                 {.name = "DI",
68                  .desc = "Logical CPU 0 in deliver mode and logical CPU 1 "
69                          "either halted, under machine clear condition, or "
70                          "transitioning to a long microcode flow",
71                  .bit = 2,
72                 },
73                 {.name = "BD",
74                  .desc = "Logical CPU 0 in build mode and "
75                          "logical CPU 1 is in deliver mode",
76                  .bit = 3,
77                 },
78                 {.name = "BB",
79                  .desc = "Both logical CPUs in build mode",
80                  .bit = 4,
81                 },
82                 {.name = "BI",
83                  .desc = "Logical CPU 0 in build mode and logical CPU 1 "
84                          "either halted, under machine clear condition, or "
85                          "transitioning to a long microcode flow",
86                  .bit = 5,
87                 },
88                 {.name = "ID",
89                  .desc = "Logical CPU 0 either halted, under machine clear "
90                          "condition, or transitioning to a long microcode "
91                          "flow, and logical CPU 1 in deliver mode",
92                  .bit = 6,
93                 },
94                 {.name = "IB",
95                  .desc = "Logical CPU 0 either halted, under machine clear "
96                          "condition, or transitioning to a long microcode "
97                          "flow, and logical CPU 1 in build mode",
98                  .bit = 7,
99                 },
100          },
101         },
102
103         /* 1 */
104         {.name = "BPU_fetch_request",
105          .desc = "Instruction fetch requests by the Branch Prediction Unit",
106          .event_select = 0x3,
107          .escr_select = 0x0,
108          .allowed_escrs = { 0, 23 },
109          .perf_code = P4_EVENT_BPU_FETCH_REQUEST,
110          .event_masks = {
111                 {.name = "TCMISS",
112                  .desc = "Trace cache lookup miss",
113                  .bit = 0,
114                  .flags = NETBURST_FL_DFL,
115                 },
116          },
117         },
118
119         /* 2 */
120         {.name = "ITLB_reference",
121          .desc = "Translations using the Instruction "
122                  "Translation Look-Aside Buffer",
123          .event_select = 0x18,
124          .escr_select = 0x3,
125          .allowed_escrs = { 3, 26 },
126          .perf_code = P4_EVENT_ITLB_REFERENCE,
127          .event_masks = {
128                 {.name = "HIT",
129                  .desc = "ITLB hit",
130                  .bit = 0,
131                 },
132                 {.name = "MISS",
133                  .desc = "ITLB miss",
134                  .bit = 1,
135                 },
136                 {.name = "HIT_UC",
137                  .desc = "Uncacheable ITLB hit",
138                  .bit = 2,
139                 },
140          },
141         },
142
143         /* 3 */
144         {.name = "memory_cancel",
145          .desc = "Canceling of various types of requests in the "
146                  "Data cache Address Control unit (DAC)",
147          .event_select = 0x2,
148          .escr_select = 0x5,
149          .allowed_escrs = { 15, 38 },
150          .perf_code = P4_EVENT_MEMORY_CANCEL,
151          .event_masks = {
152                 {.name = "ST_RB_FULL",
153                  .desc = "Replayed because no store request "
154                          "buffer is available",
155                  .bit = 2,
156                 },
157                 {.name = "64K_CONF",
158                  .desc = "Conflicts due to 64K aliasing",
159                  .bit = 3,
160                 },
161          },
162         },
163
164         /* 4 */
165         {.name = "memory_complete",
166          .desc = "Completions of a load split, store split, "
167                  "uncacheable (UC) split, or UC load",
168          .event_select = 0x8,
169          .escr_select = 0x2,
170          .allowed_escrs = { 13, 36 },
171          .perf_code = P4_EVENT_MEMORY_COMPLETE,
172          .event_masks = {
173                 {.name = "LSC",
174                  .desc = "Load split completed, excluding UC/WC loads",
175                  .bit = 0,
176                 },
177                 {.name = "SSC",
178                  .desc = "Any split stores completed",
179                  .bit = 1,
180                 },
181          },
182         },
183
184         /* 5 */
185         {.name = "load_port_replay",
186          .desc = "Replayed events at the load port",
187          .event_select = 0x4,
188          .escr_select = 0x2,
189          .allowed_escrs = { 13, 36 },
190          .perf_code = P4_EVENT_LOAD_PORT_REPLAY,
191          .event_masks = {
192                 {.name = "SPLIT_LD",
193                  .desc = "Split load",
194                  .bit = 1,
195                  .flags = NETBURST_FL_DFL,
196                 },
197          },
198         },
199
200         /* 6 */
201         {.name = "store_port_replay",
202          .desc = "Replayed events at the store port",
203          .event_select = 0x5,
204          .escr_select = 0x2,
205          .allowed_escrs = { 13, 36 },
206          .perf_code = P4_EVENT_STORE_PORT_REPLAY,
207          .event_masks = {
208                 {.name = "SPLIT_ST",
209                  .desc = "Split store",
210                  .bit = 1,
211                  .flags = NETBURST_FL_DFL,
212                 },
213          },
214         },
215
216         /* 7 */
217         {.name = "MOB_load_replay",
218          .desc = "Count of times the memory order buffer (MOB) "
219                  "caused a load operation to be replayed",
220          .event_select = 0x3,
221          .escr_select = 0x2,
222          .allowed_escrs = { 2, 25 },
223          .perf_code = P4_EVENT_MOB_LOAD_REPLAY,
224          .event_masks = {
225                 {.name = "NO_STA",
226                  .desc = "Replayed because of unknown store address",
227                  .bit = 1,
228                 },
229                 {.name = "NO_STD",
230                  .desc = "Replayed because of unknown store data",
231                  .bit = 3,
232                 },
233                 {.name = "PARTIAL_DATA",
234                  .desc = "Replayed because of partially overlapped data "
235                          "access between the load and store operations",
236                  .bit = 4,
237                 },
238                 {.name = "UNALGN_ADDR",
239                  .desc = "Replayed because the lower 4 bits of the "
240                          "linear address do not match between the "
241                          "load and store operations",
242                  .bit = 5,
243                 },
244          },
245         },
246
247         /* 8 */
248         {.name = "page_walk_type",
249          .desc = "Page walks that the page miss handler (PMH) performs",
250          .event_select = 0x1,
251          .escr_select = 0x4,
252          .allowed_escrs = { 4, 27 },
253          .perf_code = P4_EVENT_PAGE_WALK_TYPE,
254          .event_masks = {
255                 {.name = "DTMISS",
256                  .desc = "Page walk for a data TLB miss (load or store)",
257                  .bit = 0,
258                 },
259                 {.name = "ITMISS",
260                  .desc = "Page walk for an instruction TLB miss",
261                  .bit = 1,
262                 },
263          },
264         },
265
266         /* 9 */
267         {.name = "BSQ_cache_reference",
268          .desc = "Cache references (2nd or 3rd level caches) as seen by the "
269                  "bus unit. Read types include both load and RFO, and write "
270                  "types include writebacks and evictions",
271          .event_select = 0xC,
272          .escr_select = 0x7,
273          .allowed_escrs = { 7, 30 },
274          .perf_code = P4_EVENT_BSQ_CACHE_REFERENCE,
275          .event_masks = {
276                 {.name = "RD_2ndL_HITS",
277                  .desc = "Read 2nd level cache hit Shared",
278                  .bit = 0,
279                 },
280                 {.name = "RD_2ndL_HITE",
281                  .desc = "Read 2nd level cache hit Exclusive",
282                  .bit = 1,
283                 },
284                 {.name = "RD_2ndL_HITM",
285                  .desc = "Read 2nd level cache hit Modified",
286                  .bit = 2,
287                 },
288                 {.name = "RD_3rdL_HITS",
289                  .desc = "Read 3rd level cache hit Shared",
290                  .bit = 3,
291                 },
292                 {.name = "RD_3rdL_HITE",
293                  .desc = "Read 3rd level cache hit Exclusive",
294                  .bit = 4,
295                 },
296                 {.name = "RD_3rdL_HITM",
297                  .desc = "Read 3rd level cache hit Modified",
298                  .bit = 5,
299                 },
300                 {.name = "RD_2ndL_MISS",
301                  .desc = "Read 2nd level cache miss",
302                  .bit = 8,
303                 },
304                 {.name = "RD_3rdL_MISS",
305                  .desc = "Read 3rd level cache miss",
306                  .bit = 9,
307                 },
308                 {.name = "WR_2ndL_MISS",
309                  .desc = "A writeback lookup from DAC misses the 2nd "
310                          "level cache (unlikely to happen)",
311                  .bit = 10,
312                 },
313          },
314         },
315
316         /* 10 */
317         {.name = "IOQ_allocation",
318          .desc = "Count of various types of transactions on the bus. A count "
319                  "is generated each time a transaction is allocated into the "
320                  "IOQ that matches the specified mask bits. An allocated entry "
321                  "can be a sector (64 bytes) or a chunk of 8 bytes. Requests "
322                  "are counted once per retry. All 'TYPE_BIT*' event-masks "
323                  "together are treated as a single 5-bit value",
324          .event_select = 0x3,
325          .escr_select = 0x6,
326          .allowed_escrs = { 6, 29 },
327          .perf_code = P4_EVENT_IOQ_ALLOCATION,
328          .event_masks = {
329                 {.name = "TYPE_BIT0",
330                  .desc = "Bus request type (bit 0)",
331                  .bit = 0,
332                 },
333                 {.name = "TYPE_BIT1",
334                  .desc = "Bus request type (bit 1)",
335                  .bit = 1,
336                 },
337                 {.name = "TYPE_BIT2",
338                  .desc = "Bus request type (bit 2)",
339                  .bit = 2,
340                 },
341                 {.name = "TYPE_BIT3",
342                  .desc = "Bus request type (bit 3)",
343                  .bit = 3,
344                 },
345                 {.name = "TYPE_BIT4",
346                  .desc = "Bus request type (bit 4)",
347                  .bit = 4,
348                 },
349                 {.name = "ALL_READ",
350                  .desc = "Count read entries",
351                  .bit = 5,
352                 },
353                 {.name = "ALL_WRITE",
354                  .desc = "Count write entries",
355                  .bit = 6,
356                 },
357                 {.name = "MEM_UC",
358                  .desc = "Count UC memory access entries",
359                  .bit = 7,
360                 },
361                 {.name = "MEM_WC",
362                  .desc = "Count WC memory access entries",
363                  .bit = 8,
364                 },
365                 {.name = "MEM_WT",
366                  .desc = "Count write-through (WT) memory access entries",
367                  .bit = 9,
368                 },
369                 {.name = "MEM_WP",
370                  .desc = "Count write-protected (WP) memory access entries",
371                  .bit = 10,
372                 },
373                 {.name = "MEM_WB",
374                  .desc = "Count WB memory access entries",
375                  .bit = 11,
376                 },
377                 {.name = "OWN",
378                  .desc = "Count all store requests driven by processor, as "
379                          "opposed to other processor or DMA",
380                  .bit = 13,
381                 },
382                 {.name = "OTHER",
383                  .desc = "Count all requests driven by other "
384                          "processors or DMA",
385                  .bit = 14,
386                 },
387                 {.name = "PREFETCH",
388                  .desc = "Include HW and SW prefetch requests in the count",
389                  .bit = 15,
390                 },
391          },
392         },
393
394         /* 11 */
395         {.name = "IOQ_active_entries",
396          .desc = "Number of entries (clipped at 15) in the IOQ that are "
397                  "active. An allocated entry can be a sector (64 bytes) "
398                  "or a chunk of 8 bytes. This event must be programmed in "
399                  "conjunction with IOQ_allocation. All 'TYPE_BIT*' event-masks "
400                  "together are treated as a single 5-bit value",
401          .event_select = 0x1A,
402          .escr_select = 0x6,
403          .allowed_escrs = { 29, -1 },
404          .perf_code = P4_EVENT_IOQ_ACTIVE_ENTRIES,
405          .event_masks = {
406                 {.name = "TYPE_BIT0",
407                  .desc = "Bus request type (bit 0)",
408                  .bit = 0,
409                 },
410                 {.name = "TYPE_BIT1",
411                  .desc = "Bus request type (bit 1)",
412                  .bit = 1,
413                 },
414                 {.name = "TYPE_BIT2",
415                  .desc = "Bus request type (bit 2)",
416                  .bit = 2,
417                 },
418                 {.name = "TYPE_BIT3",
419                  .desc = "Bus request type (bit 3)",
420                  .bit = 3,
421                 },
422                 {.name = "TYPE_BIT4",
423                  .desc = "Bus request type (bit 4)",
424                  .bit = 4,
425                 },
426                 {.name = "ALL_READ",
427                  .desc = "Count read entries",
428                  .bit = 5,
429                 },
430                 {.name = "ALL_WRITE",
431                  .desc = "Count write entries",
432                  .bit = 6,
433                 },
434                 {.name = "MEM_UC",
435                  .desc = "Count UC memory access entries",
436                  .bit = 7,
437                 },
438                 {.name = "MEM_WC",
439                  .desc = "Count WC memory access entries",
440                  .bit = 8,
441                 },
442                 {.name = "MEM_WT",
443                  .desc = "Count write-through (WT) memory access entries",
444                  .bit = 9,
445                 },
446                 {.name = "MEM_WP",
447                  .desc = "Count write-protected (WP) memory access entries",
448                  .bit = 10,
449                 },
450                 {.name = "MEM_WB",
451                  .desc = "Count WB memory access entries",
452                  .bit = 11,
453                 },
454                 {.name = "OWN",
455                  .desc = "Count all store requests driven by processor, as "
456                          "opposed to other processor or DMA",
457                  .bit = 13,
458                 },
459                 {.name = "OTHER",
460                  .desc = "Count all requests driven by other "
461                          "processors or DMA",
462                  .bit = 14,
463                 },
464                 {.name = "PREFETCH",
465                  .desc = "Include HW and SW prefetch requests in the count",
466                  .bit = 15,
467                 },
468          },
469         },
470
471         /* 12 */
472         {.name = "FSB_data_activity",
473          .desc = "Count of DRDY or DBSY events that "
474                  "occur on the front side bus",
475          .event_select = 0x17,
476          .escr_select = 0x6,
477          .allowed_escrs = { 6, 29 },
478          .perf_code = P4_EVENT_FSB_DATA_ACTIVITY,
479          .event_masks = {
480                 {.name = "DRDY_DRV",
481                  .desc = "Count when this processor drives data onto the bus. "
482                          "Includes writes and implicit writebacks",
483                  .bit = 0,
484                 },
485                 {.name = "DRDY_OWN",
486                  .desc = "Count when this processor reads data from the bus. "
487                          "Includes loads and some PIC transactions. Count "
488                          "DRDY events that we drive. Count DRDY events sampled "
489                          "that we own",
490                  .bit = 1,
491                 },
492                 {.name = "DRDY_OTHER",
493                  .desc = "Count when data is on the bus but not being sampled "
494                          "by the processor. It may or may not be driven by "
495                          "this processor",
496                  .bit = 2,
497                 },
498                 {.name = "DBSY_DRV",
499                  .desc = "Count when this processor reserves the bus for use "
500                          "in the next bus cycle in order to drive data",
501                  .bit = 3,
502                 },
503                 {.name = "DBSY_OWN",
504                  .desc = "Count when some agent reserves the bus for use in "
505                          "the next bus cycle to drive data that this processor "
506                          "will sample",
507                  .bit = 4,
508                 },
509                 {.name = "DBSY_OTHER",
510                  .desc = "Count when some agent reserves the bus for use in "
511                          "the next bus cycle to drive data that this processor "
512                          "will NOT sample. It may or may not be being driven "
513                          "by this processor",
514                  .bit = 5,
515                 },
516          },
517         },
518
519         /* 13 */
520         {.name = "BSQ_allocation",
521          .desc = "Allocations in the Bus Sequence Unit (BSQ). The event mask "
522                  "bits consist of four sub-groups: request type, request "
523                  "length, memory type, and a sub-group consisting mostly of "
524                  "independent bits (5 through 10). Must specify a mask for "
525                  "each sub-group",
526          .event_select = 0x5,
527          .escr_select = 0x7,
528          .allowed_escrs = { 7, -1 },
529          .perf_code = P4_EVENT_BSQ_ALLOCATION,
530          .event_masks = {
531                 {.name = "REQ_TYPE0",
532                  .desc = "Along with REQ_TYPE1, request type encodings are: "
533                          "0 - Read (excludes read invalidate), 1 - Read "
534                          "invalidate, 2 - Write (other than writebacks), 3 - "
535                          "Writeback (evicted from cache)",
536                  .bit = 0,
537                 },
538                 {.name = "REQ_TYPE1",
539                  .desc = "Along with REQ_TYPE0, request type encodings are: "
540                          "0 - Read (excludes read invalidate), 1 - Read "
541                          "invalidate, 2 - Write (other than writebacks), 3 - "
542                          "Writeback (evicted from cache)",
543                  .bit = 1,
544                 },
545                 {.name = "REQ_LEN0",
546                  .desc = "Along with REQ_LEN1, request length encodings are: "
547                          "0 - zero chunks, 1 - one chunk, 3 - eight chunks",
548                  .bit = 2,
549                 },
550                 {.name = "REQ_LEN1",
551                  .desc = "Along with REQ_LEN0, request length encodings are: "
552                          "0 - zero chunks, 1 - one chunk, 3 - eight chunks",
553                  .bit = 3,
554                 },
555                 {.name = "REQ_IO_TYPE",
556                  .desc = "Request type is input or output",
557                  .bit = 5,
558                 },
559                 {.name = "REQ_LOCK_TYPE",
560                  .desc = "Request type is bus lock",
561                  .bit = 6,
562                 },
563                 {.name = "REQ_CACHE_TYPE",
564                  .desc = "Request type is cacheable",
565                  .bit = 7,
566                 },
567                 {.name = "REQ_SPLIT_TYPE",
568                  .desc = "Request type is a bus 8-byte chunk split across "
569                          "an 8-byte boundary",
570                  .bit = 8,
571                 },
572                 {.name = "REQ_DEM_TYPE",
573                  .desc = "0: Request type is HW.SW prefetch. "
574                          "1: Request type is a demand",
575                  .bit = 9,
576                 },
577                 {.name = "REQ_ORD_TYPE",
578                  .desc = "Request is an ordered type",
579                  .bit = 10,
580                 },
581                 {.name = "MEM_TYPE0",
582                  .desc = "Along with MEM_TYPE1 and MEM_TYPE2, "
583                          "memory type encodings are: 0 - UC, "
584                          "1 - USWC, 4- WT, 5 - WP, 6 - WB",
585                  .bit = 11,
586                 },
587                 {.name = "MEM_TYPE1",
588                  .desc = "Along with MEM_TYPE0 and MEM_TYPE2, "
589                          "memory type encodings are: 0 - UC, "
590                          "1 - USWC, 4- WT, 5 - WP, 6 - WB",
591                  .bit = 12,
592                 },
593                 {.name = "MEM_TYPE2",
594                  .desc = "Along with MEM_TYPE0 and MEM_TYPE1, "
595                          "memory type encodings are: 0 - UC, "
596                          "1 - USWC, 4- WT, 5 - WP, 6 - WB",
597                  .bit = 13,
598                 },
599          },
600         },
601
602         /* 14 */
603         {.name = "BSQ_active_entries",
604          .desc = "Number of BSQ entries (clipped at 15) currently active "
605                  "(valid) which meet the subevent mask criteria during "
606                  "allocation in the BSQ. Active request entries are allocated "
607                  "on the BSQ until de-allocated. De-allocation of an entry "
608                  "does not necessarily imply the request is filled. This "
609                  "event must be programmed in conjunction with BSQ_allocation",
610          .event_select = 0x6,
611          .escr_select = 0x7,
612          .allowed_escrs = { 30, -1 },
613          .perf_code = P4_EVENT_BSQ_ACTIVE_ENTRIES,
614          .event_masks = {
615                 {.name = "REQ_TYPE0",
616                  .desc = "Along with REQ_TYPE1, request type encodings are: "
617                          "0 - Read (excludes read invalidate), 1 - Read "
618                          "invalidate, 2 - Write (other than writebacks), 3 - "
619                          "Writeback (evicted from cache)",
620                  .bit = 0,
621                 },
622                 {.name = "REQ_TYPE1",
623                  .desc = "Along with REQ_TYPE0, request type encodings are: "
624                          "0 - Read (excludes read invalidate), 1 - Read "
625                          "invalidate, 2 - Write (other than writebacks), 3 - "
626                          "Writeback (evicted from cache)",
627                  .bit = 1,
628                 },
629                 {.name = "REQ_LEN0",
630                  .desc = "Along with REQ_LEN1, request length encodings are: "
631                          "0 - zero chunks, 1 - one chunk, 3 - eight chunks",
632                  .bit = 2,
633                 },
634                 {.name = "REQ_LEN1",
635                  .desc = "Along with REQ_LEN0, request length encodings are: "
636                          "0 - zero chunks, 1 - one chunk, 3 - eight chunks",
637                  .bit = 3,
638                 },
639                 {.name = "REQ_IO_TYPE",
640                  .desc = "Request type is input or output",
641                  .bit = 5,
642                 },
643                 {.name = "REQ_LOCK_TYPE",
644                  .desc = "Request type is bus lock",
645                  .bit = 6,
646                 },
647                 {.name = "REQ_CACHE_TYPE",
648                  .desc = "Request type is cacheable",
649                  .bit = 7,
650                 },
651                 {.name = "REQ_SPLIT_TYPE",
652                  .desc = "Request type is a bus 8-byte chunk split across "
653                          "an 8-byte boundary",
654                  .bit = 8,
655                 },
656                 {.name = "REQ_DEM_TYPE",
657                  .desc = "0: Request type is HW.SW prefetch. "
658                          "1: Request type is a demand",
659                  .bit = 9,
660                 },
661                 {.name = "REQ_ORD_TYPE",
662                  .desc = "Request is an ordered type",
663                  .bit = 10,
664                 },
665                 {.name = "MEM_TYPE0",
666                  .desc = "Along with MEM_TYPE1 and MEM_TYPE2, "
667                          "memory type encodings are: 0 - UC, "
668                          "1 - USWC, 4- WT, 5 - WP, 6 - WB",
669                  .bit = 11,
670                 },
671                 {.name = "MEM_TYPE1",
672                  .desc = "Along with MEM_TYPE0 and MEM_TYPE2, "
673                          "memory type encodings are: 0 - UC, "
674                          "1 - USWC, 4- WT, 5 - WP, 6 - WB",
675                  .bit = 12,
676                 },
677                 {.name = "MEM_TYPE2",
678                  .desc = "Along with MEM_TYPE0 and MEM_TYPE1, "
679                          "memory type encodings are: 0 - UC, "
680                          "1 - USWC, 4- WT, 5 - WP, 6 - WB",
681                  .bit = 13,
682                 },
683          },
684         },
685
686         /* 15 */
687         {.name = "SSE_input_assist",
688          .desc = "Number of times an assist is requested to handle problems "
689                  "with input operands for SSE/SSE2/SSE3 operations; most "
690                  "notably denormal source operands when the DAZ bit isn't set",
691          .event_select = 0x34,
692          .escr_select = 0x1,
693          .allowed_escrs = { 12, 35 },
694          .perf_code = P4_EVENT_SSE_INPUT_ASSIST,
695          .event_masks = {
696                 {.name = "ALL",
697                  .desc = "Count assists for SSE/SSE2/SSE3 uops",
698                  .bit = 15,
699                  .flags = NETBURST_FL_DFL,
700                 },
701          },
702         },
703
704         /* 16 */
705         {.name = "packed_SP_uop",
706          .desc = "Number of packed single-precision uops",
707          .event_select = 0x8,
708          .escr_select = 0x1,
709          .perf_code = P4_EVENT_PACKED_SP_UOP,
710          .allowed_escrs = { 12, 35 },
711          .event_masks = {
712                 {.name = "ALL",
713                  .desc = "Count all uops operating on packed "
714                          "single-precisions operands",
715                  .bit = 15,
716                  .flags = NETBURST_FL_DFL,
717                 },
718                 {.name = "TAG0",
719                  .desc = "Tag this event with tag bit 0 "
720                          "for retirement counting with execution_event",
721                  .bit = 16,
722                 },
723                 {.name = "TAG1",
724                  .desc = "Tag this event with tag bit 1 "
725                          "for retirement counting with execution_event",
726                  .bit = 17,
727                 },
728                 {.name = "TAG2",
729                  .desc = "Tag this event with tag bit 2 "
730                          "for retirement counting with execution_event",
731                  .bit = 18,
732                 },
733                 {.name = "TAG3",
734                  .desc = "Tag this event with tag bit 3 "
735                          "for retirement counting with execution_event",
736                  .bit = 19,
737                 },
738          },
739         },
740
741         /* 17 */
742         {.name = "packed_DP_uop",
743          .desc = "Number of packed double-precision uops",
744          .event_select = 0xC,
745          .escr_select = 0x1,
746          .allowed_escrs = { 12, 35 },
747          .perf_code = P4_EVENT_PACKED_DP_UOP,
748          .event_masks = {
749                 {.name = "ALL",
750                  .desc = "Count all uops operating on packed "
751                          "double-precisions operands",
752                  .bit = 15,
753                  .flags = NETBURST_FL_DFL,
754                 },
755                 {.name = "TAG0",
756                  .desc = "Tag this event with tag bit 0 "
757                          "for retirement counting with execution_event",
758                  .bit = 16,
759                 },
760                 {.name = "TAG1",
761                  .desc = "Tag this event with tag bit 1 "
762                          "for retirement counting with execution_event",
763                  .bit = 17,
764                 },
765                 {.name = "TAG2",
766                  .desc = "Tag this event with tag bit 2 "
767                          "for retirement counting with execution_event",
768                  .bit = 18,
769                 },
770                 {.name = "TAG3",
771                  .desc = "Tag this event with tag bit 3 "
772                          "for retirement counting with execution_event",
773                  .bit = 19,
774                 },
775          },
776         },
777
778         /* 18 */
779         {.name = "scalar_SP_uop",
780          .desc = "Number of scalar single-precision uops",
781          .event_select = 0xA,
782          .escr_select = 0x1,
783          .allowed_escrs = { 12, 35 },
784          .perf_code = P4_EVENT_SCALAR_SP_UOP,
785          .event_masks = {
786                 {.name = "ALL",
787                  .desc = "Count all uops operating on scalar "
788                          "single-precisions operands",
789                  .bit = 15,
790                  .flags = NETBURST_FL_DFL,
791                 },
792                 {.name = "TAG0",
793                  .desc = "Tag this event with tag bit 0 "
794                          "for retirement counting with execution_event",
795                  .bit = 16,
796                 },
797                 {.name = "TAG1",
798                  .desc = "Tag this event with tag bit 1 "
799                          "for retirement counting with execution_event",
800                  .bit = 17,
801                 },
802                 {.name = "TAG2",
803                  .desc = "Tag this event with tag bit 2 "
804                          "for retirement counting with execution_event",
805                  .bit = 18,
806                 },
807                 {.name = "TAG3",
808                  .desc = "Tag this event with tag bit 3 "
809                          "for retirement counting with execution_event",
810                  .bit = 19,
811                 },
812          },
813         },
814
815         /* 19 */
816         {.name = "scalar_DP_uop",
817          .desc = "Number of scalar double-precision uops",
818          .event_select = 0xE,
819          .escr_select = 0x1,
820          .allowed_escrs = { 12, 35 },
821          .perf_code = P4_EVENT_SCALAR_DP_UOP,
822          .event_masks = {
823                 {.name = "ALL",
824                  .desc = "Count all uops operating on scalar "
825                          "double-precisions operands",
826                  .bit = 15,
827                  .flags = NETBURST_FL_DFL,
828                 },
829                 {.name = "TAG0",
830                  .desc = "Tag this event with tag bit 0 "
831                          "for retirement counting with execution_event",
832                  .bit = 16,
833                 },
834                 {.name = "TAG1",
835                  .desc = "Tag this event with tag bit 1 "
836                          "for retirement counting with execution_event",
837                  .bit = 17,
838                 },
839                 {.name = "TAG2",
840                  .desc = "Tag this event with tag bit 2 "
841                          "for retirement counting with execution_event",
842                  .bit = 18,
843                 },
844                 {.name = "TAG3",
845                  .desc = "Tag this event with tag bit 3 "
846                          "for retirement counting with execution_event",
847                  .bit = 19,
848                 },
849          },
850         },
851
852         /* 20 */
853         {.name = "64bit_MMX_uop",
854          .desc = "Number of MMX instructions which "
855                  "operate on 64-bit SIMD operands",
856          .event_select = 0x2,
857          .escr_select = 0x1,
858          .allowed_escrs = { 12, 35 },
859          .perf_code = P4_EVENT_64BIT_MMX_UOP,
860          .event_masks = {
861                 {.name = "ALL",
862                  .desc = "Count all uops operating on 64-bit SIMD integer "
863                          "operands in memory or MMX registers",
864                  .bit = 15,
865                  .flags = NETBURST_FL_DFL,
866                 },
867                 {.name = "TAG0",
868                  .desc = "Tag this event with tag bit 0 "
869                          "for retirement counting with execution_event",
870                  .bit = 16,
871                 },
872                 {.name = "TAG1",
873                  .desc = "Tag this event with tag bit 1 "
874                          "for retirement counting with execution_event",
875                  .bit = 17,
876                 },
877                 {.name = "TAG2",
878                  .desc = "Tag this event with tag bit 2 "
879                          "for retirement counting with execution_event",
880                  .bit = 18,
881                 },
882                 {.name = "TAG3",
883                  .desc = "Tag this event with tag bit 3 "
884                          "for retirement counting with execution_event",
885                  .bit = 19,
886                 },
887          },
888         },
889
890         /* 21 */
891         {.name = "128bit_MMX_uop",
892          .desc = "Number of MMX instructions which "
893                  "operate on 128-bit SIMD operands",
894          .event_select = 0x1A,
895          .escr_select = 0x1,
896          .allowed_escrs = { 12, 35 },
897          .perf_code = P4_EVENT_128BIT_MMX_UOP,
898          .event_masks = {
899                 {.name = "ALL",
900                  .desc = "Count all uops operating on 128-bit SIMD integer "
901                          "operands in memory or MMX registers",
902                  .bit = 15,
903                  .flags = NETBURST_FL_DFL,
904                 },
905                 {.name = "TAG0",
906                  .desc = "Tag this event with tag bit 0 "
907                          "for retirement counting with execution_event",
908                  .bit = 16,
909                 },
910                 {.name = "TAG1",
911                  .desc = "Tag this event with tag bit 1 "
912                          "for retirement counting with execution_event",
913                  .bit = 17,
914                 },
915                 {.name = "TAG2",
916                  .desc = "Tag this event with tag bit 2 "
917                          "for retirement counting with execution_event",
918                  .bit = 18,
919                 },
920                 {.name = "TAG3",
921                  .desc = "Tag this event with tag bit 3 "
922                          "for retirement counting with execution_event",
923                  .bit = 19,
924                 },
925          },
926         },
927
928         /* 22 */
929         {.name = "x87_FP_uop",
930          .desc = "Number of x87 floating-point uops",
931          .event_select = 0x4,
932          .escr_select = 0x1,
933          .allowed_escrs = { 12, 35 },
934          .perf_code = P4_EVENT_X87_FP_UOP,
935          .event_masks = {
936                 {.name = "ALL",
937                  .desc = "Count all x87 FP uops",
938                  .bit = 15,
939                  .flags = NETBURST_FL_DFL,
940                 },
941                 {.name = "TAG0",
942                  .desc = "Tag this event with tag bit 0 "
943                          "for retirement counting with execution_event",
944                  .bit = 16,
945                 },
946                 {.name = "TAG1",
947                  .desc = "Tag this event with tag bit 1 "
948                          "for retirement counting with execution_event",
949                  .bit = 17,
950                 },
951                 {.name = "TAG2",
952                  .desc = "Tag this event with tag bit 2 "
953                          "for retirement counting with execution_event",
954                  .bit = 18,
955                 },
956                 {.name = "TAG3",
957                  .desc = "Tag this event with tag bit 3 "
958                          "for retirement counting with execution_event",
959                  .bit = 19,
960                 },
961          },
962         },
963
964         /* 23 */
965         {.name = "TC_misc",
966          .desc = "Miscellaneous events detected by the TC. The counter will "
967                  "count twice for each occurrence",
968          .event_select = 0x6,
969          .escr_select = 0x1,
970          .allowed_escrs = { 9, 32 },
971          .perf_code = P4_EVENT_TC_MISC,
972          .event_masks = {
973                 {.name = "FLUSH",
974                  .desc = "Number of flushes",
975                  .bit = 4,
976                  .flags = NETBURST_FL_DFL,
977                 },
978          },
979         },
980
981         /* 24 */
982         {.name = "global_power_events",
983          .desc = "Counts the time during which a processor is not stopped",
984          .event_select = 0x13,
985          .escr_select = 0x6,
986          .allowed_escrs = { 6, 29 },
987          .perf_code = P4_EVENT_GLOBAL_POWER_EVENTS,
988          .event_masks = {
989                 {.name = "RUNNING",
990                  .desc = "The processor is active (includes the "
991                          "handling of HLT STPCLK and throttling",
992                  .bit = 0,
993                  .flags = NETBURST_FL_DFL,
994                 },
995          },
996         },
997
998         /* 25 */
999         {.name = "tc_ms_xfer",
1000          .desc = "Number of times that uop delivery changed from TC to MS ROM",
1001          .event_select = 0x5,
1002          .escr_select = 0x0,
1003          .allowed_escrs = { 8, 31 },
1004          .perf_code = P4_EVENT_TC_MS_XFER,
1005          .event_masks = {
1006                 {.name = "CISC",
1007                  .desc = "A TC to MS transfer occurred",
1008                  .bit = 0,
1009                  .flags = NETBURST_FL_DFL,
1010                 },
1011          },
1012         },
1013
1014         /* 26 */
1015         {.name = "uop_queue_writes",
1016          .desc = "Number of valid uops written to the uop queue",
1017          .event_select = 0x9,
1018          .escr_select = 0x0,
1019          .allowed_escrs = { 8, 31 },
1020          .perf_code = P4_EVENT_UOP_QUEUE_WRITES,
1021          .event_masks = {
1022                 {.name = "FROM_TC_BUILD",
1023                  .desc = "The uops being written are from TC build mode",
1024                  .bit = 0,
1025                 },
1026                 {.name = "FROM_TC_DELIVER",
1027                  .desc = "The uops being written are from TC deliver mode",
1028                  .bit = 1,
1029                 },
1030                 {.name = "FROM_ROM",
1031                  .desc = "The uops being written are from microcode ROM",
1032                  .bit = 2,
1033                 },
1034          },
1035         },
1036
1037         /* 27 */
1038         {.name = "retired_mispred_branch_type",
1039          .desc = "Number of retiring mispredicted branches by type",
1040          .event_select = 0x5,
1041          .escr_select = 0x2,
1042          .allowed_escrs = { 10, 33 },
1043          .perf_code = P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE,
1044          .event_masks = {
1045                 {.name = "CONDITIONAL",
1046                  .desc = "Conditional jumps",
1047                  .bit = 1,
1048                 },
1049                 {.name = "CALL",
1050                  .desc = "Indirect call branches",
1051                  .bit = 2,
1052                 },
1053                 {.name = "RETURN",
1054                  .desc = "Return branches",
1055                  .bit = 3,
1056                 },
1057                 {.name = "INDIRECT",
1058                  .desc = "Returns, indirect calls, or indirect jumps",
1059                  .bit = 4,
1060                 },
1061          },
1062         },
1063
1064         /* 28 */
1065         {.name = "retired_branch_type",
1066          .desc = "Number of retiring branches by type",
1067          .event_select = 0x4,
1068          .escr_select = 0x2,
1069          .allowed_escrs = { 10, 33 },
1070          .perf_code = P4_EVENT_RETIRED_BRANCH_TYPE,
1071          .event_masks = {
1072                 {.name = "CONDITIONAL",
1073                  .desc = "Conditional jumps",
1074                  .bit = 1,
1075                 },
1076                 {.name = "CALL",
1077                  .desc = "Indirect call branches",
1078                  .bit = 2,
1079                 },
1080                 {.name = "RETURN",
1081                  .desc = "Return branches",
1082                  .bit = 3,
1083                 },
1084                 {.name = "INDIRECT",
1085                  .desc = "Returns, indirect calls, or indirect jumps",
1086                  .bit = 4,
1087                 },
1088          },
1089         },
1090
1091         /* 29 */
1092         {.name = "resource_stall",
1093          .desc = "Occurrences of latency or stalls in the Allocator",
1094          .event_select = 0x1,
1095          .escr_select = 0x1,
1096          .allowed_escrs = { 17, 40 },
1097          .perf_code = P4_EVENT_RESOURCE_STALL,
1098          .event_masks = {
1099                 {.name = "SBFULL",
1100                  .desc = "A stall due to lack of store buffers",
1101                  .bit = 5,
1102                  .flags = NETBURST_FL_DFL,
1103                 },
1104          },
1105         },
1106
1107         /* 30 */
1108         {.name = "WC_Buffer",
1109          .desc = "Number of Write Combining Buffer operations",
1110          .event_select = 0x5,
1111          .escr_select = 0x5,
1112          .allowed_escrs = { 15, 38 },
1113          .perf_code = P4_EVENT_WC_BUFFER,
1114          .event_masks = {
1115                 {.name = "WCB_EVICTS",
1116                  .desc = "WC Buffer evictions of all causes",
1117                  .bit = 0,
1118                 },
1119                 {.name = "WCB_FULL_EVICT",
1120                  .desc = "WC Buffer eviction; no WC buffer is available",
1121                  .bit = 1,
1122                 },
1123          },
1124         },
1125
1126         /* 31 */
1127         {.name = "b2b_cycles",
1128          .desc = "Number of back-to-back bus cycles",
1129          .event_select = 0x16,
1130          .escr_select = 0x3,
1131          .allowed_escrs = { 6, 29 },
1132          .perf_code = P4_EVENT_B2B_CYCLES,
1133          .event_masks = {
1134                 {.name = "BIT1",
1135                  .desc = "bit 1",
1136                  .bit = 1,
1137                 },
1138                 {.name = "BIT2",
1139                  .desc = "bit 2",
1140                  .bit = 2,
1141                 },
1142                 {.name = "BIT3",
1143                  .desc = "bit 3",
1144                  .bit = 3,
1145                 },
1146                 {.name = "BIT4",
1147                  .desc = "bit 4",
1148                  .bit = 4,
1149                 },
1150                 {.name = "BIT5",
1151                  .desc = "bit 5",
1152                  .bit = 4,
1153                 },
1154                 {.name = "BIT6",
1155                  .desc = "bit 6",
1156                  .bit = 4,
1157                 },
1158          },
1159         },
1160         /* 32 */
1161         {.name = "bnr",
1162          .desc = "Number of bus-not-ready conditions",
1163          .event_select = 0x8,
1164          .escr_select = 0x3,
1165          .allowed_escrs = { 6, 29 },
1166          .perf_code = P4_EVENT_BNR,
1167          .event_masks = {
1168                 {.name = "BIT0",
1169                  .desc = "bit 0",
1170                  .bit = 0,
1171                 },
1172                 {.name = "BIT1",
1173                  .desc = "bit 1",
1174                  .bit = 1,
1175                 },
1176                 {.name = "BIT2",
1177                  .desc = "bit 2",
1178                  .bit = 2,
1179                 },
1180          },
1181         },
1182
1183         /* 33 */
1184         {.name = "snoop",
1185          .desc = "Number of snoop hit modified bus traffic",
1186          .event_select = 0x6,
1187          .escr_select = 0x3,
1188          .allowed_escrs = { 6, 29 },
1189          .perf_code = P4_EVENT_SNOOP,
1190          .event_masks = {
1191                 {.name = "BIT2",
1192                  .desc = "bit 2",
1193                  .bit = 2,
1194                 },
1195                 {.name = "BIT6",
1196                  .desc = "bit 6",
1197                  .bit = 6,
1198                 },
1199                 {.name = "BIT7",
1200                  .desc = "bit 7",
1201                  .bit = 7,
1202                 },
1203          },
1204         },
1205
1206         /* 34 */
1207         {.name = "response",
1208          .desc = "Count of different types of responses",
1209          .event_select = 0x4,
1210          .escr_select = 0x3,
1211          .allowed_escrs = { 6, 29 },
1212          .perf_code = P4_EVENT_RESPONSE,
1213          .event_masks = {
1214                 {.name = "BIT1",
1215                  .desc = "bit 1",
1216                  .bit = 1,
1217                 },
1218                 {.name = "BIT2",
1219                  .desc = "bit 2",
1220                  .bit = 2,
1221                 },
1222                 {.name = "BIT8",
1223                  .desc = "bit 8",
1224                  .bit = 8,
1225                 },
1226                 {.name = "BIT9",
1227                  .desc = "bit 9",
1228                  .bit = 9,
1229                 },
1230          },
1231         },
1232
1233         /* 35 */
1234         {.name = "front_end_event",
1235          .desc = "Number of retirements of tagged uops which are specified "
1236                  "through the front-end tagging mechanism",
1237          .event_select = 0x8,
1238          .escr_select = 0x5,
1239          .allowed_escrs = { 21, 43 },
1240          .perf_code = P4_EVENT_FRONT_END_EVENT,
1241          .event_masks = {
1242                 {.name = "NBOGUS",
1243                  .desc = "The marked uops are not bogus",
1244                  .bit = 0,
1245                 },
1246                 {.name = "BOGUS",
1247                  .desc = "The marked uops are bogus",
1248                  .bit = 1,
1249                 },
1250          },
1251         },
1252
1253         /* 36 */
1254         {.name = "execution_event",
1255          .desc = "Number of retirements of tagged uops which are specified "
1256                  "through the execution tagging mechanism. The event-mask "
1257                  "allows from one to four types of uops to be tagged",
1258          .event_select = 0xC,
1259          .escr_select = 0x5,
1260          .allowed_escrs = { 21, 43 },
1261          .perf_code = P4_EVENT_EXECUTION_EVENT,
1262          .event_masks = {
1263                 {.name = "NBOGUS0",
1264                  .desc = "The marked uops are not bogus",
1265                  .bit = 0,
1266                 },
1267                 {.name = "NBOGUS1",
1268                  .desc = "The marked uops are not bogus",
1269                  .bit = 1,
1270                 },
1271                 {.name = "NBOGUS2",
1272                  .desc = "The marked uops are not bogus",
1273                  .bit = 2,
1274                 },
1275                 {.name = "NBOGUS3",
1276                  .desc = "The marked uops are not bogus",
1277                  .bit = 3,
1278                 },
1279                 {.name = "BOGUS0",
1280                  .desc = "The marked uops are bogus",
1281                  .bit = 4,
1282                 },
1283                 {.name = "BOGUS1",
1284                  .desc = "The marked uops are bogus",
1285                  .bit = 5,
1286                 },
1287                 {.name = "BOGUS2",
1288                  .desc = "The marked uops are bogus",
1289                  .bit = 6,
1290                 },
1291                 {.name = "BOGUS3",
1292                  .desc = "The marked uops are bogus",
1293                  .bit = 7,
1294                 },
1295          },
1296         },
1297
1298         /* 37 */
1299         {.name = "replay_event",
1300          .desc = "Number of retirements of tagged uops which are specified "
1301                  "through the replay tagging mechanism",
1302          .event_select = 0x9,
1303          .escr_select = 0x5,
1304          .allowed_escrs = { 21, 43 },
1305          .perf_code = P4_EVENT_REPLAY_EVENT,
1306          .event_masks = {
1307                 {.name = "NBOGUS",
1308                  .desc = "The marked uops are not bogus",
1309                  .bit = 0,
1310                 },
1311                 {.name = "BOGUS",
1312                  .desc = "The marked uops are bogus",
1313                  .bit = 1,
1314                 },
1315                 {.name = "L1_LD_MISS",
1316                  .desc = "Virtual mask for L1 cache load miss replays",
1317                  .bit = 2,
1318                 },
1319                 {.name = "L2_LD_MISS",
1320                  .desc = "Virtual mask for L2 cache load miss replays",
1321                  .bit = 3,
1322                 },
1323                 {.name = "DTLB_LD_MISS",
1324                  .desc = "Virtual mask for DTLB load miss replays",
1325                  .bit = 4,
1326                 },
1327                 {.name = "DTLB_ST_MISS",
1328                  .desc = "Virtual mask for DTLB store miss replays",
1329                  .bit = 5,
1330                 },
1331                 {.name = "DTLB_ALL_MISS",
1332                  .desc = "Virtual mask for all DTLB miss replays",
1333                  .bit = 6,
1334                 },
1335                 {.name = "BR_MSP",
1336                  .desc = "Virtual mask for tagged mispredicted branch replays",
1337                  .bit = 7,
1338                 },
1339                 {.name = "MOB_LD_REPLAY",
1340                  .desc = "Virtual mask for MOB load replays",
1341                  .bit = 8,
1342                 },
1343                 {.name = "SP_LD_RET",
1344                  .desc = "Virtual mask for split load replays. Use with load_port_replay event",
1345                  .bit = 9,
1346                 },
1347                 {.name = "SP_ST_RET",
1348                  .desc = "Virtual mask for split store replays. Use with store_port_replay event",
1349                  .bit = 10,
1350                 },
1351          },
1352         },
1353
1354         /* 38 */
1355         {.name = "instr_retired",
1356          .desc = "Number of instructions retired during a clock cycle",
1357          .event_select = 0x2,
1358          .escr_select = 0x4,
1359          .allowed_escrs = { 20, 42 },
1360          .perf_code = P4_EVENT_INSTR_RETIRED,
1361          .event_masks = {
1362                 {.name = "NBOGUSNTAG",
1363                  .desc = "Non-bogus instructions that are not tagged",
1364                  .bit = 0,
1365                 },
1366                 {.name = "NBOGUSTAG",
1367                  .desc = "Non-bogus instructions that are tagged",
1368                  .bit = 1,
1369                 },
1370                 {.name = "BOGUSNTAG",
1371                  .desc = "Bogus instructions that are not tagged",
1372                  .bit = 2,
1373                 },
1374                 {.name = "BOGUSTAG",
1375                  .desc = "Bogus instructions that are tagged",
1376                  .bit = 3,
1377                 },
1378          },
1379         },
1380
1381         /* 39 */
1382         {.name = "uops_retired",
1383          .desc = "Number of uops retired during a clock cycle",
1384          .event_select = 0x1,
1385          .escr_select = 0x4,
1386          .allowed_escrs = { 20, 42 },
1387          .perf_code = P4_EVENT_UOPS_RETIRED,
1388          .event_masks = {
1389                 {.name = "NBOGUS",
1390                  .desc = "The marked uops are not bogus",
1391                  .bit = 0,
1392                 },
1393                 {.name = "BOGUS",
1394                  .desc = "The marked uops are bogus",
1395                  .bit = 1,
1396                 },
1397          },
1398         },
1399
1400         /* 40 */
1401         {.name = "uops_type",
1402          .desc = "This event is used in conjunction with with the front-end "
1403                  "mechanism to tag load and store uops",
1404          .event_select = 0x2,
1405          .escr_select = 0x2,
1406          .allowed_escrs = { 18, 41 },
1407          .perf_code = P4_EVENT_UOP_TYPE,
1408          .event_masks = {
1409                 {.name = "TAGLOADS",
1410                  .desc = "The uop is a load operation",
1411                  .bit = 1,
1412                 },
1413                 {.name = "TAGSTORES",
1414                  .desc = "The uop is a store operation",
1415                  .bit = 2,
1416                 },
1417          },
1418         },
1419
1420         /* 41 */
1421         {.name = "branch_retired",
1422          .desc = "Number of retirements of a branch",
1423          .event_select = 0x6,
1424          .escr_select = 0x5,
1425          .allowed_escrs = { 21, 43 },
1426          .perf_code = P4_EVENT_BRANCH_RETIRED,
1427          .event_masks = {
1428                 {.name = "MMNP",
1429                  .desc = "Branch not-taken predicted",
1430                  .bit = 0,
1431                 },
1432                 {.name = "MMNM",
1433                  .desc = "Branch not-taken mispredicted",
1434                  .bit = 1,
1435                 },
1436                 {.name = "MMTP",
1437                  .desc = "Branch taken predicted",
1438                  .bit = 2,
1439                 },
1440                 {.name = "MMTM",
1441                  .desc = "Branch taken mispredicted",
1442                  .bit = 3,
1443                 },
1444          },
1445         },
1446
1447         /* 42 */
1448         {.name = "mispred_branch_retired",
1449          .desc = "Number of retirements of mispredicted "
1450                  "IA-32 branch instructions",
1451          .event_select = 0x3,
1452          .escr_select = 0x4,
1453          .allowed_escrs = { 20, 42 },
1454          .perf_code = P4_EVENT_MISPRED_BRANCH_RETIRED,
1455          .event_masks = {
1456                 {.name = "BOGUS",
1457                  .desc = "The retired instruction is not bogus",
1458                  .bit = 0,
1459                  .flags = NETBURST_FL_DFL,
1460                 },
1461          },
1462         },
1463
1464         /* 43 */
1465         {.name = "x87_assist",
1466          .desc = "Number of retirements of x87 instructions that required "
1467                  "special handling",
1468          .event_select = 0x3,
1469          .escr_select = 0x5,
1470          .allowed_escrs = { 21, 43 },
1471          .perf_code = P4_EVENT_X87_ASSIST,
1472          .event_masks = {
1473                 {.name = "FPSU",
1474                  .desc = "Handle FP stack underflow",
1475                  .bit = 0,
1476                 },
1477                 {.name = "FPSO",
1478                  .desc = "Handle FP stack overflow",
1479                  .bit = 1,
1480                 },
1481                 {.name = "POAO",
1482                  .desc = "Handle x87 output overflow",
1483                  .bit = 2,
1484                 },
1485                 {.name = "POAU",
1486                  .desc = "Handle x87 output underflow",
1487                  .bit = 3,
1488                 },
1489                 {.name = "PREA",
1490                  .desc = "Handle x87 input assist",
1491                  .bit = 4,
1492                 },
1493          },
1494         },
1495
1496         /* 44 */
1497         {.name = "machine_clear",
1498          .desc = "Number of occurrences when the entire "
1499                  "pipeline of the machine is cleared",
1500          .event_select = 0x2,
1501          .escr_select = 0x5,
1502          .allowed_escrs = { 21, 43 },
1503          .perf_code = P4_EVENT_MACHINE_CLEAR,
1504          .event_masks = {
1505                 {.name = "CLEAR",
1506                  .desc = "Counts for a portion of the many cycles while the "
1507                          "machine is cleared for any cause. Use edge-"
1508                          "triggering for this bit only to get a count of "
1509                          "occurrences versus a duration",
1510                  .bit = 0,
1511                 },
1512                 {.name = "MOCLEAR",
1513                  .desc = "Increments each time the machine is cleared due to "
1514                          "memory ordering issues",
1515                  .bit = 2,
1516                 },
1517                 {.name = "SMCLEAR",
1518                  .desc = "Increments each time the machine is cleared due to "
1519                          "self-modifying code issues",
1520                  .bit = 6,
1521                 },
1522          },
1523         },
1524
1525         /* 45 */
1526         {.name = "instr_completed",
1527          .desc = "Instructions that have completed and "
1528                  "retired during a clock cycle (models 3, 4, 6 only)",
1529          .event_select = 0x7,
1530          .escr_select = 0x4,
1531          .allowed_escrs = { 21, 42 },
1532          .perf_code = P4_EVENT_INSTR_COMPLETED,
1533          .event_masks = {
1534                 {.name = "NBOGUS",
1535                  .desc = "Non-bogus instructions",
1536                  .bit = 0,
1537                 },
1538                 {.name = "BOGUS",
1539                  .desc = "Bogus instructions",
1540                  .bit = 1,
1541                 },
1542          },
1543         },
1544 };
1545 #define PME_REPLAY_EVENT    37
1546 #define NETBURST_EVENT_COUNT (sizeof(netburst_events)/sizeof(netburst_entry_t))
1547
1548 #endif
1549