vmm: Move the vmcall overrides to the VM struct
[akaros.git] / user / perfmon / events / intel_ivbep_unc_pcu_events.h
1 /*
2  * Copyright (c) 2014 Google Inc. All rights reserved
3  * Contributed by Stephane Eranian <eranian@gmail.com>
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a copy
6  * of this software and associated documentation files (the "Software"), to deal
7  * in the Software without restriction, including without limitation the rights
8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
9  * of the Software, and to permit persons to whom the Software is furnished to do so,
10  * subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in all
13  * copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
16  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
17  * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
18  * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
19  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
20  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * This file is part of libpfm, a performance monitoring support library for
23  * applications on Linux.
24  *
25  * PMU: ivbep_unc_pcu (Intel IvyBridge-EP PCU uncore)
26  */
27
28 static const intel_x86_umask_t ivbep_unc_p_power_state_occupancy[]={
29   { .uname = "CORES_C0",
30     .udesc  = "Counts number of cores in C0",
31     .ucode  = 0x4000,
32     .uflags = INTEL_X86_NCOMBO,
33   },
34   { .uname = "CORES_C3",
35     .udesc  = "Counts number of cores in C3",
36     .ucode  = 0x8000,
37     .uflags = INTEL_X86_NCOMBO,
38   },
39   { .uname = "CORES_C6",
40     .udesc  = "Counts number of cores in C6",
41     .ucode  = 0xc000,
42     .uflags = INTEL_X86_NCOMBO,
43   },
44 };
45
46 static const intel_x86_umask_t ivbep_unc_p_occupancy_counters[]={
47   { .uname = "C0",
48     .udesc  = "Counts number of cores in C0",
49     .ucode  = 0x0100,
50     .uflags = INTEL_X86_NCOMBO,
51   },
52   { .uname = "C3",
53     .udesc  = "Counts number of cores in C3",
54     .ucode  = 0x0200,
55     .uflags = INTEL_X86_NCOMBO,
56   },
57   { .uname = "C6",
58     .udesc  = "Counts number of cores in C6",
59     .ucode  = 0x0300,
60     .uflags = INTEL_X86_NCOMBO,
61   },
62 };
63
64 static const intel_x86_entry_t intel_ivbep_unc_p_pe[]={
65   { .name   = "UNC_P_CLOCKTICKS",
66     .desc   = "PCU Uncore clockticks",
67     .modmsk = IVBEP_UNC_PCU_ATTRS,
68     .cntmsk = 0xf,
69     .code = 0x00,
70   },
71   { .name = "UNC_P_CORE0_TRANSITION_CYCLES",
72     .desc = "Core 0 C State Transition Cycles",
73     .code = 0x70,
74     .cntmsk = 0xf,
75     .modmsk = IVBEP_UNC_PCU_ATTRS,
76   },
77   { .name = "UNC_P_CORE1_TRANSITION_CYCLES",
78     .desc = "Core 1 C State Transition Cycles",
79     .code = 0x71,
80     .cntmsk = 0xf,
81     .modmsk = IVBEP_UNC_PCU_ATTRS,
82   },
83   { .name = "UNC_P_CORE2_TRANSITION_CYCLES",
84     .desc = "Core 2 C State Transition Cycles",
85     .code = 0x72,
86     .cntmsk = 0xf,
87     .modmsk = IVBEP_UNC_PCU_ATTRS,
88   },
89   { .name = "UNC_P_CORE3_TRANSITION_CYCLES",
90     .desc = "Core 3 C State Transition Cycles",
91     .code = 0x73,
92     .cntmsk = 0xf,
93     .modmsk = IVBEP_UNC_PCU_ATTRS,
94   },
95   { .name = "UNC_P_CORE4_TRANSITION_CYCLES",
96     .desc = "Core 4 C State Transition Cycles",
97     .code = 0x74,
98     .cntmsk = 0xf,
99     .modmsk = IVBEP_UNC_PCU_ATTRS,
100   },
101   { .name = "UNC_P_CORE5_TRANSITION_CYCLES",
102     .desc = "Core 5 C State Transition Cycles",
103     .code = 0x75,
104     .cntmsk = 0xf,
105     .modmsk = IVBEP_UNC_PCU_ATTRS,
106   },
107   { .name = "UNC_P_CORE6_TRANSITION_CYCLES",
108     .desc = "Core 6 C State Transition Cycles",
109     .code = 0x76,
110     .cntmsk = 0xf,
111     .modmsk = IVBEP_UNC_PCU_ATTRS,
112   },
113   { .name = "UNC_P_CORE7_TRANSITION_CYCLES",
114     .desc = "Core 7 C State Transition Cycles",
115     .code = 0x77,
116     .cntmsk = 0xf,
117     .modmsk = IVBEP_UNC_PCU_ATTRS,
118   },
119   { .name = "UNC_P_CORE8_TRANSITION_CYCLES",
120     .desc = "Core 8 C State Transition Cycles",
121     .code = 0x78,
122     .cntmsk = 0xf,
123     .modmsk = IVBEP_UNC_PCU_ATTRS,
124   },
125   { .name = "UNC_P_CORE9_TRANSITION_CYCLES",
126     .desc = "Core 9 C State Transition Cycles",
127     .code = 0x79,
128     .cntmsk = 0xf,
129     .modmsk = IVBEP_UNC_PCU_ATTRS,
130   },
131   { .name = "UNC_P_CORE10_TRANSITION_CYCLES",
132     .desc = "Core 10 C State Transition Cycles",
133     .code = 0x7a,
134     .cntmsk = 0xf,
135     .modmsk = IVBEP_UNC_PCU_ATTRS,
136   },
137   { .name = "UNC_P_CORE11_TRANSITION_CYCLES",
138     .desc = "Core 11 C State Transition Cycles",
139     .code = 0x7b,
140     .cntmsk = 0xf,
141     .modmsk = IVBEP_UNC_PCU_ATTRS,
142   },
143   { .name = "UNC_P_CORE12_TRANSITION_CYCLES",
144     .desc = "Core 12 C State Transition Cycles",
145     .code = 0x7c,
146     .cntmsk = 0xf,
147     .modmsk = IVBEP_UNC_PCU_ATTRS,
148   },
149   { .name = "UNC_P_CORE13_TRANSITION_CYCLES",
150     .desc = "Core 13 C State Transition Cycles",
151     .code = 0x7d,
152     .cntmsk = 0xf,
153     .modmsk = IVBEP_UNC_PCU_ATTRS,
154   },
155   { .name = "UNC_P_CORE14_TRANSITION_CYCLES",
156     .desc = "Core 14 C State Transition Cycles",
157     .code = 0x7e,
158     .cntmsk = 0xf,
159     .modmsk = IVBEP_UNC_PCU_ATTRS,
160   },
161   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE0",
162     .desc = "Deep C state rejection Core 0",
163     .code = 0x17 | (1ULL << 21), /* sel_ext */
164     .cntmsk = 0xf,
165     .modmsk = IVBEP_UNC_PCU_ATTRS,
166   },
167   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE1",
168     .desc = "Deep C state rejection Core 1",
169     .code = 0x18 | (1ULL << 21), /* sel_ext */
170     .cntmsk = 0xf,
171     .modmsk = IVBEP_UNC_PCU_ATTRS,
172   },
173   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE2",
174     .desc = "Deep C state rejection Core 2",
175     .code = 0x19 | (1ULL << 21), /* sel_ext */
176     .cntmsk = 0xf,
177     .modmsk = IVBEP_UNC_PCU_ATTRS,
178   },
179   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE3",
180     .desc = "Deep C state rejection Core 3",
181     .code = 0x1a | (1ULL << 21), /* sel_ext */
182     .cntmsk = 0xf,
183     .modmsk = IVBEP_UNC_PCU_ATTRS,
184   },
185   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE4",
186     .desc = "Deep C state rejection Core 4",
187     .code = 0x1b | (1ULL << 21), /* sel_ext */
188     .cntmsk = 0xf,
189     .modmsk = IVBEP_UNC_PCU_ATTRS,
190   },
191   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE5",
192     .desc = "Deep C state rejection Core 5",
193     .code = 0x1c | (1ULL << 21), /* sel_ext */
194     .cntmsk = 0xf,
195     .modmsk = IVBEP_UNC_PCU_ATTRS,
196   },
197   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE6",
198     .desc = "Deep C state rejection Core 6",
199     .code = 0x1d | (1ULL << 21), /* sel_ext */
200     .cntmsk = 0xf,
201     .modmsk = IVBEP_UNC_PCU_ATTRS,
202   },
203   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE7",
204     .desc = "Deep C state rejection Core 7",
205     .code = 0x1e | (1ULL << 21), /* sel_ext */
206     .cntmsk = 0xf,
207     .modmsk = IVBEP_UNC_PCU_ATTRS,
208   },
209   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE8",
210     .desc = "Deep C state rejection Core 8",
211     .code = 0x1f | (1ULL << 21), /* sel_ext */
212     .cntmsk = 0xf,
213     .modmsk = IVBEP_UNC_PCU_ATTRS,
214   },
215   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE9",
216     .desc = "Deep C state rejection Core 9",
217     .code = 0x20 | (1ULL << 21), /* sel_ext */
218     .cntmsk = 0xf,
219     .modmsk = IVBEP_UNC_PCU_ATTRS,
220   },
221   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE10",
222     .desc = "Deep C state rejection Core 10",
223     .code = 0x21 | (1ULL << 21), /* sel_ext */
224     .cntmsk = 0xf,
225     .modmsk = IVBEP_UNC_PCU_ATTRS,
226   },
227   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE11",
228     .desc = "Deep C state rejection Core 11",
229     .code = 0x22 | (1ULL << 21), /* sel_ext */
230     .cntmsk = 0xf,
231     .modmsk = IVBEP_UNC_PCU_ATTRS,
232   },
233   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE12",
234     .desc = "Deep C state rejection Core 12",
235     .code = 0x23 | (1ULL << 21), /* sel_ext */
236     .cntmsk = 0xf,
237     .modmsk = IVBEP_UNC_PCU_ATTRS,
238   },
239   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE13",
240     .desc = "Deep C state rejection Core 13",
241     .code = 0x24 | (1ULL << 21), /* sel_ext */
242     .cntmsk = 0xf,
243     .modmsk = IVBEP_UNC_PCU_ATTRS,
244   },
245   { .name = "UNC_P_DELAYED_C_STATE_ABORT_CORE14",
246     .desc = "Deep C state rejection Core 14",
247     .code = 0x25 | (1ULL << 21), /* sel_ext */
248     .cntmsk = 0xf,
249     .modmsk = IVBEP_UNC_PCU_ATTRS,
250   },
251   { .name = "UNC_P_DEMOTIONS_CORE0",
252     .desc = "Core 0 C State Demotions",
253     .code = 0x1e,
254     .cntmsk = 0xf,
255     .modmsk = IVBEP_UNC_PCU_ATTRS,
256   },
257   { .name = "UNC_P_DEMOTIONS_CORE1",
258     .desc = "Core 1 C State Demotions",
259     .code = 0x1f,
260     .cntmsk = 0xf,
261     .modmsk = IVBEP_UNC_PCU_ATTRS,
262   },
263   { .name = "UNC_P_DEMOTIONS_CORE2",
264     .desc = "Core 2 C State Demotions",
265     .code = 0x20,
266     .cntmsk = 0xf,
267     .modmsk = IVBEP_UNC_PCU_ATTRS,
268   },
269   { .name = "UNC_P_DEMOTIONS_CORE3",
270     .desc = "Core 3 C State Demotions",
271     .code = 0x21,
272     .cntmsk = 0xf,
273     .modmsk = IVBEP_UNC_PCU_ATTRS,
274   },
275   { .name = "UNC_P_DEMOTIONS_CORE4",
276     .desc = "Core 4 C State Demotions",
277     .code = 0x22,
278     .cntmsk = 0xf,
279     .modmsk = IVBEP_UNC_PCU_ATTRS,
280   },
281   { .name = "UNC_P_DEMOTIONS_CORE5",
282     .desc = "Core 5 C State Demotions",
283     .code = 0x23,
284     .cntmsk = 0xf,
285     .modmsk = IVBEP_UNC_PCU_ATTRS,
286   },
287   { .name = "UNC_P_DEMOTIONS_CORE6",
288     .desc = "Core 6 C State Demotions",
289     .code = 0x24,
290     .cntmsk = 0xf,
291     .modmsk = IVBEP_UNC_PCU_ATTRS,
292   },
293   { .name = "UNC_P_DEMOTIONS_CORE7",
294     .desc = "Core 7 C State Demotions",
295     .code = 0x25,
296     .cntmsk = 0xf,
297     .modmsk = IVBEP_UNC_PCU_ATTRS,
298   },
299   { .name = "UNC_P_DEMOTIONS_CORE8",
300     .desc = "Core 8 C State Demotions",
301     .code = 0x40,
302     .cntmsk = 0xf,
303     .modmsk = IVBEP_UNC_PCU_ATTRS,
304   },
305   { .name = "UNC_P_DEMOTIONS_CORE9",
306     .desc = "Core 9 C State Demotions",
307     .code = 0x41,
308     .cntmsk = 0xf,
309     .modmsk = IVBEP_UNC_PCU_ATTRS,
310   },
311   { .name = "UNC_P_DEMOTIONS_CORE10",
312     .desc = "Core 10 C State Demotions",
313     .code = 0x42,
314     .cntmsk = 0xf,
315     .modmsk = IVBEP_UNC_PCU_ATTRS,
316   },
317   { .name = "UNC_P_DEMOTIONS_CORE11",
318     .desc = "Core 11 C State Demotions",
319     .code = 0x43,
320     .cntmsk = 0xf,
321     .modmsk = IVBEP_UNC_PCU_ATTRS,
322   },
323   { .name = "UNC_P_DEMOTIONS_CORE12",
324     .desc = "Core 12 C State Demotions",
325     .code = 0x44,
326     .cntmsk = 0xf,
327     .modmsk = IVBEP_UNC_PCU_ATTRS,
328   },
329   { .name = "UNC_P_DEMOTIONS_CORE13",
330     .desc = "Core 13 C State Demotions",
331     .code = 0x45,
332     .cntmsk = 0xf,
333     .modmsk = IVBEP_UNC_PCU_ATTRS,
334   },
335   { .name = "UNC_P_DEMOTIONS_CORE14",
336     .desc = "Core 14 C State Demotions",
337     .code = 0x46,
338     .cntmsk = 0xf,
339     .modmsk = IVBEP_UNC_PCU_ATTRS,
340   },
341   { .name = "UNC_P_FREQ_BAND0_CYCLES",
342     .desc = "Frequency Residency",
343     .code = 0xb,
344     .cntmsk = 0xf,
345     .flags = INTEL_X86_NO_AUTOENCODE,
346     .modmsk = IVBEP_UNC_PCU_BAND_ATTRS,
347     .modmsk_req = _SNBEP_UNC_ATTR_FF,
348   },
349   { .name = "UNC_P_FREQ_BAND1_CYCLES",
350     .desc = "Frequency Residency",
351     .code = 0xc,
352     .cntmsk = 0xf,
353     .flags = INTEL_X86_NO_AUTOENCODE,
354     .modmsk = IVBEP_UNC_PCU_BAND_ATTRS,
355     .modmsk_req = _SNBEP_UNC_ATTR_FF,
356   },
357   { .name = "UNC_P_FREQ_BAND2_CYCLES",
358     .desc = "Frequency Residency",
359     .code = 0xd,
360     .cntmsk = 0xf,
361     .flags = INTEL_X86_NO_AUTOENCODE,
362     .modmsk = IVBEP_UNC_PCU_BAND_ATTRS,
363     .modmsk_req = _SNBEP_UNC_ATTR_FF,
364   },
365   { .name = "UNC_P_FREQ_BAND3_CYCLES",
366     .desc = "Frequency Residency",
367     .code = 0xe,
368     .cntmsk = 0xf,
369     .flags = INTEL_X86_NO_AUTOENCODE,
370     .modmsk = IVBEP_UNC_PCU_BAND_ATTRS,
371     .modmsk_req = _SNBEP_UNC_ATTR_FF,
372   },
373   { .name = "UNC_P_FREQ_MAX_CURRENT_CYCLES",
374     .desc = "Current Strongest Upper Limit Cycles",
375     .code = 0x7,
376     .cntmsk = 0xf,
377     .modmsk = IVBEP_UNC_PCU_ATTRS,
378   },
379   { .name = "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
380     .desc = "Thermal Strongest Upper Limit Cycles",
381     .code = 0x4,
382     .cntmsk = 0xf,
383     .modmsk = IVBEP_UNC_PCU_ATTRS,
384   },
385   { .name = "UNC_P_FREQ_MAX_OS_CYCLES",
386     .desc = "OS Strongest Upper Limit Cycles",
387     .code = 0x6,
388     .cntmsk = 0xf,
389     .modmsk = IVBEP_UNC_PCU_ATTRS,
390   },
391   { .name = "UNC_P_FREQ_MAX_POWER_CYCLES",
392     .desc = "Power Strongest Upper Limit Cycles",
393     .code = 0x5,
394     .cntmsk = 0xf,
395     .modmsk = IVBEP_UNC_PCU_ATTRS,
396   },
397   { .name = "UNC_P_FREQ_MIN_PERF_P_CYCLES",
398     .desc = "Perf P Limit Strongest Lower Limit Cycles",
399     .code = 0x02 | (1ULL << 21), /* sel_ext */
400     .cntmsk = 0xf,
401     .modmsk = IVBEP_UNC_PCU_ATTRS,
402   },
403
404   { .name = "UNC_P_FREQ_MIN_IO_P_CYCLES",
405     .desc = "IO P Limit Strongest Lower Limit Cycles",
406     .code = 0x61,
407     .cntmsk = 0xf,
408     .modmsk = IVBEP_UNC_PCU_ATTRS,
409   },
410   { .name = "UNC_P_FREQ_TRANS_CYCLES",
411     .desc = "Cycles spent changing Frequency",
412     .code = 0x60,
413     .cntmsk = 0xf,
414     .modmsk = IVBEP_UNC_PCU_ATTRS,
415   },
416   { .name = "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
417     .desc = "Memory Phase Shedding Cycles",
418     .code = 0x2f,
419     .cntmsk = 0xf,
420     .modmsk = IVBEP_UNC_PCU_ATTRS,
421   },
422   { .name = "UNC_P_PKG_C_EXIT_LATENCY",
423     .desc = "Package C state exit latency. Counts cycles the package is transitioning from C2 to C3",
424     .code = 0x26 | (1ULL << 21), /* sel_ext */
425     .cntmsk = 0xf,
426     .modmsk = IVBEP_UNC_PCU_ATTRS,
427   },
428   { .name = "UNC_P_POWER_STATE_OCCUPANCY",
429     .desc = "Number of cores in C0",
430     .code = 0x80,
431     .cntmsk = 0xf,
432     .ngrp = 1,
433     .modmsk = IVBEP_UNC_PCU_ATTRS,
434     .numasks = LIBPFM_ARRAY_SIZE(ivbep_unc_p_power_state_occupancy),
435     .umasks  = ivbep_unc_p_power_state_occupancy
436   },
437   { .name = "UNC_P_PROCHOT_EXTERNAL_CYCLES",
438     .desc = "External Prochot",
439     .code = 0xa,
440     .cntmsk = 0xf,
441     .modmsk = IVBEP_UNC_PCU_ATTRS,
442   },
443   { .name = "UNC_P_PROCHOT_INTERNAL_CYCLES",
444     .desc = "Internal Prochot",
445     .code = 0x9,
446     .cntmsk = 0xf,
447     .modmsk = IVBEP_UNC_PCU_ATTRS,
448   },
449   { .name = "UNC_P_TOTAL_TRANSITION_CYCLES",
450     .desc = "Total Core C State Transition Cycles",
451     .code = 0x63,
452     .cntmsk = 0xf,
453     .modmsk = IVBEP_UNC_PCU_ATTRS,
454   },
455   { .name = "UNC_P_VOLT_TRANS_CYCLES_CHANGE",
456     .desc = "Cycles Changing Voltage",
457     .code = 0x3,
458     .cntmsk = 0xf,
459     .modmsk = IVBEP_UNC_PCU_ATTRS,
460   },
461   { .name = "UNC_P_VOLT_TRANS_CYCLES_DECREASE",
462     .desc = "Cycles Decreasing Voltage",
463     .code = 0x2,
464     .cntmsk = 0xf,
465     .modmsk = IVBEP_UNC_PCU_ATTRS,
466   },
467   { .name = "UNC_P_VOLT_TRANS_CYCLES_INCREASE",
468     .desc = "Cycles Increasing Voltage",
469     .code = 0x1,
470     .cntmsk = 0xf,
471     .modmsk = IVBEP_UNC_PCU_ATTRS,
472   },
473   { .name = "UNC_P_VR_HOT_CYCLES",
474     .desc = "VR Hot",
475     .code = 0x32,
476     .cntmsk = 0xf,
477     .modmsk = IVBEP_UNC_PCU_ATTRS,
478   },
479 };