2 * Copyright (c) 2011 Google, Inc
3 * Contributed by Stephane Eranian <eranian@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
16 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
17 * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
18 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
19 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
20 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * This file is part of libpfm, a performance monitoring support library for
23 * applications on Linux.
25 * This file has been automatically generated.
27 * PMU: amd64_fam15h (AMD64 Fam15h Interlagos)
29 * Based on libpfm patch by Robert Richter <robert.richter@amd.com>:
30 * Family 15h Microarchitecture performance monitor events
34 * Apr 29 2011 -- Robert Richter, robert.richter@amd.com:
35 * Source: BKDG for AMD Family 15h Models 00h-0Fh Processors,
36 * 42301, Rev 1.15, April 18, 2011
38 * Dec 09 2010 -- Robert Richter, robert.richter@amd.com:
39 * Source: BIOS and Kernel Developer's Guide for the AMD Family 15h
40 * Processors, Rev 0.90, May 18, 2010
43 #define CORE_SELECT(b) \
45 .udesc = "Measure on Core0",\
48 .uflags= AMD64_FL_NCOMBO,\
51 .udesc = "Measure on Core1",\
54 .uflags= AMD64_FL_NCOMBO,\
57 .udesc = "Measure on Core2",\
60 .uflags= AMD64_FL_NCOMBO,\
63 .udesc = "Measure on Core3",\
66 .uflags= AMD64_FL_NCOMBO,\
69 .udesc = "Measure on Core4",\
72 .uflags= AMD64_FL_NCOMBO,\
75 .udesc = "Measure on Core5",\
78 .uflags= AMD64_FL_NCOMBO,\
81 .udesc = "Measure on Core6",\
84 .uflags= AMD64_FL_NCOMBO,\
87 .udesc = "Measure on Core7",\
90 .uflags= AMD64_FL_NCOMBO,\
92 { .uname = "ANY_CORE",\
93 .udesc = "Measure on any core",\
96 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,\
99 static const amd64_umask_t amd64_fam15h_dispatched_fpu_ops[]={
100 { .uname = "OPS_PIPE0",
101 .udesc = "Total number uops assigned to Pipe 0",
104 { .uname = "OPS_PIPE1",
105 .udesc = "Total number uops assigned to Pipe 1",
108 { .uname = "OPS_PIPE2",
109 .udesc = "Total number uops assigned to Pipe 2",
112 { .uname = "OPS_PIPE3",
113 .udesc = "Total number uops assigned to Pipe 3",
116 { .uname = "OPS_DUAL_PIPE0",
117 .udesc = "Total number dual-pipe uops assigned to Pipe 0",
120 { .uname = "OPS_DUAL_PIPE1",
121 .udesc = "Total number dual-pipe uops assigned to Pipe 1",
124 { .uname = "OPS_DUAL_PIPE2",
125 .udesc = "Total number dual-pipe uops assigned to Pipe 2",
128 { .uname = "OPS_DUAL_PIPE3",
129 .udesc = "Total number dual-pipe uops assigned to Pipe 3",
133 .udesc = "All sub-events selected",
135 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
139 static const amd64_umask_t amd64_fam15h_retired_sse_ops[]={
140 { .uname = "SINGLE_ADD_SUB_OPS",
141 .udesc = "Single-precision add/subtract FLOPS",
144 { .uname = "SINGLE_MUL_OPS",
145 .udesc = "Single-precision multiply FLOPS",
148 { .uname = "SINGLE_DIV_OPS",
149 .udesc = "Single-precision divide/square root FLOPS",
152 { .uname = "SINGLE_MUL_ADD_OPS",
153 .udesc = "Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS",
156 { .uname = "DOUBLE_ADD_SUB_OPS",
157 .udesc = "Double precision add/subtract FLOPS",
160 { .uname = "DOUBLE_MUL_OPS",
161 .udesc = "Double precision multiply FLOPS",
164 { .uname = "DOUBLE_DIV_OPS",
165 .udesc = "Double precision divide/square root FLOPS",
168 { .uname = "DOUBLE_MUL_ADD_OPS",
169 .udesc = "Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS",
173 .udesc = "All sub-events selected",
175 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
179 static const amd64_umask_t amd64_fam15h_move_scalar_optimization[]={
180 { .uname = "SSE_MOVE_OPS",
181 .udesc = "Number of SSE Move Ops",
184 { .uname = "SSE_MOVE_OPS_ELIM",
185 .udesc = "Number of SSE Move Ops eliminated",
188 { .uname = "OPT_CAND",
189 .udesc = "Number of Ops that are candidates for optimization (Z-bit set or pass)",
192 { .uname = "SCALAR_OPS_OPTIMIZED",
193 .udesc = "Number of Scalar ops optimized",
197 .udesc = "All sub-events selected",
199 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
203 static const amd64_umask_t amd64_fam15h_retired_serializing_ops[]={
204 { .uname = "SSE_RETIRED",
205 .udesc = "SSE bottom-executing uops retired",
208 { .uname = "SSE_MISPREDICTED",
209 .udesc = "SSE control word mispredict traps due to mispredictions",
212 { .uname = "X87_RETIRED",
213 .udesc = "X87 bottom-executing uops retired",
216 { .uname = "X87_MISPREDICTED",
217 .udesc = "X87 control word mispredict traps due to mispredictions",
221 .udesc = "All sub-events selected",
223 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
227 static const amd64_umask_t amd64_fam15h_segment_register_loads[]={
257 .udesc = "All sub-events selected",
259 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
263 static const amd64_umask_t amd64_fam15h_load_q_store_q_full[]={
264 { .uname = "LOAD_QUEUE",
265 .udesc = "The number of cycles that the load buffer is full",
268 { .uname = "STORE_QUEUE",
269 .udesc = "The number of cycles that the store buffer is full",
273 .udesc = "All sub-events selected",
275 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
279 static const amd64_umask_t amd64_fam15h_locked_ops[]={
280 { .uname = "EXECUTED",
281 .udesc = "Number of locked instructions executed",
284 { .uname = "CYCLES_NON_SPECULATIVE_PHASE",
285 .udesc = "Number of cycles spent in non-speculative phase, excluding cache miss penalty",
288 { .uname = "CYCLES_WAITING",
289 .udesc = "Number of cycles spent in non-speculative phase, including the cache miss penalty",
293 .udesc = "All sub-events selected",
295 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
299 static const amd64_umask_t amd64_fam15h_cancelled_store_to_load[]={
300 { .uname = "SIZE_ADDRESS_MISMATCHES",
301 .udesc = "Store is smaller than load or different starting byte but partial overlap",
305 .udesc = "All sub-events selected",
307 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
311 static const amd64_umask_t amd64_fam15h_data_cache_misses[]={
312 { .uname = "DC_MISS_STREAMING_STORE",
313 .udesc = "First data cache miss or streaming store to a 64B cache line",
316 { .uname = "STREAMING_STORE",
317 .udesc = "First streaming store to a 64B cache line",
321 .udesc = "All sub-events selected",
323 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
327 static const amd64_umask_t amd64_fam15h_data_cache_refills_from_l2_or_northbridge[]={
329 .udesc = "Fill with good data. (Final valid status is valid)",
332 { .uname = "INVALID",
333 .udesc = "Early valid status turned out to be invalid",
337 .udesc = "Fill with poison data",
340 { .uname = "READ_ERROR",
341 .udesc = "Fill with read data error",
345 .udesc = "All sub-events selected",
347 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
351 static const amd64_umask_t amd64_fam15h_unified_tlb_hit[]={
352 { .uname = "4K_DATA",
353 .udesc = "4 KB unified TLB hit for data",
356 { .uname = "2M_DATA",
357 .udesc = "2 MB unified TLB hit for data",
360 { .uname = "1G_DATA",
361 .udesc = "1 GB unified TLB hit for data",
364 { .uname = "4K_INST",
365 .udesc = "4 KB unified TLB hit for instruction",
368 { .uname = "2M_INST",
369 .udesc = "2 MB unified TLB hit for instruction",
372 { .uname = "1G_INST",
373 .udesc = "1 GB unified TLB hit for instruction",
377 .udesc = "All sub-events selected",
379 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
383 static const amd64_umask_t amd64_fam15h_unified_tlb_miss[]={
384 { .uname = "4K_DATA",
385 .udesc = "4 KB unified TLB miss for data",
388 { .uname = "2M_DATA",
389 .udesc = "2 MB unified TLB miss for data",
392 { .uname = "1GB_DATA",
393 .udesc = "1 GB unified TLB miss for data",
396 { .uname = "4K_INST",
397 .udesc = "4 KB unified TLB miss for instruction",
400 { .uname = "2M_INST",
401 .udesc = "2 MB unified TLB miss for instruction",
404 { .uname = "1G_INST",
405 .udesc = "1 GB unified TLB miss for instruction",
409 .udesc = "All sub-events selected",
411 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
415 static const amd64_umask_t amd64_fam15h_prefetch_instructions_dispatched[]={
417 .udesc = "Load (Prefetch, PrefetchT0/T1/T2)",
421 .udesc = "Store (PrefetchW)",
425 .udesc = "NTA (PrefetchNTA)",
429 .udesc = "All sub-events selected",
431 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
435 static const amd64_umask_t amd64_fam15h_ineffective_sw_prefetches[]={
436 { .uname = "SW_PREFETCH_HIT_IN_L1",
437 .udesc = "Software prefetch hit in the L1",
440 { .uname = "SW_PREFETCH_HIT_IN_L2",
441 .udesc = "Software prefetch hit in the L2",
445 .udesc = "All sub-events selected",
447 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
451 static const amd64_umask_t amd64_fam15h_memory_requests[]={
452 { .uname = "NON_CACHEABLE",
453 .udesc = "Requests to non-cacheable (UC) memory",
456 { .uname = "WRITE_COMBINING",
457 .udesc = "Requests to non-cacheable (WC, but not WC+/SS) memory",
460 { .uname = "STREAMING_STORE",
461 .udesc = "Requests to non-cacheable (WC+/SS, but not WC) memory",
465 .udesc = "All sub-events selected",
467 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
471 static const amd64_umask_t amd64_fam15h_data_prefetcher[]={
472 { .uname = "ATTEMPTED",
473 .udesc = "Prefetch attempts",
477 .udesc = "All sub-events selected",
479 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
483 static const amd64_umask_t amd64_fam15h_mab_reqs[]={
484 { .uname = "BUFFER_BIT_0",
485 .udesc = "Buffer entry index bit 0",
488 { .uname = "BUFFER_BIT_1",
489 .udesc = "Buffer entry index bit 1",
492 { .uname = "BUFFER_BIT_2",
493 .udesc = "Buffer entry index bit 2",
496 { .uname = "BUFFER_BIT_3",
497 .udesc = "Buffer entry index bit 3",
500 { .uname = "BUFFER_BIT_4",
501 .udesc = "Buffer entry index bit 4",
504 { .uname = "BUFFER_BIT_5",
505 .udesc = "Buffer entry index bit 5",
508 { .uname = "BUFFER_BIT_6",
509 .udesc = "Buffer entry index bit 6",
512 { .uname = "BUFFER_BIT_7",
513 .udesc = "Buffer entry index bit 7",
517 .udesc = "All sub-events selected",
519 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
523 static const amd64_umask_t amd64_fam15h_system_read_responses[]={
524 { .uname = "EXCLUSIVE",
525 .udesc = "Exclusive",
528 { .uname = "MODIFIED",
529 .udesc = "Modified (D18F0x68[ATMModeEn]==0), Modified written (D18F0x68[ATMModeEn]==1)",
540 { .uname = "DATA_ERROR",
541 .udesc = "Data Error",
544 { .uname = "MODIFIED_UNWRITTEN",
545 .udesc = "Modified unwritten",
549 .udesc = "All sub-events selected",
551 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
555 static const amd64_umask_t amd64_fam15h_octword_write_transfers[]={
556 { .uname = "OCTWORD_WRITE_TRANSFER",
557 .udesc = "OW write transfer",
561 .udesc = "All sub-events selected",
563 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
567 static const amd64_umask_t amd64_fam15h_requests_to_l2[]={
568 { .uname = "INSTRUCTIONS",
576 { .uname = "TLB_WALK",
577 .udesc = "TLB fill (page table walks)",
581 .udesc = "NB probe request",
584 { .uname = "CANCELLED",
585 .udesc = "Canceled request",
588 { .uname = "PREFETCHER",
589 .udesc = "L2 cache prefetcher request",
593 .udesc = "All sub-events selected",
595 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
599 static const amd64_umask_t amd64_fam15h_l2_cache_miss[]={
600 { .uname = "INSTRUCTIONS",
605 .udesc = "DC fill (includes possible replays, whereas PMCx041 does not)",
608 { .uname = "TLB_WALK",
609 .udesc = "TLB page table walk",
612 { .uname = "PREFETCHER",
613 .udesc = "L2 Cache Prefetcher request",
617 .udesc = "All sub-events selected",
619 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
623 static const amd64_umask_t amd64_fam15h_l2_cache_fill_writeback[]={
624 { .uname = "L2_FILLS",
625 .udesc = "L2 fills from system",
628 { .uname = "L2_WRITEBACKS",
629 .udesc = "L2 Writebacks to system (Clean and Dirty)",
632 { .uname = "L2_WRITEBACKS_CLEAN",
633 .udesc = "L2 Clean Writebacks to system",
637 .udesc = "All sub-events selected",
639 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
643 static const amd64_umask_t amd64_fam15h_page_splintering[]={
644 { .uname = "GUEST_LARGER",
645 .udesc = "Guest page size is larger than host page size when nested paging is enabled",
648 { .uname = "MTRR_MISMATCH",
649 .udesc = "Splintering due to MTRRs, IORRs, APIC, TOMs or other special address region",
652 { .uname = "HOST_LARGER",
653 .udesc = "Host page size is larger than the guest page size",
657 .udesc = "All sub-events selected",
659 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
663 static const amd64_umask_t amd64_fam15h_l1_itlb_miss_and_l2_itlb_miss[]={
664 { .uname = "4K_PAGE_FETCHES",
665 .udesc = "Instruction fetches to a 4 KB page",
668 { .uname = "2M_PAGE_FETCHES",
669 .udesc = "Instruction fetches to a 2 MB page",
672 { .uname = "1G_PAGE_FETCHES",
673 .udesc = "Instruction fetches to a 1 GB page",
677 .udesc = "All sub-events selected",
679 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
683 static const amd64_umask_t amd64_fam15h_instruction_cache_invalidated[]={
684 { .uname = "NON_SMC_PROBE_MISS",
685 .udesc = "Non-SMC invalidating probe that missed on in-flight instructions",
688 { .uname = "NON_SMC_PROBE_HIT",
689 .udesc = "Non-SMC invalidating probe that hit on in-flight instructions",
692 { .uname = "SMC_PROBE_MISS",
693 .udesc = "SMC invalidating probe that missed on in-flight instructions",
696 { .uname = "SMC_PROBE_HIT",
697 .udesc = "SMC invalidating probe that hit on in-flight instructions",
701 .udesc = "All sub-events selected",
703 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
707 static const amd64_umask_t amd64_fam15h_retired_mmx_fp_instructions[]={
709 .udesc = "X87 instructions",
713 .udesc = "MMX(tm) instructions",
717 .udesc = "SSE instructions (SSE,SSE2,SSE3,SSSE3,SSE4A,SSE4.1,SSE4.2,AVX,XOP,FMA4)",
721 .udesc = "All sub-events selected",
723 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
727 static const amd64_umask_t amd64_fam15h_fpu_exceptions[]={
728 { .uname = "TOTAL_FAULTS",
729 .udesc = "Total microfaults",
732 { .uname = "TOTAL_TRAPS",
733 .udesc = "Total microtraps",
736 { .uname = "INT2EXT_FAULTS",
737 .udesc = "Int2Ext faults",
740 { .uname = "EXT2INT_FAULTS",
741 .udesc = "Ext2Int faults",
744 { .uname = "BYPASS_FAULTS",
745 .udesc = "Bypass faults",
749 .udesc = "All sub-events selected",
751 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
755 static const amd64_umask_t amd64_fam15h_ibs_ops_tagged[]={
757 .udesc = "Number of ops tagged by IBS",
760 { .uname = "RETIRED",
761 .udesc = "Number of ops tagged by IBS that retired",
764 { .uname = "IGNORED",
765 .udesc = "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired",
769 .udesc = "All sub-events selected",
771 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
775 static const amd64_umask_t amd64_fam15h_ls_dispatch[]={
784 { .uname = "LOAD_OP_STORES",
785 .udesc = "Load-op-Stores",
789 .udesc = "All sub-events selected",
791 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
795 static const amd64_umask_t amd64_fam15h_l2_prefetcher_trigger_events[]={
796 { .uname = "LOAD_L1_MISS_SEEN_BY_PREFETCHER",
797 .udesc = "Load L1 miss seen by prefetcher",
800 { .uname = "STORE_L1_MISS_SEEN_BY_PREFETCHER",
801 .udesc = "Store L1 miss seen by prefetcher",
805 .udesc = "All sub-events selected",
807 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
811 static const amd64_umask_t amd64_fam15h_dram_accesses[]={
812 { .uname = "DCT0_PAGE_HIT",
813 .udesc = "DCT0 Page hit",
816 { .uname = "DCT0_PAGE_MISS",
817 .udesc = "DCT0 Page Miss",
820 { .uname = "DCT0_PAGE_CONFLICT",
821 .udesc = "DCT0 Page Conflict",
824 { .uname = "DCT1_PAGE_HIT",
825 .udesc = "DCT1 Page hit",
828 { .uname = "DCT1_PAGE_MISS",
829 .udesc = "DCT1 Page Miss",
832 { .uname = "DCT1_PAGE_CONFLICT",
833 .udesc = "DCT1 Page Conflict",
837 .udesc = "All sub-events selected",
839 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
843 static const amd64_umask_t amd64_fam15h_dram_controller_page_table_overflows[]={
844 { .uname = "DCT0_PAGE_TABLE_OVERFLOW",
845 .udesc = "DCT0 Page Table Overflow",
848 { .uname = "DCT1_PAGE_TABLE_OVERFLOW",
849 .udesc = "DCT1 Page Table Overflow",
853 .udesc = "All sub-events selected",
855 .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
859 static const amd64_umask_t amd64_fam15h_memory_controller_dram_command_slots_missed[]={
860 { .uname = "DCT0_COMMAND_SLOTS_MISSED",
861 .udesc = "DCT0 Command Slots Missed (in MemClks)",
864 { .uname = "DCT1_COMMAND_SLOTS_MISSED",
865 .udesc = "DCT1 Command Slots Missed (in MemClks)",
869 .udesc = "All sub-events selected",
871 .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
875 static const amd64_umask_t amd64_fam15h_memory_controller_turnarounds[]={
876 { .uname = "DCT0_DIMM_TURNAROUND",
877 .udesc = "DCT0 DIMM (chip select) turnaround",
880 { .uname = "DCT0_READ_WRITE_TURNAROUND",
881 .udesc = "DCT0 Read to write turnaround",
884 { .uname = "DCT0_WRITE_READ_TURNAROUND",
885 .udesc = "DCT0 Write to read turnaround",
888 { .uname = "DCT1_DIMM_TURNAROUND",
889 .udesc = "DCT1 DIMM (chip select) turnaround",
892 { .uname = "DCT1_READ_WRITE_TURNAROUND",
893 .udesc = "DCT1 Read to write turnaround",
896 { .uname = "DCT1_WRITE_READ_TURNAROUND",
897 .udesc = "DCT1 Write to read turnaround",
901 .udesc = "All sub-events selected",
903 .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
907 static const amd64_umask_t amd64_fam15h_memory_controller_bypass_counter_saturation[]={
908 { .uname = "MEMORY_CONTROLLER_HIGH_PRIORITY_BYPASS",
909 .udesc = "Memory controller high priority bypass",
912 { .uname = "MEMORY_CONTROLLER_MEDIUM_PRIORITY_BYPASS",
913 .udesc = "Memory controller medium priority bypass",
916 { .uname = "DCT0_DCQ_BYPASS",
917 .udesc = "DCT0 DCQ bypass",
920 { .uname = "DCT1_DCQ_BYPASS",
921 .udesc = "DCT1 DCQ bypass",
925 .udesc = "All sub-events selected",
927 .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
931 static const amd64_umask_t amd64_fam15h_thermal_status[]={
932 { .uname = "NUM_HTC_TRIP_POINT_CROSSED",
933 .udesc = "Number of times the HTC trip point is crossed",
936 { .uname = "NUM_CLOCKS_HTC_PSTATE_INACTIVE",
937 .udesc = "Number of clocks HTC P-state is inactive",
940 { .uname = "NUM_CLOCKS_HTC_PSTATE_ACTIVE",
941 .udesc = "Number of clocks HTC P-state is active",
945 .udesc = "All sub-events selected",
947 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
951 static const amd64_umask_t amd64_fam15h_cpu_io_requests_to_memory_io[]={
952 { .uname = "REMOTE_IO_TO_LOCAL_IO",
953 .udesc = "Remote IO to Local IO",
955 .uflags= AMD64_FL_NCOMBO,
957 { .uname = "REMOTE_CPU_TO_LOCAL_IO",
958 .udesc = "Remote CPU to Local IO",
960 .uflags= AMD64_FL_NCOMBO,
962 { .uname = "LOCAL_IO_TO_REMOTE_IO",
963 .udesc = "Local IO to Remote IO",
965 .uflags= AMD64_FL_NCOMBO,
967 { .uname = "LOCAL_IO_TO_REMOTE_MEM",
968 .udesc = "Local IO to Remote Mem",
970 .uflags= AMD64_FL_NCOMBO,
972 { .uname = "LOCAL_CPU_TO_REMOTE_IO",
973 .udesc = "Local CPU to Remote IO",
975 .uflags= AMD64_FL_NCOMBO,
977 { .uname = "LOCAL_CPU_TO_REMOTE_MEM",
978 .udesc = "Local CPU to Remote Mem",
980 .uflags= AMD64_FL_NCOMBO,
982 { .uname = "LOCAL_IO_TO_LOCAL_IO",
983 .udesc = "Local IO to Local IO",
985 .uflags= AMD64_FL_NCOMBO,
987 { .uname = "LOCAL_IO_TO_LOCAL_MEM",
988 .udesc = "Local IO to Local Mem",
990 .uflags= AMD64_FL_NCOMBO,
992 { .uname = "LOCAL_CPU_TO_LOCAL_IO",
993 .udesc = "Local CPU to Local IO",
995 .uflags= AMD64_FL_NCOMBO,
997 { .uname = "LOCAL_CPU_TO_LOCAL_MEM",
998 .udesc = "Local CPU to Local Mem",
1000 .uflags= AMD64_FL_NCOMBO,
1004 static const amd64_umask_t amd64_fam15h_cache_block_commands[]={
1005 { .uname = "VICTIM_BLOCK",
1006 .udesc = "Victim Block (Writeback)",
1009 { .uname = "READ_BLOCK",
1010 .udesc = "Read Block (Dcache load miss refill)",
1013 { .uname = "READ_BLOCK_SHARED",
1014 .udesc = "Read Block Shared (Icache refill)",
1017 { .uname = "READ_BLOCK_MODIFIED",
1018 .udesc = "Read Block Modified (Dcache store miss refill)",
1021 { .uname = "CHANGE_TO_DIRTY",
1022 .udesc = "Change-to-Dirty (first store to clean block already in cache)",
1026 .udesc = "All sub-events selected",
1028 .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
1032 static const amd64_umask_t amd64_fam15h_sized_commands[]={
1033 { .uname = "NON-POSTED_SZWR_BYTE",
1034 .udesc = "Non-Posted SzWr Byte (1-32 bytes). Typical Usage: Legacy or mapped IO, typically 1-4 bytes.",
1037 { .uname = "NON-POSTED_SZWR_DW",
1038 .udesc = "Non-Posted SzWr DW (1-16 dwords). Typical Usage: Legacy or mapped IO, typically 1",
1041 { .uname = "POSTED_SZWR_BYTE",
1042 .udesc = "Posted SzWr Byte (1-32 bytes). Typical Usage: Subcache-line DMA writes, size varies; also",
1045 { .uname = "POSTED_SZWR_DW",
1046 .udesc = "Posted SzWr DW (1-16 dwords). Typical Usage: Block-oriented DMA writes, often cache-line",
1049 { .uname = "SZRD_BYTE",
1050 .udesc = "SzRd Byte (4 bytes). Typical Usage: Legacy or mapped IO.",
1053 { .uname = "SZRD_DW",
1054 .udesc = "SzRd DW (1-16 dwords). Typical Usage: Block-oriented DMA reads, typically cache-line size.",
1058 .udesc = "All sub-events selected",
1060 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1064 static const amd64_umask_t amd64_fam15h_probe_responses_and_upstream_requests[]={
1065 { .uname = "PROBE_MISS",
1066 .udesc = "Probe miss",
1069 { .uname = "PROBE_HIT_CLEAN",
1070 .udesc = "Probe hit clean",
1073 { .uname = "PROBE_HIT_DIRTY_WITHOUT_MEMORY_CANCEL",
1074 .udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)",
1077 { .uname = "PROBE_HIT_DIRTY_WITH_MEMORY_CANCEL",
1078 .udesc = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)",
1081 { .uname = "UPSTREAM_DISPLAY_REFRESH_ISOC_READS",
1082 .udesc = "Upstream display refresh/ISOC reads",
1085 { .uname = "UPSTREAM_NON-DISPLAY_REFRESH_READS",
1086 .udesc = "Upstream non-display refresh reads",
1089 { .uname = "UPSTREAM_ISOC_WRITES",
1090 .udesc = "Upstream ISOC writes",
1093 { .uname = "UPSTREAM_NON-ISOC_WRITES",
1094 .udesc = "Upstream non-ISOC writes",
1098 .udesc = "All sub-events selected",
1100 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1104 static const amd64_umask_t amd64_fam15h_gart_events[]={
1105 { .uname = "GART_APERTURE_HIT_ON_ACCESS_FROM_CPU",
1106 .udesc = "GART aperture hit on access from CPU",
1109 { .uname = "GART_APERTURE_HIT_ON_ACCESS_FROM_IO",
1110 .udesc = "GART aperture hit on access from IO",
1113 { .uname = "GART_MISS",
1114 .udesc = "GART miss",
1117 { .uname = "GART_REQUEST_HIT_TABLE_WALK_IN_PROGRESS",
1118 .udesc = "GART Request hit table walk in progress",
1121 { .uname = "GART_MULTIPLE_TABLE_WALK_IN_PROGRESS",
1122 .udesc = "GART multiple table walk in progress",
1126 .udesc = "All sub-events selected",
1128 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1132 static const amd64_umask_t amd64_fam15h_link_transmit_bandwidth[]={
1133 { .uname = "COMMAND_DW_SENT",
1134 .udesc = "Command DW sent",
1138 { .uname = "DATA_DW_SENT",
1139 .udesc = "Data DW sent",
1143 { .uname = "BUFFER_RELEASE_DW_SENT",
1144 .udesc = "Buffer release DW sent",
1148 { .uname = "NOP_DW_SENT",
1149 .udesc = "NOP DW sent (idle)",
1153 { .uname = "ADDRESS_DW_SENT",
1154 .udesc = "Address (including extensions) DW sent",
1158 { .uname = "PER_PACKET_CRC_SENT",
1159 .udesc = "Per packet CRC sent",
1164 .udesc = "All sub-events selected",
1166 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1169 { .uname = "SUBLINK_1",
1170 .udesc = "When links are unganged, enable this umask to select sublink 1",
1173 .uflags= AMD64_FL_NCOMBO,
1175 { .uname = "SUBLINK_0",
1176 .udesc = "When links are unganged, enable this umask to select sublink 0 (default when links ganged)",
1179 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1185 static const amd64_umask_t amd64_fam15h_cpu_to_dram_requests_to_target_node[]={
1186 { .uname = "LOCAL_TO_NODE_0",
1187 .udesc = "From Local node to Node 0",
1190 { .uname = "LOCAL_TO_NODE_1",
1191 .udesc = "From Local node to Node 1",
1194 { .uname = "LOCAL_TO_NODE_2",
1195 .udesc = "From Local node to Node 2",
1198 { .uname = "LOCAL_TO_NODE_3",
1199 .udesc = "From Local node to Node 3",
1202 { .uname = "LOCAL_TO_NODE_4",
1203 .udesc = "From Local node to Node 4",
1206 { .uname = "LOCAL_TO_NODE_5",
1207 .udesc = "From Local node to Node 5",
1210 { .uname = "LOCAL_TO_NODE_6",
1211 .udesc = "From Local node to Node 6",
1214 { .uname = "LOCAL_TO_NODE_7",
1215 .udesc = "From Local node to Node 7",
1219 .udesc = "All sub-events selected",
1221 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1225 static const amd64_umask_t amd64_fam15h_io_to_dram_requests_to_target_node[]={
1226 { .uname = "LOCAL_TO_NODE_0",
1227 .udesc = "From Local node to Node 0",
1230 { .uname = "LOCAL_TO_NODE_1",
1231 .udesc = "From Local node to Node 1",
1234 { .uname = "LOCAL_TO_NODE_2",
1235 .udesc = "From Local node to Node 2",
1238 { .uname = "LOCAL_TO_NODE_3",
1239 .udesc = "From Local node to Node 3",
1242 { .uname = "LOCAL_TO_NODE_4",
1243 .udesc = "From Local node to Node 4",
1246 { .uname = "LOCAL_TO_NODE_5",
1247 .udesc = "From Local node to Node 5",
1250 { .uname = "LOCAL_TO_NODE_6",
1251 .udesc = "From Local node to Node 6",
1254 { .uname = "LOCAL_TO_NODE_7",
1255 .udesc = "From Local node to Node 7",
1259 .udesc = "All sub-events selected",
1261 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1265 static const amd64_umask_t amd64_fam15h_cpu_read_command_requests_to_target_node_0_3[]={
1266 { .uname = "READ_BLOCK_LOCAL_TO_NODE_0",
1267 .udesc = "Read block From Local node to Node 0",
1269 .uflags= AMD64_FL_NCOMBO,
1271 { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_0",
1272 .udesc = "Read block shared From Local node to Node 0",
1274 .uflags= AMD64_FL_NCOMBO,
1276 { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_0",
1277 .udesc = "Read block modified From Local node to Node 0",
1279 .uflags= AMD64_FL_NCOMBO,
1281 { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_0",
1282 .udesc = "Change-to-Dirty From Local node to Node 0",
1284 .uflags= AMD64_FL_NCOMBO,
1286 { .uname = "READ_BLOCK_LOCAL_TO_NODE_1",
1287 .udesc = "Read block From Local node to Node 1",
1289 .uflags= AMD64_FL_NCOMBO,
1291 { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_1",
1292 .udesc = "Read block shared From Local node to Node 1",
1294 .uflags= AMD64_FL_NCOMBO,
1296 { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_1",
1297 .udesc = "Read block modified From Local node to Node 1",
1299 .uflags= AMD64_FL_NCOMBO,
1301 { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_1",
1302 .udesc = "Change-to-Dirty From Local node to Node 1",
1304 .uflags= AMD64_FL_NCOMBO,
1306 { .uname = "READ_BLOCK_LOCAL_TO_NODE_2",
1307 .udesc = "Read block From Local node to Node 2",
1309 .uflags= AMD64_FL_NCOMBO,
1311 { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_2",
1312 .udesc = "Read block shared From Local node to Node 2",
1314 .uflags= AMD64_FL_NCOMBO,
1316 { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_2",
1317 .udesc = "Read block modified From Local node to Node 2",
1319 .uflags= AMD64_FL_NCOMBO,
1321 { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_2",
1322 .udesc = "Change-to-Dirty From Local node to Node 2",
1324 .uflags= AMD64_FL_NCOMBO,
1326 { .uname = "READ_BLOCK_LOCAL_TO_NODE_3",
1327 .udesc = "Read block From Local node to Node 3",
1329 .uflags= AMD64_FL_NCOMBO,
1331 { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_3",
1332 .udesc = "Read block shared From Local node to Node 3",
1334 .uflags= AMD64_FL_NCOMBO,
1336 { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_3",
1337 .udesc = "Read block modified From Local node to Node 3",
1339 .uflags= AMD64_FL_NCOMBO,
1341 { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_3",
1342 .udesc = "Change-to-Dirty From Local node to Node 3",
1344 .uflags= AMD64_FL_NCOMBO,
1347 .udesc = "All sub-events selected",
1349 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1353 static const amd64_umask_t amd64_fam15h_cpu_read_command_requests_to_target_node_4_7[]={
1354 { .uname = "READ_BLOCK_LOCAL_TO_NODE_4",
1355 .udesc = "Read block From Local node to Node 4",
1357 .uflags= AMD64_FL_NCOMBO,
1359 { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_4",
1360 .udesc = "Read block shared From Local node to Node 4",
1362 .uflags= AMD64_FL_NCOMBO,
1364 { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_4",
1365 .udesc = "Read block modified From Local node to Node 4",
1367 .uflags= AMD64_FL_NCOMBO,
1369 { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_4",
1370 .udesc = "Change-to-Dirty From Local node to Node 4",
1372 .uflags= AMD64_FL_NCOMBO,
1374 { .uname = "READ_BLOCK_LOCAL_TO_NODE_5",
1375 .udesc = "Read block From Local node to Node 5",
1377 .uflags= AMD64_FL_NCOMBO,
1379 { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_5",
1380 .udesc = "Read block shared From Local node to Node 5",
1382 .uflags= AMD64_FL_NCOMBO,
1384 { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_5",
1385 .udesc = "Read block modified From Local node to Node 5",
1387 .uflags= AMD64_FL_NCOMBO,
1389 { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_5",
1390 .udesc = "Change-to-Dirty From Local node to Node 5",
1392 .uflags= AMD64_FL_NCOMBO,
1394 { .uname = "READ_BLOCK_LOCAL_TO_NODE_6",
1395 .udesc = "Read block From Local node to Node 6",
1397 .uflags= AMD64_FL_NCOMBO,
1399 { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_6",
1400 .udesc = "Read block shared From Local node to Node 6",
1402 .uflags= AMD64_FL_NCOMBO,
1404 { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_6",
1405 .udesc = "Read block modified From Local node to Node 6",
1407 .uflags= AMD64_FL_NCOMBO,
1409 { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_6",
1410 .udesc = "Change-to-Dirty From Local node to Node 6",
1412 .uflags= AMD64_FL_NCOMBO,
1414 { .uname = "READ_BLOCK_LOCAL_TO_NODE_7",
1415 .udesc = "Read block From Local node to Node 7",
1417 .uflags= AMD64_FL_NCOMBO,
1419 { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_7",
1420 .udesc = "Read block shared From Local node to Node 7",
1422 .uflags= AMD64_FL_NCOMBO,
1424 { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_7",
1425 .udesc = "Read block modified From Local node to Node 7",
1427 .uflags= AMD64_FL_NCOMBO,
1429 { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_7",
1430 .udesc = "Change-to-Dirty From Local node to Node 7",
1432 .uflags= AMD64_FL_NCOMBO,
1435 .udesc = "All sub-events selected",
1437 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1441 static const amd64_umask_t amd64_fam15h_cpu_command_requests_to_target_node[]={
1442 { .uname = "READ_SIZED_LOCAL_TO_NODE_0",
1443 .udesc = "Read Sized From Local node to Node 0",
1445 .uflags= AMD64_FL_NCOMBO,
1447 { .uname = "WRITE_SIZED_LOCAL_TO_NODE_0",
1448 .udesc = "Write Sized From Local node to Node 0",
1450 .uflags= AMD64_FL_NCOMBO,
1452 { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_0",
1453 .udesc = "Victim Block From Local node to Node 0",
1455 .uflags= AMD64_FL_NCOMBO,
1457 { .uname = "READ_SIZED_LOCAL_TO_NODE_1",
1458 .udesc = "Read Sized From Local node to Node 1",
1460 .uflags= AMD64_FL_NCOMBO,
1462 { .uname = "WRITE_SIZED_LOCAL_TO_NODE_1",
1463 .udesc = "Write Sized From Local node to Node 1",
1465 .uflags= AMD64_FL_NCOMBO,
1467 { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_1",
1468 .udesc = "Victim Block From Local node to Node 1",
1470 .uflags= AMD64_FL_NCOMBO,
1472 { .uname = "READ_SIZED_LOCAL_TO_NODE_2",
1473 .udesc = "Read Sized From Local node to Node 2",
1475 .uflags= AMD64_FL_NCOMBO,
1477 { .uname = "WRITE_SIZED_LOCAL_TO_NODE_2",
1478 .udesc = "Write Sized From Local node to Node 2",
1480 .uflags= AMD64_FL_NCOMBO,
1482 { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_2",
1483 .udesc = "Victim Block From Local node to Node 2",
1485 .uflags= AMD64_FL_NCOMBO,
1487 { .uname = "READ_SIZED_LOCAL_TO_NODE_3",
1488 .udesc = "Read Sized From Local node to Node 3",
1490 .uflags= AMD64_FL_NCOMBO,
1492 { .uname = "WRITE_SIZED_LOCAL_TO_NODE_3",
1493 .udesc = "Write Sized From Local node to Node 3",
1495 .uflags= AMD64_FL_NCOMBO,
1497 { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_3",
1498 .udesc = "Victim Block From Local node to Node 3",
1500 .uflags= AMD64_FL_NCOMBO,
1502 { .uname = "READ_SIZED_LOCAL_TO_NODE_4",
1503 .udesc = "Read Sized From Local node to Node 4",
1505 .uflags= AMD64_FL_NCOMBO,
1507 { .uname = "WRITE_SIZED_LOCAL_TO_NODE_4",
1508 .udesc = "Write Sized From Local node to Node 4",
1510 .uflags= AMD64_FL_NCOMBO,
1512 { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_4",
1513 .udesc = "Victim Block From Local node to Node 4",
1515 .uflags= AMD64_FL_NCOMBO,
1517 { .uname = "READ_SIZED_LOCAL_TO_NODE_5",
1518 .udesc = "Read Sized From Local node to Node 5",
1520 .uflags= AMD64_FL_NCOMBO,
1522 { .uname = "WRITE_SIZED_LOCAL_TO_NODE_5",
1523 .udesc = "Write Sized From Local node to Node 5",
1525 .uflags= AMD64_FL_NCOMBO,
1527 { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_5",
1528 .udesc = "Victim Block From Local node to Node 5",
1530 .uflags= AMD64_FL_NCOMBO,
1532 { .uname = "READ_SIZED_LOCAL_TO_NODE_6",
1533 .udesc = "Read Sized From Local node to Node 6",
1535 .uflags= AMD64_FL_NCOMBO,
1537 { .uname = "WRITE_SIZED_LOCAL_TO_NODE_6",
1538 .udesc = "Write Sized From Local node to Node 6",
1540 .uflags= AMD64_FL_NCOMBO,
1542 { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_6",
1543 .udesc = "Victim Block From Local node to Node 6",
1545 .uflags= AMD64_FL_NCOMBO,
1547 { .uname = "READ_SIZED_LOCAL_TO_NODE_7",
1548 .udesc = "Read Sized From Local node to Node 7",
1550 .uflags= AMD64_FL_NCOMBO,
1552 { .uname = "WRITE_SIZED_LOCAL_TO_NODE_7",
1553 .udesc = "Write Sized From Local node to Node 7",
1555 .uflags= AMD64_FL_NCOMBO,
1557 { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_7",
1558 .udesc = "Victim Block From Local node to Node 7",
1560 .uflags= AMD64_FL_NCOMBO,
1562 { .uname = "ALL_LOCAL_TO_NODE_0_3",
1563 .udesc = "All From Local node to Node 0-3",
1565 .uflags= AMD64_FL_NCOMBO,
1567 { .uname = "ALL_LOCAL_TO_NODE_4_7",
1568 .udesc = "All From Local node to Node 4-7",
1570 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1574 static const amd64_umask_t amd64_fam15h_request_cache_status_0[]={
1575 { .uname = "PROBE_HIT_S",
1576 .udesc = "Probe Hit S",
1579 { .uname = "PROBE_HIT_E",
1580 .udesc = "Probe Hit E",
1583 { .uname = "PROBE_HIT_MUW_OR_O",
1584 .udesc = "Probe Hit MuW or O",
1587 { .uname = "PROBE_HIT_M",
1588 .udesc = "Probe Hit M",
1591 { .uname = "PROBE_MISS",
1592 .udesc = "Probe Miss",
1595 { .uname = "DIRECTED_PROBE",
1596 .udesc = "Directed Probe",
1599 { .uname = "TRACK_CACHE_STAT_FOR_RDBLK",
1600 .udesc = "Track Cache Stat for RdBlk",
1603 { .uname = "TRACK_CACHE_STAT_FOR_RDBLKS",
1604 .udesc = "Track Cache Stat for RdBlkS",
1608 .udesc = "All sub-events selected",
1610 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1614 static const amd64_umask_t amd64_fam15h_request_cache_status_1[]={
1615 { .uname = "PROBE_HIT_S",
1616 .udesc = "Probe Hit S",
1619 { .uname = "PROBE_HIT_E",
1620 .udesc = "Probe Hit E",
1623 { .uname = "PROBE_HIT_MUW_OR_O",
1624 .udesc = "Probe Hit MuW or O",
1627 { .uname = "PROBE_HIT_M",
1628 .udesc = "Probe Hit M",
1631 { .uname = "PROBE_MISS",
1632 .udesc = "Probe Miss",
1635 { .uname = "DIRECTED_PROBE",
1636 .udesc = "Directed Probe",
1639 { .uname = "TRACK_CACHE_STAT_FOR_CHGTODIRTY",
1640 .udesc = "Track Cache Stat for ChgToDirty",
1643 { .uname = "TRACK_CACHE_STAT_FOR_RDBLKM",
1644 .udesc = "Track Cache Stat for RdBlkM",
1648 .udesc = "All sub-events selected",
1650 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1654 static const amd64_umask_t amd64_fam15h_memory_controller_requests[]={
1655 { .uname = "WRITE_REQUESTS_TO_DCT",
1656 .udesc = "Write requests sent to the DCT",
1659 { .uname = "READ_REQUESTS_TO_DCT",
1660 .udesc = "Read requests (including prefetch requests) sent to the DCT",
1663 { .uname = "PREFETCH_REQUESTS_TO_DCT",
1664 .udesc = "Prefetch requests sent to the DCT",
1667 { .uname = "32_BYTES_SIZED_WRITES",
1668 .udesc = "32 Bytes Sized Writes",
1671 { .uname = "64_BYTES_SIZED_WRITES",
1672 .udesc = "64 Bytes Sized Writes",
1675 { .uname = "32_BYTES_SIZED_READS",
1676 .udesc = "32 Bytes Sized Reads",
1679 { .uname = "64_BYTE_SIZED_READS",
1680 .udesc = "64 Byte Sized Reads",
1683 { .uname = "READ_REQUESTS_TO_DCT_WHILE_WRITES_PENDING",
1684 .udesc = "Read requests sent to the DCT while writes requests are pending in the DCT",
1688 .udesc = "All sub-events selected",
1690 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1694 static const amd64_umask_t amd64_fam15h_read_request_to_l3_cache[]={
1695 { .uname = "READ_BLOCK_EXCLUSIVE",
1696 .udesc = "Read Block Exclusive (Data cache read)",
1700 { .uname = "READ_BLOCK_SHARED",
1701 .udesc = "Read Block Shared (Instruction cache read)",
1705 { .uname = "READ_BLOCK_MODIFY",
1706 .udesc = "Read Block Modify",
1710 { .uname = "PREFETCH",
1711 .udesc = "Count prefetches only",
1715 { .uname = "READ_BLOCK_ANY",
1716 .udesc = "Count any read request",
1719 .uflags= AMD64_FL_DFL | AMD64_FL_NCOMBO,
1724 static const amd64_umask_t amd64_fam15h_l3_fills_caused_by_l2_evictions[]={
1725 { .uname = "SHARED",
1730 { .uname = "EXCLUSIVE",
1731 .udesc = "Exclusive",
1740 { .uname = "MODIFIED",
1741 .udesc = "Modified",
1746 .udesc = "All sub-events selected",
1748 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1754 static const amd64_umask_t amd64_fam15h_l3_evictions[]={
1755 { .uname = "SHARED",
1759 { .uname = "EXCLUSIVE",
1760 .udesc = "Exclusive",
1767 { .uname = "MODIFIED",
1768 .udesc = "Modified",
1772 .udesc = "All sub-events selected",
1774 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1778 static const amd64_umask_t amd64_fam15h_l3_latency[]={
1779 { .uname = "L3_REQUEST_CYCLE",
1780 .udesc = "L3 Request cycle count.",
1783 { .uname = "L3_REQUEST",
1784 .udesc = "L3 request count.",
1788 .udesc = "All sub-events selected",
1790 .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1794 static const amd64_entry_t amd64_fam15h_pe[]={
1795 { .name = "DISPATCHED_FPU_OPS",
1796 .desc = "FPU Pipe Assignment",
1797 .modmsk = AMD64_FAM15H_ATTRS,
1799 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_dispatched_fpu_ops),
1801 .umasks = amd64_fam15h_dispatched_fpu_ops,
1803 { .name = "CYCLES_FPU_EMPTY",
1804 .desc = "FP Scheduler Empty",
1805 .modmsk = AMD64_FAM15H_ATTRS,
1808 { .name = "RETIRED_SSE_OPS",
1809 .desc = "Retired SSE/BNI Ops",
1810 .modmsk = AMD64_FAM15H_ATTRS,
1812 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_retired_sse_ops),
1814 .umasks = amd64_fam15h_retired_sse_ops,
1816 { .name = "MOVE_SCALAR_OPTIMIZATION",
1817 .desc = "Number of Move Elimination and Scalar Op Optimization",
1818 .modmsk = AMD64_FAM15H_ATTRS,
1820 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_move_scalar_optimization),
1822 .umasks = amd64_fam15h_move_scalar_optimization,
1824 { .name = "RETIRED_SERIALIZING_OPS",
1825 .desc = "Retired Serializing Ops",
1826 .modmsk = AMD64_FAM15H_ATTRS,
1828 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_retired_serializing_ops),
1830 .umasks = amd64_fam15h_retired_serializing_ops,
1832 { .name = "BOTTOM_EXECUTE_OP",
1833 .desc = "Number of Cycles that a Bottom-Execute uop is in the FP Scheduler",
1834 .modmsk = AMD64_FAM15H_ATTRS,
1837 { .name = "SEGMENT_REGISTER_LOADS",
1838 .desc = "Segment Register Loads",
1839 .modmsk = AMD64_FAM15H_ATTRS,
1841 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_segment_register_loads),
1843 .umasks = amd64_fam15h_segment_register_loads,
1845 { .name = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE",
1846 .desc = "Pipeline Restart Due to Self-Modifying Code",
1847 .modmsk = AMD64_FAM15H_ATTRS,
1850 { .name = "PIPELINE_RESTART_DUE_TO_PROBE_HIT",
1851 .desc = "Pipeline Restart Due to Probe Hit",
1852 .modmsk = AMD64_FAM15H_ATTRS,
1855 { .name = "LOAD_Q_STORE_Q_FULL",
1856 .desc = "Load Queue/Store Queue Full",
1857 .modmsk = AMD64_FAM15H_ATTRS,
1859 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_load_q_store_q_full),
1861 .umasks = amd64_fam15h_load_q_store_q_full,
1863 { .name = "LOCKED_OPS",
1864 .desc = "Locked Operations",
1865 .modmsk = AMD64_FAM15H_ATTRS,
1867 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_locked_ops),
1869 .umasks = amd64_fam15h_locked_ops,
1871 { .name = "RETIRED_CLFLUSH_INSTRUCTIONS",
1872 .desc = "Retired CLFLUSH Instructions",
1873 .modmsk = AMD64_FAM15H_ATTRS,
1876 { .name = "RETIRED_CPUID_INSTRUCTIONS",
1877 .desc = "Retired CPUID Instructions",
1878 .modmsk = AMD64_FAM15H_ATTRS,
1881 { .name = "CANCELLED_STORE_TO_LOAD",
1882 .desc = "Canceled Store to Load Forward Operations",
1883 .modmsk = AMD64_FAM15H_ATTRS,
1885 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_cancelled_store_to_load),
1887 .umasks = amd64_fam15h_cancelled_store_to_load,
1889 { .name = "SMIS_RECEIVED",
1890 .desc = "SMIs Received",
1891 .modmsk = AMD64_FAM15H_ATTRS,
1894 { .name = "DATA_CACHE_ACCESSES",
1895 .desc = "Data Cache Accesses",
1896 .modmsk = AMD64_FAM15H_ATTRS,
1899 { .name = "DATA_CACHE_MISSES",
1900 .desc = "Data Cache Misses",
1901 .modmsk = AMD64_FAM15H_ATTRS,
1903 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_data_cache_misses),
1905 .umasks = amd64_fam15h_data_cache_misses,
1907 { .name = "DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE",
1908 .desc = "Data Cache Refills from L2 or System",
1909 .modmsk = AMD64_FAM15H_ATTRS,
1911 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_data_cache_refills_from_l2_or_northbridge),
1913 .umasks = amd64_fam15h_data_cache_refills_from_l2_or_northbridge,
1915 { .name = "DATA_CACHE_REFILLS_FROM_NORTHBRIDGE",
1916 .desc = "Data Cache Refills from System",
1917 .modmsk = AMD64_FAM15H_ATTRS,
1920 { .name = "UNIFIED_TLB_HIT",
1921 .desc = "Unified TLB Hit",
1922 .modmsk = AMD64_FAM15H_ATTRS,
1924 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_unified_tlb_hit),
1926 .umasks = amd64_fam15h_unified_tlb_hit,
1928 { .name = "UNIFIED_TLB_MISS",
1929 .desc = "Unified TLB Miss",
1930 .modmsk = AMD64_FAM15H_ATTRS,
1932 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_unified_tlb_miss),
1934 .umasks = amd64_fam15h_unified_tlb_miss,
1936 { .name = "MISALIGNED_ACCESSES",
1937 .desc = "Misaligned Accesses",
1938 .modmsk = AMD64_FAM15H_ATTRS,
1941 { .name = "PREFETCH_INSTRUCTIONS_DISPATCHED",
1942 .desc = "Prefetch Instructions Dispatched",
1943 .modmsk = AMD64_FAM15H_ATTRS,
1945 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_prefetch_instructions_dispatched),
1947 .umasks = amd64_fam15h_prefetch_instructions_dispatched,
1949 { .name = "INEFFECTIVE_SW_PREFETCHES",
1950 .desc = "Ineffective Software Prefetches",
1951 .modmsk = AMD64_FAM15H_ATTRS,
1953 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_ineffective_sw_prefetches),
1955 .umasks = amd64_fam15h_ineffective_sw_prefetches,
1957 { .name = "MEMORY_REQUESTS",
1958 .desc = "Memory Requests by Type",
1959 .modmsk = AMD64_FAM15H_ATTRS,
1961 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_memory_requests),
1963 .umasks = amd64_fam15h_memory_requests,
1965 { .name = "DATA_PREFETCHER",
1966 .desc = "Data Prefetcher",
1967 .modmsk = AMD64_FAM15H_ATTRS,
1969 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_data_prefetcher),
1971 .umasks = amd64_fam15h_data_prefetcher,
1973 { .name = "MAB_REQS",
1974 .desc = "MAB Requests",
1975 .modmsk = AMD64_FAM15H_ATTRS,
1977 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_mab_reqs),
1979 .umasks = amd64_fam15h_mab_reqs,
1981 { .name = "MAB_WAIT",
1982 .desc = "MAB Wait Cycles",
1983 .modmsk = AMD64_FAM15H_ATTRS,
1985 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_mab_reqs),
1987 .umasks = amd64_fam15h_mab_reqs, /* identical to actual umasks list for this event */
1989 { .name = "SYSTEM_READ_RESPONSES",
1990 .desc = "Response From System on Cache Refills",
1991 .modmsk = AMD64_FAM15H_ATTRS,
1993 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_system_read_responses),
1995 .umasks = amd64_fam15h_system_read_responses,
1997 { .name = "OCTWORD_WRITE_TRANSFERS",
1998 .desc = "Octwords Written to System",
1999 .modmsk = AMD64_FAM15H_ATTRS,
2001 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_octword_write_transfers),
2003 .umasks = amd64_fam15h_octword_write_transfers,
2005 { .name = "CPU_CLK_UNHALTED",
2006 .desc = "CPU Clocks not Halted",
2007 .modmsk = AMD64_FAM15H_ATTRS,
2010 { .name = "REQUESTS_TO_L2",
2011 .desc = "Requests to L2 Cache",
2012 .modmsk = AMD64_FAM15H_ATTRS,
2014 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_requests_to_l2),
2016 .umasks = amd64_fam15h_requests_to_l2,
2018 { .name = "L2_CACHE_MISS",
2019 .desc = "L2 Cache Misses",
2020 .modmsk = AMD64_FAM15H_ATTRS,
2022 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l2_cache_miss),
2024 .umasks = amd64_fam15h_l2_cache_miss,
2026 { .name = "L2_CACHE_FILL_WRITEBACK",
2027 .desc = "L2 Fill/Writeback",
2028 .modmsk = AMD64_FAM15H_ATTRS,
2030 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l2_cache_fill_writeback),
2032 .umasks = amd64_fam15h_l2_cache_fill_writeback,
2034 { .name = "PAGE_SPLINTERING",
2035 .desc = "Page Splintering",
2036 .modmsk = AMD64_FAM15H_ATTRS,
2038 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_page_splintering),
2040 .umasks = amd64_fam15h_page_splintering,
2042 { .name = "INSTRUCTION_CACHE_FETCHES",
2043 .desc = "Instruction Cache Fetches",
2044 .modmsk = AMD64_FAM15H_ATTRS,
2047 { .name = "INSTRUCTION_CACHE_MISSES",
2048 .desc = "Instruction Cache Misses",
2049 .modmsk = AMD64_FAM15H_ATTRS,
2052 { .name = "INSTRUCTION_CACHE_REFILLS_FROM_L2",
2053 .desc = "Instruction Cache Refills from L2",
2054 .modmsk = AMD64_FAM15H_ATTRS,
2057 { .name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM",
2058 .desc = "Instruction Cache Refills from System",
2059 .modmsk = AMD64_FAM15H_ATTRS,
2062 { .name = "L1_ITLB_MISS_AND_L2_ITLB_HIT",
2063 .desc = "L1 ITLB Miss, L2 ITLB Hit",
2064 .modmsk = AMD64_FAM15H_ATTRS,
2067 { .name = "L1_ITLB_MISS_AND_L2_ITLB_MISS",
2068 .desc = "L1 ITLB Miss, L2 ITLB Miss",
2069 .modmsk = AMD64_FAM15H_ATTRS,
2071 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l1_itlb_miss_and_l2_itlb_miss),
2073 .umasks = amd64_fam15h_l1_itlb_miss_and_l2_itlb_miss,
2075 { .name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE",
2076 .desc = "Pipeline Restart Due to Instruction Stream Probe",
2077 .modmsk = AMD64_FAM15H_ATTRS,
2080 { .name = "INSTRUCTION_FETCH_STALL",
2081 .desc = "Instruction Fetch Stall",
2082 .modmsk = AMD64_FAM15H_ATTRS,
2085 { .name = "RETURN_STACK_HITS",
2086 .desc = "Return Stack Hits",
2087 .modmsk = AMD64_FAM15H_ATTRS,
2090 { .name = "RETURN_STACK_OVERFLOWS",
2091 .desc = "Return Stack Overflows",
2092 .modmsk = AMD64_FAM15H_ATTRS,
2095 { .name = "INSTRUCTION_CACHE_VICTIMS",
2096 .desc = "Instruction Cache Victims",
2097 .modmsk = AMD64_FAM15H_ATTRS,
2100 { .name = "INSTRUCTION_CACHE_INVALIDATED",
2101 .desc = "Instruction Cache Lines Invalidated",
2102 .modmsk = AMD64_FAM15H_ATTRS,
2104 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_instruction_cache_invalidated),
2106 .umasks = amd64_fam15h_instruction_cache_invalidated,
2108 { .name = "ITLB_RELOADS",
2109 .desc = "ITLB Reloads",
2110 .modmsk = AMD64_FAM15H_ATTRS,
2113 { .name = "ITLB_RELOADS_ABORTED",
2114 .desc = "ITLB Reloads Aborted",
2115 .modmsk = AMD64_FAM15H_ATTRS,
2118 { .name = "RETIRED_INSTRUCTIONS",
2119 .desc = "Retired Instructions",
2120 .modmsk = AMD64_FAM15H_ATTRS,
2123 { .name = "RETIRED_UOPS",
2124 .desc = "Retired uops",
2125 .modmsk = AMD64_FAM15H_ATTRS,
2128 { .name = "RETIRED_BRANCH_INSTRUCTIONS",
2129 .desc = "Retired Branch Instructions",
2130 .modmsk = AMD64_FAM15H_ATTRS,
2133 { .name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS",
2134 .desc = "Retired Mispredicted Branch Instructions",
2135 .modmsk = AMD64_FAM15H_ATTRS,
2138 { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS",
2139 .desc = "Retired Taken Branch Instructions",
2140 .modmsk = AMD64_FAM15H_ATTRS,
2143 { .name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED",
2144 .desc = "Retired Taken Branch Instructions Mispredicted",
2145 .modmsk = AMD64_FAM15H_ATTRS,
2148 { .name = "RETIRED_FAR_CONTROL_TRANSFERS",
2149 .desc = "Retired Far Control Transfers",
2150 .modmsk = AMD64_FAM15H_ATTRS,
2153 { .name = "RETIRED_BRANCH_RESYNCS",
2154 .desc = "Retired Branch Resyncs",
2155 .modmsk = AMD64_FAM15H_ATTRS,
2158 { .name = "RETIRED_NEAR_RETURNS",
2159 .desc = "Retired Near Returns",
2160 .modmsk = AMD64_FAM15H_ATTRS,
2163 { .name = "RETIRED_NEAR_RETURNS_MISPREDICTED",
2164 .desc = "Retired Near Returns Mispredicted",
2165 .modmsk = AMD64_FAM15H_ATTRS,
2168 { .name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED",
2169 .desc = "Retired Indirect Branches Mispredicted",
2170 .modmsk = AMD64_FAM15H_ATTRS,
2173 { .name = "RETIRED_MMX_FP_INSTRUCTIONS",
2174 .desc = "Retired MMX/FP Instructions",
2175 .modmsk = AMD64_FAM15H_ATTRS,
2177 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_retired_mmx_fp_instructions),
2179 .umasks = amd64_fam15h_retired_mmx_fp_instructions,
2181 { .name = "INTERRUPTS_MASKED_CYCLES",
2182 .desc = "Interrupts-Masked Cycles",
2183 .modmsk = AMD64_FAM15H_ATTRS,
2186 { .name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING",
2187 .desc = "Interrupts-Masked Cycles with Interrupt Pending",
2188 .modmsk = AMD64_FAM15H_ATTRS,
2191 { .name = "INTERRUPTS_TAKEN",
2192 .desc = "Interrupts Taken",
2193 .modmsk = AMD64_FAM15H_ATTRS,
2196 { .name = "DECODER_EMPTY",
2197 .desc = "Decoder Empty",
2198 .modmsk = AMD64_FAM15H_ATTRS,
2201 { .name = "DISPATCH_STALLS",
2202 .desc = "Dispatch Stalls",
2203 .modmsk = AMD64_FAM15H_ATTRS,
2206 { .name = "DISPATCH_STALL_FOR_SERIALIZATION",
2207 .desc = "Microsequencer Stall due to Serialization",
2208 .modmsk = AMD64_FAM15H_ATTRS,
2211 { .name = "DISPATCH_STALL_FOR_RETIRE_QUEUE_FULL",
2212 .desc = "Dispatch Stall for Instruction Retire Q Full",
2213 .modmsk = AMD64_FAM15H_ATTRS,
2216 { .name = "DISPATCH_STALL_FOR_INT_SCHED_QUEUE_FULL",
2217 .desc = "Dispatch Stall for Integer Scheduler Queue Full",
2218 .modmsk = AMD64_FAM15H_ATTRS,
2221 { .name = "DISPATCH_STALL_FOR_FPU_FULL",
2222 .desc = "Dispatch Stall for FP Scheduler Queue Full",
2223 .modmsk = AMD64_FAM15H_ATTRS,
2226 { .name = "DISPATCH_STALL_FOR_LDQ_FULL",
2227 .desc = "Dispatch Stall for LDQ Full",
2228 .modmsk = AMD64_FAM15H_ATTRS,
2231 { .name = "MICROSEQ_STALL_WAITING_FOR_ALL_QUIET",
2232 .desc = "Microsequencer Stall Waiting for All Quiet",
2233 .modmsk = AMD64_FAM15H_ATTRS,
2236 { .name = "FPU_EXCEPTIONS",
2237 .desc = "FPU Exceptions",
2238 .modmsk = AMD64_FAM15H_ATTRS,
2240 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_fpu_exceptions),
2242 .umasks = amd64_fam15h_fpu_exceptions,
2244 { .name = "DR0_BREAKPOINTS",
2245 .desc = "DR0 Breakpoint Match",
2246 .modmsk = AMD64_FAM15H_ATTRS,
2249 { .name = "DR1_BREAKPOINTS",
2250 .desc = "DR1 Breakpoint Match",
2251 .modmsk = AMD64_FAM15H_ATTRS,
2254 { .name = "DR2_BREAKPOINTS",
2255 .desc = "DR2 Breakpoint Match",
2256 .modmsk = AMD64_FAM15H_ATTRS,
2259 { .name = "DR3_BREAKPOINTS",
2260 .desc = "DR3 Breakpoint Match",
2261 .modmsk = AMD64_FAM15H_ATTRS,
2264 { .name = "IBS_OPS_TAGGED",
2265 .desc = "Tagged IBS Ops",
2266 .modmsk = AMD64_FAM15H_ATTRS,
2268 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_ibs_ops_tagged),
2270 .umasks = amd64_fam15h_ibs_ops_tagged,
2272 { .name = "LS_DISPATCH",
2273 .desc = "LS Dispatch",
2274 .modmsk = AMD64_FAM15H_ATTRS,
2276 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_ls_dispatch),
2278 .umasks = amd64_fam15h_ls_dispatch,
2280 { .name = "EXECUTED_CLFLUSH_INSTRUCTIONS",
2281 .desc = "Executed CLFLUSH Instructions",
2282 .modmsk = AMD64_FAM15H_ATTRS,
2285 { .name = "L2_PREFETCHER_TRIGGER_EVENTS",
2286 .desc = "L2 Prefetcher Trigger Events",
2287 .modmsk = AMD64_FAM15H_ATTRS,
2289 .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l2_prefetcher_trigger_events),
2291 .umasks = amd64_fam15h_l2_prefetcher_trigger_events,
2293 { .name = "DISPATCH_STALL_FOR_STQ_FULL",
2294 .desc = "Dispatch Stall for STQ Full",
2295 .modmsk = AMD64_FAM15H_ATTRS,