vmm: Fix use-after-free in load_elf()
[akaros.git] / user / perfmon / events / amd64_events_fam12h.h
1 /*
2  * Copyright (c) 2011 University of Tennessee
3  * Contributed by Vince Weaver <vweaver1@utk.edu>
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a copy
6  * of this software and associated documentation files (the "Software"), to deal
7  * in the Software without restriction, including without limitation the rights
8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
9  * of the Software, and to permit persons to whom the Software is furnished to do so,
10  * subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in all
13  * copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
16  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
17  * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
18  * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
19  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
20  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * This file is part of libpfm, a performance monitoring support library for
23  * applications on Linux.
24  *
25  * PMU: amd64_fam12h (AMD64 Fam12h)
26  */
27
28 static const amd64_umask_t amd64_fam12h_dispatched_fpu[]={
29    { .uname  = "OPS_ADD",
30      .udesc  = "Add pipe ops excluding load ops and SSE move ops",
31      .ucode = 0x1,
32    },
33    { .uname  = "OPS_MULTIPLY",
34      .udesc  = "Multiply pipe ops excluding load ops and SSE move ops",
35      .ucode = 0x2,
36    },
37    { .uname  = "OPS_STORE",
38      .udesc  = "Store pipe ops excluding load ops and SSE move ops",
39      .ucode = 0x4,
40    },
41    { .uname  = "OPS_ADD_PIPE_LOAD_OPS",
42      .udesc  = "Add pipe load ops and SSE move ops",
43      .ucode = 0x8,
44    },
45    { .uname  = "OPS_MULTIPLY_PIPE_LOAD_OPS",
46      .udesc  = "Multiply pipe load ops and SSE move ops",
47      .ucode = 0x10,
48    },
49    { .uname  = "OPS_STORE_PIPE_LOAD_OPS",
50      .udesc  = "Store pipe load ops and SSE move ops",
51      .ucode = 0x20,
52    },
53    { .uname  = "ALL",
54      .udesc  = "All sub-events selected",
55      .ucode = 0x3f,
56      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
57    },
58 };
59
60 static const amd64_umask_t amd64_fam12h_retired_sse_operations[]={
61    { .uname  = "SINGLE_ADD_SUB_OPS",
62      .udesc  = "Single precision add/subtract ops",
63      .ucode = 0x1,
64    },
65    { .uname  = "SINGLE_MUL_OPS",
66      .udesc  = "Single precision multiply ops",
67      .ucode = 0x2,
68    },
69    { .uname  = "SINGLE_DIV_OPS",
70      .udesc  = "Single precision divide/square root ops",
71      .ucode = 0x4,
72    },
73    { .uname  = "DOUBLE_ADD_SUB_OPS",
74      .udesc  = "Double precision add/subtract ops",
75      .ucode = 0x8,
76    },
77    { .uname  = "DOUBLE_MUL_OPS",
78      .udesc  = "Double precision multiply ops",
79      .ucode = 0x10,
80    },
81    { .uname  = "DOUBLE_DIV_OPS",
82      .udesc  = "Double precision divide/square root ops",
83      .ucode = 0x20,
84    },
85    { .uname  = "OP_TYPE",
86      .udesc  = "Op type: 0=uops. 1=FLOPS",
87      .ucode = 0x40,
88    },
89    { .uname  = "ALL",
90      .udesc  = "All sub-events selected",
91      .ucode = 0x7f,
92      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
93    },
94 };
95
96 static const amd64_umask_t amd64_fam12h_retired_move_ops[]={
97    { .uname  = "LOW_QW_MOVE_UOPS",
98      .udesc  = "Merging low quadword move uops",
99      .ucode = 0x1,
100    },
101    { .uname  = "HIGH_QW_MOVE_UOPS",
102      .udesc  = "Merging high quadword move uops",
103      .ucode = 0x2,
104    },
105    { .uname  = "ALL_OTHER_MERGING_MOVE_UOPS",
106      .udesc  = "All other merging move uops",
107      .ucode = 0x4,
108    },
109    { .uname  = "ALL_OTHER_MOVE_UOPS",
110      .udesc  = "All other move uops",
111      .ucode = 0x8,
112    },
113    { .uname  = "ALL",
114      .udesc  = "All sub-events selected",
115      .ucode = 0xf,
116      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
117    },
118 };
119
120 static const amd64_umask_t amd64_fam12h_retired_serializing_ops[]={
121    { .uname  = "SSE_BOTTOM_EXECUTING_UOPS",
122      .udesc  = "SSE bottom-executing uops retired",
123      .ucode = 0x1,
124    },
125    { .uname  = "SSE_BOTTOM_SERIALIZING_UOPS",
126      .udesc  = "SSE bottom-serializing uops retired",
127      .ucode = 0x2,
128    },
129    { .uname  = "X87_BOTTOM_EXECUTING_UOPS",
130      .udesc  = "X87 bottom-executing uops retired",
131      .ucode = 0x4,
132    },
133    { .uname  = "X87_BOTTOM_SERIALIZING_UOPS",
134      .udesc  = "X87 bottom-serializing uops retired",
135      .ucode = 0x8,
136    },
137    { .uname  = "ALL",
138      .udesc  = "All sub-events selected",
139      .ucode = 0xf,
140      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
141    },
142 };
143 static const amd64_umask_t amd64_fam12h_fp_scheduler_cycles[]={
144    { .uname  = "BOTTOM_EXECUTE_CYCLES",
145      .udesc  = "Number of cycles a bottom-execute uop is in the FP scheduler",
146      .ucode = 0x1,
147    },
148    { .uname  = "BOTTOM_SERIALIZING_CYCLES",
149      .udesc  = "Number of cycles a bottom-serializing uop is in the FP scheduler",
150      .ucode = 0x2,
151    },
152    { .uname  = "ALL",
153      .udesc  = "All sub-events selected",
154      .ucode = 0x3,
155      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
156    },
157 };
158
159 static const amd64_umask_t amd64_fam12h_segment_register_loads[]={
160    { .uname  = "ES",
161      .udesc  = "ES",
162      .ucode = 0x1,
163    },
164    { .uname  = "CS",
165      .udesc  = "CS",
166      .ucode = 0x2,
167    },
168    { .uname  = "SS",
169      .udesc  = "SS",
170      .ucode = 0x4,
171    },
172    { .uname  = "DS",
173      .udesc  = "DS",
174      .ucode = 0x8,
175    },
176    { .uname  = "FS",
177      .udesc  = "FS",
178      .ucode = 0x10,
179    },
180    { .uname  = "GS",
181      .udesc  = "GS",
182      .ucode = 0x20,
183    },
184    { .uname  = "HS",
185      .udesc  = "HS",
186      .ucode = 0x40,
187    },
188    { .uname  = "ALL",
189      .udesc  = "All sub-events selected",
190      .ucode = 0x7f,
191      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
192    },
193 };
194
195 static const amd64_umask_t amd64_fam12h_locked_ops[]={
196    { .uname  = "EXECUTED",
197      .udesc  = "The number of locked instructions executed",
198      .ucode = 0x1,
199    },
200    { .uname  = "CYCLES_SPECULATIVE_PHASE",
201      .udesc  = "The number of cycles spent in speculative phase",
202      .ucode = 0x2,
203    },
204    { .uname  = "CYCLES_NON_SPECULATIVE_PHASE",
205      .udesc  = "The number of cycles spent in non-speculative phase (including cache miss penalty)",
206      .ucode = 0x4,
207    },
208    { .uname  = "CYCLES_WAITING",
209      .udesc  = "The number of cycles waiting for a cache hit (cache miss penalty).",
210      .ucode = 0x8,
211    },
212    { .uname  = "ALL",
213      .udesc  = "All sub-events selected",
214      .ucode = 0xf,
215      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
216    },
217 };
218
219 static const amd64_umask_t amd64_fam12h_cancelled_store_to_load_forward_operations[]={
220    { .uname  = "ADDRESS_MISMATCHES",
221      .udesc  = "Address mismatches (starting byte not the same).",
222      .ucode = 0x1,
223    },
224    { .uname  = "STORE_IS_SMALLER_THAN_LOAD",
225      .udesc  = "Store is smaller than load.",
226      .ucode = 0x2,
227    },
228    { .uname  = "MISALIGNED",
229      .udesc  = "Misaligned.",
230      .ucode = 0x4,
231    },
232    { .uname  = "ALL",
233      .udesc  = "All sub-events selected",
234      .ucode = 0x7,
235      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
236    },
237 };
238
239 static const amd64_umask_t amd64_fam12h_data_cache_refills[]={
240    { .uname  = "SYSTEM",
241      .udesc  = "Refill from the Northbridge",
242      .ucode = 0x1,
243    },
244    { .uname  = "L2_SHARED",
245      .udesc  = "Shared-state line from L2",
246      .ucode = 0x2,
247    },
248    { .uname  = "L2_EXCLUSIVE",
249      .udesc  = "Exclusive-state line from L2",
250      .ucode = 0x4,
251    },
252    { .uname  = "L2_OWNED",
253      .udesc  = "Owned-state line from L2",
254      .ucode = 0x8,
255    },
256    { .uname  = "L2_MODIFIED",
257      .udesc  = "Modified-state line from L2",
258      .ucode = 0x10,
259    },
260    { .uname  = "ALL",
261      .udesc  = "All sub-events selected",
262      .ucode = 0x1f,
263      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
264    },
265 };
266
267 static const amd64_umask_t amd64_fam12h_data_cache_refills_from_northbridge[]={
268    { .uname  = "INVALID",
269      .udesc  = "Invalid",
270      .ucode = 0x1,
271    },
272    { .uname  = "SHARED",
273      .udesc  = "Shared",
274      .ucode = 0x2,
275    },
276    { .uname  = "EXCLUSIVE",
277      .udesc  = "Exclusive",
278      .ucode = 0x4,
279    },
280    { .uname  = "OWNED",
281      .udesc  = "Owned",
282      .ucode = 0x8,
283    },
284    { .uname  = "MODIFIED",
285      .udesc  = "Modified",
286      .ucode = 0x10,
287    },
288    { .uname  = "ALL",
289      .udesc  = "All sub-events selected",
290      .ucode = 0x1f,
291      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
292    },
293 };
294
295 static const amd64_umask_t amd64_fam12h_data_cache_lines_evicted[]={
296    { .uname  = "INVALID",
297      .udesc  = "Invalid",
298      .ucode = 0x1,
299    },
300    { .uname  = "SHARED",
301      .udesc  = "Shared",
302      .ucode = 0x2,
303    },
304    { .uname  = "EXCLUSIVE",
305      .udesc  = "Exclusive",
306      .ucode = 0x4,
307    },
308    { .uname  = "OWNED",
309      .udesc  = "Owned",
310      .ucode = 0x8,
311    },
312    { .uname  = "MODIFIED",
313      .udesc  = "Modified",
314      .ucode = 0x10,
315    },
316    { .uname  = "BY_PREFETCHNTA",
317      .udesc  = "Cache line evicted was brought into the cache with by a PrefetchNTA instruction.",
318      .ucode = 0x20,
319    },
320    { .uname  = "NOT_BY_PREFETCHNTA",
321      .udesc  = "Cache line evicted was not brought into the cache with by a PrefetchNTA instruction.",
322      .ucode = 0x40,
323    },
324    { .uname  = "ALL",
325      .udesc  = "All sub-events selected",
326      .ucode = 0x7f,
327      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
328    },
329 };
330
331 static const amd64_umask_t amd64_fam12h_l1_dtlb_miss_and_l2_dtlb_hit[]={
332    { .uname  = "L2_4K_TLB_HIT",
333      .udesc  = "L2 4K TLB hit",
334      .ucode = 0x1,
335    },
336    { .uname  = "L2_2M_TLB_HIT",
337      .udesc  = "L2 2M TLB hit",
338      .ucode = 0x2,
339    },
340    { .uname  = "L2_1G_TLB_HIT",
341      .udesc  = "L2 1G TLB hit",
342      .ucode = 0x4,
343    },
344    { .uname  = "ALL",
345      .udesc  = "All sub-events selected",
346      .ucode = 0x7,
347      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL, 
348    },
349 };
350
351 static const amd64_umask_t amd64_fam12h_l1_dtlb_and_l2_dtlb_miss[]={
352    { .uname  = "4K_TLB_RELOAD",
353      .udesc  = "4K TLB reload",
354      .ucode = 0x1,
355    },
356    { .uname  = "2M_TLB_RELOAD",
357      .udesc  = "2M TLB reload",
358      .ucode = 0x2,
359    },
360    { .uname  = "1G_TLB_RELOAD",
361      .udesc  = "1G TLB reload",
362      .ucode = 0x4,
363    },
364    { .uname  = "ALL",
365      .udesc  = "All sub-events selected",
366      .ucode = 0x7,
367      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
368    },
369 };
370
371 static const amd64_umask_t amd64_fam12h_prefetch_instructions_dispatched[]={
372    { .uname  = "LOAD",
373      .udesc  = "Load (Prefetch, PrefetchT0/T1/T2)",
374      .ucode = 0x1,
375    },
376    { .uname  = "STORE",
377      .udesc  = "Store (PrefetchW)",
378      .ucode = 0x2,
379    },
380    { .uname  = "NTA",
381      .udesc  = "NTA (PrefetchNTA)",
382      .ucode = 0x4,
383    },
384    { .uname  = "ALL",
385      .udesc  = "All sub-events selected",
386      .ucode = 0x7,
387      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
388    },
389 };
390
391 static const amd64_umask_t amd64_fam12h_dcache_misses_by_locked_instructions[]={
392    { .uname  = "DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONS",
393      .udesc  = "Data cache misses by locked instructions",
394      .ucode = 0x2,
395    },
396    { .uname  = "ALL",
397      .udesc  = "All sub-events selected",
398      .ucode = 0x2,
399      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
400    },
401 };
402
403 static const amd64_umask_t amd64_fam12h_l1_dtlb_hit[]={
404    { .uname  = "L1_4K_TLB_HIT",
405      .udesc  = "L1 4K TLB hit",
406      .ucode = 0x1,
407    },
408    { .uname  = "L1_2M_TLB_HIT",
409      .udesc  = "L1 2M TLB hit",
410      .ucode = 0x2,
411    },
412    { .uname  = "L1_1G_TLB_HIT",
413      .udesc  = "L1 1G TLB hit",
414      .ucode = 0x4,
415    },
416    { .uname  = "ALL",
417      .udesc  = "All sub-events selected",
418      .ucode = 0x7,
419      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
420    },
421 };
422
423 static const amd64_umask_t amd64_fam12h_ineffective_sw_prefetches[]={
424    { .uname  = "SW_PREFETCH_HIT_IN_L1",
425      .udesc  = "Software prefetch hit in the L1.",
426      .ucode = 0x1,
427    },
428    { .uname  = "SW_PREFETCH_HIT_IN_L2",
429      .udesc  = "Software prefetch hit in L2.",
430      .ucode = 0x8,
431    },
432    { .uname  = "ALL",
433      .udesc  = "All sub-events selected",
434      .ucode = 0x9,
435      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
436    },
437 };
438
439 static const amd64_umask_t amd64_fam12h_memory_requests[]={
440    { .uname  = "NON_CACHEABLE",
441      .udesc  = "Requests to non-cacheable (UC) memory",
442      .ucode = 0x1,
443    },
444    { .uname  = "WRITE_COMBINING",
445      .udesc  = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory",
446      .ucode = 0x2,
447    },
448    { .uname  = "CACHE_DISABLED",
449      .udesc  = "Requests to cache-disabled (CD) memory",
450      .ucode = 0x4,
451    },
452    { .uname  = "STREAMING_STORE",
453      .udesc  = "Streaming store (SS) requests",
454      .ucode = 0x80,
455    },
456    { .uname  = "ALL",
457      .udesc  = "All sub-events selected",
458      .ucode = 0x87,
459      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
460    },
461 };
462
463 static const amd64_umask_t amd64_fam12h_data_prefetches[]={
464    { .uname  = "CANCELLED",
465      .udesc  = "Cancelled prefetches",
466      .ucode = 0x1,
467    },
468    { .uname  = "ATTEMPTED",
469      .udesc  = "Prefetch attempts",
470      .ucode = 0x2,
471    },
472    { .uname  = "ALL",
473      .udesc  = "All sub-events selected",
474      .ucode = 0x3,
475      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
476    },
477 };
478
479 static const amd64_umask_t amd64_fam12h_northbridge_read_responses[]={
480    { .uname  = "EXCLUSIVE",
481      .udesc  = "Exclusive",
482      .ucode = 0x1,
483    },
484    { .uname  = "MODIFIED",
485      .udesc  = "Modified",
486      .ucode = 0x2,
487    },
488    { .uname  = "SHARED",
489      .udesc  = "Shared",
490      .ucode = 0x4,
491    },
492    { .uname  = "OWNED",
493      .udesc  = "Owned",
494      .ucode = 0x8,
495    },
496    { .uname  = "DATA_ERROR",
497      .udesc  = "Data Error",
498      .ucode = 0x10,
499    },
500    { .uname  = "ALL",
501      .udesc  = "All sub-events selected",
502      .ucode = 0x1f,
503      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
504    },
505 };
506
507 static const amd64_umask_t amd64_fam12h_octwords_written_to_system[]={
508    { .uname  = "OCTWORD_WRITE_TRANSFER",
509      .udesc  = "Octword write transfer",
510      .ucode = 0x1,
511    },
512    { .uname  = "ALL",
513      .udesc  = "All sub-events selected",
514      .ucode = 0x1,
515      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
516    },
517 };
518
519 static const amd64_umask_t amd64_fam12h_requests_to_l2[]={
520    { .uname  = "INSTRUCTIONS",
521      .udesc  = "IC fill",
522      .ucode = 0x1,
523    },
524    { .uname  = "DATA",
525      .udesc  = "DC fill",
526      .ucode = 0x2,
527    },
528    { .uname  = "TLB_WALK",
529      .udesc  = "TLB fill (page table walks)",
530      .ucode = 0x4,
531    },
532    { .uname  = "SNOOP",
533      .udesc  = "Tag snoop request",
534      .ucode = 0x8,
535    },
536    { .uname  = "CANCELLED",
537      .udesc  = "Cancelled request",
538      .ucode = 0x10,
539    },
540    { .uname  = "HW_PREFETCH_FROM_DC",
541      .udesc  = "Hardware prefetch from DC",
542      .ucode = 0x20,
543    },
544    { .uname  = "ALL",
545      .udesc  = "All sub-events selected",
546      .ucode = 0x3f,
547      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
548    },
549 };
550
551 static const amd64_umask_t amd64_fam12h_l2_cache_miss[]={
552    { .uname  = "INSTRUCTIONS",
553      .udesc  = "IC fill",
554      .ucode = 0x1,
555    },
556    { .uname  = "DATA",
557      .udesc  = "DC fill (includes possible replays, whereas EventSelect 041h does not)",
558      .ucode = 0x2,
559    },
560    { .uname  = "TLB_WALK",
561      .udesc  = "TLB page table walk",
562      .ucode = 0x4,
563    },
564    { .uname  = "HW_PREFETCH_FROM_DC",
565      .udesc  = "Hardware prefetch from DC",
566      .ucode = 0x8,
567    },
568    { .uname  = "ALL",
569      .udesc  = "All sub-events selected",
570      .ucode = 0xf,
571      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
572    },
573 };
574
575 static const amd64_umask_t amd64_fam12h_l2_fill_writeback[]={
576    { .uname  = "L2_FILLS",
577      .udesc  = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)",
578      .ucode = 0x1,
579    },
580    { .uname  = "L2_WRITEBACKS",
581      .udesc  = "L2 Writebacks to system.",
582      .ucode = 0x2,
583    },
584    { .uname  = "ALL",
585      .udesc  = "All sub-events selected",
586      .ucode = 0x3,
587      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
588    },
589 };
590
591 static const amd64_umask_t amd64_fam12h_l1_itlb_miss_and_l2_itlb_miss[]={
592    { .uname  = "4K_PAGE_FETCHES",
593      .udesc  = "Instruction fetches to a 4K page.",
594      .ucode = 0x1,
595    },
596    { .uname  = "2M_PAGE_FETCHES",
597      .udesc  = "Instruction fetches to a 2M page.",
598      .ucode = 0x2,
599    },
600    { .uname  = "ALL",
601      .udesc  = "All sub-events selected",
602      .ucode = 0x3,
603      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
604    },
605 };
606
607 static const amd64_umask_t amd64_fam12h_instruction_cache_lines_invalidated[]={
608    { .uname  = "INVALIDATING_PROBE_NO_IN_FLIGHT",
609      .udesc  = "Invalidating probe that did not hit any in-flight instructions.",
610      .ucode = 0x1,
611    },
612    { .uname  = "INVALIDATING_PROBE_ONE_OR_MORE_IN_FLIGHT",
613      .udesc  = "Invalidating probe that hit one or more in-flight instructions.",
614      .ucode = 0x2,
615    },
616    { .uname  = "SMC_NO_INFLIGHT",
617      .udesc  = "SMC that did not hit any in-flight instructions.",
618      .ucode = 0x4,
619    },
620    { .uname  = "SMC_INFLIGHT",
621      .udesc  = "SMC that hit one or more in-flight instructions.",
622      .ucode = 0x8,
623    },
624    { .uname  = "ALL",
625      .udesc  = "All sub-events selected",
626      .ucode = 0xf,
627      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
628    },
629 };
630
631 static const amd64_umask_t amd64_fam12h_retired_mmx_and_fp_instructions[]={
632    { .uname  = "X87",
633      .udesc  = "X87 instructions",
634      .ucode = 0x1,
635    },
636    { .uname  = "MMX_AND_3DNOW",
637      .udesc  = "MMX and 3DNow! instructions",
638      .ucode = 0x2,
639    },
640    { .uname  = "SSE_AND_SSE2",
641      .udesc  = "SSE and SSE2 instructions",
642      .ucode = 0x4,
643    },
644    { .uname  = "ALL",
645      .udesc  = "All sub-events selected",
646      .ucode = 0x7,
647      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
648    },
649 };
650
651 static const amd64_umask_t amd64_fam12h_interrupt_events[]={
652    { .uname  = "FIXED_AND_LPA",
653      .udesc  = "Fixed and LPA",
654      .ucode = 0x1,
655    },
656    { .uname  = "LPA",
657      .udesc  = "LPA",
658      .ucode = 0x2,
659    },
660    { .uname  = "SMI",
661      .udesc  = "SMI",
662      .ucode = 0x4,
663    },
664    { .uname  = "NMI",
665      .udesc  = "NMI",
666      .ucode = 0x8,
667    },
668    { .uname  = "INIT",
669      .udesc  = "INIT",
670      .ucode = 0x10,
671    },
672    { .uname  = "STARTUP",
673      .udesc  = "STARTUP",
674      .ucode = 0x20,
675    },
676    { .uname  = "INT",
677      .udesc  = "INT",
678      .ucode = 0x40,
679    },
680    { .uname  = "EOI",
681      .udesc  = "EOI",
682      .ucode = 0x80,
683    },
684    { .uname  = "ALL",
685      .udesc  = "All sub-events selected",
686      .ucode = 0xff,
687      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
688    },
689 };
690
691 static const amd64_umask_t amd64_fam12h_sideband_signals[]={
692    { .uname  = "STOPGRANT",
693      .udesc  = "STOPGRANT",
694      .ucode = 0x2,
695    },
696    { .uname  = "SHUTDOWN",
697      .udesc  = "SHUTDOWN",
698      .ucode = 0x4,
699    },
700    { .uname  = "WBINVD",
701      .udesc  = "WBINVD",
702      .ucode = 0x8,
703    },
704    { .uname  = "INVD",
705      .udesc  = "INVD",
706      .ucode = 0x10,
707    },
708    { .uname  = "ALL",
709      .udesc  = "All sub-events selected",
710      .ucode = 0x1e,
711      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
712    },
713 };
714
715 static const amd64_umask_t amd64_fam12h_fpu_exceptions[]={
716    { .uname  = "X87_RECLASS_MICROFAULTS",
717      .udesc  = "X87 reclass microfaults",
718      .ucode = 0x1,
719    },
720    { .uname  = "SSE_RETYPE_MICROFAULTS",
721      .udesc  = "SSE retype microfaults",
722      .ucode = 0x2,
723    },
724    { .uname  = "SSE_RECLASS_MICROFAULTS",
725      .udesc  = "SSE reclass microfaults",
726      .ucode = 0x4,
727    },
728    { .uname  = "SSE_AND_X87_MICROTRAPS",
729      .udesc  = "SSE and x87 microtraps",
730      .ucode = 0x8,
731    },
732    { .uname  = "ALL",
733      .udesc  = "All sub-events selected",
734      .ucode = 0xf,
735      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
736    },
737 };
738
739 static const amd64_umask_t amd64_fam12h_dram_accesses_page[]={
740    { .uname  = "DCT0_HIT",
741      .udesc  = "DCT0 Page hit",
742      .ucode = 0x1,
743    },
744    { .uname  = "DCT0_MISS",
745      .udesc  = "DCT0 Page Miss",
746      .ucode = 0x2,
747    },
748    { .uname  = "DCT0_CONFLICT",
749      .udesc  = "DCT0 Page Conflict",
750      .ucode = 0x4,
751    },
752    { .uname  = "DCT1_PAGE_HIT",
753      .udesc  = "DCT1 Page hit",
754      .ucode = 0x8,
755    },
756    { .uname  = "DCT1_PAGE_MISS",
757      .udesc  = "DCT1 Page Miss",
758      .ucode = 0x10,
759    },
760    { .uname  = "DCT1_PAGE_CONFLICT",
761      .udesc  = "DCT1 Page Conflict",
762      .ucode = 0x20,
763    },
764    { .uname  = "WRITE_REQUEST",
765      .udesc  = "Write request.",
766      .ucode = 0x40,
767    },
768    { .uname  = "READ_REQUEST",
769      .udesc  = "Read request.",
770      .ucode = 0x80,
771    },
772    { .uname  = "ALL",
773      .udesc  = "All sub-events selected",
774      .ucode = 0xff,
775      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
776    },
777 };
778
779 static const amd64_umask_t amd64_fam12h_memory_controller_page_table_events[]={
780    { .uname  = "PAGE_TABLE_OVERFLOW",
781      .udesc  = "Page Table Overflow",
782      .ucode = 0x1,
783    },
784    { .uname  = "STALE_TABLE_ENTRY_HITS",
785      .udesc  = "Number of stale table entry hits. (hit on a page closed too soon).",
786      .ucode = 0x2,
787    },
788    { .uname  = "PAGE_TABLE_IDLE_CYCLE_LIMIT_INCREMENTED",
789      .udesc  = "Page table idle cycle limit incremented.",
790      .ucode = 0x4,
791    },
792    { .uname  = "PAGE_TABLE_IDLE_CYCLE_LIMIT_DECREMENTED",
793      .udesc  = "Page table idle cycle limit decremented.",
794      .ucode = 0x8,
795    },
796    { .uname  = "PAGE_TABLE_CLOSED_INACTIVITY",
797      .udesc  = "Page table is closed due to row inactivity.",
798      .ucode = 0x10,
799    },
800    { .uname  = "ALL",
801      .udesc  = "All sub-events selected",
802      .ucode = 0x1f,
803      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
804    },
805 };
806
807 static const amd64_umask_t amd64_fam12h_memory_controller_slot_misses[]={
808    { .uname  = "DCT0_RBD",
809      .udesc  = "DCT0 RBD.",
810      .ucode = 0x10,
811    },
812    { .uname  = "DCT1_RBD",
813      .udesc  = "DCT1 RBD.",
814      .ucode = 0x20,
815    },
816    { .uname  = "DCT0_PREFETCH",
817      .udesc  = "DCT0 Prefetch.",
818      .ucode = 0x40,
819    },
820    { .uname  = "DCT1_PREFETCH",
821      .udesc  = "DCT1 Prefetch.",
822      .ucode = 0x80,
823    },
824    { .uname  = "ALL",
825      .udesc  = "All sub-events selected",
826      .ucode = 0xf0,
827      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
828    },
829 };
830
831 static const amd64_umask_t amd64_fam12h_memory_controller_turnarounds[]={
832    { .uname  = "DCT0_READ_TO_WRITE",
833      .udesc  = "DCT0 read-to-write turnaround.",
834      .ucode = 0x1,
835    },
836    { .uname  = "DCT0_WRITE_TO_READ",
837      .udesc  = "DCT0 write-to-read turnaround",
838      .ucode = 0x2,
839    },
840    { .uname  = "DCT1_READ_TO_WRITE",
841      .udesc  = "DCT1 read-to-write turnaround.",
842      .ucode = 0x8,
843    },
844    { .uname  = "DCT1_WRITE_TO_READ",
845      .udesc  = "DCT1 write-to-read turnaround",
846      .ucode = 0x10,
847    },
848    { .uname  = "ALL",
849      .udesc  = "All sub-events selected",
850      .ucode = 0x1b,
851      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
852    },
853 };
854
855 static const amd64_umask_t amd64_fam12h_memory_rbd_queue[]={
856    { .uname  = "COUNTER_REACHED",
857      .udesc  = "D18F2x[1,0]94[DcqBypassMax] counter reached.",
858      .ucode = 0x4,
859    },
860    { .uname  = "BANK_CLOSED",
861      .udesc  = "Bank is closed due to bank conflict with an outstanding request in the RBD queue.",
862      .ucode = 0x8,
863    },
864    { .uname  = "ALL",
865      .udesc  = "All sub-events selected",
866      .ucode = 0xc,
867      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
868    },
869 };
870
871 static const amd64_umask_t amd64_fam12h_thermal_status[]={
872    { .uname  = "MEMHOT_L_ASSERTIONS",
873      .udesc  = "MEMHOT_L assertions.",
874      .ucode = 0x1,
875    },
876    { .uname  = "HTC_TRANSITIONS",
877      .udesc  = "Number of times the HTC transitions from inactive to active.",
878      .ucode = 0x4,
879    },
880    { .uname  = "CLOCKS_HTC_P_STATE_INACTIVE",
881      .udesc  = "Number of clocks HTC P-state is inactive.",
882      .ucode = 0x20,
883    },
884    { .uname  = "CLOCKS_HTC_P_STATE_ACTIVE",
885      .udesc  = "Number of clocks HTC P-state is active",
886      .ucode = 0x40,
887    },
888    { .uname  = "PROCHOT_L_ASSERTIONS",
889      .udesc  = "PROCHOT_L asserted by an external source and the assertion causes a P-state change.",
890      .ucode = 0x80,
891    },
892    { .uname  = "ALL",
893      .udesc  = "All sub-events selected",
894      .ucode = 0xe5,
895      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
896    },
897 };
898
899 static const amd64_umask_t amd64_fam12h_cpu_io_requests_to_memory_io[]={
900    { .uname  = "I_O_TO_I_O",
901      .udesc  = "IO to IO",
902      .ucode = 0x1,
903    },
904    { .uname  = "I_O_TO_MEM",
905      .udesc  = "IO to Mem",
906      .ucode = 0x2,
907    },
908    { .uname  = "CPU_TO_I_O",
909      .udesc  = "CPU to IO",
910      .ucode = 0x4,
911    },
912    { .uname  = "CPU_TO_MEM",
913      .udesc  = "CPU to Mem",
914      .ucode = 0x8,
915    },
916    { .uname  = "ALL",
917      .udesc  = "All sub-events selected",
918      .ucode = 0x0f,
919      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
920    },
921 };
922
923 static const amd64_umask_t amd64_fam12h_cache_block[]={
924    { .uname  = "VICTIM_WRITEBACK",
925      .udesc  = "Victim Block (Writeback)",
926      .ucode = 0x1,
927    },
928    { .uname  = "DCACHE_LOAD_MISS",
929      .udesc  = "Read Block (Dcache load miss refill)",
930      .ucode = 0x4,
931    },
932    { .uname  = "SHARED_ICACHE_REFILL",
933      .udesc  = "Read Block Shared (Icache refill)",
934      .ucode = 0x8,
935    },
936    { .uname  = "READ_BLOCK_MODIFIED",
937      .udesc  = "Read Block Modified (Dcache store miss refill)",
938      .ucode = 0x10,
939    },
940    { .uname  = "READ_TO_DIRTY",
941      .udesc  = "Change-to-Dirty (first store to clean block already in cache)",
942      .ucode = 0x20,
943    },
944    { .uname  = "ALL",
945      .udesc  = "All sub-events selected",
946      .ucode = 0x3d,
947      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
948    },
949 };
950
951 static const amd64_umask_t amd64_fam12h_sized_commands[]={
952    { .uname  = "NON_POSTED_WRITE_BYTE",
953      .udesc  = "Non-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytes",
954      .ucode = 0x1,
955    },
956    { .uname  = "NON_POSTED_WRITE_DWORD",
957      .udesc  = "Non-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORD",
958      .ucode = 0x2,
959    },
960    { .uname  = "POSTED_WRITE_BYTE",
961      .udesc  = "Posted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer",
962      .ucode = 0x4,
963    },
964    { .uname  = "POSTED_WRITE_DWORD",
965      .udesc  = "Posted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes",
966      .ucode = 0x8,
967    },
968    { .uname  = "READ_BYTE_4_BYTES",
969      .udesc  = "SzRd Byte (4 bytes) Legacy or mapped IO",
970      .ucode = 0x10,
971    },
972    { .uname  = "READ_DWORD_1_16_DWORDS",
973      .udesc  = "SzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size",
974      .ucode = 0x20,
975    },
976    { .uname  = "ALL",
977      .udesc  = "All sub-events selected",
978      .ucode = 0x3f,
979      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
980    },
981 };
982
983 static const amd64_umask_t amd64_fam12h_probe[]={
984    { .uname  = "MISS",
985      .udesc  = "Probe miss",
986      .ucode = 0x1,
987    },
988    { .uname  = "HIT_CLEAN",
989      .udesc  = "Probe hit clean",
990      .ucode = 0x2,
991    },
992    { .uname  = "HIT_DIRTY_NO_MEMORY_CANCEL",
993      .udesc  = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)",
994      .ucode = 0x4,
995    },
996    { .uname  = "HIT_DIRTY_WITH_MEMORY_CANCEL",
997      .udesc  = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)",
998      .ucode = 0x8,
999    },
1000    { .uname  = "UPSTREAM_HIGH_PRIORITY_READS",
1001      .udesc  = "Upstream high priority reads.",
1002      .ucode = 0x10,
1003    },
1004    { .uname  = "UPSTREAM_LOW_PRIORITY_READS",
1005      .udesc  = "Upstream low priority reads.",
1006      .ucode = 0x20,
1007    },
1008    { .uname  = "UPSTREAM_LOW_PRIORITY_WRITES",
1009      .udesc  = "Upstream low priority writes.",
1010      .ucode = 0x80,
1011    },
1012    { .uname  = "ALL",
1013      .udesc  = "All sub-events selected",
1014      .ucode = 0xbf,
1015      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1016    },
1017 };
1018
1019 static const amd64_umask_t amd64_fam12h_dev[]={
1020    { .uname  = "DEV_HIT",
1021      .udesc  = "DEV hit",
1022      .ucode = 0x10,
1023    },
1024    { .uname  = "DEV_MISS",
1025      .udesc  = "DEV miss",
1026      .ucode = 0x20,
1027    },
1028    { .uname  = "DEV_ERROR",
1029      .udesc  = "DEV error",
1030      .ucode = 0x40,
1031    },
1032    { .uname  = "ALL",
1033      .udesc  = "All sub-events selected",
1034      .ucode = 0x70,
1035      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1036    },
1037 };
1038
1039 static const amd64_umask_t amd64_fam12h_memory_controller_requests[]={
1040    { .uname  = "32_BYTES_WRITES",
1041      .udesc  = "32 Bytes Sized Writes",
1042      .ucode = 0x8,
1043    },
1044    { .uname  = "64_BYTES_WRITES",
1045      .udesc  = "64 Bytes Sized Writes",
1046      .ucode = 0x10,
1047    },
1048    { .uname  = "32_BYTES_READS",
1049      .udesc  = "32 Bytes Sized Reads",
1050      .ucode = 0x20,
1051    },
1052    { .uname  = "64_BYTES_READS",
1053      .udesc  = "64 Byte Sized Reads",
1054      .ucode = 0x40,
1055    },
1056    { .uname  = "ALL",
1057      .udesc  = "All sub-events selected",
1058      .ucode = 0x78,
1059      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1060    },
1061 };
1062
1063 static const amd64_umask_t amd64_fam12h_page_size_mismatches[]={
1064    { .uname  = "GUEST_LARGER",
1065      .udesc  = "Guest page size is larger than the host page size.",
1066      .ucode = 0x1,
1067    },
1068    { .uname  = "MTRR_MISMATCH",
1069      .udesc  = "MTRR mismatch.",
1070      .ucode = 0x2,
1071    },
1072    { .uname  = "HOST_LARGER",
1073      .udesc  = "Host page size is larger than the guest page size.",
1074      .ucode = 0x4,
1075    },
1076    { .uname  = "ALL",
1077      .udesc  = "All sub-events selected",
1078      .ucode = 0x7,
1079      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1080    },
1081 };
1082 static const amd64_umask_t amd64_fam12h_retired_x87_ops[]={
1083    { .uname  = "ADD_SUB_OPS",
1084      .udesc  = "Add/subtract ops",
1085      .ucode = 0x1,
1086    },
1087    { .uname  = "MUL_OPS",
1088      .udesc  = "Multiply ops",
1089      .ucode = 0x2,
1090    },
1091    { .uname  = "DIV_OPS",
1092      .udesc  = "Divide ops",
1093      .ucode = 0x4,
1094    },
1095    { .uname  = "ALL",
1096      .udesc  = "All sub-events selected",
1097      .ucode = 0x7,
1098      .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
1099    },
1100 };
1101
1102 static const amd64_entry_t amd64_fam12h_pe[]={
1103 { .name    = "DISPATCHED_FPU",
1104   .desc    = "Dispatched FPU Operations",
1105   .modmsk  = AMD64_FAM10H_ATTRS,
1106   .code    = 0x0,
1107   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_dispatched_fpu),
1108   .ngrp    = 1,
1109   .umasks  = amd64_fam12h_dispatched_fpu,
1110 },
1111 { .name    = "CYCLES_NO_FPU_OPS_RETIRED",
1112   .desc    = "Cycles in which the FPU is Empty",
1113   .modmsk  = AMD64_FAM10H_ATTRS,
1114   .code    = 0x1,
1115 },
1116 { .name    = "DISPATCHED_FPU_OPS_FAST_FLAG",
1117   .desc    = "Dispatched Fast Flag FPU Operations",
1118   .modmsk  = AMD64_FAM10H_ATTRS,
1119   .code    = 0x2,
1120 },
1121 { .name    = "RETIRED_SSE_OPERATIONS",
1122   .desc    = "Retired SSE Operations",
1123   .modmsk  = AMD64_FAM10H_ATTRS,
1124   .code    = 0x3,
1125   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_sse_operations),
1126   .ngrp    = 1,
1127   .umasks  = amd64_fam12h_retired_sse_operations,
1128 },
1129 { .name    = "RETIRED_MOVE_OPS",
1130   .desc    = "Retired Move Ops",
1131   .modmsk  = AMD64_FAM10H_ATTRS,
1132   .code    = 0x4,
1133   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_move_ops),
1134   .ngrp    = 1,
1135   .umasks  = amd64_fam12h_retired_move_ops,
1136 },
1137 { .name    = "RETIRED_SERIALIZING_OPS",
1138   .desc    = "Retired Serializing Ops",
1139   .modmsk  = AMD64_FAM10H_ATTRS,
1140   .code    = 0x5,
1141   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_serializing_ops),
1142   .ngrp    = 1,
1143   .umasks  = amd64_fam12h_retired_serializing_ops,
1144 },
1145 { .name    = "FP_SCHEDULER_CYCLES",
1146   .desc    = "Number of Cycles that a Serializing uop is in the FP Scheduler",
1147   .modmsk  = AMD64_FAM10H_ATTRS,
1148   .code    = 0x6,
1149   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_fp_scheduler_cycles),
1150   .ngrp    = 1,
1151   .umasks  = amd64_fam12h_fp_scheduler_cycles,
1152 },
1153 { .name    = "SEGMENT_REGISTER_LOADS",
1154   .desc    = "Segment Register Loads",
1155   .modmsk  = AMD64_FAM10H_ATTRS,
1156   .code    = 0x20,
1157   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_segment_register_loads),
1158   .ngrp    = 1,
1159   .umasks  = amd64_fam12h_segment_register_loads,
1160 },
1161 { .name    = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE",
1162   .desc    = "Pipeline Restart Due to Self-Modifying Code",
1163   .modmsk  = AMD64_FAM10H_ATTRS,
1164   .code    = 0x21,
1165 },
1166 { .name    = "PIPELINE_RESTART_DUE_TO_PROBE_HIT",
1167   .desc    = "Pipeline Restart Due to Probe Hit",
1168   .modmsk  = AMD64_FAM10H_ATTRS,
1169   .code    = 0x22,
1170 },
1171 { .name    = "LS_BUFFER_2_FULL_CYCLES",
1172   .desc    = "LS Buffer 2 Full",
1173   .modmsk  = AMD64_FAM10H_ATTRS,
1174   .code    = 0x23,
1175 },
1176 { .name    = "LOCKED_OPS",
1177   .desc    = "Locked Operations",
1178   .modmsk  = AMD64_FAM10H_ATTRS,
1179   .code    = 0x24,
1180   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_locked_ops),
1181   .ngrp    = 1,
1182   .umasks  = amd64_fam12h_locked_ops,
1183 },
1184 { .name    = "RETIRED_CLFLUSH_INSTRUCTIONS",
1185   .desc    = "Retired CLFLUSH Instructions",
1186   .modmsk  = AMD64_FAM10H_ATTRS,
1187   .code    = 0x26,
1188 },
1189 { .name    = "RETIRED_CPUID_INSTRUCTIONS",
1190   .desc    = "Retired CPUID Instructions",
1191   .modmsk  = AMD64_FAM10H_ATTRS,
1192   .code    = 0x27,
1193 },
1194 { .name    = "CANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONS",
1195   .desc    = "Cancelled Store to Load Forward Operations",
1196   .modmsk  = AMD64_FAM10H_ATTRS,
1197   .code    = 0x2a,
1198   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_cancelled_store_to_load_forward_operations),
1199   .ngrp    = 1,
1200   .umasks  = amd64_fam12h_cancelled_store_to_load_forward_operations,
1201 },
1202 { .name    = "SMIS_RECEIVED",
1203   .desc    = "SMIs Received",
1204   .modmsk  = AMD64_FAM10H_ATTRS,
1205   .code    = 0x2b,
1206 },
1207 { .name    = "DATA_CACHE_ACCESSES",
1208   .desc    = "Data Cache Accesses",
1209   .modmsk  = AMD64_FAM10H_ATTRS,
1210   .code    = 0x40,
1211 },
1212 { .name    = "DATA_CACHE_MISSES",
1213   .desc    = "Data Cache Misses",
1214   .modmsk  = AMD64_FAM10H_ATTRS,
1215   .code    = 0x41,
1216 },
1217 { .name    = "DATA_CACHE_REFILLS",
1218   .desc    = "Data Cache Refills from L2 or Northbridge",
1219   .modmsk  = AMD64_FAM10H_ATTRS,
1220   .code    = 0x42,
1221   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_data_cache_refills),
1222   .ngrp    = 1,
1223   .umasks  = amd64_fam12h_data_cache_refills,
1224 },
1225 { .name    = "DATA_CACHE_REFILLS_FROM_SYSTEM",
1226   .desc    = "Data Cache Refills from the Northbridge",
1227   .modmsk  = AMD64_FAM10H_ATTRS,
1228   .code    = 0x43,
1229   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_data_cache_refills_from_northbridge),
1230   .ngrp    = 1,
1231   .umasks  = amd64_fam12h_data_cache_refills_from_northbridge,
1232 },
1233 { .name    = "DATA_CACHE_LINES_EVICTED",
1234   .desc    = "Data Cache Lines Evicted",
1235   .modmsk  = AMD64_FAM10H_ATTRS,
1236   .code    = 0x44,
1237   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_data_cache_lines_evicted),
1238   .ngrp    = 1,
1239   .umasks  = amd64_fam12h_data_cache_lines_evicted,
1240 },
1241 { .name    = "L1_DTLB_MISS_AND_L2_DTLB_HIT",
1242   .desc    = "L1 DTLB Miss and L2 DTLB Hit",
1243   .modmsk  = AMD64_FAM10H_ATTRS,
1244   .code    = 0x45,
1245   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l1_dtlb_miss_and_l2_dtlb_hit),
1246   .ngrp    = 1,
1247   .umasks  = amd64_fam12h_l1_dtlb_miss_and_l2_dtlb_hit,
1248 },
1249 { .name    = "L1_DTLB_AND_L2_DTLB_MISS",
1250   .desc    = "L1 DTLB and L2 DTLB Miss",
1251   .modmsk  = AMD64_FAM10H_ATTRS,
1252   .code    = 0x46,
1253   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l1_dtlb_and_l2_dtlb_miss),
1254   .ngrp    = 1,
1255   .umasks  = amd64_fam12h_l1_dtlb_and_l2_dtlb_miss,
1256 },
1257 { .name    = "MISALIGNED_ACCESSES",
1258   .desc    = "Misaligned Accesses",
1259   .modmsk  = AMD64_FAM10H_ATTRS,
1260   .code    = 0x47,
1261 },
1262 { .name    = "MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS",
1263   .desc    = "Microarchitectural Late Cancel of an Access",
1264   .modmsk  = AMD64_FAM10H_ATTRS,
1265   .code    = 0x48,
1266 },
1267 { .name    = "MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS",
1268   .desc    = "Microarchitectural Early Cancel of an Access",
1269   .modmsk  = AMD64_FAM10H_ATTRS,
1270   .code    = 0x49,
1271 },
1272 { .name    = "PREFETCH_INSTRUCTIONS_DISPATCHED",
1273   .desc    = "Prefetch Instructions Dispatched",
1274   .modmsk  = AMD64_FAM10H_ATTRS,
1275   .code    = 0x4b,
1276   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_prefetch_instructions_dispatched),
1277   .ngrp    = 1,
1278   .umasks  = amd64_fam12h_prefetch_instructions_dispatched,
1279 },
1280 { .name    = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS",
1281   .desc    = "DCACHE Misses by Locked Instructions",
1282   .modmsk  = AMD64_FAM10H_ATTRS,
1283   .code    = 0x4c,
1284   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_dcache_misses_by_locked_instructions),
1285   .ngrp    = 1,
1286   .umasks  = amd64_fam12h_dcache_misses_by_locked_instructions,
1287 },
1288 { .name    = "L1_DTLB_HIT",
1289   .desc    = "L1 DTLB Hit",
1290   .modmsk  = AMD64_FAM10H_ATTRS,
1291   .code    = 0x4d,
1292   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l1_dtlb_hit),
1293   .ngrp    = 1,
1294   .umasks  = amd64_fam12h_l1_dtlb_hit,
1295 },
1296 { .name    = "INEFFECTIVE_SW_PREFETCHES",
1297   .desc    = "Ineffective Software Prefetches",
1298   .modmsk  = AMD64_FAM10H_ATTRS,
1299   .code    = 0x52,
1300   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_ineffective_sw_prefetches),
1301   .ngrp    = 1,
1302   .umasks  = amd64_fam12h_ineffective_sw_prefetches,
1303 },
1304 { .name    = "GLOBAL_TLB_FLUSHES",
1305   .desc    = "Global TLB Flushes",
1306   .modmsk  = AMD64_FAM10H_ATTRS,
1307   .code    = 0x54,
1308 },
1309 { .name    = "MEMORY_REQUESTS",
1310   .desc    = "Memory Requests by Type",
1311   .modmsk  = AMD64_FAM10H_ATTRS,
1312   .code    = 0x65,
1313   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_requests),
1314   .ngrp    = 1,
1315   .umasks  = amd64_fam12h_memory_requests,
1316 },
1317 { .name    = "DATA_PREFETCHES",
1318   .desc    = "Data Prefetcher",
1319   .modmsk  = AMD64_FAM10H_ATTRS,
1320   .code    = 0x67,
1321   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_data_prefetches),
1322   .ngrp    = 1,
1323   .umasks  = amd64_fam12h_data_prefetches,
1324 },
1325 { .name    = "NORTHBRIDGE_READ_RESPONSES",
1326   .desc    = "Northbridge Read Responses by Coherency State",
1327   .modmsk  = AMD64_FAM10H_ATTRS,
1328   .code    = 0x6c,
1329   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_northbridge_read_responses),
1330   .ngrp    = 1,
1331   .umasks  = amd64_fam12h_northbridge_read_responses,
1332 },
1333 { .name    = "OCTWORDS_WRITTEN_TO_SYSTEM",
1334   .desc    = "Octwords Written to System",
1335   .modmsk  = AMD64_FAM10H_ATTRS,
1336   .code    = 0x6d,
1337   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_octwords_written_to_system),
1338   .ngrp    = 1,
1339   .umasks  = amd64_fam12h_octwords_written_to_system,
1340 },
1341 { .name    = "CPU_CLK_UNHALTED",
1342   .desc    = "CPU Clocks not Halted",
1343   .modmsk  = AMD64_FAM10H_ATTRS,
1344   .code    = 0x76,
1345 },
1346 { .name    = "REQUESTS_TO_L2",
1347   .desc    = "Requests to L2 Cache",
1348   .modmsk  = AMD64_FAM10H_ATTRS,
1349   .code    = 0x7d,
1350   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_requests_to_l2),
1351   .ngrp    = 1,
1352   .umasks  = amd64_fam12h_requests_to_l2,
1353 },
1354 { .name    = "L2_CACHE_MISS",
1355   .desc    = "L2 Cache Misses",
1356   .modmsk  = AMD64_FAM10H_ATTRS,
1357   .code    = 0x7e,
1358   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l2_cache_miss),
1359   .ngrp    = 1,
1360   .umasks  = amd64_fam12h_l2_cache_miss,
1361 },
1362 { .name    = "L2_FILL_WRITEBACK",
1363   .desc    = "L2 Fill/Writeback",
1364   .modmsk  = AMD64_FAM10H_ATTRS,
1365   .code    = 0x7f,
1366   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l2_fill_writeback),
1367   .ngrp    = 1,
1368   .umasks  = amd64_fam12h_l2_fill_writeback,
1369 },
1370 { .name    = "PAGE_SIZE_MISMATCHES",
1371   .desc    = "Page Size Mismatches",
1372   .modmsk  = AMD64_FAM10H_ATTRS,
1373   .code    = 0x165,
1374   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_page_size_mismatches),
1375   .ngrp    = 1,
1376   .umasks  = amd64_fam12h_page_size_mismatches,
1377 },
1378 { .name    = "INSTRUCTION_CACHE_FETCHES",
1379   .desc    = "Instruction Cache Fetches",
1380   .modmsk  = AMD64_FAM10H_ATTRS,
1381   .code    = 0x80,
1382 },
1383 { .name    = "INSTRUCTION_CACHE_MISSES",
1384   .desc    = "Instruction Cache Misses",
1385   .modmsk  = AMD64_FAM10H_ATTRS,
1386   .code    = 0x81,
1387 },
1388 { .name    = "INSTRUCTION_CACHE_REFILLS_FROM_L2",
1389   .desc    = "Instruction Cache Refills from L2",
1390   .modmsk  = AMD64_FAM10H_ATTRS,
1391   .code    = 0x82,
1392 },
1393 { .name    = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM",
1394   .desc    = "Instruction Cache Refills from System",
1395   .modmsk  = AMD64_FAM10H_ATTRS,
1396   .code    = 0x83,
1397 },
1398 { .name    = "L1_ITLB_MISS_AND_L2_ITLB_HIT",
1399   .desc    = "L1 ITLB Miss and L2 ITLB Hit",
1400   .modmsk  = AMD64_FAM10H_ATTRS,
1401   .code    = 0x84,
1402 },
1403 { .name    = "L1_ITLB_MISS_AND_L2_ITLB_MISS",
1404   .desc    = "L1 ITLB Miss and L2 ITLB Miss",
1405   .modmsk  = AMD64_FAM10H_ATTRS,
1406   .code    = 0x85,
1407   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_l1_itlb_miss_and_l2_itlb_miss),
1408   .ngrp    = 1,
1409   .umasks  = amd64_fam12h_l1_itlb_miss_and_l2_itlb_miss,
1410 },
1411 { .name    = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE",
1412   .desc    = "Pipeline Restart Due to Instruction Stream Probe",
1413   .modmsk  = AMD64_FAM10H_ATTRS,
1414   .code    = 0x86,
1415 },
1416 { .name    = "INSTRUCTION_FETCH_STALL",
1417   .desc    = "Instruction Fetch Stall",
1418   .modmsk  = AMD64_FAM10H_ATTRS,
1419   .code    = 0x87,
1420 },
1421 { .name    = "RETURN_STACK_HITS",
1422   .desc    = "Return Stack Hits",
1423   .modmsk  = AMD64_FAM10H_ATTRS,
1424   .code    = 0x88,
1425 },
1426 { .name    = "RETURN_STACK_OVERFLOWS",
1427   .desc    = "Return Stack Overflows",
1428   .modmsk  = AMD64_FAM10H_ATTRS,
1429   .code    = 0x89,
1430 },
1431 { .name    = "INSTRUCTION_CACHE_VICTIMS",
1432   .desc    = "Instruction Cache Victims",
1433   .modmsk  = AMD64_FAM10H_ATTRS,
1434   .code    = 0x8b,
1435 },
1436 { .name    = "INSTRUCTION_CACHE_LINES_INVALIDATED",
1437   .desc    = "Instruction Cache Lines Invalidated",
1438   .modmsk  = AMD64_FAM10H_ATTRS,
1439   .code    = 0x8c,
1440   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_instruction_cache_lines_invalidated),
1441   .ngrp    = 1,
1442   .umasks  = amd64_fam12h_instruction_cache_lines_invalidated,
1443 },
1444 { .name    = "ITLB_RELOADS",
1445   .desc    = "ITLB Reloads",
1446   .modmsk  = AMD64_FAM10H_ATTRS,
1447   .code    = 0x99,
1448 },
1449 { .name    = "ITLB_RELOADS_ABORTED",
1450   .desc    = "ITLB Reloads Aborted",
1451   .modmsk  = AMD64_FAM10H_ATTRS,
1452   .code    = 0x9a,
1453 },
1454 { .name    = "RETIRED_INSTRUCTIONS",
1455   .desc    = "Retired Instructions",
1456   .modmsk  = AMD64_FAM10H_ATTRS,
1457   .code    = 0xc0,
1458 },
1459 { .name    = "RETIRED_UOPS",
1460   .desc    = "Retired uops",
1461   .modmsk  = AMD64_FAM10H_ATTRS,
1462   .code    = 0xc1,
1463 },
1464 { .name    = "RETIRED_BRANCH_INSTRUCTIONS",
1465   .desc    = "Retired Branch Instructions",
1466   .modmsk  = AMD64_FAM10H_ATTRS,
1467   .code    = 0xc2,
1468 },
1469 { .name    = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS",
1470   .desc    = "Retired Mispredicted Branch Instructions",
1471   .modmsk  = AMD64_FAM10H_ATTRS,
1472   .code    = 0xc3,
1473 },
1474 { .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS",
1475   .desc    = "Retired Taken Branch Instructions",
1476   .modmsk  = AMD64_FAM10H_ATTRS,
1477   .code    = 0xc4,
1478 },
1479 { .name    = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED",
1480   .desc    = "Retired Taken Branch Instructions Mispredicted",
1481   .modmsk  = AMD64_FAM10H_ATTRS,
1482   .code    = 0xc5,
1483 },
1484 { .name    = "RETIRED_FAR_CONTROL_TRANSFERS",
1485   .desc    = "Retired Far Control Transfers",
1486   .modmsk  = AMD64_FAM10H_ATTRS,
1487   .code    = 0xc6,
1488 },
1489 { .name    = "RETIRED_BRANCH_RESYNCS",
1490   .desc    = "Retired Branch Resyncs",
1491   .modmsk  = AMD64_FAM10H_ATTRS,
1492   .code    = 0xc7,
1493 },
1494 { .name    = "RETIRED_NEAR_RETURNS",
1495   .desc    = "Retired Near Returns",
1496   .modmsk  = AMD64_FAM10H_ATTRS,
1497   .code    = 0xc8,
1498 },
1499 { .name    = "RETIRED_NEAR_RETURNS_MISPREDICTED",
1500   .desc    = "Retired Near Returns Mispredicted",
1501   .modmsk  = AMD64_FAM10H_ATTRS,
1502   .code    = 0xc9,
1503 },
1504 { .name    = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED",
1505   .desc    = "Retired Indirect Branches Mispredicted",
1506   .modmsk  = AMD64_FAM10H_ATTRS,
1507   .code    = 0xca,
1508 },
1509 { .name    = "RETIRED_MMX_AND_FP_INSTRUCTIONS",
1510   .desc    = "Retired MMX/FP Instructions",
1511   .modmsk  = AMD64_FAM10H_ATTRS,
1512   .code    = 0xcb,
1513   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_mmx_and_fp_instructions),
1514   .ngrp    = 1,
1515   .umasks  = amd64_fam12h_retired_mmx_and_fp_instructions,
1516 },
1517 { .name    = "INTERRUPTS_MASKED_CYCLES",
1518   .desc    = "Interrupts-Masked Cycles",
1519   .modmsk  = AMD64_FAM10H_ATTRS,
1520   .code    = 0xcd,
1521 },
1522 { .name    = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING",
1523   .desc    = "Interrupts-Masked Cycles with Interrupt Pending",
1524   .modmsk  = AMD64_FAM10H_ATTRS,
1525   .code    = 0xce,
1526 },
1527 { .name    = "INTERRUPTS_TAKEN",
1528   .desc    = "Interrupts Taken",
1529   .modmsk  = AMD64_FAM10H_ATTRS,
1530   .code    = 0xcf,
1531 },
1532 { .name    = "DECODER_EMPTY",
1533   .desc    = "Decoder Empty",
1534   .modmsk  = AMD64_FAM10H_ATTRS,
1535   .code    = 0xd0,
1536 },
1537 { .name    = "DISPATCH_STALLS",
1538   .desc    = "Dispatch Stalls",
1539   .modmsk  = AMD64_FAM10H_ATTRS,
1540   .code    = 0xd1,
1541 },
1542 { .name    = "DISPATCH_STALL_FOR_BRANCH_ABORT",
1543   .desc    = "Dispatch Stall for Branch Abort to Retire",
1544   .modmsk  = AMD64_FAM10H_ATTRS,
1545   .code    = 0xd2,
1546 },
1547 { .name    = "DISPATCH_STALL_FOR_SERIALIZATION",
1548   .desc    = "Dispatch Stall for Serialization",
1549   .modmsk  = AMD64_FAM10H_ATTRS,
1550   .code    = 0xd3,
1551 },
1552 { .name    = "DISPATCH_STALL_FOR_SEGMENT_LOAD",
1553   .desc    = "Dispatch Stall for Segment Load",
1554   .modmsk  = AMD64_FAM10H_ATTRS,
1555   .code    = 0xd4,
1556 },
1557 { .name    = "DISPATCH_STALL_FOR_REORDER_BUFFER_FULL",
1558   .desc    = "Dispatch Stall for Reorder Buffer Full",
1559   .modmsk  = AMD64_FAM10H_ATTRS,
1560   .code    = 0xd5,
1561 },
1562 { .name    = "DISPATCH_STALL_FOR_RESERVATION_STATION_FULL",
1563   .desc    = "Dispatch Stall for Reservation Station Full",
1564   .modmsk  = AMD64_FAM10H_ATTRS,
1565   .code    = 0xd6,
1566 },
1567 { .name    = "DISPATCH_STALL_FOR_FPU_FULL",
1568   .desc    = "Dispatch Stall for FPU Full",
1569   .modmsk  = AMD64_FAM10H_ATTRS,
1570   .code    = 0xd7,
1571 },
1572 { .name    = "DISPATCH_STALL_FOR_LS_FULL",
1573   .desc    = "Dispatch Stall for LS Full",
1574   .modmsk  = AMD64_FAM10H_ATTRS,
1575   .code    = 0xd8,
1576 },
1577 { .name    = "DISPATCH_STALL_WAITING_FOR_ALL_QUIET",
1578   .desc    = "Dispatch Stall Waiting for All Quiet",
1579   .modmsk  = AMD64_FAM10H_ATTRS,
1580   .code    = 0xd9,
1581 },
1582 { .name    = "DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNC",
1583   .desc    = "Dispatch Stall for Far Transfer or Resync to Retire",
1584   .modmsk  = AMD64_FAM10H_ATTRS,
1585   .code    = 0xda,
1586 },
1587 { .name    = "FPU_EXCEPTIONS",
1588   .desc    = "FPU Exceptions",
1589   .modmsk  = AMD64_FAM10H_ATTRS,
1590   .code    = 0xdb,
1591   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_fpu_exceptions),
1592   .ngrp    = 1,
1593   .umasks  = amd64_fam12h_fpu_exceptions,
1594 },
1595 { .name    = "DR0_BREAKPOINT_MATCHES",
1596   .desc    = "DR0 Breakpoint Matches",
1597   .modmsk  = AMD64_FAM10H_ATTRS,
1598   .code    = 0xdc,
1599 },
1600 { .name    = "DR1_BREAKPOINT_MATCHES",
1601   .desc    = "DR1 Breakpoint Matches",
1602   .modmsk  = AMD64_FAM10H_ATTRS,
1603   .code    = 0xdd,
1604 },
1605 { .name    = "DR2_BREAKPOINT_MATCHES",
1606   .desc    = "DR2 Breakpoint Matches",
1607   .modmsk  = AMD64_FAM10H_ATTRS,
1608   .code    = 0xde,
1609 },
1610 { .name    = "DR3_BREAKPOINT_MATCHES",
1611   .desc    = "DR3 Breakpoint Matches",
1612   .modmsk  = AMD64_FAM10H_ATTRS,
1613   .code    = 0xdf,
1614 },
1615 { .name    = "RETIRED_X87_OPS",
1616   .desc    = "Retired x87 Floating Point Operations",
1617   .modmsk  = AMD64_FAM10H_ATTRS,
1618   .code    = 0x1c0,
1619   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_retired_x87_ops),
1620   .ngrp    = 1,
1621   .umasks  = amd64_fam12h_retired_x87_ops,
1622 },
1623 { .name    = "LFENCE_INST_RETIRED",
1624   .desc    = "LFENCE Instructions Retired",
1625   .modmsk  = AMD64_FAM10H_ATTRS,
1626   .code    = 0x1d3,
1627 },
1628 { .name    = "SFENCE_INST_RETIRED",
1629   .desc    = "SFENCE Instructions Retired",
1630   .modmsk  = AMD64_FAM10H_ATTRS,
1631   .code    = 0x1d4,
1632 },
1633 { .name    = "MFENCE_INST_RETIRED",
1634   .desc    = "MFENCE Instructions Retired",
1635   .modmsk  = AMD64_FAM10H_ATTRS,
1636   .code    = 0x1d5,
1637 },
1638 { .name    = "DRAM_ACCESSES_PAGE",
1639   .desc    = "DRAM Accesses",
1640   .modmsk  = AMD64_FAM10H_ATTRS,
1641   .code    = 0xe0,
1642   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_dram_accesses_page),
1643   .ngrp    = 1,
1644   .umasks  = amd64_fam12h_dram_accesses_page,
1645 },
1646 { .name    = "MEMORY_CONTROLLER_0_PAGE",
1647   .desc    = "DRAM Controller 0 Page Table Events",
1648   .modmsk  = AMD64_FAM10H_ATTRS,
1649   .code    = 0xe1,
1650   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_page_table_events),
1651   .ngrp    = 1,
1652   .umasks  = amd64_fam12h_memory_controller_page_table_events,
1653 },
1654 { .name    = "MEMORY_CONTROLLER_SLOT_MISSES",
1655   .desc    = "Memory Controller DRAM Command Slots Missed",
1656   .modmsk  = AMD64_FAM10H_ATTRS,
1657   .code    = 0xe2,
1658   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_slot_misses),
1659   .ngrp    = 1,
1660   .umasks  = amd64_fam12h_memory_controller_slot_misses,
1661 },
1662 { .name    = "MEMORY_CONTROLLER_TURNAROUNDS",
1663   .desc    = "Memory Controller Turnarounds",
1664   .modmsk  = AMD64_FAM10H_ATTRS,
1665   .code    = 0xe3,
1666   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_turnarounds),
1667   .ngrp    = 1,
1668   .umasks  = amd64_fam12h_memory_controller_turnarounds,
1669 },
1670 { .name    = "MEMORY_CONTROLLER_RBD_QUEUE",
1671   .desc    = "Memory Controller RBD Queue Events",
1672   .modmsk  = AMD64_FAM10H_ATTRS,
1673   .code    = 0xe4,
1674   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_rbd_queue),
1675   .ngrp    = 1,
1676   .umasks  = amd64_fam12h_memory_rbd_queue,
1677 },
1678 { .name    = "MEMORY_CONTROLLER_1_PAGE",
1679   .desc    = "DRAM Controller 1 Page Table Events",
1680   .modmsk  = AMD64_FAM10H_ATTRS,
1681   .code    = 0xe5,
1682   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_page_table_events),
1683   .ngrp    = 1,
1684   .umasks  = amd64_fam12h_memory_controller_page_table_events,
1685 },
1686 { .name    = "THERMAL_STATUS",
1687   .desc    = "Thermal Status",
1688   .modmsk  = AMD64_FAM10H_ATTRS,
1689   .code    = 0xe8,
1690   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_thermal_status),
1691   .ngrp    = 1,
1692   .umasks  = amd64_fam12h_thermal_status,
1693 },
1694 { .name    = "CPU_IO_REQUESTS_TO_MEMORY_IO",
1695   .desc    = "CPU/IO Requests to Memory/IO",
1696   .modmsk  = AMD64_FAM10H_ATTRS,
1697   .code    = 0xe9,
1698   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_cpu_io_requests_to_memory_io),
1699   .ngrp    = 1,
1700   .umasks  = amd64_fam12h_cpu_io_requests_to_memory_io,
1701 },
1702 { .name    = "CACHE_BLOCK",
1703   .desc    = "Cache Block Commands",
1704   .modmsk  = AMD64_FAM10H_ATTRS,
1705   .code    = 0xea,
1706   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_cache_block),
1707   .ngrp    = 1,
1708   .umasks  = amd64_fam12h_cache_block,
1709 },
1710 { .name    = "SIZED_COMMANDS",
1711   .desc    = "Sized Commands",
1712   .modmsk  = AMD64_FAM10H_ATTRS,
1713   .code    = 0xeb,
1714   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_sized_commands),
1715   .ngrp    = 1,
1716   .umasks  = amd64_fam12h_sized_commands,
1717 },
1718 { .name    = "PROBE",
1719   .desc    = "Probe Responses and Upstream Requests",
1720   .modmsk  = AMD64_FAM10H_ATTRS,
1721   .code    = 0xec,
1722   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_probe),
1723   .ngrp    = 1,
1724   .umasks  = amd64_fam12h_probe,
1725 },
1726 { .name    = "DEV",
1727   .desc    = "DEV Events",
1728   .modmsk  = AMD64_FAM10H_ATTRS,
1729   .code    = 0xee,
1730   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_dev),
1731   .ngrp    = 1,
1732   .umasks  = amd64_fam12h_dev,
1733 },
1734 { .name    = "MEMORY_CONTROLLER_REQUESTS",
1735   .desc    = "Memory Controller Requests",
1736   .modmsk  = AMD64_FAM10H_ATTRS,
1737   .code    = 0x1f0,
1738   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_memory_controller_requests),
1739   .ngrp    = 1,
1740   .umasks  = amd64_fam12h_memory_controller_requests,
1741 },
1742 { .name    = "SIDEBAND_SIGNALS",
1743   .desc    = "Sideband Signals and Special Cycles",
1744   .modmsk  = AMD64_FAM10H_ATTRS,
1745   .code    = 0x1e9,
1746   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_sideband_signals),
1747   .ngrp    = 1,
1748   .umasks  = amd64_fam12h_sideband_signals,
1749 },
1750 { .name    = "Interrupt Events",
1751   .desc    = "Interrupt Events",
1752   .modmsk  = AMD64_FAM10H_ATTRS,
1753   .code    = 0x1ea,
1754   .numasks = LIBPFM_ARRAY_SIZE(amd64_fam12h_interrupt_events),
1755   .ngrp    = 1,
1756   .umasks  = amd64_fam12h_interrupt_events,
1757 },
1758 };