Andrew's port to sparc
[akaros.git] / kern / src / testing.c
1 #ifdef __DEPUTY__
2 #pragma nodeputy
3 #endif
4
5 #include <arch/mmu.h>
6 #include <arch/arch.h>
7 #include <smp.h>
8
9 #include <ros/memlayout.h>
10
11 #include <atomic.h>
12 #include <stdio.h>
13 #include <assert.h>
14 #include <string.h>
15 #include <testing.h>
16 #include <trap.h>
17 #include <env.h>
18 #include <syscall.h>
19
20 #define test_vector 0xeb
21
22 #if 0
23
24 void test_ipi_sending(void)
25 {
26         extern handler_t interrupt_handlers[];
27         int8_t state = 0;
28
29         register_interrupt_handler(interrupt_handlers, test_vector,
30                                    test_hello_world_handler, 0);
31         enable_irqsave(&state);
32         cprintf("\nCORE 0 sending broadcast\n");
33         send_broadcast_ipi(test_vector);
34         udelay(3000000);
35         cprintf("\nCORE 0 sending all others\n");
36         send_all_others_ipi(test_vector);
37         udelay(3000000);
38         cprintf("\nCORE 0 sending self\n");
39         send_self_ipi(test_vector);
40         udelay(3000000);
41         cprintf("\nCORE 0 sending ipi to physical 1\n");
42         send_ipi(0x01, 0, test_vector);
43         udelay(3000000);
44         cprintf("\nCORE 0 sending ipi to physical 2\n");
45         send_ipi(0x02, 0, test_vector);
46         udelay(3000000);
47         cprintf("\nCORE 0 sending ipi to physical 3\n");
48         send_ipi(0x03, 0, test_vector);
49         udelay(3000000);
50         cprintf("\nCORE 0 sending ipi to physical 15\n");
51         send_ipi(0x0f, 0, test_vector);
52         udelay(3000000);
53         cprintf("\nCORE 0 sending ipi to logical 2\n");
54         send_ipi(0x02, 1, test_vector);
55         udelay(3000000);
56         cprintf("\nCORE 0 sending ipi to logical 1\n");
57         send_ipi(0x01, 1, test_vector);
58         udelay(3000000);
59         cprintf("\nDone!\n");
60         disable_irqsave(&state);
61 }
62
63 // Note this never returns and will muck with any other timer work
64 void test_pic_reception(void)
65 {
66         register_interrupt_handler(interrupt_handlers, 0x20, test_hello_world_handler, 0);
67         pit_set_timer(100,TIMER_RATEGEN); // totally arbitrary time
68         pic_unmask_irq(0);
69         cprintf("PIC1 Mask = 0x%04x\n", inb(PIC1_DATA));
70         cprintf("PIC2 Mask = 0x%04x\n", inb(PIC2_DATA));
71         unmask_lapic_lvt(LAPIC_LVT_LINT0);
72         cprintf("Core %d's LINT0: 0x%08x\n", core_id(), read_mmreg32(LAPIC_LVT_LINT0));
73         enable_irq();
74         while(1);
75 }
76
77 #endif
78
79 void test_print_info(void)
80 {
81         cprintf("\nCORE 0 asking all cores to print info:\n");
82         smp_call_function_all(test_print_info_handler, 0, 0);
83         cprintf("\nDone!\n");
84 }
85
86
87 extern uint8_t num_cpus;
88 barrier_t test_cpu_array;
89
90 void test_barrier(void)
91 {
92         cprintf("Core 0 initializing barrier\n");
93         init_barrier(&test_cpu_array, num_cpus);
94         cprintf("Core 0 asking all cores to print ids, barrier, rinse, repeat\n");
95         smp_call_function_all(test_barrier_handler, 0, 0);
96 }
97
98 void test_interrupts_irqsave(void)
99 {
100         int8_t state = 0;
101         printd("Testing Nesting Enabling first, turning ints off:\n");
102         disable_irq();
103         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
104         assert(!irq_is_enabled());
105         printd("Enabling IRQSave\n");
106         enable_irqsave(&state);
107         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
108         assert(irq_is_enabled());
109         printd("Enabling IRQSave Again\n");
110         enable_irqsave(&state);
111         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
112         assert(irq_is_enabled());
113         printd("Disabling IRQSave Once\n");
114         disable_irqsave(&state);
115         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
116         assert(irq_is_enabled());
117         printd("Disabling IRQSave Again\n");
118         disable_irqsave(&state);
119         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
120         assert(!irq_is_enabled());
121         printd("Done.  Should have been 0, 200, 200, 200, 0\n");
122
123         printd("Testing Nesting Disabling first, turning ints on:\n");
124         state = 0;
125         enable_irq();
126         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
127         assert(irq_is_enabled());
128         printd("Disabling IRQSave Once\n");
129         disable_irqsave(&state);
130         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
131         assert(!irq_is_enabled());
132         printd("Disabling IRQSave Again\n");
133         disable_irqsave(&state);
134         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
135         assert(!irq_is_enabled());
136         printd("Enabling IRQSave Once\n");
137         enable_irqsave(&state);
138         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
139         assert(!irq_is_enabled());
140         printd("Enabling IRQSave Again\n");
141         enable_irqsave(&state);
142         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
143         assert(irq_is_enabled());
144         printd("Done.  Should have been 200, 0, 0, 0, 200 \n");
145
146         state = 0;
147         disable_irq();
148         printd("Ints are off, enabling then disabling.\n");
149         enable_irqsave(&state);
150         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
151         assert(irq_is_enabled());
152         disable_irqsave(&state);
153         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
154         assert(!irq_is_enabled());
155         printd("Done.  Should have been 200, 0\n");
156
157         state = 0;
158         enable_irq();
159         printd("Ints are on, enabling then disabling.\n");
160         enable_irqsave(&state);
161         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
162         assert(irq_is_enabled());
163         disable_irqsave(&state);
164         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
165         assert(irq_is_enabled());
166         printd("Done.  Should have been 200, 200\n");
167
168         state = 0;
169         disable_irq();
170         printd("Ints are off, disabling then enabling.\n");
171         disable_irqsave(&state);
172         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
173         assert(!irq_is_enabled());
174         enable_irqsave(&state);
175         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
176         assert(!irq_is_enabled());
177         printd("Done.  Should have been 0, 0\n");
178
179         state = 0;
180         enable_irq();
181         printd("Ints are on, disabling then enabling.\n");
182         disable_irqsave(&state);
183         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
184         assert(!irq_is_enabled());
185         enable_irqsave(&state);
186         printd("Interrupts are: %x\n", read_eflags() & FL_IF);
187         assert(irq_is_enabled());
188         printd("Done.  Should have been 0, 200\n");
189
190         disable_irq();
191         cprintf("Passed enable_irqsave tests\n");
192 }
193
194 void test_bitmasks(void)
195 {
196 #define masksize 67
197         DECL_BITMASK(mask, masksize);
198         printk("size of mask %d\n", sizeof(mask));
199         CLR_BITMASK(mask, masksize);
200         PRINT_BITMASK(mask, masksize);
201         printk("cleared\n");
202         SET_BITMASK_BIT(mask, 0);
203         SET_BITMASK_BIT(mask, 11);
204         SET_BITMASK_BIT(mask, 17);
205         SET_BITMASK_BIT(mask, masksize-1);
206         printk("bits set\n");
207         PRINT_BITMASK(mask, masksize);
208         DECL_BITMASK(mask2, masksize);
209         COPY_BITMASK(mask2, mask, masksize);
210         printk("copy of original mask, should be the same as the prev\n");
211         PRINT_BITMASK(mask2, masksize);
212         CLR_BITMASK_BIT(mask, 11);
213         printk("11 cleared\n");
214         PRINT_BITMASK(mask, masksize);
215         printk("bit 17 is %d (should be 1)\n", GET_BITMASK_BIT(mask, 17));
216         printk("bit 11 is %d (should be 0)\n", GET_BITMASK_BIT(mask, 11));
217         FILL_BITMASK(mask, masksize);
218         PRINT_BITMASK(mask, masksize);
219         printk("should be all 1's, except for a few at the end\n");
220         printk("Is Clear?: %d (should be 0)\n", BITMASK_IS_CLEAR(mask,masksize));
221         CLR_BITMASK(mask, masksize);
222         PRINT_BITMASK(mask, masksize);
223         printk("Is Clear?: %d (should be 1)\n", BITMASK_IS_CLEAR(mask,masksize));
224         printk("should be cleared\n");
225 }
226
227 checklist_t* the_global_list;
228
229 void test_checklist_handler(trapframe_t *tf, void* data)
230 {
231         for (int i = 0; i < SMP_BOOT_TIMEOUT; i++);
232         for (int i = 0; i < SMP_BOOT_TIMEOUT; i++);
233         cprintf("down_checklist(%x,%d)\n",the_global_list,core_id());
234         down_checklist(the_global_list);
235 }
236
237 extern uint8_t num_cpus;
238
239 void test_checklists(void)
240 {
241         INIT_CHECKLIST(a_list, MAX_NUM_CPUS);
242         the_global_list = &a_list;
243         printk("Checklist Build, mask size: %d\n", sizeof(a_list.mask.bits));
244         printk("mask\n");
245         PRINT_BITMASK(a_list.mask.bits, a_list.mask.size);
246         SET_BITMASK_BIT(a_list.mask.bits, 11);
247         printk("Set bit 11\n");
248         PRINT_BITMASK(a_list.mask.bits, a_list.mask.size);
249
250         CLR_BITMASK(a_list.mask.bits, a_list.mask.size);
251         INIT_CHECKLIST_MASK(a_mask, MAX_NUM_CPUS);
252         FILL_BITMASK(a_mask.bits, num_cpus);
253         //CLR_BITMASK_BIT(a_mask.bits, core_id());
254         //SET_BITMASK_BIT(a_mask.bits, 1);
255         //printk("New mask (1, 17, 25):\n");
256         printk("Created new mask, filled up to num_cpus\n");
257         PRINT_BITMASK(a_mask.bits, a_mask.size);
258         printk("committing new mask\n");
259         commit_checklist_wait(&a_list, &a_mask);
260         printk("Old mask (copied onto):\n");
261         PRINT_BITMASK(a_list.mask.bits, a_list.mask.size);
262         //smp_call_function_single(1, test_checklist_handler, 0, 0);
263
264         smp_call_function_all(test_checklist_handler, 0, 0);
265
266         printk("Waiting on checklist\n");
267         waiton_checklist(&a_list);
268         printk("Done Waiting!\n");
269
270 }
271
272 atomic_t a = atomic_init(0), b = atomic_init(0), c = atomic_init(0);
273
274 void test_incrementer_handler(trapframe_t *tf, void* data)
275 {
276         assert(data);
277         atomic_inc((atomic_t*)data);
278 }
279
280 void test_null_handler(trapframe_t *tf, void* data)
281 {
282         asm volatile("nop");
283 }
284
285 void test_smp_call_functions(void)
286 {
287         int i;
288         handler_wrapper_t *waiter0 = 0, *waiter1 = 0, *waiter2 = 0, *waiter3 = 0,
289                           *waiter4 = 0, *waiter5 = 0;
290         uint8_t me = core_id();
291         printk("\nCore %d: SMP Call Self (nowait):\n", me);
292         printk("---------------------\n");
293         smp_call_function_self(test_hello_world_handler, 0, 0);
294         printk("\nCore %d: SMP Call Self (wait):\n", me);
295         printk("---------------------\n");
296         smp_call_function_self(test_hello_world_handler, 0, &waiter0);
297         smp_call_wait(waiter0);
298         printk("\nCore %d: SMP Call All (nowait):\n", me);
299         printk("---------------------\n");
300         smp_call_function_all(test_hello_world_handler, 0, 0);
301         printk("\nCore %d: SMP Call All (wait):\n", me);
302         printk("---------------------\n");
303         smp_call_function_all(test_hello_world_handler, 0, &waiter0);
304         smp_call_wait(waiter0);
305         printk("\nCore %d: SMP Call All-Else Individually, in order (nowait):\n", me);
306         printk("---------------------\n");
307         for(i = 1; i < num_cpus; i++)
308                 smp_call_function_single(i, test_hello_world_handler, 0, 0);
309         printk("\nCore %d: SMP Call Self (wait):\n", me);
310         printk("---------------------\n");
311         smp_call_function_self(test_hello_world_handler, 0, &waiter0);
312         smp_call_wait(waiter0);
313         printk("\nCore %d: SMP Call All-Else Individually, in order (wait):\n", me);
314         printk("---------------------\n");
315         for(i = 1; i < num_cpus; i++)
316         {
317                 smp_call_function_single(i, test_hello_world_handler, 0, &waiter0);
318                 smp_call_wait(waiter0);
319         }
320         printk("\nTesting to see if any IPI-functions are dropped when not waiting:\n");
321         printk("A: %d, B: %d, C: %d (should be 0,0,0)\n", atomic_read(&a), atomic_read(&b), atomic_read(&c));
322         smp_call_function_all(test_incrementer_handler, &a, 0);
323         smp_call_function_all(test_incrementer_handler, &b, 0);
324         smp_call_function_all(test_incrementer_handler, &c, 0);
325         // if i can clobber a previous IPI, the interleaving might do it
326         smp_call_function_single(1 % num_cpus, test_incrementer_handler, &a, 0);
327         smp_call_function_single(2 % num_cpus, test_incrementer_handler, &b, 0);
328         smp_call_function_single(3 % num_cpus, test_incrementer_handler, &c, 0);
329         smp_call_function_single(4 % num_cpus, test_incrementer_handler, &a, 0);
330         smp_call_function_single(5 % num_cpus, test_incrementer_handler, &b, 0);
331         smp_call_function_single(6 % num_cpus, test_incrementer_handler, &c, 0);
332         smp_call_function_all(test_incrementer_handler, &a, 0);
333         smp_call_function_single(3 % num_cpus, test_incrementer_handler, &c, 0);
334         smp_call_function_all(test_incrementer_handler, &b, 0);
335         smp_call_function_single(1 % num_cpus, test_incrementer_handler, &a, 0);
336         smp_call_function_all(test_incrementer_handler, &c, 0);
337         smp_call_function_single(2 % num_cpus, test_incrementer_handler, &b, 0);
338         // wait, so we're sure the others finish before printing.
339         // without this, we could (and did) get 19,18,19, since the B_inc
340         // handler didn't finish yet
341         smp_call_function_self(test_null_handler, 0, &waiter0);
342         // need to grab all 5 handlers (max), since the code moves to the next free.
343         smp_call_function_self(test_null_handler, 0, &waiter1);
344         smp_call_function_self(test_null_handler, 0, &waiter2);
345         smp_call_function_self(test_null_handler, 0, &waiter3);
346         smp_call_function_self(test_null_handler, 0, &waiter4);
347         smp_call_wait(waiter0);
348         smp_call_wait(waiter1);
349         smp_call_wait(waiter2);
350         smp_call_wait(waiter3);
351         smp_call_wait(waiter4);
352         printk("A: %d, B: %d, C: %d (should be 19,19,19)\n", atomic_read(&a), atomic_read(&b), atomic_read(&c));
353         printk("Attempting to deadlock by smp_calling with an outstanding wait:\n");
354         smp_call_function_self(test_null_handler, 0, &waiter0);
355         smp_call_function_self(test_null_handler, 0, &waiter1);
356         smp_call_wait(waiter0);
357         smp_call_wait(waiter1);
358         printk("\tMade it through!\n");
359         printk("Attempting to deadlock by smp_calling more than are available:\n");
360         printk("\tShould see an Insufficient message and a kernel warning.\n");
361         if (smp_call_function_self(test_null_handler, 0, &waiter0))
362                 printk("\tInsufficient handlers to call function (0)\n");
363         if (smp_call_function_self(test_null_handler, 0, &waiter1))
364                 printk("\tInsufficient handlers to call function (1)\n");
365         if (smp_call_function_self(test_null_handler, 0, &waiter2))
366                 printk("\tInsufficient handlers to call function (2)\n");
367         if (smp_call_function_self(test_null_handler, 0, &waiter3))
368                 printk("\tInsufficient handlers to call function (3)\n");
369         if (smp_call_function_self(test_null_handler, 0, &waiter4))
370                 printk("\tInsufficient handlers to call function (4)\n");
371         if (smp_call_function_self(test_null_handler, 0, &waiter5))
372                 printk("\tInsufficient handlers to call function (5)\n");
373         smp_call_wait(waiter0);
374         smp_call_wait(waiter1);
375         smp_call_wait(waiter2);
376         smp_call_wait(waiter3);
377         smp_call_wait(waiter4);
378         smp_call_wait(waiter5);
379         printk("\tMade it through!\n");
380
381         printk("Done\n");
382 }
383
384 #if 0
385 void test_lapic_status_bit(void)
386 {
387         register_interrupt_handler(interrupt_handlers, test_vector,
388                                    test_incrementer_handler, &a);
389         #define NUM_IPI 100000
390         atomic_set(&a,0);
391         printk("IPIs received (should be 0): %d\n", a);
392         for(int i = 0; i < NUM_IPI; i++) {
393                 send_ipi(7, 0, test_vector);
394                 lapic_wait_to_send();
395         }
396         // need to wait a bit to let those IPIs get there
397         udelay(5000000);
398         printk("IPIs received (should be %d): %d\n", a, NUM_IPI);
399         // hopefully that handler never fires again.  leaving it registered for now.
400 }
401 #endif
402
403 /******************************************************************************/
404 /*            Test Measurements: Couples with measurement.c                   */
405 // All user processes can R/W the UGDATA page
406 barrier_t* bar = (barrier_t*)UGDATA;
407 uint32_t* job_to_run = (uint32_t*)(UGDATA + sizeof(barrier_t));
408 env_t* env_batch[64]; // Fairly arbitrary, just the max I plan to use.
409
410 /* Helpers for test_run_measurements */
411 static void wait_for_all_envs_to_die(void)
412 {
413         while (atomic_read(&num_envs))
414                 cpu_relax();
415 }
416
417 // this never returns.
418 static void sync_tests(int start_core, int num_threads, int job_num)
419 {
420         assert(start_core + num_threads <= num_cpus);
421         wait_for_all_envs_to_die();
422         for (int i = start_core; i < start_core + num_threads; i++)
423                 env_batch[i] = ENV_CREATE(roslib_measurements);
424         init_barrier(bar, num_threads);
425         *job_to_run = job_num;
426         for (int i = start_core; i < start_core + num_threads; i++)
427                 smp_call_function_single(i, run_env_handler, env_batch[i], 0);
428         process_workqueue();
429         // we want to fake a run, to reenter manager for the next case
430         env_t *env = ENV_CREATE(roslib_null);
431         smp_call_function_single(0, run_env_handler, env, 0);
432         process_workqueue();
433         panic("whoops!\n");
434 }
435
436 static void async_tests(int start_core, int num_threads, int job_num)
437 {
438         int count;
439
440         assert(start_core + num_threads <= num_cpus);
441         wait_for_all_envs_to_die();
442         for (int i = start_core; i < start_core + num_threads; i++)
443                 env_batch[i] = ENV_CREATE(roslib_measurements);
444         init_barrier(bar, num_threads);
445         *job_to_run = job_num;
446         for (int i = start_core; i < start_core + num_threads; i++)
447                 smp_call_function_single(i, run_env_handler, env_batch[i], 0);
448         count = 0;
449         while (count > -num_threads) {
450                 count = 0;
451                 for (int i = start_core; i < start_core + num_threads; i++) {
452                         count += process_generic_syscalls(env_batch[i], 1);
453                 }
454                 cpu_relax();
455         }
456         // we want to fake a run, to reenter manager for the next case
457         env_t *env = ENV_CREATE(roslib_null);
458         smp_call_function_single(0, run_env_handler, env, 0);
459         process_workqueue();
460         // this all never returns
461         panic("whoops!\n");
462 }
463
464 void test_run_measurements(uint32_t job_num)
465 {
466         switch (job_num) {
467                 case 0: // Nulls
468                         printk("Case 0:\n");
469                         async_tests(2, 1, job_num);  // start core 2, 1 core total
470                         break;
471                 case 1: // Sync
472                         printk("Case 1:\n");
473                         sync_tests(2, 1, job_num);
474                         break;
475                 case 2:
476                         printk("Case 2:\n");
477                         sync_tests(2, 2, job_num);
478                         break;
479                 case 3:
480                         printk("Case 3:\n");
481                         sync_tests(0, 3, job_num);
482                         break;
483                 case 4:
484                         printk("Case 4:\n");
485                         sync_tests(0, 4, job_num);
486                         break;
487                 case 5:
488                         printk("Case 5:\n");
489                         sync_tests(0, 5, job_num);
490                         break;
491                 case 6:
492                         printk("Case 6:\n");
493                         sync_tests(0, 6, job_num);
494                         break;
495                 case 7:
496                         printk("Case 7:\n");
497                         sync_tests(0, 7, job_num);
498                         break;
499                 case 8:
500                         printk("Case 8:\n");
501                         sync_tests(0, 8, job_num);
502                         break;
503                 case 9:
504                         printk("Case 9:\n");
505                         async_tests(2, 1, job_num);
506                         break;
507                 case 10:
508                         printk("Case 10:\n");
509                         async_tests(2, 2, job_num);
510                         break;
511                 case 11:
512                         printk("Case 11:\n");
513                         async_tests(2, 3, job_num);
514                         break;
515                 case 12:
516                         printk("Case 12:\n");
517                         async_tests(2, 4, job_num);
518                         break;
519                 case 13:
520                         printk("Case 13:\n");
521                         async_tests(2, 5, job_num);
522                         break;
523                 case 14:
524                         printk("Case 14:\n");
525                         async_tests(2, 6, job_num);
526                         break;
527                 default:
528                         warn("Invalid test number!!");
529         }
530         panic("Error in test setup!!");
531 }
532
533 /************************************************************/
534 /* ISR Handler Functions */
535
536 void test_hello_world_handler(trapframe_t *tf, void* data)
537 {
538         int trapno;
539         #if defined(__i386__)
540         trapno = tf->tf_trapno;
541         #elif defined(__sparc_v8__)
542         trapno = (tf->tbr >> 4) & 0xFF;
543         #else
544         trapno = 0;
545         #endif
546
547         cprintf("Incoming IRQ, ISR: %d on core %d with tf at 0x%08x\n",
548                 trapno, core_id(), tf);
549 }
550
551 uint32_t print_info_lock = 0;
552
553 void test_print_info_handler(trapframe_t *tf, void* data)
554 {
555         spin_lock_irqsave(&print_info_lock);
556         cprintf("----------------------------\n");
557         cprintf("This is Core %d\n", core_id());
558 #if 0
559         cprintf("MTRR_DEF_TYPE = 0x%08x\n", read_msr(IA32_MTRR_DEF_TYPE));
560         cprintf("MTRR Phys0 Base = 0x%016llx, Mask = 0x%016llx\n",
561                 read_msr(0x200), read_msr(0x201));
562         cprintf("MTRR Phys1 Base = 0x%016llx, Mask = 0x%016llx\n",
563                 read_msr(0x202), read_msr(0x203));
564         cprintf("MTRR Phys2 Base = 0x%016llx, Mask = 0x%016llx\n",
565                 read_msr(0x204), read_msr(0x205));
566         cprintf("MTRR Phys3 Base = 0x%016llx, Mask = 0x%016llx\n",
567                 read_msr(0x206), read_msr(0x207));
568         cprintf("MTRR Phys4 Base = 0x%016llx, Mask = 0x%016llx\n",
569                 read_msr(0x208), read_msr(0x209));
570         cprintf("MTRR Phys5 Base = 0x%016llx, Mask = 0x%016llx\n",
571                 read_msr(0x20a), read_msr(0x20b));
572         cprintf("MTRR Phys6 Base = 0x%016llx, Mask = 0x%016llx\n",
573                 read_msr(0x20c), read_msr(0x20d));
574         cprintf("MTRR Phys7 Base = 0x%016llx, Mask = 0x%016llx\n",
575                 read_msr(0x20e), read_msr(0x20f));
576 #endif
577         cprintf("----------------------------\n");
578         spin_unlock_irqsave(&print_info_lock);
579 }
580
581 void test_barrier_handler(trapframe_t *tf, void* data)
582 {
583         cprintf("Round 1: Core %d\n", core_id());
584         waiton_barrier(&test_cpu_array);
585         waiton_barrier(&test_cpu_array);
586         waiton_barrier(&test_cpu_array);
587         waiton_barrier(&test_cpu_array);
588         waiton_barrier(&test_cpu_array);
589         waiton_barrier(&test_cpu_array);
590         cprintf("Round 2: Core %d\n", core_id());
591         waiton_barrier(&test_cpu_array);
592         cprintf("Round 3: Core %d\n", core_id());
593         // uncomment to see it fucked up
594         //cprintf("Round 4: Core %d\n", core_id());
595 }
596
597 static void test_waiting_handler(trapframe_t *tf, void* data)
598 {
599         {HANDLER_ATOMIC atomic_dec((atomic_t*)data);}
600 }
601
602 #if 0
603 void test_pit(void)
604 {
605         cprintf("Starting test for PIT now (10s)\n");
606         udelay_pit(10000000);
607         cprintf("End now\n");
608         cprintf("Starting test for TSC (if stable) now (10s)\n");
609         udelay(10000000);
610         cprintf("End now\n");
611
612         cprintf("Starting test for LAPIC (if stable) now (10s)\n");
613         enable_irq();
614         lapic_set_timer(10000000, FALSE);
615
616         atomic_t waiting = atomic_init(1);
617         register_interrupt_handler(interrupt_handlers, test_vector,
618                                    test_waiting_handler, &waiting);
619         while(atomic_read(&waiting))
620                 cpu_relax();
621         cprintf("End now\n");
622 }
623 #endif