EOI virtualization and virtual APIC success.
[akaros.git] / kern / include / ros / vmx.h
1 /*
2  * vmx.h: VMX Architecture related definitions
3  * Copyright (c) 2004, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16  * Place - Suite 330, Boston, MA 02111-1307 USA.
17  *
18  * A few random additions are:
19  * Copyright (C) 2006 Qumranet
20  *    Avi Kivity <avi@qumranet.com>
21  *    Yaniv Kamay <yaniv@qumranet.com>
22  *
23  */
24 #ifndef ROS_INC_VMX_H
25 #define ROS_INC_VMX_H
26
27 #define CPU_BASED_VIRTUAL_INTR_PENDING  0x00000004
28 #define CPU_BASED_USE_TSC_OFFSETING     0x00000008
29 #define CPU_BASED_HLT_EXITING           0x00000080
30 #define CPU_BASED_INVDPG_EXITING        0x00000200
31 #define CPU_BASED_MWAIT_EXITING         0x00000400
32 #define CPU_BASED_RDPMC_EXITING         0x00000800
33 #define CPU_BASED_RDTSC_EXITING         0x00001000
34 #define CPU_BASED_CR8_LOAD_EXITING      0x00080000
35 #define CPU_BASED_CR8_STORE_EXITING     0x00100000
36 #define CPU_BASED_TPR_SHADOW            0x00200000
37 #define CPU_BASED_MOV_DR_EXITING        0x00800000
38 #define CPU_BASED_UNCOND_IO_EXITING     0x01000000
39 #define CPU_BASED_ACTIVATE_IO_BITMAP    0x02000000
40 #define CPU_BASED_MSR_BITMAPS           0x10000000
41 #define CPU_BASED_MONITOR_EXITING       0x20000000
42 #define CPU_BASED_PAUSE_EXITING         0x40000000
43
44 /*
45  * Definitions of Primary Processor-Based VM-Execution Controls.
46  */
47 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
48 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
49 #define CPU_BASED_HLT_EXITING                   0x00000080
50 #define CPU_BASED_INVLPG_EXITING                0x00000200
51 #define CPU_BASED_MWAIT_EXITING                 0x00000400
52 #define CPU_BASED_RDPMC_EXITING                 0x00000800
53 #define CPU_BASED_RDTSC_EXITING                 0x00001000
54 #define CPU_BASED_CR3_LOAD_EXITING              0x00008000
55 #define CPU_BASED_CR3_STORE_EXITING             0x00010000
56 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
57 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
58 #define CPU_BASED_TPR_SHADOW                    0x00200000
59 #define CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
60 #define CPU_BASED_MOV_DR_EXITING                0x00800000
61 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
62 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
63 #define CPU_BASED_MONITOR_TRAP                  0x08000000
64 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
65 #define CPU_BASED_MONITOR_EXITING               0x20000000
66 #define CPU_BASED_PAUSE_EXITING                 0x40000000
67 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
68 /*
69  * Definitions of Secondary Processor-Based VM-Execution Controls.
70  */
71 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
72 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
73 #define SECONDARY_EXEC_DESCRIPTOR_EXITING       0x00000004
74 #define SECONDARY_EXEC_RDTSCP                   0x00000008
75 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x00000010
76 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
77 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
78 #define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
79 #define SECONDARY_EXEC_APIC_REGISTER_VIRT       0x00000100
80 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    0x00000200
81 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
82 #define SECONDARY_EXEC_RDRAND_EXITING           0x00000800
83 #define SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
84 #define SECONDARY_EXEC_ENABLE_VMFUNC            0x00002000
85 #define SECONDARY_EXEC_SHADOW_VMCS              0x00004000
86 #define SECONDARY_EXEC_RDSEED_EXITING           0x00010000
87 #define SECONDARY_EPT_VE                        0x00040000
88 #define SECONDARY_ENABLE_XSAV_RESTORE           0x00100000
89
90 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
91 #define PIN_BASED_NMI_EXITING                   0x00000008
92 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
93 #define PIN_BASED_VMX_PREEMPTION_TIMER          0x00000040
94 #define PIN_BASED_POSTED_INTR                   0x00000080
95
96 #define VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000004
97 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
98 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
99 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
100 #define VM_EXIT_SAVE_IA32_PAT                   0x00040000
101 #define VM_EXIT_LOAD_IA32_PAT                   0x00080000
102 #define VM_EXIT_SAVE_IA32_EFER                  0x00100000
103 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
104 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
105
106 #define VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000004
107 #define VM_ENTRY_IA32E_MODE                     0x00000200
108 #define VM_ENTRY_SMM                            0x00000400
109 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
110 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
111 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
112 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
113
114 /* VMCS Encodings */
115 enum vmcs_field {
116         VIRTUAL_PROCESSOR_ID            = 0x00000000,
117         POSTED_NOTIFICATION_VEC         = 0x00000002,
118         GUEST_ES_SELECTOR               = 0x00000800,
119         GUEST_CS_SELECTOR               = 0x00000802,
120         GUEST_SS_SELECTOR               = 0x00000804,
121         GUEST_DS_SELECTOR               = 0x00000806,
122         GUEST_FS_SELECTOR               = 0x00000808,
123         GUEST_GS_SELECTOR               = 0x0000080a,
124         GUEST_LDTR_SELECTOR             = 0x0000080c,
125         GUEST_TR_SELECTOR               = 0x0000080e,
126         GUEST_INTR_STATUS               = 0x00000810,
127         GUEST_PML_INDEX                 = 0x00000812,
128         HOST_ES_SELECTOR                = 0x00000c00,
129         HOST_CS_SELECTOR                = 0x00000c02,
130         HOST_SS_SELECTOR                = 0x00000c04,
131         HOST_DS_SELECTOR                = 0x00000c06,
132         HOST_FS_SELECTOR                = 0x00000c08,
133         HOST_GS_SELECTOR                = 0x00000c0a,
134         HOST_TR_SELECTOR                = 0x00000c0c,
135         IO_BITMAP_A                     = 0x00002000,
136         IO_BITMAP_A_HIGH                = 0x00002001,
137         IO_BITMAP_B                     = 0x00002002,
138         IO_BITMAP_B_HIGH                = 0x00002003,
139         MSR_BITMAP                      = 0x00002004,
140         MSR_BITMAP_HIGH                 = 0x00002005,
141         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
142         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
143         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
144         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
145         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
146         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
147         TSC_OFFSET                      = 0x00002010,
148         TSC_OFFSET_HIGH                 = 0x00002011,
149         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
150         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
151         APIC_ACCESS_ADDR                = 0x00002014,
152         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
153         POSTED_INTR_DESC_ADDR           = 0x00002016,
154         POSTED_INTR_DESC_ADDR_HIGH      = 0x00002017,
155         EPT_POINTER                     = 0x0000201a,
156         EPT_POINTER_HIGH                = 0x0000201b,
157         EOI_EXIT_BITMAP0                = 0x0000201c,
158         EOI_EXIT_BITMAP0_HIGH           = 0x0000201d,
159         EOI_EXIT_BITMAP1                = 0x0000201e,
160         EOI_EXIT_BITMAP1_HIGH           = 0x0000201f,
161         EOI_EXIT_BITMAP2                = 0x00002020,
162         EOI_EXIT_BITMAP2_HIGH           = 0x00002021,
163         EOI_EXIT_BITMAP3                = 0x00002022,
164         EOI_EXIT_BITMAP3_HIGH           = 0x00002023,
165         VMREAD_BITMAP                   = 0x00002026,
166         VMWRITE_BITMAP                  = 0x00002028,
167         XSS_EXIT_BITMAP                 = 0x0000202C,
168         XSS_EXIT_BITMAP_HIGH            = 0x0000202D,
169         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
170         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
171         VMCS_LINK_POINTER               = 0x00002800,
172         VMCS_LINK_POINTER_HIGH          = 0x00002801,
173         GUEST_IA32_DEBUGCTL             = 0x00002802,
174         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
175         GUEST_IA32_PAT                  = 0x00002804,
176         GUEST_IA32_PAT_HIGH             = 0x00002805,
177         GUEST_IA32_EFER                 = 0x00002806,
178         GUEST_IA32_EFER_HIGH            = 0x00002807,
179         GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
180         GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
181         GUEST_PDPTR0                    = 0x0000280a,
182         GUEST_PDPTR0_HIGH               = 0x0000280b,
183         GUEST_PDPTR1                    = 0x0000280c,
184         GUEST_PDPTR1_HIGH               = 0x0000280d,
185         GUEST_PDPTR2                    = 0x0000280e,
186         GUEST_PDPTR2_HIGH               = 0x0000280f,
187         GUEST_PDPTR3                    = 0x00002810,
188         GUEST_PDPTR3_HIGH               = 0x00002811,
189         HOST_IA32_PAT                   = 0x00002c00,
190         HOST_IA32_PAT_HIGH              = 0x00002c01,
191         HOST_IA32_EFER                  = 0x00002c02,
192         HOST_IA32_EFER_HIGH             = 0x00002c03,
193         HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
194         HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
195         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
196         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
197         EXCEPTION_BITMAP                = 0x00004004,
198         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
199         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
200         CR3_TARGET_COUNT                = 0x0000400a,
201         VM_EXIT_CONTROLS                = 0x0000400c,
202         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
203         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
204         VM_ENTRY_CONTROLS               = 0x00004012,
205         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
206         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
207         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
208         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
209         TPR_THRESHOLD                   = 0x0000401c,
210         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
211         PLE_GAP                         = 0x00004020,
212         PLE_WINDOW                      = 0x00004022,
213         VM_INSTRUCTION_ERROR            = 0x00004400,
214         VM_EXIT_REASON                  = 0x00004402,
215         VM_EXIT_INTR_INFO               = 0x00004404,
216         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
217         IDT_VECTORING_INFO_FIELD        = 0x00004408,
218         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
219         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
220         VMX_INSTRUCTION_INFO            = 0x0000440e,
221         GUEST_ES_LIMIT                  = 0x00004800,
222         GUEST_CS_LIMIT                  = 0x00004802,
223         GUEST_SS_LIMIT                  = 0x00004804,
224         GUEST_DS_LIMIT                  = 0x00004806,
225         GUEST_FS_LIMIT                  = 0x00004808,
226         GUEST_GS_LIMIT                  = 0x0000480a,
227         GUEST_LDTR_LIMIT                = 0x0000480c,
228         GUEST_TR_LIMIT                  = 0x0000480e,
229         GUEST_GDTR_LIMIT                = 0x00004810,
230         GUEST_IDTR_LIMIT                = 0x00004812,
231         GUEST_ES_AR_BYTES               = 0x00004814,
232         GUEST_CS_AR_BYTES               = 0x00004816,
233         GUEST_SS_AR_BYTES               = 0x00004818,
234         GUEST_DS_AR_BYTES               = 0x0000481a,
235         GUEST_FS_AR_BYTES               = 0x0000481c,
236         GUEST_GS_AR_BYTES               = 0x0000481e,
237         GUEST_LDTR_AR_BYTES             = 0x00004820,
238         GUEST_TR_AR_BYTES               = 0x00004822,
239         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
240         GUEST_ACTIVITY_STATE            = 0X00004826,
241         GUEST_SYSENTER_CS               = 0x0000482A,
242         HOST_IA32_SYSENTER_CS           = 0x00004c00,
243         CR0_GUEST_HOST_MASK             = 0x00006000,
244         CR4_GUEST_HOST_MASK             = 0x00006002,
245         CR0_READ_SHADOW                 = 0x00006004,
246         CR4_READ_SHADOW                 = 0x00006006,
247         CR3_TARGET_VALUE0               = 0x00006008,
248         CR3_TARGET_VALUE1               = 0x0000600a,
249         CR3_TARGET_VALUE2               = 0x0000600c,
250         CR3_TARGET_VALUE3               = 0x0000600e,
251         EXIT_QUALIFICATION              = 0x00006400,
252         GUEST_LINEAR_ADDRESS            = 0x0000640a,
253         GUEST_CR0                       = 0x00006800,
254         GUEST_CR3                       = 0x00006802,
255         GUEST_CR4                       = 0x00006804,
256         GUEST_ES_BASE                   = 0x00006806,
257         GUEST_CS_BASE                   = 0x00006808,
258         GUEST_SS_BASE                   = 0x0000680a,
259         GUEST_DS_BASE                   = 0x0000680c,
260         GUEST_FS_BASE                   = 0x0000680e,
261         GUEST_GS_BASE                   = 0x00006810,
262         GUEST_LDTR_BASE                 = 0x00006812,
263         GUEST_TR_BASE                   = 0x00006814,
264         GUEST_GDTR_BASE                 = 0x00006816,
265         GUEST_IDTR_BASE                 = 0x00006818,
266         GUEST_DR7                       = 0x0000681a,
267         GUEST_RSP                       = 0x0000681c,
268         GUEST_RIP                       = 0x0000681e,
269         GUEST_RFLAGS                    = 0x00006820,
270         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
271         GUEST_SYSENTER_ESP              = 0x00006824,
272         GUEST_SYSENTER_EIP              = 0x00006826,
273         HOST_CR0                        = 0x00006c00,
274         HOST_CR3                        = 0x00006c02,
275         HOST_CR4                        = 0x00006c04,
276         HOST_FS_BASE                    = 0x00006c06,
277         HOST_GS_BASE                    = 0x00006c08,
278         HOST_TR_BASE                    = 0x00006c0a,
279         HOST_GDTR_BASE                  = 0x00006c0c,
280         HOST_IDTR_BASE                  = 0x00006c0e,
281         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
282         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
283         HOST_RSP                        = 0x00006c14,
284         HOST_RIP                        = 0x00006c16,
285 };
286
287 #define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000
288
289 #define EXIT_REASON_EXCEPTION_NMI       0
290 #define EXIT_REASON_EXTERNAL_INTERRUPT  1
291 #define EXIT_REASON_TRIPLE_FAULT        2
292
293 #define EXIT_REASON_PENDING_INTERRUPT   7
294 #define EXIT_REASON_INTERRUPT_WINDOW    7
295 #define EXIT_REASON_NMI_WINDOW          8
296 #define EXIT_REASON_TASK_SWITCH         9
297 #define EXIT_REASON_CPUID               10
298 #define EXIT_REASON_HLT                 12
299 #define EXIT_REASON_INVD                13
300 #define EXIT_REASON_INVLPG              14
301 #define EXIT_REASON_RDPMC               15
302 #define EXIT_REASON_RDTSC               16
303 #define EXIT_REASON_VMCALL              18
304 #define EXIT_REASON_VMCLEAR             19
305 #define EXIT_REASON_VMLAUNCH            20
306 #define EXIT_REASON_VMPTRLD             21
307 #define EXIT_REASON_VMPTRST             22
308 #define EXIT_REASON_VMREAD              23
309 #define EXIT_REASON_VMRESUME            24
310 #define EXIT_REASON_VMWRITE             25
311 #define EXIT_REASON_VMOFF               26
312 #define EXIT_REASON_VMON                27
313 #define EXIT_REASON_CR_ACCESS           28
314 #define EXIT_REASON_DR_ACCESS           29
315 #define EXIT_REASON_IO_INSTRUCTION      30
316 #define EXIT_REASON_MSR_READ            31
317 #define EXIT_REASON_MSR_WRITE           32
318 #define EXIT_REASON_INVALID_STATE       33
319 #define EXIT_REASON_MWAIT_INSTRUCTION   36
320 #define EXIT_REASON_MONITOR_INSTRUCTION 39
321 #define EXIT_REASON_PAUSE_INSTRUCTION   40
322 #define EXIT_REASON_MCE_DURING_VMENTRY  41
323 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
324 #define EXIT_REASON_APIC_ACCESS         44
325 #define EXIT_REASON_EPT_VIOLATION       48
326 #define EXIT_REASON_EPT_MISCONFIG       49
327 #define EXIT_REASON_WBINVD              54
328 #define EXIT_REASON_XSETBV              55
329 #define EXIT_REASON_APIC_WRITE          56
330 #define EXIT_REASON_INVPCID             58
331
332 #define VMX_EXIT_REASONS \
333         { EXIT_REASON_EXCEPTION_NMI,         "EXCEPTION_NMI" }, \
334         { EXIT_REASON_EXTERNAL_INTERRUPT,    "EXTERNAL_INTERRUPT" }, \
335         { EXIT_REASON_TRIPLE_FAULT,          "TRIPLE_FAULT" }, \
336         { EXIT_REASON_PENDING_INTERRUPT,     "PENDING_INTERRUPT" }, \
337         { EXIT_REASON_NMI_WINDOW,            "NMI_WINDOW" }, \
338         { EXIT_REASON_TASK_SWITCH,           "TASK_SWITCH" }, \
339         { EXIT_REASON_CPUID,                 "CPUID" }, \
340         { EXIT_REASON_HLT,                   "HLT" }, \
341         { EXIT_REASON_INVLPG,                "INVLPG" }, \
342         { EXIT_REASON_RDPMC,                 "RDPMC" }, \
343         { EXIT_REASON_RDTSC,                 "RDTSC" }, \
344         { EXIT_REASON_VMCALL,                "VMCALL" }, \
345         { EXIT_REASON_VMCLEAR,               "VMCLEAR" }, \
346         { EXIT_REASON_VMLAUNCH,              "VMLAUNCH" }, \
347         { EXIT_REASON_VMPTRLD,               "VMPTRLD" }, \
348         { EXIT_REASON_VMPTRST,               "VMPTRST" }, \
349         { EXIT_REASON_VMREAD,                "VMREAD" }, \
350         { EXIT_REASON_VMRESUME,              "VMRESUME" }, \
351         { EXIT_REASON_VMWRITE,               "VMWRITE" }, \
352         { EXIT_REASON_VMOFF,                 "VMOFF" }, \
353         { EXIT_REASON_VMON,                  "VMON" }, \
354         { EXIT_REASON_CR_ACCESS,             "CR_ACCESS" }, \
355         { EXIT_REASON_DR_ACCESS,             "DR_ACCESS" }, \
356         { EXIT_REASON_IO_INSTRUCTION,        "IO_INSTRUCTION" }, \
357         { EXIT_REASON_MSR_READ,              "MSR_READ" }, \
358         { EXIT_REASON_MSR_WRITE,             "MSR_WRITE" }, \
359         { EXIT_REASON_MWAIT_INSTRUCTION,     "MWAIT_INSTRUCTION" }, \
360         { EXIT_REASON_MONITOR_INSTRUCTION,   "MONITOR_INSTRUCTION" }, \
361         { EXIT_REASON_PAUSE_INSTRUCTION,     "PAUSE_INSTRUCTION" }, \
362         { EXIT_REASON_MCE_DURING_VMENTRY,    "MCE_DURING_VMENTRY" }, \
363         { EXIT_REASON_TPR_BELOW_THRESHOLD,   "TPR_BELOW_THRESHOLD" }, \
364         { EXIT_REASON_APIC_ACCESS,           "APIC_ACCESS" }, \
365         { EXIT_REASON_EPT_VIOLATION,         "EPT_VIOLATION" }, \
366         { EXIT_REASON_EPT_MISCONFIG,         "EPT_MISCONFIG" }, \
367         { EXIT_REASON_WBINVD,                "WBINVD" }
368
369 /*
370  * Interruption-information format
371  */
372 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
373 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
374 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
375 #define INTR_INFO_UNBLOCK_NMI           0x1000          /* 12 */
376 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
377 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
378
379 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
380 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
381 #define VECTORING_INFO_DELIEVER_CODE_MASK       INTR_INFO_DELIEVER_CODE_MASK
382 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
383
384 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
385 #define INTR_TYPE_NMI_INTR              (2 << 8) /* NMI */
386 #define INTR_TYPE_HARD_EXCEPTION        (3 << 8) /* processor exception */
387 #define INTR_TYPE_EXCEPTION             (3 << 8)       /* processor exception */  
388 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
389 #define INTR_TYPE_SOFT_EXCEPTION        (6 << 8) /* software exception */
390
391 /* GUEST_INTERRUPTIBILITY_INFO flags. */
392 #define GUEST_INTR_STATE_STI            0x00000001
393 #define GUEST_INTR_STATE_MOV_SS         0x00000002
394 #define GUEST_INTR_STATE_SMI            0x00000004
395 #define GUEST_INTR_STATE_NMI            0x00000008
396
397 /* GUEST_ACTIVITY_STATE flags */
398 #define GUEST_ACTIVITY_ACTIVE           0
399 #define GUEST_ACTIVITY_HLT              1
400 #define GUEST_ACTIVITY_SHUTDOWN         2
401 #define GUEST_ACTIVITY_WAIT_SIPI        3
402
403 /*
404  * Exit Qualifications for MOV for Control Register Access
405  */
406 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control register */
407 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
408 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose register */
409 #define LMSW_SOURCE_DATA_SHIFT 16
410 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT)    /* 16:31 lmsw source */
411 #define REG_EAX                         (0 << 8)
412 #define REG_ECX                         (1 << 8)
413 #define REG_EDX                         (2 << 8)
414 #define REG_EBX                         (3 << 8)
415 #define REG_ESP                         (4 << 8)
416 #define REG_EBP                         (5 << 8)
417 #define REG_ESI                         (6 << 8)
418 #define REG_EDI                         (7 << 8)
419 #define REG_R8                         (8 << 8)
420 #define REG_R9                         (9 << 8)
421 #define REG_R10                        (10 << 8)
422 #define REG_R11                        (11 << 8)
423 #define REG_R12                        (12 << 8)
424 #define REG_R13                        (13 << 8)
425 #define REG_R14                        (14 << 8)
426 #define REG_R15                        (15 << 8)
427
428 /*
429  * Exit Qualifications for MOV for Debug Register Access
430  */
431 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug register */
432 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
433 #define TYPE_MOV_TO_DR                  (0 << 4)
434 #define TYPE_MOV_FROM_DR                (1 << 4)
435 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
436
437
438 /*
439  * Exit Qualifications for APIC-Access
440  */
441 #define APIC_ACCESS_OFFSET              0xfff   /* 11:0, offset within the APIC page */
442 #define APIC_ACCESS_TYPE                0xf000  /* 15:12, access type */
443 #define TYPE_LINEAR_APIC_INST_READ      (0 << 12)
444 #define TYPE_LINEAR_APIC_INST_WRITE     (1 << 12)
445 #define TYPE_LINEAR_APIC_INST_FETCH     (2 << 12)
446 #define TYPE_LINEAR_APIC_EVENT          (3 << 12)
447 #define TYPE_PHYSICAL_APIC_EVENT        (10 << 12)
448 #define TYPE_PHYSICAL_APIC_INST         (15 << 12)
449
450 /* segment AR */
451 #define SEGMENT_AR_L_MASK (1 << 13)
452
453 /* entry controls */
454 #define VM_ENTRY_CONTROLS_IA32E_MASK (1 << 9)
455
456 #define AR_TYPE_ACCESSES_MASK 1
457 #define AR_TYPE_READABLE_MASK (1 << 1)
458 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
459 #define AR_TYPE_CODE_MASK (1 << 3)
460 #define AR_TYPE_MASK 0x0f
461 #define AR_TYPE_BUSY_64_TSS 11
462 #define AR_TYPE_BUSY_32_TSS 11
463 #define AR_TYPE_BUSY_16_TSS 3
464 #define AR_TYPE_LDT 2
465
466 #define AR_UNUSABLE_MASK (1 << 16)
467 #define AR_S_MASK (1 << 4)
468 #define AR_P_MASK (1 << 7)
469 #define AR_L_MASK (1 << 13)
470 #define AR_DB_MASK (1 << 14)
471 #define AR_G_MASK (1 << 15)
472 #define AR_DPL_SHIFT 5
473 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
474
475 #define AR_RESERVD_MASK 0xfffe0f00
476
477 #define TSS_PRIVATE_MEMSLOT                     (KVM_MEMORY_SLOTS + 0)
478 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        (KVM_MEMORY_SLOTS + 1)
479 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT      (KVM_MEMORY_SLOTS + 2)
480
481 #define VMX_NR_VPIDS                            (1 << 16)
482 #define VMX_VPID_EXTENT_SINGLE_CONTEXT          1
483 #define VMX_VPID_EXTENT_ALL_CONTEXT             2
484
485 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR          0
486 #define VMX_EPT_EXTENT_CONTEXT                  1
487 #define VMX_EPT_EXTENT_GLOBAL                   2
488
489 #define VMX_EPT_EXECUTE_ONLY_BIT                (1ull)
490 #define VMX_EPT_PAGE_WALK_4_BIT                 (1ull << 6)
491 #define VMX_EPTP_UC_BIT                         (1ull << 8)
492 #define VMX_EPTP_WB_BIT                         (1ull << 14)
493 #define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
494 #define VMX_EPT_1GB_PAGE_BIT                    (1ull << 17)
495 #define VMX_EPT_INVEPT_BIT                              (1ull << 20)
496 #define VMX_EPT_AD_BIT                              (1ull << 21)
497 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
498 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
499 #define VMX_EPT_EXTENT_INDIVIDUAL_BIT           (1ull << 24)
500
501 #define SHUTDOWN_REASON(r)      ((r) >> 16)
502 #define SHUTDOWN_STATUS(r)      ((r) & 0xffff)
503
504 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT      (1ull << 9) /* (41 - 32) */
505 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT      (1ull << 10) /* (42 - 32) */
506
507 #define VMX_EPT_GAW_4_LVL                               3       /* LVL - 1 */
508 #define VMX_EPT_MAX_GAW                                 0x4
509 #define VMX_EPT_MT_EPTE_SHIFT                   3
510 #define VMX_EPT_GAW_EPTP_SHIFT                  3
511 #define VMX_EPT_AD_ENABLE_BIT                   (1ull << 6)
512 #define VMX_EPT_MEM_TYPE_WB                             0x6ull
513 #define VMX_EPT_READABLE_MASK                   0x1ull
514 #define VMX_EPT_WRITABLE_MASK                   0x2ull
515 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
516 #define VMX_EPT_IPAT_BIT                        (1ull << 6)
517 #define VMX_EPT_ACCESS_BIT                              (1ull << 8)
518 #define VMX_EPT_DIRTY_BIT                               (1ull << 9)
519
520 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
521
522 #define VMX_EPT_FAULT_READ      0x01
523 #define VMX_EPT_FAULT_WRITE     0x02
524 #define VMX_EPT_FAULT_INS       0x04
525
526 #define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
527 #define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
528 #define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
529 #define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
530 #define ASM_VMX_VMPTRST_RAX       ".byte 0x0f, 0xc7, 0x38"
531 #define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
532 #define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
533 #define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
534 #define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
535 #define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
536 #define ASM_VMX_INVEPT            ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
537 #define ASM_VMX_INVVPID           ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
538
539 struct vmx_msr_entry {
540         uint32_t index;
541         uint32_t reserved;
542         uint64_t value;
543 } __attribute__((aligned(16))) ;
544
545 /*
546  * Exit Qualifications for entry failure during or after loading guest state
547  */
548 #define ENTRY_FAIL_DEFAULT              0
549 #define ENTRY_FAIL_PDPTE                2
550 #define ENTRY_FAIL_NMI                  3
551 #define ENTRY_FAIL_VMCS_LINK_PTR        4
552
553 /*
554  * VM-instruction error numbers
555  */
556 enum vm_instruction_error_number {
557         VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
558         VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
559         VMXERR_VMCLEAR_VMXON_POINTER = 3,
560         VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
561         VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
562         VMXERR_VMRESUME_AFTER_VMXOFF = 6,
563         VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
564         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
565         VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
566         VMXERR_VMPTRLD_VMXON_POINTER = 10,
567         VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
568         VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
569         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
570         VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
571         VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
572         VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
573         VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
574         VMXERR_VMCALL_NONCLEAR_VMCS = 19,
575         VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
576         VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
577         VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
578         VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
579         VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
580         VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
581         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
582 };
583
584 #define MSR_IA32_VMX_BASIC_MSR                  0x480
585 #define MSR_IA32_VMX_PINBASED_CTLS_MSR          0x481
586 #define MSR_IA32_VMX_PROCBASED_CTLS_MSR         0x482
587 #define MSR_IA32_VMX_EXIT_CTLS_MSR              0x483
588 #define MSR_IA32_VMX_ENTRY_CTLS_MSR             0x484
589
590 /*
591  * shutdown reasons
592  */
593 enum shutdown_reason {
594         SHUTDOWN_SYS_EXIT = 1,
595         SHUTDOWN_SYS_EXIT_GROUP,
596         SHUTDOWN_SYS_EXECVE,
597         SHUTDOWN_FATAL_SIGNAL,
598         SHUTDOWN_EPT_VIOLATION,
599         SHUTDOWN_NMI_EXCEPTION,
600         SHUTDOWN_UNHANDLED_EXIT_REASON,
601 };
602
603 /* Additional bits for VMMCPs, originally from the Dune version of kvm. */
604 /*
605  * vmx.h - header file for USM VMX driver.
606  */
607
608 /* This is per-guest per-core, and the implementation specific area
609  * should be assumed to have hidden fields.
610  */
611 struct vmcs {
612         uint32_t revision_id;
613         uint32_t abort_code;
614         char _impl_specific[PGSIZE - sizeof(uint32_t) * 2];
615 };
616
617 typedef uint64_t gpa_t;
618 typedef uint64_t gva_t;
619 #define rdmsrl(msr, val) (val) = read_msr((msr))
620 #define rdmsr(msr, low, high) do {uint64_t m = read_msr(msr); low = m; high = m>>32;} while (0)
621
622 struct vmx_capability {
623         uint32_t ept;
624         uint32_t vpid;
625 };
626
627 extern struct vmx_capability vmx_capability;
628
629 struct vmcs_config {
630         int size;
631         int order;
632         uint32_t revision_id;
633         uint32_t pin_based_exec_ctrl;
634         uint32_t cpu_based_exec_ctrl;
635         uint32_t cpu_based_2nd_exec_ctrl;
636         uint32_t vmexit_ctrl;
637         uint32_t vmentry_ctrl;
638 };
639
640 extern struct vmcs_config vmcs_config;
641
642 #define NR_AUTOLOAD_MSRS 8
643
644 /* the horror. */
645 struct desc_struct {
646         union {
647                 struct {
648                         unsigned int a;
649                         unsigned int b;
650                 };
651                 struct {
652                         uint16_t limit0;
653                         uint16_t base0;
654                         unsigned base1: 8, type: 4, s: 1, dpl: 2, p: 1;
655                         unsigned limit: 4, avl: 1, l: 1, d: 1, g: 1, base2: 8;
656                 };
657         };
658 } __attribute__((packed));
659
660 /* LDT or TSS descriptor in the GDT. 16 bytes. */
661 struct ldttss_desc64 {
662         uint16_t limit0;
663         uint16_t base0;
664         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
665         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
666         uint32_t base3;
667         uint32_t zero1;
668 } __attribute__((packed));
669
670 struct vmx_vcpu {
671
672         int cpu;
673         int launched;
674         struct hw_trapframe regs;
675         uint8_t  fail;
676         uint64_t exit_reason;
677         uint64_t host_rsp;
678
679         uint64_t cr2;
680
681         int shutdown;
682         int ret_code;
683         struct proc *proc;
684
685         struct msr_autoload {
686                 unsigned nr;
687                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
688                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
689         } msr_autoload;
690
691         struct vmcs *vmcs;
692 };
693
694 #endif /* ROS_INC_VMX_H */