9284c242e3f2fb5262ba680fd8b138731e42d107
[akaros.git] / kern / include / ros / vmx.h
1 /*
2  * vmx.h: VMX Architecture related definitions
3  * Copyright (c) 2004, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16  * Place - Suite 330, Boston, MA 02111-1307 USA.
17  *
18  * A few random additions are:
19  * Copyright (C) 2006 Qumranet
20  *    Avi Kivity <avi@qumranet.com>
21  *    Yaniv Kamay <yaniv@qumranet.com>
22  *
23  */
24 #ifndef ROS_INC_VMX_H
25 #define ROS_INC_VMX_H
26
27 #define CPU_BASED_VIRTUAL_INTR_PENDING  0x00000004
28 #define CPU_BASED_USE_TSC_OFFSETING     0x00000008
29 #define CPU_BASED_HLT_EXITING           0x00000080
30 #define CPU_BASED_INVDPG_EXITING        0x00000200
31 #define CPU_BASED_MWAIT_EXITING         0x00000400
32 #define CPU_BASED_RDPMC_EXITING         0x00000800
33 #define CPU_BASED_RDTSC_EXITING         0x00001000
34 #define CPU_BASED_CR8_LOAD_EXITING      0x00080000
35 #define CPU_BASED_CR8_STORE_EXITING     0x00100000
36 #define CPU_BASED_TPR_SHADOW            0x00200000
37 #define CPU_BASED_MOV_DR_EXITING        0x00800000
38 #define CPU_BASED_UNCOND_IO_EXITING     0x01000000
39 #define CPU_BASED_ACTIVATE_IO_BITMAP    0x02000000
40 #define CPU_BASED_MSR_BITMAPS           0x10000000
41 #define CPU_BASED_MONITOR_EXITING       0x20000000
42 #define CPU_BASED_PAUSE_EXITING         0x40000000
43
44 /*
45  * Definitions of Primary Processor-Based VM-Execution Controls.
46  */
47 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
48 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
49 #define CPU_BASED_HLT_EXITING                   0x00000080
50 #define CPU_BASED_INVLPG_EXITING                0x00000200
51 #define CPU_BASED_MWAIT_EXITING                 0x00000400
52 #define CPU_BASED_RDPMC_EXITING                 0x00000800
53 #define CPU_BASED_RDTSC_EXITING                 0x00001000
54 #define CPU_BASED_CR3_LOAD_EXITING              0x00008000
55 #define CPU_BASED_CR3_STORE_EXITING             0x00010000
56 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
57 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
58 #define CPU_BASED_TPR_SHADOW                    0x00200000
59 #define CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
60 #define CPU_BASED_MOV_DR_EXITING                0x00800000
61 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
62 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
63 #define CPU_BASED_MONITOR_TRAP                  0x08000000
64 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
65 #define CPU_BASED_MONITOR_EXITING               0x20000000
66 #define CPU_BASED_PAUSE_EXITING                 0x40000000
67 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
68 /*
69  * Definitions of Secondary Processor-Based VM-Execution Controls.
70  */
71 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
72 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
73 #define SECONDARY_EXEC_DESCRIPTOR_EXITING       0x00000004
74 #define SECONDARY_EXEC_RDTSCP                   0x00000008
75 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x00000010
76 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
77 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
78 #define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
79 #define SECONDARY_EXEC_APIC_REGISTER_VIRT       0x00000100
80 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    0x00000200
81 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
82 #define SECONDARY_EXEC_RDRAND_EXITING           0x00000800
83 #define SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
84 #define SECONDARY_EXEC_ENABLE_VMFUNC            0x00002000
85 #define SECONDARY_EXEC_SHADOW_VMCS              0x00004000
86 #define SECONDARY_EXEC_RDSEED_EXITING           0x00010000
87 #define SECONDARY_EPT_VE                        0x00040000
88 #define SECONDARY_ENABLE_XSAV_RESTORE           0x00100000
89
90 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
91 #define PIN_BASED_NMI_EXITING                   0x00000008
92 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
93 #define PIN_BASED_VMX_PREEMPTION_TIMER          0x00000040
94 #define PIN_BASED_POSTED_INTR                   0x00000080
95
96 #define VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000004
97 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
98 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
99 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
100 #define VM_EXIT_SAVE_IA32_PAT                   0x00040000
101 #define VM_EXIT_LOAD_IA32_PAT                   0x00080000
102 #define VM_EXIT_SAVE_IA32_EFER                  0x00100000
103 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
104 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
105
106 #define VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000004
107 #define VM_ENTRY_IA32E_MODE                     0x00000200
108 #define VM_ENTRY_SMM                            0x00000400
109 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
110 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
111 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
112 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
113
114 /* VMCS Encodings */
115 enum vmcs_field {
116         VIRTUAL_PROCESSOR_ID            = 0x00000000,
117         GUEST_ES_SELECTOR               = 0x00000800,
118         GUEST_CS_SELECTOR               = 0x00000802,
119         GUEST_SS_SELECTOR               = 0x00000804,
120         GUEST_DS_SELECTOR               = 0x00000806,
121         GUEST_FS_SELECTOR               = 0x00000808,
122         GUEST_GS_SELECTOR               = 0x0000080a,
123         GUEST_LDTR_SELECTOR             = 0x0000080c,
124         GUEST_TR_SELECTOR               = 0x0000080e,
125         HOST_ES_SELECTOR                = 0x00000c00,
126         HOST_CS_SELECTOR                = 0x00000c02,
127         HOST_SS_SELECTOR                = 0x00000c04,
128         HOST_DS_SELECTOR                = 0x00000c06,
129         HOST_FS_SELECTOR                = 0x00000c08,
130         HOST_GS_SELECTOR                = 0x00000c0a,
131         HOST_TR_SELECTOR                = 0x00000c0c,
132         IO_BITMAP_A                     = 0x00002000,
133         IO_BITMAP_A_HIGH                = 0x00002001,
134         IO_BITMAP_B                     = 0x00002002,
135         IO_BITMAP_B_HIGH                = 0x00002003,
136         MSR_BITMAP                      = 0x00002004,
137         MSR_BITMAP_HIGH                 = 0x00002005,
138         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
139         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
140         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
141         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
142         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
143         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
144         TSC_OFFSET                      = 0x00002010,
145         TSC_OFFSET_HIGH                 = 0x00002011,
146         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
147         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
148         APIC_ACCESS_ADDR                = 0x00002014,
149         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
150         EPT_POINTER                     = 0x0000201a,
151         EPT_POINTER_HIGH                = 0x0000201b,
152         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
153         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
154         VMCS_LINK_POINTER               = 0x00002800,
155         VMCS_LINK_POINTER_HIGH          = 0x00002801,
156         GUEST_IA32_DEBUGCTL             = 0x00002802,
157         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
158         GUEST_IA32_PAT                  = 0x00002804,
159         GUEST_IA32_PAT_HIGH             = 0x00002805,
160         GUEST_IA32_EFER                 = 0x00002806,
161         GUEST_IA32_EFER_HIGH            = 0x00002807,
162         GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
163         GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
164         GUEST_PDPTR0                    = 0x0000280a,
165         GUEST_PDPTR0_HIGH               = 0x0000280b,
166         GUEST_PDPTR1                    = 0x0000280c,
167         GUEST_PDPTR1_HIGH               = 0x0000280d,
168         GUEST_PDPTR2                    = 0x0000280e,
169         GUEST_PDPTR2_HIGH               = 0x0000280f,
170         GUEST_PDPTR3                    = 0x00002810,
171         GUEST_PDPTR3_HIGH               = 0x00002811,
172         HOST_IA32_PAT                   = 0x00002c00,
173         HOST_IA32_PAT_HIGH              = 0x00002c01,
174         HOST_IA32_EFER                  = 0x00002c02,
175         HOST_IA32_EFER_HIGH             = 0x00002c03,
176         HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
177         HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
178         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
179         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
180         EXCEPTION_BITMAP                = 0x00004004,
181         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
182         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
183         CR3_TARGET_COUNT                = 0x0000400a,
184         VM_EXIT_CONTROLS                = 0x0000400c,
185         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
186         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
187         VM_ENTRY_CONTROLS               = 0x00004012,
188         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
189         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
190         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
191         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
192         TPR_THRESHOLD                   = 0x0000401c,
193         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
194         PLE_GAP                         = 0x00004020,
195         PLE_WINDOW                      = 0x00004022,
196         VM_INSTRUCTION_ERROR            = 0x00004400,
197         VM_EXIT_REASON                  = 0x00004402,
198         VM_EXIT_INTR_INFO               = 0x00004404,
199         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
200         IDT_VECTORING_INFO_FIELD        = 0x00004408,
201         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
202         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
203         VMX_INSTRUCTION_INFO            = 0x0000440e,
204         GUEST_ES_LIMIT                  = 0x00004800,
205         GUEST_CS_LIMIT                  = 0x00004802,
206         GUEST_SS_LIMIT                  = 0x00004804,
207         GUEST_DS_LIMIT                  = 0x00004806,
208         GUEST_FS_LIMIT                  = 0x00004808,
209         GUEST_GS_LIMIT                  = 0x0000480a,
210         GUEST_LDTR_LIMIT                = 0x0000480c,
211         GUEST_TR_LIMIT                  = 0x0000480e,
212         GUEST_GDTR_LIMIT                = 0x00004810,
213         GUEST_IDTR_LIMIT                = 0x00004812,
214         GUEST_ES_AR_BYTES               = 0x00004814,
215         GUEST_CS_AR_BYTES               = 0x00004816,
216         GUEST_SS_AR_BYTES               = 0x00004818,
217         GUEST_DS_AR_BYTES               = 0x0000481a,
218         GUEST_FS_AR_BYTES               = 0x0000481c,
219         GUEST_GS_AR_BYTES               = 0x0000481e,
220         GUEST_LDTR_AR_BYTES             = 0x00004820,
221         GUEST_TR_AR_BYTES               = 0x00004822,
222         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
223         GUEST_ACTIVITY_STATE            = 0X00004826,
224         GUEST_SYSENTER_CS               = 0x0000482A,
225         HOST_IA32_SYSENTER_CS           = 0x00004c00,
226         CR0_GUEST_HOST_MASK             = 0x00006000,
227         CR4_GUEST_HOST_MASK             = 0x00006002,
228         CR0_READ_SHADOW                 = 0x00006004,
229         CR4_READ_SHADOW                 = 0x00006006,
230         CR3_TARGET_VALUE0               = 0x00006008,
231         CR3_TARGET_VALUE1               = 0x0000600a,
232         CR3_TARGET_VALUE2               = 0x0000600c,
233         CR3_TARGET_VALUE3               = 0x0000600e,
234         EXIT_QUALIFICATION              = 0x00006400,
235         GUEST_LINEAR_ADDRESS            = 0x0000640a,
236         GUEST_CR0                       = 0x00006800,
237         GUEST_CR3                       = 0x00006802,
238         GUEST_CR4                       = 0x00006804,
239         GUEST_ES_BASE                   = 0x00006806,
240         GUEST_CS_BASE                   = 0x00006808,
241         GUEST_SS_BASE                   = 0x0000680a,
242         GUEST_DS_BASE                   = 0x0000680c,
243         GUEST_FS_BASE                   = 0x0000680e,
244         GUEST_GS_BASE                   = 0x00006810,
245         GUEST_LDTR_BASE                 = 0x00006812,
246         GUEST_TR_BASE                   = 0x00006814,
247         GUEST_GDTR_BASE                 = 0x00006816,
248         GUEST_IDTR_BASE                 = 0x00006818,
249         GUEST_DR7                       = 0x0000681a,
250         GUEST_RSP                       = 0x0000681c,
251         GUEST_RIP                       = 0x0000681e,
252         GUEST_RFLAGS                    = 0x00006820,
253         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
254         GUEST_SYSENTER_ESP              = 0x00006824,
255         GUEST_SYSENTER_EIP              = 0x00006826,
256         HOST_CR0                        = 0x00006c00,
257         HOST_CR3                        = 0x00006c02,
258         HOST_CR4                        = 0x00006c04,
259         HOST_FS_BASE                    = 0x00006c06,
260         HOST_GS_BASE                    = 0x00006c08,
261         HOST_TR_BASE                    = 0x00006c0a,
262         HOST_GDTR_BASE                  = 0x00006c0c,
263         HOST_IDTR_BASE                  = 0x00006c0e,
264         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
265         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
266         HOST_RSP                        = 0x00006c14,
267         HOST_RIP                        = 0x00006c16,
268 };
269
270 #define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000
271
272 #define EXIT_REASON_EXCEPTION_NMI       0
273 #define EXIT_REASON_EXTERNAL_INTERRUPT  1
274 #define EXIT_REASON_TRIPLE_FAULT        2
275
276 #define EXIT_REASON_PENDING_INTERRUPT   7
277 #define EXIT_REASON_INTERRUPT_WINDOW    7
278 #define EXIT_REASON_NMI_WINDOW          8
279 #define EXIT_REASON_TASK_SWITCH         9
280 #define EXIT_REASON_CPUID               10
281 #define EXIT_REASON_HLT                 12
282 #define EXIT_REASON_INVD                13
283 #define EXIT_REASON_INVLPG              14
284 #define EXIT_REASON_RDPMC               15
285 #define EXIT_REASON_RDTSC               16
286 #define EXIT_REASON_VMCALL              18
287 #define EXIT_REASON_VMCLEAR             19
288 #define EXIT_REASON_VMLAUNCH            20
289 #define EXIT_REASON_VMPTRLD             21
290 #define EXIT_REASON_VMPTRST             22
291 #define EXIT_REASON_VMREAD              23
292 #define EXIT_REASON_VMRESUME            24
293 #define EXIT_REASON_VMWRITE             25
294 #define EXIT_REASON_VMOFF               26
295 #define EXIT_REASON_VMON                27
296 #define EXIT_REASON_CR_ACCESS           28
297 #define EXIT_REASON_DR_ACCESS           29
298 #define EXIT_REASON_IO_INSTRUCTION      30
299 #define EXIT_REASON_MSR_READ            31
300 #define EXIT_REASON_MSR_WRITE           32
301 #define EXIT_REASON_INVALID_STATE       33
302 #define EXIT_REASON_MWAIT_INSTRUCTION   36
303 #define EXIT_REASON_MONITOR_INSTRUCTION 39
304 #define EXIT_REASON_PAUSE_INSTRUCTION   40
305 #define EXIT_REASON_MCE_DURING_VMENTRY  41
306 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
307 #define EXIT_REASON_APIC_ACCESS         44
308 #define EXIT_REASON_EPT_VIOLATION       48
309 #define EXIT_REASON_EPT_MISCONFIG       49
310 #define EXIT_REASON_WBINVD              54
311 #define EXIT_REASON_XSETBV              55
312 #define EXIT_REASON_INVPCID             58
313
314 #define VMX_EXIT_REASONS \
315         { EXIT_REASON_EXCEPTION_NMI,         "EXCEPTION_NMI" }, \
316         { EXIT_REASON_EXTERNAL_INTERRUPT,    "EXTERNAL_INTERRUPT" }, \
317         { EXIT_REASON_TRIPLE_FAULT,          "TRIPLE_FAULT" }, \
318         { EXIT_REASON_PENDING_INTERRUPT,     "PENDING_INTERRUPT" }, \
319         { EXIT_REASON_NMI_WINDOW,            "NMI_WINDOW" }, \
320         { EXIT_REASON_TASK_SWITCH,           "TASK_SWITCH" }, \
321         { EXIT_REASON_CPUID,                 "CPUID" }, \
322         { EXIT_REASON_HLT,                   "HLT" }, \
323         { EXIT_REASON_INVLPG,                "INVLPG" }, \
324         { EXIT_REASON_RDPMC,                 "RDPMC" }, \
325         { EXIT_REASON_RDTSC,                 "RDTSC" }, \
326         { EXIT_REASON_VMCALL,                "VMCALL" }, \
327         { EXIT_REASON_VMCLEAR,               "VMCLEAR" }, \
328         { EXIT_REASON_VMLAUNCH,              "VMLAUNCH" }, \
329         { EXIT_REASON_VMPTRLD,               "VMPTRLD" }, \
330         { EXIT_REASON_VMPTRST,               "VMPTRST" }, \
331         { EXIT_REASON_VMREAD,                "VMREAD" }, \
332         { EXIT_REASON_VMRESUME,              "VMRESUME" }, \
333         { EXIT_REASON_VMWRITE,               "VMWRITE" }, \
334         { EXIT_REASON_VMOFF,                 "VMOFF" }, \
335         { EXIT_REASON_VMON,                  "VMON" }, \
336         { EXIT_REASON_CR_ACCESS,             "CR_ACCESS" }, \
337         { EXIT_REASON_DR_ACCESS,             "DR_ACCESS" }, \
338         { EXIT_REASON_IO_INSTRUCTION,        "IO_INSTRUCTION" }, \
339         { EXIT_REASON_MSR_READ,              "MSR_READ" }, \
340         { EXIT_REASON_MSR_WRITE,             "MSR_WRITE" }, \
341         { EXIT_REASON_MWAIT_INSTRUCTION,     "MWAIT_INSTRUCTION" }, \
342         { EXIT_REASON_MONITOR_INSTRUCTION,   "MONITOR_INSTRUCTION" }, \
343         { EXIT_REASON_PAUSE_INSTRUCTION,     "PAUSE_INSTRUCTION" }, \
344         { EXIT_REASON_MCE_DURING_VMENTRY,    "MCE_DURING_VMENTRY" }, \
345         { EXIT_REASON_TPR_BELOW_THRESHOLD,   "TPR_BELOW_THRESHOLD" }, \
346         { EXIT_REASON_APIC_ACCESS,           "APIC_ACCESS" }, \
347         { EXIT_REASON_EPT_VIOLATION,         "EPT_VIOLATION" }, \
348         { EXIT_REASON_EPT_MISCONFIG,         "EPT_MISCONFIG" }, \
349         { EXIT_REASON_WBINVD,                "WBINVD" }
350
351 /*
352  * Interruption-information format
353  */
354 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
355 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
356 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
357 #define INTR_INFO_UNBLOCK_NMI           0x1000          /* 12 */
358 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
359 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
360
361 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
362 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
363 #define VECTORING_INFO_DELIEVER_CODE_MASK       INTR_INFO_DELIEVER_CODE_MASK
364 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
365
366 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
367 #define INTR_TYPE_NMI_INTR              (2 << 8) /* NMI */
368 #define INTR_TYPE_HARD_EXCEPTION        (3 << 8) /* processor exception */
369 #define INTR_TYPE_EXCEPTION             (3 << 8)       /* processor exception */  
370 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
371 #define INTR_TYPE_SOFT_EXCEPTION        (6 << 8) /* software exception */
372
373 /* GUEST_INTERRUPTIBILITY_INFO flags. */
374 #define GUEST_INTR_STATE_STI            0x00000001
375 #define GUEST_INTR_STATE_MOV_SS         0x00000002
376 #define GUEST_INTR_STATE_SMI            0x00000004
377 #define GUEST_INTR_STATE_NMI            0x00000008
378
379 /* GUEST_ACTIVITY_STATE flags */
380 #define GUEST_ACTIVITY_ACTIVE           0
381 #define GUEST_ACTIVITY_HLT              1
382 #define GUEST_ACTIVITY_SHUTDOWN         2
383 #define GUEST_ACTIVITY_WAIT_SIPI        3
384
385 /*
386  * Exit Qualifications for MOV for Control Register Access
387  */
388 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control register */
389 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
390 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose register */
391 #define LMSW_SOURCE_DATA_SHIFT 16
392 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT)    /* 16:31 lmsw source */
393 #define REG_EAX                         (0 << 8)
394 #define REG_ECX                         (1 << 8)
395 #define REG_EDX                         (2 << 8)
396 #define REG_EBX                         (3 << 8)
397 #define REG_ESP                         (4 << 8)
398 #define REG_EBP                         (5 << 8)
399 #define REG_ESI                         (6 << 8)
400 #define REG_EDI                         (7 << 8)
401 #define REG_R8                         (8 << 8)
402 #define REG_R9                         (9 << 8)
403 #define REG_R10                        (10 << 8)
404 #define REG_R11                        (11 << 8)
405 #define REG_R12                        (12 << 8)
406 #define REG_R13                        (13 << 8)
407 #define REG_R14                        (14 << 8)
408 #define REG_R15                        (15 << 8)
409
410 /*
411  * Exit Qualifications for MOV for Debug Register Access
412  */
413 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug register */
414 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
415 #define TYPE_MOV_TO_DR                  (0 << 4)
416 #define TYPE_MOV_FROM_DR                (1 << 4)
417 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
418
419
420 /*
421  * Exit Qualifications for APIC-Access
422  */
423 #define APIC_ACCESS_OFFSET              0xfff   /* 11:0, offset within the APIC page */
424 #define APIC_ACCESS_TYPE                0xf000  /* 15:12, access type */
425 #define TYPE_LINEAR_APIC_INST_READ      (0 << 12)
426 #define TYPE_LINEAR_APIC_INST_WRITE     (1 << 12)
427 #define TYPE_LINEAR_APIC_INST_FETCH     (2 << 12)
428 #define TYPE_LINEAR_APIC_EVENT          (3 << 12)
429 #define TYPE_PHYSICAL_APIC_EVENT        (10 << 12)
430 #define TYPE_PHYSICAL_APIC_INST         (15 << 12)
431
432 /* segment AR */
433 #define SEGMENT_AR_L_MASK (1 << 13)
434
435 /* entry controls */
436 #define VM_ENTRY_CONTROLS_IA32E_MASK (1 << 9)
437
438 #define AR_TYPE_ACCESSES_MASK 1
439 #define AR_TYPE_READABLE_MASK (1 << 1)
440 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
441 #define AR_TYPE_CODE_MASK (1 << 3)
442 #define AR_TYPE_MASK 0x0f
443 #define AR_TYPE_BUSY_64_TSS 11
444 #define AR_TYPE_BUSY_32_TSS 11
445 #define AR_TYPE_BUSY_16_TSS 3
446 #define AR_TYPE_LDT 2
447
448 #define AR_UNUSABLE_MASK (1 << 16)
449 #define AR_S_MASK (1 << 4)
450 #define AR_P_MASK (1 << 7)
451 #define AR_L_MASK (1 << 13)
452 #define AR_DB_MASK (1 << 14)
453 #define AR_G_MASK (1 << 15)
454 #define AR_DPL_SHIFT 5
455 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
456
457 #define AR_RESERVD_MASK 0xfffe0f00
458
459 #define TSS_PRIVATE_MEMSLOT                     (KVM_MEMORY_SLOTS + 0)
460 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        (KVM_MEMORY_SLOTS + 1)
461 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT      (KVM_MEMORY_SLOTS + 2)
462
463 #define VMX_NR_VPIDS                            (1 << 16)
464 #define VMX_VPID_EXTENT_SINGLE_CONTEXT          1
465 #define VMX_VPID_EXTENT_ALL_CONTEXT             2
466
467 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR          0
468 #define VMX_EPT_EXTENT_CONTEXT                  1
469 #define VMX_EPT_EXTENT_GLOBAL                   2
470
471 #define VMX_EPT_EXECUTE_ONLY_BIT                (1ull)
472 #define VMX_EPT_PAGE_WALK_4_BIT                 (1ull << 6)
473 #define VMX_EPTP_UC_BIT                         (1ull << 8)
474 #define VMX_EPTP_WB_BIT                         (1ull << 14)
475 #define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
476 #define VMX_EPT_1GB_PAGE_BIT                    (1ull << 17)
477 #define VMX_EPT_INVEPT_BIT                              (1ull << 20)
478 #define VMX_EPT_AD_BIT                              (1ull << 21)
479 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
480 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
481 #define VMX_EPT_EXTENT_INDIVIDUAL_BIT           (1ull << 24)
482
483 #define SHUTDOWN_REASON(r)      ((r) >> 16)
484 #define SHUTDOWN_STATUS(r)      ((r) & 0xffff)
485
486 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT      (1ull << 9) /* (41 - 32) */
487 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT      (1ull << 10) /* (42 - 32) */
488
489 #define VMX_EPT_GAW_4_LVL                               3       /* LVL - 1 */
490 #define VMX_EPT_MAX_GAW                                 0x4
491 #define VMX_EPT_MT_EPTE_SHIFT                   3
492 #define VMX_EPT_GAW_EPTP_SHIFT                  3
493 #define VMX_EPT_AD_ENABLE_BIT                   (1ull << 6)
494 #define VMX_EPT_MEM_TYPE_WB                             0x6ull
495 #define VMX_EPT_READABLE_MASK                   0x1ull
496 #define VMX_EPT_WRITABLE_MASK                   0x2ull
497 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
498 #define VMX_EPT_IPAT_BIT                        (1ull << 6)
499 #define VMX_EPT_ACCESS_BIT                              (1ull << 8)
500 #define VMX_EPT_DIRTY_BIT                               (1ull << 9)
501
502 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
503
504 #define VMX_EPT_FAULT_READ      0x01
505 #define VMX_EPT_FAULT_WRITE     0x02
506 #define VMX_EPT_FAULT_INS       0x04
507
508 #define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
509 #define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
510 #define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
511 #define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
512 #define ASM_VMX_VMPTRST_RAX       ".byte 0x0f, 0xc7, 0x38"
513 #define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
514 #define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
515 #define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
516 #define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
517 #define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
518 #define ASM_VMX_INVEPT            ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
519 #define ASM_VMX_INVVPID           ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
520
521 struct vmx_msr_entry {
522         uint32_t index;
523         uint32_t reserved;
524         uint64_t value;
525 } __attribute__((aligned(16))) ;
526
527 /*
528  * Exit Qualifications for entry failure during or after loading guest state
529  */
530 #define ENTRY_FAIL_DEFAULT              0
531 #define ENTRY_FAIL_PDPTE                2
532 #define ENTRY_FAIL_NMI                  3
533 #define ENTRY_FAIL_VMCS_LINK_PTR        4
534
535 /*
536  * VM-instruction error numbers
537  */
538 enum vm_instruction_error_number {
539         VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
540         VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
541         VMXERR_VMCLEAR_VMXON_POINTER = 3,
542         VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
543         VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
544         VMXERR_VMRESUME_AFTER_VMXOFF = 6,
545         VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
546         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
547         VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
548         VMXERR_VMPTRLD_VMXON_POINTER = 10,
549         VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
550         VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
551         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
552         VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
553         VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
554         VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
555         VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
556         VMXERR_VMCALL_NONCLEAR_VMCS = 19,
557         VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
558         VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
559         VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
560         VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
561         VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
562         VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
563         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
564 };
565
566 #define MSR_IA32_VMX_BASIC_MSR                  0x480
567 #define MSR_IA32_VMX_PINBASED_CTLS_MSR          0x481
568 #define MSR_IA32_VMX_PROCBASED_CTLS_MSR         0x482
569 #define MSR_IA32_VMX_EXIT_CTLS_MSR              0x483
570 #define MSR_IA32_VMX_ENTRY_CTLS_MSR             0x484
571
572 /*
573  * shutdown reasons
574  */
575 enum shutdown_reason {
576         SHUTDOWN_SYS_EXIT = 1,
577         SHUTDOWN_SYS_EXIT_GROUP,
578         SHUTDOWN_SYS_EXECVE,
579         SHUTDOWN_FATAL_SIGNAL,
580         SHUTDOWN_EPT_VIOLATION,
581         SHUTDOWN_NMI_EXCEPTION,
582         SHUTDOWN_UNHANDLED_EXIT_REASON,
583 };
584
585 /* Additional bits for VMMCPs, originally from the Dune version of kvm. */
586 /*
587  * vmx.h - header file for USM VMX driver.
588  */
589
590 /* This is per-guest per-core, and the implementation specific area
591  * should be assumed to have hidden fields.
592  */
593 struct vmcs {
594         uint32_t revision_id;
595         uint32_t abort_code;
596         char _impl_specific[PGSIZE - sizeof(uint32_t) * 2];
597 };
598
599 typedef uint64_t gpa_t;
600 typedef uint64_t gva_t;
601 #define rdmsrl(msr, val) (val) = read_msr((msr))
602 #define rdmsr(msr, low, high) do {uint64_t m = read_msr(msr); low = m; high = m>>32;} while (0)
603
604 struct vmx_capability {
605         uint32_t ept;
606         uint32_t vpid;
607 };
608
609 extern struct vmx_capability vmx_capability;
610
611 struct vmcs_config {
612         int size;
613         int order;
614         uint32_t revision_id;
615         uint32_t pin_based_exec_ctrl;
616         uint32_t cpu_based_exec_ctrl;
617         uint32_t cpu_based_2nd_exec_ctrl;
618         uint32_t vmexit_ctrl;
619         uint32_t vmentry_ctrl;
620 };
621
622 extern struct vmcs_config vmcs_config;
623
624 #define NR_AUTOLOAD_MSRS 8
625
626 /* the horror. */
627 struct desc_struct {
628         union {
629                 struct {
630                         unsigned int a;
631                         unsigned int b;
632                 };
633                 struct {
634                         uint16_t limit0;
635                         uint16_t base0;
636                         unsigned base1: 8, type: 4, s: 1, dpl: 2, p: 1;
637                         unsigned limit: 4, avl: 1, l: 1, d: 1, g: 1, base2: 8;
638                 };
639         };
640 } __attribute__((packed));
641
642 /* LDT or TSS descriptor in the GDT. 16 bytes. */
643 struct ldttss_desc64 {
644         uint16_t limit0;
645         uint16_t base0;
646         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
647         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
648         uint32_t base3;
649         uint32_t zero1;
650 } __attribute__((packed));
651
652 struct vmx_vcpu {
653
654         int cpu;
655         int launched;
656         struct hw_trapframe regs;
657         uint8_t  fail;
658         uint64_t exit_reason;
659         uint64_t host_rsp;
660
661         uint64_t cr2;
662
663         int shutdown;
664         int ret_code;
665         struct proc *proc;
666
667         struct msr_autoload {
668                 unsigned nr;
669                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
670                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
671         } msr_autoload;
672
673         struct vmcs *vmcs;
674 };
675
676 #endif /* ROS_INC_VMX_H */