9ns: Support rename
[akaros.git] / kern / drivers / net / r8169.c
1 /*
2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3  *
4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6  * Copyright (c) a lot of people too. Please respect their work.
7  *
8  * See MAINTAINERS file for support contact information.
9  */
10
11 #include <linux_compat.h>
12 #include "linux_mii.h"
13 #include <net/tcp.h>
14
15 #define RTL8169_VERSION "2.3LK-NAPI"
16 #define MODULENAME "r8169"
17 #define PFX MODULENAME ": "
18
19 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
20 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
21 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
22 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
23 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
24 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
25 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
26 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
27 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
28 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
29 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
30 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
31 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
32 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
33 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
34 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
35 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
36 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
37 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
38
39 #ifdef RTL8169_DEBUG
40 #define dprintk(fmt, args...) \
41         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
42 #else
43 #define dprintk(fmt, args...)   do {} while (0)
44 #endif /* RTL8169_DEBUG */
45
46 #define R8169_MSG_DEFAULT \
47         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
48
49 #define TX_SLOTS_AVAIL(tp) \
50         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
51
52 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
53 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
54         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
55
56 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
57    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
58 static const int multicast_filter_limit = 32;
59
60 #define MAX_READ_REQUEST_SHIFT  12
61 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
62 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
63
64 #define R8169_REGS_SIZE         256
65 #define R8169_NAPI_WEIGHT       64
66 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
67 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
68 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
69 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
70
71 #define RTL8169_TX_TIMEOUT      (6*HZ)
72 #define RTL8169_PHY_TIMEOUT     (10*HZ)
73
74 /* write/read MMIO register */
75 #define RTL_W8(reg, val8)       write8 ((val8), ioaddr + (reg))
76 #define RTL_W16(reg, val16)     write16 ((val16), ioaddr + (reg))
77 #define RTL_W32(reg, val32)     write32 ((val32), ioaddr + (reg))
78 #define RTL_R8(reg)             read8 (ioaddr + (reg))
79 #define RTL_R16(reg)            read16 (ioaddr + (reg))
80 #define RTL_R32(reg)            read32 (ioaddr + (reg))
81
82 enum mac_version {
83         RTL_GIGA_MAC_VER_01 = 0,
84         RTL_GIGA_MAC_VER_02,
85         RTL_GIGA_MAC_VER_03,
86         RTL_GIGA_MAC_VER_04,
87         RTL_GIGA_MAC_VER_05,
88         RTL_GIGA_MAC_VER_06,
89         RTL_GIGA_MAC_VER_07,
90         RTL_GIGA_MAC_VER_08,
91         RTL_GIGA_MAC_VER_09,
92         RTL_GIGA_MAC_VER_10,
93         RTL_GIGA_MAC_VER_11,
94         RTL_GIGA_MAC_VER_12,
95         RTL_GIGA_MAC_VER_13,
96         RTL_GIGA_MAC_VER_14,
97         RTL_GIGA_MAC_VER_15,
98         RTL_GIGA_MAC_VER_16,
99         RTL_GIGA_MAC_VER_17,
100         RTL_GIGA_MAC_VER_18,
101         RTL_GIGA_MAC_VER_19,
102         RTL_GIGA_MAC_VER_20,
103         RTL_GIGA_MAC_VER_21,
104         RTL_GIGA_MAC_VER_22,
105         RTL_GIGA_MAC_VER_23,
106         RTL_GIGA_MAC_VER_24,
107         RTL_GIGA_MAC_VER_25,
108         RTL_GIGA_MAC_VER_26,
109         RTL_GIGA_MAC_VER_27,
110         RTL_GIGA_MAC_VER_28,
111         RTL_GIGA_MAC_VER_29,
112         RTL_GIGA_MAC_VER_30,
113         RTL_GIGA_MAC_VER_31,
114         RTL_GIGA_MAC_VER_32,
115         RTL_GIGA_MAC_VER_33,
116         RTL_GIGA_MAC_VER_34,
117         RTL_GIGA_MAC_VER_35,
118         RTL_GIGA_MAC_VER_36,
119         RTL_GIGA_MAC_VER_37,
120         RTL_GIGA_MAC_VER_38,
121         RTL_GIGA_MAC_VER_39,
122         RTL_GIGA_MAC_VER_40,
123         RTL_GIGA_MAC_VER_41,
124         RTL_GIGA_MAC_VER_42,
125         RTL_GIGA_MAC_VER_43,
126         RTL_GIGA_MAC_VER_44,
127         RTL_GIGA_MAC_VER_45,
128         RTL_GIGA_MAC_VER_46,
129         RTL_GIGA_MAC_VER_47,
130         RTL_GIGA_MAC_VER_48,
131         RTL_GIGA_MAC_VER_49,
132         RTL_GIGA_MAC_VER_50,
133         RTL_GIGA_MAC_VER_51,
134         RTL_GIGA_MAC_NONE   = 0xff,
135 };
136
137 enum rtl_tx_desc_version {
138         RTL_TD_0        = 0,
139         RTL_TD_1        = 1,
140 };
141
142 #define JUMBO_1K        ETHERMAXTU
143 #define JUMBO_4K        (4*1024 - ETHERHDRSIZE - 2)
144 #define JUMBO_6K        (6*1024 - ETHERHDRSIZE - 2)
145 #define JUMBO_7K        (7*1024 - ETHERHDRSIZE - 2)
146 #define JUMBO_9K        (9*1024 - ETHERHDRSIZE - 2)
147
148 #define _R(NAME,TD,FW,SZ,B) {   \
149         .name = NAME,           \
150         .txd_version = TD,      \
151         .fw_name = FW,          \
152         .jumbo_max = SZ,        \
153         .jumbo_tx_csum = B      \
154 }
155
156 static const struct {
157         const char *name;
158         enum rtl_tx_desc_version txd_version;
159         const char *fw_name;
160         uint16_t jumbo_max;
161         bool jumbo_tx_csum;
162 } rtl_chip_infos[] = {
163         /* PCI devices. */
164         [RTL_GIGA_MAC_VER_01] =
165                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
166         [RTL_GIGA_MAC_VER_02] =
167                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
168         [RTL_GIGA_MAC_VER_03] =
169                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
170         [RTL_GIGA_MAC_VER_04] =
171                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
172         [RTL_GIGA_MAC_VER_05] =
173                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
174         [RTL_GIGA_MAC_VER_06] =
175                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
176         /* PCI-E devices. */
177         [RTL_GIGA_MAC_VER_07] =
178                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
179         [RTL_GIGA_MAC_VER_08] =
180                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
181         [RTL_GIGA_MAC_VER_09] =
182                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
183         [RTL_GIGA_MAC_VER_10] =
184                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
185         [RTL_GIGA_MAC_VER_11] =
186                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
187         [RTL_GIGA_MAC_VER_12] =
188                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
189         [RTL_GIGA_MAC_VER_13] =
190                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
191         [RTL_GIGA_MAC_VER_14] =
192                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
193         [RTL_GIGA_MAC_VER_15] =
194                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
195         [RTL_GIGA_MAC_VER_16] =
196                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
197         [RTL_GIGA_MAC_VER_17] =
198                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
199         [RTL_GIGA_MAC_VER_18] =
200                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
201         [RTL_GIGA_MAC_VER_19] =
202                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
203         [RTL_GIGA_MAC_VER_20] =
204                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
205         [RTL_GIGA_MAC_VER_21] =
206                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
207         [RTL_GIGA_MAC_VER_22] =
208                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
209         [RTL_GIGA_MAC_VER_23] =
210                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
211         [RTL_GIGA_MAC_VER_24] =
212                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
213         [RTL_GIGA_MAC_VER_25] =
214                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
215                                                         JUMBO_9K, false),
216         [RTL_GIGA_MAC_VER_26] =
217                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
218                                                         JUMBO_9K, false),
219         [RTL_GIGA_MAC_VER_27] =
220                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
221         [RTL_GIGA_MAC_VER_28] =
222                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
223         [RTL_GIGA_MAC_VER_29] =
224                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
225                                                         JUMBO_1K, true),
226         [RTL_GIGA_MAC_VER_30] =
227                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
228                                                         JUMBO_1K, true),
229         [RTL_GIGA_MAC_VER_31] =
230                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
231         [RTL_GIGA_MAC_VER_32] =
232                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
233                                                         JUMBO_9K, false),
234         [RTL_GIGA_MAC_VER_33] =
235                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
236                                                         JUMBO_9K, false),
237         [RTL_GIGA_MAC_VER_34] =
238                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
239                                                         JUMBO_9K, false),
240         [RTL_GIGA_MAC_VER_35] =
241                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
242                                                         JUMBO_9K, false),
243         [RTL_GIGA_MAC_VER_36] =
244                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
245                                                         JUMBO_9K, false),
246         [RTL_GIGA_MAC_VER_37] =
247                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
248                                                         JUMBO_1K, true),
249         [RTL_GIGA_MAC_VER_38] =
250                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
251                                                         JUMBO_9K, false),
252         [RTL_GIGA_MAC_VER_39] =
253                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
254                                                         JUMBO_1K, true),
255         [RTL_GIGA_MAC_VER_40] =
256                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
257                                                         JUMBO_9K, false),
258         [RTL_GIGA_MAC_VER_41] =
259                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
260         [RTL_GIGA_MAC_VER_42] =
261                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
262                                                         JUMBO_9K, false),
263         [RTL_GIGA_MAC_VER_43] =
264                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
265                                                         JUMBO_1K, true),
266         [RTL_GIGA_MAC_VER_44] =
267                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
268                                                         JUMBO_9K, false),
269         [RTL_GIGA_MAC_VER_45] =
270                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
271                                                         JUMBO_9K, false),
272         [RTL_GIGA_MAC_VER_46] =
273                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
274                                                         JUMBO_9K, false),
275         [RTL_GIGA_MAC_VER_47] =
276                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
277                                                         JUMBO_1K, false),
278         [RTL_GIGA_MAC_VER_48] =
279                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
280                                                         JUMBO_1K, false),
281         [RTL_GIGA_MAC_VER_49] =
282                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
283                                                         JUMBO_9K, false),
284         [RTL_GIGA_MAC_VER_50] =
285                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
286                                                         JUMBO_9K, false),
287         [RTL_GIGA_MAC_VER_51] =
288                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
289                                                         JUMBO_9K, false),
290 };
291 #undef _R
292
293 enum cfg_version {
294         RTL_CFG_0 = 0x00,
295         RTL_CFG_1,
296         RTL_CFG_2
297 };
298
299 static const struct pci_device_id rtl8169_pci_tbl[] = {
300         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
301         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
302         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
303         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
304         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
305         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
306         { PCI_VENDOR_ID_DLINK,                  0x4300,
307                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
308         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
309         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
310         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
311         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
312         { PCI_VENDOR_ID_LINKSYS,                0x1032,
313                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
314         { 0x0001,                               0x8168,
315                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
316         {0,},
317 };
318
319 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
320
321 static int rx_buf_sz = 16383;
322 static int use_dac = -1;
323 static struct {
324         uint32_t msg_enable;
325 } debug = { -1 };
326
327 enum rtl_registers {
328         MAC0            = 0,    /* Ethernet hardware address. */
329         MAC4            = 4,
330         MAR0            = 8,    /* Multicast filter. */
331         CounterAddrLow          = 0x10,
332         CounterAddrHigh         = 0x14,
333         TxDescStartAddrLow      = 0x20,
334         TxDescStartAddrHigh     = 0x24,
335         TxHDescStartAddrLow     = 0x28,
336         TxHDescStartAddrHigh    = 0x2c,
337         FLASH           = 0x30,
338         ERSR            = 0x36,
339         ChipCmd         = 0x37,
340         TxPoll          = 0x38,
341         IntrMask        = 0x3c,
342         IntrStatus      = 0x3e,
343
344         TxConfig        = 0x40,
345 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
346 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
347
348         RxConfig        = 0x44,
349 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
350 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
351 #define RXCFG_FIFO_SHIFT                13
352                                         /* No threshold before first PCI xfer */
353 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
354 #define RX_EARLY_OFF                    (1 << 11)
355 #define RXCFG_DMA_SHIFT                 8
356                                         /* Unlimited maximum PCI burst. */
357 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
358
359         RxMissed        = 0x4c,
360         Cfg9346         = 0x50,
361         Config0         = 0x51,
362         Config1         = 0x52,
363         Config2         = 0x53,
364 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
365
366         Config3         = 0x54,
367         Config4         = 0x55,
368         Config5         = 0x56,
369         MultiIntr       = 0x5c,
370         PHYAR           = 0x60,
371         PHYstatus       = 0x6c,
372         RxMaxSize       = 0xda,
373         CPlusCmd        = 0xe0,
374         IntrMitigate    = 0xe2,
375         RxDescAddrLow   = 0xe4,
376         RxDescAddrHigh  = 0xe8,
377         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
378
379 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
380
381         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
382
383 #define TxPacketMax     (8064 >> 7)
384 #define EarlySize       0x27
385
386         FuncEvent       = 0xf0,
387         FuncEventMask   = 0xf4,
388         FuncPresetState = 0xf8,
389         IBCR0           = 0xf8,
390         IBCR2           = 0xf9,
391         IBIMR0          = 0xfa,
392         IBISR0          = 0xfb,
393         FuncForceEvent  = 0xfc,
394 };
395
396 enum rtl8110_registers {
397         TBICSR                  = 0x64,
398         TBI_ANAR                = 0x68,
399         TBI_LPAR                = 0x6a,
400 };
401
402 enum rtl8168_8101_registers {
403         CSIDR                   = 0x64,
404         CSIAR                   = 0x68,
405 #define CSIAR_FLAG                      0x80000000
406 #define CSIAR_WRITE_CMD                 0x80000000
407 #define CSIAR_BYTE_ENABLE               0x0f
408 #define CSIAR_BYTE_ENABLE_SHIFT         12
409 #define CSIAR_ADDR_MASK                 0x0fff
410 #define CSIAR_FUNC_CARD                 0x00000000
411 #define CSIAR_FUNC_SDIO                 0x00010000
412 #define CSIAR_FUNC_NIC                  0x00020000
413 #define CSIAR_FUNC_NIC2                 0x00010000
414         PMCH                    = 0x6f,
415         EPHYAR                  = 0x80,
416 #define EPHYAR_FLAG                     0x80000000
417 #define EPHYAR_WRITE_CMD                0x80000000
418 #define EPHYAR_REG_MASK                 0x1f
419 #define EPHYAR_REG_SHIFT                16
420 #define EPHYAR_DATA_MASK                0xffff
421         DLLPR                   = 0xd0,
422 #define PFM_EN                          (1 << 6)
423 #define TX_10M_PS_EN                    (1 << 7)
424         DBG_REG                 = 0xd1,
425 #define FIX_NAK_1                       (1 << 4)
426 #define FIX_NAK_2                       (1 << 3)
427         TWSI                    = 0xd2,
428         MCU                     = 0xd3,
429 #define NOW_IS_OOB                      (1 << 7)
430 #define TX_EMPTY                        (1 << 5)
431 #define RX_EMPTY                        (1 << 4)
432 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
433 #define EN_NDP                          (1 << 3)
434 #define EN_OOB_RESET                    (1 << 2)
435 #define LINK_LIST_RDY                   (1 << 1)
436         EFUSEAR                 = 0xdc,
437 #define EFUSEAR_FLAG                    0x80000000
438 #define EFUSEAR_WRITE_CMD               0x80000000
439 #define EFUSEAR_READ_CMD                0x00000000
440 #define EFUSEAR_REG_MASK                0x03ff
441 #define EFUSEAR_REG_SHIFT               8
442 #define EFUSEAR_DATA_MASK               0xff
443         MISC_1                  = 0xf2,
444 #define PFM_D3COLD_EN                   (1 << 6)
445 };
446
447 enum rtl8168_registers {
448         LED_FREQ                = 0x1a,
449         EEE_LED                 = 0x1b,
450         ERIDR                   = 0x70,
451         ERIAR                   = 0x74,
452 #define ERIAR_FLAG                      0x80000000
453 #define ERIAR_WRITE_CMD                 0x80000000
454 #define ERIAR_READ_CMD                  0x00000000
455 #define ERIAR_ADDR_BYTE_ALIGN           4
456 #define ERIAR_TYPE_SHIFT                16
457 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
458 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
459 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
460 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
461 #define ERIAR_MASK_SHIFT                12
462 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
463 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
464 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
465 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
466 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
467         EPHY_RXER_NUM           = 0x7c,
468         OCPDR                   = 0xb0, /* OCP GPHY access */
469 #define OCPDR_WRITE_CMD                 0x80000000
470 #define OCPDR_READ_CMD                  0x00000000
471 #define OCPDR_REG_MASK                  0x7f
472 #define OCPDR_GPHY_REG_SHIFT            16
473 #define OCPDR_DATA_MASK                 0xffff
474         OCPAR                   = 0xb4,
475 #define OCPAR_FLAG                      0x80000000
476 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
477 #define OCPAR_GPHY_READ_CMD             0x0000f060
478         GPHY_OCP                = 0xb8,
479         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
480         MISC                    = 0xf0, /* 8168e only. */
481 #define TXPLA_RST                       (1 << 29)
482 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
483 #define PWM_EN                          (1 << 22)
484 #define RXDV_GATED_EN                   (1 << 19)
485 #define EARLY_TALLY_EN                  (1 << 16)
486 };
487
488 enum rtl_register_content {
489         /* InterruptStatusBits */
490         SYSErr          = 0x8000,
491         PCSTimeout      = 0x4000,
492         SWInt           = 0x0100,
493         TxDescUnavail   = 0x0080,
494         RxFIFOOver      = 0x0040,
495         LinkChg         = 0x0020,
496         RxOverflow      = 0x0010,
497         TxErr           = 0x0008,
498         TxOK            = 0x0004,
499         RxErr           = 0x0002,
500         RxOK            = 0x0001,
501
502         /* RxStatusDesc */
503         RxBOVF  = (1 << 24),
504         RxFOVF  = (1 << 23),
505         RxRWT   = (1 << 22),
506         RxRES   = (1 << 21),
507         RxRUNT  = (1 << 20),
508         RxCRC   = (1 << 19),
509
510         /* ChipCmdBits */
511         StopReq         = 0x80,
512         CmdReset        = 0x10,
513         CmdRxEnb        = 0x08,
514         CmdTxEnb        = 0x04,
515         RxBufEmpty      = 0x01,
516
517         /* TXPoll register p.5 */
518         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
519         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
520         FSWInt          = 0x01,         /* Forced software interrupt */
521
522         /* Cfg9346Bits */
523         Cfg9346_Lock    = 0x00,
524         Cfg9346_Unlock  = 0xc0,
525
526         /* rx_mode_bits */
527         AcceptErr       = 0x20,
528         AcceptRunt      = 0x10,
529         AcceptBroadcast = 0x08,
530         AcceptMulticast = 0x04,
531         AcceptMyPhys    = 0x02,
532         AcceptAllPhys   = 0x01,
533 #define RX_CONFIG_ACCEPT_MASK           0x3f
534
535         /* TxConfigBits */
536         TxInterFrameGapShift = 24,
537         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
538
539         /* Config1 register p.24 */
540         LEDS1           = (1 << 7),
541         LEDS0           = (1 << 6),
542         Speed_down      = (1 << 4),
543         MEMMAP          = (1 << 3),
544         IOMAP           = (1 << 2),
545         VPD             = (1 << 1),
546         PMEnable        = (1 << 0),     /* Power Management Enable */
547
548         /* Config2 register p. 25 */
549         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
550         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
551         PCI_Clock_66MHz = 0x01,
552         PCI_Clock_33MHz = 0x00,
553
554         /* Config3 register p.25 */
555         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
556         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
557         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
558         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
559         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
560
561         /* Config4 register */
562         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
563
564         /* Config5 register p.27 */
565         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
566         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
567         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
568         Spi_en          = (1 << 3),
569         LanWake         = (1 << 1),     /* LanWake enable/disable */
570         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
571         ASPM_en         = (1 << 0),     /* ASPM enable */
572
573         /* TBICSR p.28 */
574         TBIReset        = 0x80000000,
575         TBILoopback     = 0x40000000,
576         TBINwEnable     = 0x20000000,
577         TBINwRestart    = 0x10000000,
578         TBILinkOk       = 0x02000000,
579         TBINwComplete   = 0x01000000,
580
581         /* CPlusCmd p.31 */
582         EnableBist      = (1 << 15),    // 8168 8101
583         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
584         Normal_mode     = (1 << 13),    // unused
585         Force_half_dup  = (1 << 12),    // 8168 8101
586         Force_rxflow_en = (1 << 11),    // 8168 8101
587         Force_txflow_en = (1 << 10),    // 8168 8101
588         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
589         ASF             = (1 << 8),     // 8168 8101
590         PktCntrDisable  = (1 << 7),     // 8168 8101
591         Mac_dbgo_sel    = 0x001c,       // 8168
592         RxVlan          = (1 << 6),
593         RxChkSum        = (1 << 5),
594         PCIDAC          = (1 << 4),
595         PCIMulRW        = (1 << 3),
596         INTT_0          = 0x0000,       // 8168
597         INTT_1          = 0x0001,       // 8168
598         INTT_2          = 0x0002,       // 8168
599         INTT_3          = 0x0003,       // 8168
600
601         /* rtl8169_PHYstatus */
602         TBI_Enable      = 0x80,
603         TxFlowCtrl      = 0x40,
604         RxFlowCtrl      = 0x20,
605         _1000bpsF       = 0x10,
606         _100bps         = 0x08,
607         _10bps          = 0x04,
608         LinkStatus      = 0x02,
609         FullDup         = 0x01,
610
611         /* _TBICSRBit */
612         TBILinkOK       = 0x02000000,
613
614         /* ResetCounterCommand */
615         CounterReset    = 0x1,
616
617         /* DumpCounterCommand */
618         CounterDump     = 0x8,
619
620         /* magic enable v2 */
621         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
622 };
623
624 enum rtl_desc_bit {
625         /* First doubleword. */
626         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
627         RingEnd         = (1 << 30), /* End of descriptor ring */
628         FirstFrag       = (1 << 29), /* First segment of a packet */
629         LastFrag        = (1 << 28), /* Final segment of a packet */
630 };
631
632 /* Generic case. */
633 enum rtl_tx_desc_bit {
634         /* First doubleword. */
635         TD_LSO          = (1 << 27),            /* Large Send Offload */
636 #define TD_MSS_MAX                      0x07ffu /* MSS value */
637
638         /* Second doubleword. */
639         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
640 };
641
642 /* 8169, 8168b and 810x except 8102e. */
643 enum rtl_tx_desc_bit_0 {
644         /* First doubleword. */
645 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
646         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
647         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
648         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
649 };
650
651 /* 8102e, 8168c and beyond. */
652 enum rtl_tx_desc_bit_1 {
653         /* First doubleword. */
654         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
655         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
656 #define GTTCPHO_SHIFT                   18
657 #define GTTCPHO_MAX                     0x7fU
658
659         /* Second doubleword. */
660 #define TCPHO_SHIFT                     18
661 #define TCPHO_MAX                       0x3ffU
662 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
663         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
664         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
665         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
666         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
667 };
668
669 enum rtl_rx_desc_bit {
670         /* Rx private */
671         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
672         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
673
674 #define RxProtoUDP      (PID1)
675 #define RxProtoTCP      (PID0)
676 #define RxProtoIP       (PID1 | PID0)
677 #define RxProtoMask     RxProtoIP
678
679         IPFail          = (1 << 16), /* IP checksum failed */
680         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
681         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
682         RxVlanTag       = (1 << 16), /* VLAN tag available */
683 };
684
685 #define RsvdMask        0x3fffc000
686
687 struct TxDesc {
688         __le32 opts1;
689         __le32 opts2;
690         __le64 addr;
691 };
692
693 struct RxDesc {
694         __le32 opts1;
695         __le32 opts2;
696         __le64 addr;
697 };
698
699 struct ring_info {
700         struct block    *block;
701         uint32_t                len;
702         uint8_t         __pad[sizeof(void *) - sizeof(uint32_t)];
703 };
704
705 enum features {
706         RTL_FEATURE_WOL         = (1 << 0),
707         RTL_FEATURE_MSI         = (1 << 1),
708         RTL_FEATURE_GMII        = (1 << 2),
709 };
710
711 struct rtl8169_counters {
712         __le64  tx_packets;
713         __le64  rx_packets;
714         __le64  tx_errors;
715         __le32  rx_errors;
716         __le16  rx_missed;
717         __le16  align_errors;
718         __le32  tx_one_collision;
719         __le32  tx_multi_collision;
720         __le64  rx_unicast;
721         __le64  rx_broadcast;
722         __le32  rx_multicast;
723         __le16  tx_aborted;
724         __le16  tx_underun;
725 };
726
727 struct rtl8169_tc_offsets {
728         bool    inited;
729         __le64  tx_errors;
730         __le32  tx_multi_collision;
731         __le16  tx_aborted;
732 };
733
734 enum rtl_flag {
735         RTL_FLAG_TASK_ENABLED,
736         RTL_FLAG_TASK_SLOW_PENDING,
737         RTL_FLAG_TASK_RESET_PENDING,
738         RTL_FLAG_TASK_PHY_PENDING,
739         RTL_FLAG_MAX
740 };
741
742 struct rtl8169_stats {
743         uint64_t                        packets;
744         uint64_t                        bytes;
745         struct u64_stats_sync   syncp;
746 };
747
748 struct rtl_poke_args {
749         struct ether *edev;
750         struct rtl8169_private *tp;
751 };
752
753 struct rtl8169_private {
754         /* 9ns compat */
755         struct pci_device                       *pcidev;
756         struct ether                            *edev;
757         TAILQ_ENTRY(rtl8169_private) link9ns;
758         const struct pci_device_id      *pci_id;                        /* for navigating pci/pnp */
759         struct rendez                           irq_task;                       /* bottom half IRQ */
760         struct poke_tracker                     poker;                          /* tx concurrency */
761         bool                                            active;
762         bool                                            attached;
763
764         void __iomem *mmio_addr;        /* memory map physical address */
765         struct pci_device *pci_dev;
766         struct ether *dev;
767         struct napi_struct napi;
768         uint32_t msg_enable;
769         uint16_t txd_version;
770         uint16_t mac_version;
771         uint32_t cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
772         uint32_t cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
773         uint32_t dirty_tx;
774         struct rtl8169_stats rx_stats;
775         struct rtl8169_stats tx_stats;
776         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
777         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
778         dma_addr_t TxPhyAddr;
779         dma_addr_t RxPhyAddr;
780         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
781         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
782         struct timer_list timer;
783         uint16_t cp_cmd;
784
785         uint16_t event_slow;
786
787         struct mdio_ops {
788                 void (*write)(struct rtl8169_private *, int, int);
789                 int (*read)(struct rtl8169_private *, int);
790         } mdio_ops;
791
792         struct pll_power_ops {
793                 void (*down)(struct rtl8169_private *);
794                 void (*up)(struct rtl8169_private *);
795         } pll_power_ops;
796
797         struct jumbo_ops {
798                 void (*enable)(struct rtl8169_private *);
799                 void (*disable)(struct rtl8169_private *);
800         } jumbo_ops;
801
802         struct csi_ops {
803                 void (*write)(struct rtl8169_private *, int, int);
804                 uint32_t (*read)(struct rtl8169_private *, int);
805         } csi_ops;
806
807         int (*set_speed)(struct ether *, uint8_t aneg, uint16_t sp,
808                          uint8_t dpx, uint32_t adv);
809 #if 0 // AKAROS_PORT
810         int (*get_link_ksettings)(struct ether *,
811                                   struct ethtool_link_ksettings *);
812 #endif
813         void (*phy_reset_enable)(struct rtl8169_private *tp);
814         void (*hw_start)(struct ether *);
815         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
816         unsigned int (*link_ok)(void __iomem *);
817 #if 0 // AKAROS_PORT
818         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
819 #endif
820         bool (*tso_csum)(struct rtl8169_private *, struct block *,
821                          uint32_t *);
822
823         struct {
824                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
825                 qlock_t mutex;
826                 struct work_struct work;
827         } wk;
828
829         unsigned features;
830
831         struct mii_if_info mii;
832         dma_addr_t counters_phys_addr;
833         struct rtl8169_counters *counters;
834         struct rtl8169_tc_offsets tc_offset;
835         uint32_t saved_wolopts;
836         uint32_t opts1_mask;
837
838         struct rtl_fw {
839                 const struct firmware *fw;
840
841 #define RTL_VER_SIZE            32
842
843                 char version[RTL_VER_SIZE];
844
845                 struct rtl_fw_phy_action {
846                         __le32 *code;
847                         size_t size;
848                 } phy_action;
849         } *rtl_fw;
850 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
851
852         uint32_t ocp_base;
853 };
854
855 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
856 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
857 module_param(use_dac, int, 0);
858 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
859 module_param_named(debug, debug.msg_enable, int, 0);
860 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
861 MODULE_LICENSE("GPL");
862 MODULE_VERSION(RTL8169_VERSION);
863 MODULE_FIRMWARE(FIRMWARE_8168D_1);
864 MODULE_FIRMWARE(FIRMWARE_8168D_2);
865 MODULE_FIRMWARE(FIRMWARE_8168E_1);
866 MODULE_FIRMWARE(FIRMWARE_8168E_2);
867 MODULE_FIRMWARE(FIRMWARE_8168E_3);
868 MODULE_FIRMWARE(FIRMWARE_8105E_1);
869 MODULE_FIRMWARE(FIRMWARE_8168F_1);
870 MODULE_FIRMWARE(FIRMWARE_8168F_2);
871 MODULE_FIRMWARE(FIRMWARE_8402_1);
872 MODULE_FIRMWARE(FIRMWARE_8411_1);
873 MODULE_FIRMWARE(FIRMWARE_8411_2);
874 MODULE_FIRMWARE(FIRMWARE_8106E_1);
875 MODULE_FIRMWARE(FIRMWARE_8106E_2);
876 MODULE_FIRMWARE(FIRMWARE_8168G_2);
877 MODULE_FIRMWARE(FIRMWARE_8168G_3);
878 MODULE_FIRMWARE(FIRMWARE_8168H_1);
879 MODULE_FIRMWARE(FIRMWARE_8168H_2);
880 MODULE_FIRMWARE(FIRMWARE_8107E_1);
881 MODULE_FIRMWARE(FIRMWARE_8107E_2);
882
883 static void rtl_lock_work(struct rtl8169_private *tp)
884 {
885         qlock(&tp->wk.mutex);
886 }
887
888 static void rtl_unlock_work(struct rtl8169_private *tp)
889 {
890         qunlock(&tp->wk.mutex);
891 }
892
893 static void rtl_tx_performance_tweak(struct pci_device *pdev, uint16_t force)
894 {
895         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
896                                            PCI_EXP_DEVCTL_READRQ, force);
897 }
898
899 struct rtl_cond {
900         bool (*check)(struct rtl8169_private *);
901         const char *msg;
902 };
903
904 static void rtl_udelay(unsigned int d)
905 {
906         udelay(d);
907 }
908
909 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
910                           void (*delay)(unsigned int), unsigned int d, int n,
911                           bool high)
912 {
913         int i;
914
915         for (i = 0; i < n; i++) {
916                 delay(d);
917                 if (c->check(tp) == high)
918                         return true;
919         }
920         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
921                   c->msg, !high, n, d);
922         return false;
923 }
924
925 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
926                                       const struct rtl_cond *c,
927                                       unsigned int d, int n)
928 {
929         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
930 }
931
932 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
933                                      const struct rtl_cond *c,
934                                      unsigned int d, int n)
935 {
936         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
937 }
938
939 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
940                                       const struct rtl_cond *c,
941                                       unsigned int d, int n)
942 {
943         return rtl_loop_wait(tp, c, msleep, d, n, true);
944 }
945
946 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
947                                      const struct rtl_cond *c,
948                                      unsigned int d, int n)
949 {
950         return rtl_loop_wait(tp, c, msleep, d, n, false);
951 }
952
953 #define DECLARE_RTL_COND(name)                          \
954 static bool name ## _check(struct rtl8169_private *);   \
955                                                         \
956 static const struct rtl_cond name = {                   \
957         .check  = name ## _check,                       \
958         .msg    = #name                                 \
959 };                                                      \
960                                                         \
961 static bool name ## _check(struct rtl8169_private *tp)
962
963 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, uint32_t reg)
964 {
965         if (reg & 0xffff0001) {
966                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
967                 return true;
968         }
969         return false;
970 }
971
972 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
973 {
974         void __iomem *ioaddr = tp->mmio_addr;
975
976         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
977 }
978
979 static void r8168_phy_ocp_write(struct rtl8169_private *tp, uint32_t reg,
980                                 uint32_t data)
981 {
982         void __iomem *ioaddr = tp->mmio_addr;
983
984         if (rtl_ocp_reg_failure(tp, reg))
985                 return;
986
987         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
988
989         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
990 }
991
992 static uint16_t r8168_phy_ocp_read(struct rtl8169_private *tp, uint32_t reg)
993 {
994         void __iomem *ioaddr = tp->mmio_addr;
995
996         if (rtl_ocp_reg_failure(tp, reg))
997                 return 0;
998
999         RTL_W32(GPHY_OCP, reg << 15);
1000
1001         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1002                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1003 }
1004
1005 static void r8168_mac_ocp_write(struct rtl8169_private *tp, uint32_t reg,
1006                                 uint32_t data)
1007 {
1008         void __iomem *ioaddr = tp->mmio_addr;
1009
1010         if (rtl_ocp_reg_failure(tp, reg))
1011                 return;
1012
1013         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1014 }
1015
1016 static uint16_t r8168_mac_ocp_read(struct rtl8169_private *tp, uint32_t reg)
1017 {
1018         void __iomem *ioaddr = tp->mmio_addr;
1019
1020         if (rtl_ocp_reg_failure(tp, reg))
1021                 return 0;
1022
1023         RTL_W32(OCPDR, reg << 15);
1024
1025         return RTL_R32(OCPDR);
1026 }
1027
1028 #define OCP_STD_PHY_BASE        0xa400
1029
1030 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1031 {
1032         if (reg == 0x1f) {
1033                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1034                 return;
1035         }
1036
1037         if (tp->ocp_base != OCP_STD_PHY_BASE)
1038                 reg -= 0x10;
1039
1040         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1041 }
1042
1043 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1044 {
1045         if (tp->ocp_base != OCP_STD_PHY_BASE)
1046                 reg -= 0x10;
1047
1048         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1049 }
1050
1051 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1052 {
1053         if (reg == 0x1f) {
1054                 tp->ocp_base = value << 4;
1055                 return;
1056         }
1057
1058         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1059 }
1060
1061 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1062 {
1063         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1064 }
1065
1066 DECLARE_RTL_COND(rtl_phyar_cond)
1067 {
1068         void __iomem *ioaddr = tp->mmio_addr;
1069
1070         return RTL_R32(PHYAR) & 0x80000000;
1071 }
1072
1073 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1074 {
1075         void __iomem *ioaddr = tp->mmio_addr;
1076
1077         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1078
1079         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1080         /*
1081          * According to hardware specs a 20us delay is required after write
1082          * complete indication, but before sending next command.
1083          */
1084         udelay(20);
1085 }
1086
1087 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1088 {
1089         void __iomem *ioaddr = tp->mmio_addr;
1090         int value;
1091
1092         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1093
1094         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1095                 RTL_R32(PHYAR) & 0xffff : ~0;
1096
1097         /*
1098          * According to hardware specs a 20us delay is required after read
1099          * complete indication, but before sending next command.
1100          */
1101         udelay(20);
1102
1103         return value;
1104 }
1105
1106 DECLARE_RTL_COND(rtl_ocpar_cond)
1107 {
1108         void __iomem *ioaddr = tp->mmio_addr;
1109
1110         return RTL_R32(OCPAR) & OCPAR_FLAG;
1111 }
1112
1113 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg,
1114                                   uint32_t data)
1115 {
1116         void __iomem *ioaddr = tp->mmio_addr;
1117
1118         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1119         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1120         RTL_W32(EPHY_RXER_NUM, 0);
1121
1122         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1123 }
1124
1125 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1126 {
1127         r8168dp_1_mdio_access(tp, reg,
1128                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1129 }
1130
1131 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1132 {
1133         void __iomem *ioaddr = tp->mmio_addr;
1134
1135         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1136
1137         mdelay(1);
1138         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1139         RTL_W32(EPHY_RXER_NUM, 0);
1140
1141         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1142                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1143 }
1144
1145 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1146
1147 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1148 {
1149         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1150 }
1151
1152 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1153 {
1154         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1155 }
1156
1157 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1158 {
1159         void __iomem *ioaddr = tp->mmio_addr;
1160
1161         r8168dp_2_mdio_start(ioaddr);
1162
1163         r8169_mdio_write(tp, reg, value);
1164
1165         r8168dp_2_mdio_stop(ioaddr);
1166 }
1167
1168 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1169 {
1170         void __iomem *ioaddr = tp->mmio_addr;
1171         int value;
1172
1173         r8168dp_2_mdio_start(ioaddr);
1174
1175         value = r8169_mdio_read(tp, reg);
1176
1177         r8168dp_2_mdio_stop(ioaddr);
1178
1179         return value;
1180 }
1181
1182 static void rtl_writephy(struct rtl8169_private *tp, int location,
1183                          uint32_t val)
1184 {
1185         tp->mdio_ops.write(tp, location, val);
1186 }
1187
1188 static int rtl_readphy(struct rtl8169_private *tp, int location)
1189 {
1190         return tp->mdio_ops.read(tp, location);
1191 }
1192
1193 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1194 {
1195         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1196 }
1197
1198 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1199 {
1200         int val;
1201
1202         val = rtl_readphy(tp, reg_addr);
1203         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1204 }
1205
1206 static void rtl_mdio_write(struct ether *dev, int phy_id, int location,
1207                            int val)
1208 {
1209         struct rtl8169_private *tp = netdev_priv(dev);
1210
1211         rtl_writephy(tp, location, val);
1212 }
1213
1214 static int rtl_mdio_read(struct ether *dev, int phy_id, int location)
1215 {
1216         struct rtl8169_private *tp = netdev_priv(dev);
1217
1218         return rtl_readphy(tp, location);
1219 }
1220
1221 DECLARE_RTL_COND(rtl_ephyar_cond)
1222 {
1223         void __iomem *ioaddr = tp->mmio_addr;
1224
1225         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1226 }
1227
1228 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1229 {
1230         void __iomem *ioaddr = tp->mmio_addr;
1231
1232         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1233                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1234
1235         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1236
1237         udelay(10);
1238 }
1239
1240 static uint16_t rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1241 {
1242         void __iomem *ioaddr = tp->mmio_addr;
1243
1244         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1245
1246         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1247                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1248 }
1249
1250 DECLARE_RTL_COND(rtl_eriar_cond)
1251 {
1252         void __iomem *ioaddr = tp->mmio_addr;
1253
1254         return RTL_R32(ERIAR) & ERIAR_FLAG;
1255 }
1256
1257 static void rtl_eri_write(struct rtl8169_private *tp, int addr, uint32_t mask,
1258                           uint32_t val, int type)
1259 {
1260         void __iomem *ioaddr = tp->mmio_addr;
1261
1262         assert(!((addr & 3) || (mask == 0)));
1263         RTL_W32(ERIDR, val);
1264         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1265
1266         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1267 }
1268
1269 static uint32_t rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1270 {
1271         void __iomem *ioaddr = tp->mmio_addr;
1272
1273         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1274
1275         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1276                 RTL_R32(ERIDR) : ~0;
1277 }
1278
1279 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, uint32_t mask,
1280                          uint32_t p, uint32_t m, int type)
1281 {
1282         uint32_t val;
1283
1284         val = rtl_eri_read(tp, addr, type);
1285         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1286 }
1287
1288 static uint32_t r8168dp_ocp_read(struct rtl8169_private *tp, uint8_t mask,
1289                                  uint16_t reg)
1290 {
1291         void __iomem *ioaddr = tp->mmio_addr;
1292
1293         RTL_W32(OCPAR, ((uint32_t)mask & 0x0f) << 12 | (reg & 0x0fff));
1294         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1295                 RTL_R32(OCPDR) : ~0;
1296 }
1297
1298 static uint32_t r8168ep_ocp_read(struct rtl8169_private *tp, uint8_t mask,
1299                             uint16_t reg)
1300 {
1301         return rtl_eri_read(tp, reg, ERIAR_OOB);
1302 }
1303
1304 static uint32_t ocp_read(struct rtl8169_private *tp, uint8_t mask, uint16_t reg)
1305 {
1306         switch (tp->mac_version) {
1307         case RTL_GIGA_MAC_VER_27:
1308         case RTL_GIGA_MAC_VER_28:
1309         case RTL_GIGA_MAC_VER_31:
1310                 return r8168dp_ocp_read(tp, mask, reg);
1311         case RTL_GIGA_MAC_VER_49:
1312         case RTL_GIGA_MAC_VER_50:
1313         case RTL_GIGA_MAC_VER_51:
1314                 return r8168ep_ocp_read(tp, mask, reg);
1315         default:
1316                 panic("BUG");
1317                 return ~0;
1318         }
1319 }
1320
1321 static void r8168dp_ocp_write(struct rtl8169_private *tp, uint8_t mask,
1322                               uint16_t reg, uint32_t data)
1323 {
1324         void __iomem *ioaddr = tp->mmio_addr;
1325
1326         RTL_W32(OCPDR, data);
1327         RTL_W32(OCPAR, OCPAR_FLAG | ((uint32_t)mask & 0x0f) << 12 | (reg & 0x0fff));
1328         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1329 }
1330
1331 static void r8168ep_ocp_write(struct rtl8169_private *tp, uint8_t mask,
1332                               uint16_t reg, uint32_t data)
1333 {
1334         rtl_eri_write(tp, reg, ((uint32_t)mask & 0x0f) << ERIAR_MASK_SHIFT,
1335                       data, ERIAR_OOB);
1336 }
1337
1338 static void ocp_write(struct rtl8169_private *tp, uint8_t mask, uint16_t reg,
1339                       uint32_t data)
1340 {
1341         switch (tp->mac_version) {
1342         case RTL_GIGA_MAC_VER_27:
1343         case RTL_GIGA_MAC_VER_28:
1344         case RTL_GIGA_MAC_VER_31:
1345                 r8168dp_ocp_write(tp, mask, reg, data);
1346                 break;
1347         case RTL_GIGA_MAC_VER_49:
1348         case RTL_GIGA_MAC_VER_50:
1349         case RTL_GIGA_MAC_VER_51:
1350                 r8168ep_ocp_write(tp, mask, reg, data);
1351                 break;
1352         default:
1353                 panic("BUG");
1354                 break;
1355         }
1356 }
1357
1358 static void rtl8168_oob_notify(struct rtl8169_private *tp, uint8_t cmd)
1359 {
1360         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1361
1362         ocp_write(tp, 0x1, 0x30, 0x00000001);
1363 }
1364
1365 #define OOB_CMD_RESET           0x00
1366 #define OOB_CMD_DRIVER_START    0x05
1367 #define OOB_CMD_DRIVER_STOP     0x06
1368
1369 static uint16_t rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1370 {
1371         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1372 }
1373
1374 DECLARE_RTL_COND(rtl_ocp_read_cond)
1375 {
1376         uint16_t reg;
1377
1378         reg = rtl8168_get_ocp_reg(tp);
1379
1380         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1381 }
1382
1383 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1384 {
1385         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1386 }
1387
1388 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1389 {
1390         void __iomem *ioaddr = tp->mmio_addr;
1391
1392         return RTL_R8(IBISR0) & 0x02;
1393 }
1394
1395 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1396 {
1397         void __iomem *ioaddr = tp->mmio_addr;
1398
1399         RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1400         rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1401         RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1402         RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1403 }
1404
1405 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1406 {
1407         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1408         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1409 }
1410
1411 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1412 {
1413         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1414         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1415         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1416 }
1417
1418 static void rtl8168_driver_start(struct rtl8169_private *tp)
1419 {
1420         switch (tp->mac_version) {
1421         case RTL_GIGA_MAC_VER_27:
1422         case RTL_GIGA_MAC_VER_28:
1423         case RTL_GIGA_MAC_VER_31:
1424                 rtl8168dp_driver_start(tp);
1425                 break;
1426         case RTL_GIGA_MAC_VER_49:
1427         case RTL_GIGA_MAC_VER_50:
1428         case RTL_GIGA_MAC_VER_51:
1429                 rtl8168ep_driver_start(tp);
1430                 break;
1431         default:
1432                 panic("BUG");
1433                 break;
1434         }
1435 }
1436
1437 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1438 {
1439         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1440         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1441 }
1442
1443 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1444 {
1445         rtl8168ep_stop_cmac(tp);
1446         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1447         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1448         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1449 }
1450
1451 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1452 {
1453         switch (tp->mac_version) {
1454         case RTL_GIGA_MAC_VER_27:
1455         case RTL_GIGA_MAC_VER_28:
1456         case RTL_GIGA_MAC_VER_31:
1457                 rtl8168dp_driver_stop(tp);
1458                 break;
1459         case RTL_GIGA_MAC_VER_49:
1460         case RTL_GIGA_MAC_VER_50:
1461         case RTL_GIGA_MAC_VER_51:
1462                 rtl8168ep_driver_stop(tp);
1463                 break;
1464         default:
1465                 panic("BUG");
1466                 break;
1467         }
1468 }
1469
1470 static int r8168dp_check_dash(struct rtl8169_private *tp)
1471 {
1472         uint16_t reg = rtl8168_get_ocp_reg(tp);
1473
1474         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1475 }
1476
1477 static int r8168ep_check_dash(struct rtl8169_private *tp)
1478 {
1479         return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1480 }
1481
1482 static int r8168_check_dash(struct rtl8169_private *tp)
1483 {
1484         switch (tp->mac_version) {
1485         case RTL_GIGA_MAC_VER_27:
1486         case RTL_GIGA_MAC_VER_28:
1487         case RTL_GIGA_MAC_VER_31:
1488                 return r8168dp_check_dash(tp);
1489         case RTL_GIGA_MAC_VER_49:
1490         case RTL_GIGA_MAC_VER_50:
1491         case RTL_GIGA_MAC_VER_51:
1492                 return r8168ep_check_dash(tp);
1493         default:
1494                 return 0;
1495         }
1496 }
1497
1498 struct exgmac_reg {
1499         uint16_t addr;
1500         uint16_t mask;
1501         uint32_t val;
1502 };
1503
1504 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1505                                    const struct exgmac_reg *r, int len)
1506 {
1507         while (len-- > 0) {
1508                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1509                 r++;
1510         }
1511 }
1512
1513 DECLARE_RTL_COND(rtl_efusear_cond)
1514 {
1515         void __iomem *ioaddr = tp->mmio_addr;
1516
1517         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1518 }
1519
1520 static uint8_t rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1521 {
1522         void __iomem *ioaddr = tp->mmio_addr;
1523
1524         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1525
1526         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1527                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1528 }
1529
1530 static uint16_t rtl_get_events(struct rtl8169_private *tp)
1531 {
1532         void __iomem *ioaddr = tp->mmio_addr;
1533
1534         return RTL_R16(IntrStatus);
1535 }
1536
1537 static void rtl_ack_events(struct rtl8169_private *tp, uint16_t bits)
1538 {
1539         void __iomem *ioaddr = tp->mmio_addr;
1540
1541         RTL_W16(IntrStatus, bits);
1542         bus_wmb();
1543 }
1544
1545 static void rtl_irq_disable(struct rtl8169_private *tp)
1546 {
1547         void __iomem *ioaddr = tp->mmio_addr;
1548
1549         RTL_W16(IntrMask, 0);
1550         bus_wmb();
1551 }
1552
1553 static void rtl_irq_enable(struct rtl8169_private *tp, uint16_t bits)
1554 {
1555         void __iomem *ioaddr = tp->mmio_addr;
1556
1557         RTL_W16(IntrMask, bits);
1558 }
1559
1560 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1561 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1562 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1563
1564 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1565 {
1566         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1567 }
1568
1569 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1570 {
1571         void __iomem *ioaddr = tp->mmio_addr;
1572
1573         rtl_irq_disable(tp);
1574         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1575         RTL_R8(ChipCmd);
1576 }
1577
1578 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1579 {
1580         void __iomem *ioaddr = tp->mmio_addr;
1581
1582         return RTL_R32(TBICSR) & TBIReset;
1583 }
1584
1585 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1586 {
1587         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1588 }
1589
1590 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1591 {
1592         return RTL_R32(TBICSR) & TBILinkOk;
1593 }
1594
1595 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1596 {
1597         return RTL_R8(PHYstatus) & LinkStatus;
1598 }
1599
1600 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1601 {
1602         void __iomem *ioaddr = tp->mmio_addr;
1603
1604         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1605 }
1606
1607 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1608 {
1609         unsigned int val;
1610
1611         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1612         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1613 }
1614
1615 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1616 {
1617         void __iomem *ioaddr = tp->mmio_addr;
1618         struct ether *dev = tp->dev;
1619
1620         if (!netif_running(dev))
1621                 return;
1622
1623         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1624             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1625                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1626                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1627                                       ERIAR_EXGMAC);
1628                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1629                                       ERIAR_EXGMAC);
1630                 } else if (RTL_R8(PHYstatus) & _100bps) {
1631                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1632                                       ERIAR_EXGMAC);
1633                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1634                                       ERIAR_EXGMAC);
1635                 } else {
1636                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1637                                       ERIAR_EXGMAC);
1638                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1639                                       ERIAR_EXGMAC);
1640                 }
1641                 /* Reset packet filter */
1642                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1643                              ERIAR_EXGMAC);
1644                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1645                              ERIAR_EXGMAC);
1646         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1647                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1648                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1649                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1650                                       ERIAR_EXGMAC);
1651                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1652                                       ERIAR_EXGMAC);
1653                 } else {
1654                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1655                                       ERIAR_EXGMAC);
1656                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1657                                       ERIAR_EXGMAC);
1658                 }
1659         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1660                 if (RTL_R8(PHYstatus) & _10bps) {
1661                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1662                                       ERIAR_EXGMAC);
1663                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1664                                       ERIAR_EXGMAC);
1665                 } else {
1666                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1667                                       ERIAR_EXGMAC);
1668                 }
1669         }
1670 }
1671
1672 static void __rtl8169_check_link_status(struct ether *dev,
1673                                         struct rtl8169_private *tp,
1674                                         void __iomem *ioaddr, bool pm)
1675 {
1676         if (tp->link_ok(ioaddr)) {
1677                 rtl_link_chg_patch(tp);
1678                 /* This is to cancel a scheduled suspend if there's one. */
1679                 if (pm)
1680                         pm_request_resume(&tp->pci_dev->device);
1681                 netif_carrier_on(dev);
1682                 if (net_ratelimit())
1683                         netif_info(tp, ifup, dev, "link up\n");
1684         } else {
1685                 netif_carrier_off(dev);
1686                 netif_info(tp, ifdown, dev, "link down\n");
1687                 if (pm)
1688                         pm_schedule_suspend(&tp->pci_dev->device, 5000);
1689         }
1690 }
1691
1692 static void rtl8169_check_link_status(struct ether *dev,
1693                                       struct rtl8169_private *tp,
1694                                       void __iomem *ioaddr)
1695 {
1696         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1697 }
1698
1699 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1700
1701 static uint32_t __rtl8169_get_wol(struct rtl8169_private *tp)
1702 {
1703         void __iomem *ioaddr = tp->mmio_addr;
1704         uint8_t options;
1705         uint32_t wolopts = 0;
1706
1707         options = RTL_R8(Config1);
1708         if (!(options & PMEnable))
1709                 return 0;
1710
1711         options = RTL_R8(Config3);
1712         if (options & LinkUp)
1713                 wolopts |= WAKE_PHY;
1714         switch (tp->mac_version) {
1715         case RTL_GIGA_MAC_VER_34:
1716         case RTL_GIGA_MAC_VER_35:
1717         case RTL_GIGA_MAC_VER_36:
1718         case RTL_GIGA_MAC_VER_37:
1719         case RTL_GIGA_MAC_VER_38:
1720         case RTL_GIGA_MAC_VER_40:
1721         case RTL_GIGA_MAC_VER_41:
1722         case RTL_GIGA_MAC_VER_42:
1723         case RTL_GIGA_MAC_VER_43:
1724         case RTL_GIGA_MAC_VER_44:
1725         case RTL_GIGA_MAC_VER_45:
1726         case RTL_GIGA_MAC_VER_46:
1727         case RTL_GIGA_MAC_VER_47:
1728         case RTL_GIGA_MAC_VER_48:
1729         case RTL_GIGA_MAC_VER_49:
1730         case RTL_GIGA_MAC_VER_50:
1731         case RTL_GIGA_MAC_VER_51:
1732                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1733                         wolopts |= WAKE_MAGIC;
1734                 break;
1735         default:
1736                 if (options & MagicPacket)
1737                         wolopts |= WAKE_MAGIC;
1738                 break;
1739         }
1740
1741         options = RTL_R8(Config5);
1742         if (options & UWF)
1743                 wolopts |= WAKE_UCAST;
1744         if (options & BWF)
1745                 wolopts |= WAKE_BCAST;
1746         if (options & MWF)
1747                 wolopts |= WAKE_MCAST;
1748
1749         return wolopts;
1750 }
1751
1752 #if 0 // AKAROS_PORT
1753 static void rtl8169_get_wol(struct ether *dev, struct ethtool_wolinfo *wol)
1754 {
1755         struct rtl8169_private *tp = netdev_priv(dev);
1756         struct device *d = &tp->pci_dev->device;
1757
1758         pm_runtime_get_noresume(d);
1759
1760         rtl_lock_work(tp);
1761
1762         wol->supported = WAKE_ANY;
1763         if (pm_runtime_active(d))
1764                 wol->wolopts = __rtl8169_get_wol(tp);
1765         else
1766                 wol->wolopts = tp->saved_wolopts;
1767
1768         rtl_unlock_work(tp);
1769
1770         pm_runtime_put_noidle(d);
1771 }
1772 #endif
1773
1774 static void __rtl8169_set_wol(struct rtl8169_private *tp, uint32_t wolopts)
1775 {
1776         void __iomem *ioaddr = tp->mmio_addr;
1777         unsigned int i, tmp;
1778         static const struct {
1779                 uint32_t opt;
1780                 uint16_t reg;
1781                 uint8_t  mask;
1782         } cfg[] = {
1783                 { WAKE_PHY,   Config3, LinkUp },
1784                 { WAKE_UCAST, Config5, UWF },
1785                 { WAKE_BCAST, Config5, BWF },
1786                 { WAKE_MCAST, Config5, MWF },
1787                 { WAKE_ANY,   Config5, LanWake },
1788                 { WAKE_MAGIC, Config3, MagicPacket }
1789         };
1790         uint8_t options;
1791
1792         RTL_W8(Cfg9346, Cfg9346_Unlock);
1793
1794         switch (tp->mac_version) {
1795         case RTL_GIGA_MAC_VER_34:
1796         case RTL_GIGA_MAC_VER_35:
1797         case RTL_GIGA_MAC_VER_36:
1798         case RTL_GIGA_MAC_VER_37:
1799         case RTL_GIGA_MAC_VER_38:
1800         case RTL_GIGA_MAC_VER_40:
1801         case RTL_GIGA_MAC_VER_41:
1802         case RTL_GIGA_MAC_VER_42:
1803         case RTL_GIGA_MAC_VER_43:
1804         case RTL_GIGA_MAC_VER_44:
1805         case RTL_GIGA_MAC_VER_45:
1806         case RTL_GIGA_MAC_VER_46:
1807         case RTL_GIGA_MAC_VER_47:
1808         case RTL_GIGA_MAC_VER_48:
1809         case RTL_GIGA_MAC_VER_49:
1810         case RTL_GIGA_MAC_VER_50:
1811         case RTL_GIGA_MAC_VER_51:
1812                 tmp = ARRAY_SIZE(cfg) - 1;
1813                 if (wolopts & WAKE_MAGIC)
1814                         rtl_w0w1_eri(tp,
1815                                      0x0dc,
1816                                      ERIAR_MASK_0100,
1817                                      MagicPacket_v2,
1818                                      0x0000,
1819                                      ERIAR_EXGMAC);
1820                 else
1821                         rtl_w0w1_eri(tp,
1822                                      0x0dc,
1823                                      ERIAR_MASK_0100,
1824                                      0x0000,
1825                                      MagicPacket_v2,
1826                                      ERIAR_EXGMAC);
1827                 break;
1828         default:
1829                 tmp = ARRAY_SIZE(cfg);
1830                 break;
1831         }
1832
1833         for (i = 0; i < tmp; i++) {
1834                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1835                 if (wolopts & cfg[i].opt)
1836                         options |= cfg[i].mask;
1837                 RTL_W8(cfg[i].reg, options);
1838         }
1839
1840         switch (tp->mac_version) {
1841         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1842                 options = RTL_R8(Config1) & ~PMEnable;
1843                 if (wolopts)
1844                         options |= PMEnable;
1845                 RTL_W8(Config1, options);
1846                 break;
1847         default:
1848                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1849                 if (wolopts)
1850                         options |= PME_SIGNAL;
1851                 RTL_W8(Config2, options);
1852                 break;
1853         }
1854
1855         RTL_W8(Cfg9346, Cfg9346_Lock);
1856 }
1857
1858 #if 0 // AKAROS_PORT
1859 static int rtl8169_set_wol(struct ether *dev, struct ethtool_wolinfo *wol)
1860 {
1861         struct rtl8169_private *tp = netdev_priv(dev);
1862         struct device *d = &tp->pci_dev->device;
1863
1864         pm_runtime_get_noresume(d);
1865
1866         rtl_lock_work(tp);
1867
1868         if (wol->wolopts)
1869                 tp->features |= RTL_FEATURE_WOL;
1870         else
1871                 tp->features &= ~RTL_FEATURE_WOL;
1872         if (pm_runtime_active(d))
1873                 __rtl8169_set_wol(tp, wol->wolopts);
1874         else
1875                 tp->saved_wolopts = wol->wolopts;
1876
1877         rtl_unlock_work(tp);
1878
1879         device_set_wakeup_enable(&tp->pci_dev->device, wol->wolopts);
1880
1881         pm_runtime_put_noidle(d);
1882
1883         return 0;
1884 }
1885 #endif
1886
1887 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1888 {
1889         return rtl_chip_infos[tp->mac_version].fw_name;
1890 }
1891
1892 #if 0 // AKAROS_PORT
1893 static void rtl8169_get_drvinfo(struct ether *dev,
1894                                 struct ethtool_drvinfo *info)
1895 {
1896         struct rtl8169_private *tp = netdev_priv(dev);
1897         struct rtl_fw *rtl_fw = tp->rtl_fw;
1898
1899         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1900         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1901         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1902         static_assert(!(sizeof(info->fw_version) < sizeof(rtl_fw->version)));
1903         if (!IS_ERR_OR_NULL(rtl_fw))
1904                 strlcpy(info->fw_version, rtl_fw->version,
1905                         sizeof(info->fw_version));
1906 }
1907 #endif
1908
1909 static int rtl8169_get_regs_len(struct ether *dev)
1910 {
1911         return R8169_REGS_SIZE;
1912 }
1913
1914 static int rtl8169_set_speed_tbi(struct ether *dev,
1915                                  uint8_t autoneg, uint16_t speed, uint8_t duplex,
1916                                  uint32_t ignored)
1917 {
1918         struct rtl8169_private *tp = netdev_priv(dev);
1919         void __iomem *ioaddr = tp->mmio_addr;
1920         int ret = 0;
1921         uint32_t reg;
1922
1923         reg = RTL_R32(TBICSR);
1924         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1925             (duplex == DUPLEX_FULL)) {
1926                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1927         } else if (autoneg == AUTONEG_ENABLE)
1928                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1929         else {
1930                 netif_warn(tp, link, dev,
1931                            "incorrect speed setting refused in TBI mode\n");
1932                 ret = -EOPNOTSUPP;
1933         }
1934
1935         return ret;
1936 }
1937
1938 static int rtl8169_set_speed_xmii(struct ether *dev,
1939                                   uint8_t autoneg, uint16_t speed, uint8_t duplex,
1940                                   uint32_t adv)
1941 {
1942         struct rtl8169_private *tp = netdev_priv(dev);
1943         int giga_ctrl, bmcr;
1944         int rc = -EINVAL;
1945
1946         rtl_writephy(tp, 0x1f, 0x0000);
1947
1948         if (autoneg == AUTONEG_ENABLE) {
1949                 int auto_nego;
1950
1951                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1952                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1953                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1954
1955                 if (adv & ADVERTISED_10baseT_Half)
1956                         auto_nego |= ADVERTISE_10HALF;
1957                 if (adv & ADVERTISED_10baseT_Full)
1958                         auto_nego |= ADVERTISE_10FULL;
1959                 if (adv & ADVERTISED_100baseT_Half)
1960                         auto_nego |= ADVERTISE_100HALF;
1961                 if (adv & ADVERTISED_100baseT_Full)
1962                         auto_nego |= ADVERTISE_100FULL;
1963
1964                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1965
1966                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1967                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1968
1969                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1970                 if (tp->mii.supports_gmii) {
1971                         if (adv & ADVERTISED_1000baseT_Half)
1972                                 giga_ctrl |= ADVERTISE_1000HALF;
1973                         if (adv & ADVERTISED_1000baseT_Full)
1974                                 giga_ctrl |= ADVERTISE_1000FULL;
1975                 } else if (adv & (ADVERTISED_1000baseT_Half |
1976                                   ADVERTISED_1000baseT_Full)) {
1977                         netif_info(tp, link, dev,
1978                                    "PHY does not support 1000Mbps\n");
1979                         goto out;
1980                 }
1981
1982                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1983
1984                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1985                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1986         } else {
1987                 giga_ctrl = 0;
1988
1989                 if (speed == SPEED_10)
1990                         bmcr = 0;
1991                 else if (speed == SPEED_100)
1992                         bmcr = BMCR_SPEED100;
1993                 else
1994                         goto out;
1995
1996                 if (duplex == DUPLEX_FULL)
1997                         bmcr |= BMCR_FULLDPLX;
1998         }
1999
2000         rtl_writephy(tp, MII_BMCR, bmcr);
2001
2002         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
2003             tp->mac_version == RTL_GIGA_MAC_VER_03) {
2004                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
2005                         rtl_writephy(tp, 0x17, 0x2138);
2006                         rtl_writephy(tp, 0x0e, 0x0260);
2007                 } else {
2008                         rtl_writephy(tp, 0x17, 0x2108);
2009                         rtl_writephy(tp, 0x0e, 0x0000);
2010                 }
2011         }
2012
2013         rc = 0;
2014 out:
2015         return rc;
2016 }
2017
2018 static int rtl8169_set_speed(struct ether *dev,
2019                              uint8_t autoneg, uint16_t speed, uint8_t duplex,
2020                              uint32_t advertising)
2021 {
2022         struct rtl8169_private *tp = netdev_priv(dev);
2023         int ret;
2024
2025         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
2026         if (ret < 0)
2027                 goto out;
2028
2029         dev->mbps = speed;
2030
2031         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2032             (advertising & ADVERTISED_1000baseT_Full) &&
2033             !pci_is_pcie(tp->pci_dev)) {
2034                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2035         }
2036 out:
2037         return ret;
2038 }
2039
2040 #if 0 // AKAROS_PORT
2041 static int rtl8169_set_settings(struct ether *dev, struct ethtool_cmd *cmd)
2042 {
2043         struct rtl8169_private *tp = netdev_priv(dev);
2044         int ret;
2045
2046         del_timer_sync(&tp->timer);
2047
2048         rtl_lock_work(tp);
2049         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2050                                 cmd->duplex, cmd->advertising);
2051         rtl_unlock_work(tp);
2052
2053         return ret;
2054 }
2055 #endif
2056
2057 static netdev_features_t rtl8169_fix_features(struct ether *dev,
2058         netdev_features_t features)
2059 {
2060         struct rtl8169_private *tp = netdev_priv(dev);
2061
2062         if (dev->mtu > TD_MSS_MAX)
2063                 features &= ~NETIF_F_ALL_TSO;
2064
2065         if (dev->mtu > JUMBO_1K &&
2066             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2067                 features &= ~NETIF_F_IP_CSUM;
2068
2069         return features;
2070 }
2071
2072 static void __rtl8169_set_features(struct ether *dev,
2073                                    netdev_features_t features)
2074 {
2075         struct rtl8169_private *tp = netdev_priv(dev);
2076         void __iomem *ioaddr = tp->mmio_addr;
2077         uint32_t rx_config;
2078
2079         rx_config = RTL_R32(RxConfig);
2080         if (features & NETIF_F_RXALL)
2081                 rx_config |= (AcceptErr | AcceptRunt);
2082         else
2083                 rx_config &= ~(AcceptErr | AcceptRunt);
2084
2085         RTL_W32(RxConfig, rx_config);
2086
2087         if (features & NETIF_F_RXCSUM)
2088                 tp->cp_cmd |= RxChkSum;
2089         else
2090                 tp->cp_cmd &= ~RxChkSum;
2091
2092         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2093                 tp->cp_cmd |= RxVlan;
2094         else
2095                 tp->cp_cmd &= ~RxVlan;
2096
2097         tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2098
2099         RTL_W16(CPlusCmd, tp->cp_cmd);
2100         RTL_R16(CPlusCmd);
2101 }
2102
2103 static int rtl8169_set_features(struct ether *dev,
2104                                 netdev_features_t features)
2105 {
2106         struct rtl8169_private *tp = netdev_priv(dev);
2107
2108         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2109
2110         rtl_lock_work(tp);
2111         if (features ^ dev->feat)
2112                 __rtl8169_set_features(dev, features);
2113         rtl_unlock_work(tp);
2114
2115         return 0;
2116 }
2117
2118
2119 static inline uint32_t rtl8169_tx_vlan_tag(struct block *bp)
2120 {
2121 #if 0 // AKAROS_PORT
2122         return (skb_vlan_tag_present(skb)) ?
2123                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2124 #else
2125         return 0x00;
2126 #endif
2127 }
2128
2129 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2130 {
2131         uint32_t opts2 = le32_to_cpu(desc->opts2);
2132
2133 #if 0 // AKAROS_PORT
2134         if (opts2 & RxVlanTag)
2135                 __vlan_hwaccel_put_tag(skb, cpu_to_be16(ETH_P_8021Q),
2136                                        swab16(opts2 & 0xffff));
2137 #endif
2138 }
2139
2140 #if 0 // AKAROS_PORT
2141 static int rtl8169_get_link_ksettings_tbi(struct ether *dev,
2142                                           struct ethtool_link_ksettings *cmd)
2143 {
2144         struct rtl8169_private *tp = netdev_priv(dev);
2145         void __iomem *ioaddr = tp->mmio_addr;
2146         uint32_t status;
2147         uint32_t supported, advertising;
2148
2149         supported =
2150                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2151         cmd->base.port = PORT_FIBRE;
2152
2153         status = RTL_R32(TBICSR);
2154         advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
2155         cmd->base.autoneg = !!(status & TBINwEnable);
2156
2157         cmd->base.speed = SPEED_1000;
2158         cmd->base.duplex = DUPLEX_FULL; /* Always set */
2159
2160         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2161                                                 supported);
2162         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2163                                                 advertising);
2164
2165         return 0;
2166 }
2167
2168 static int rtl8169_get_link_ksettings_xmii(struct ether *dev,
2169                                            struct ethtool_link_ksettings *cmd)
2170 {
2171         struct rtl8169_private *tp = netdev_priv(dev);
2172
2173         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2174
2175         return 0;
2176 }
2177
2178 static int rtl8169_get_link_ksettings(struct ether *dev,
2179                                       struct ethtool_link_ksettings *cmd)
2180 {
2181         struct rtl8169_private *tp = netdev_priv(dev);
2182         int rc;
2183
2184         rtl_lock_work(tp);
2185         rc = tp->get_link_ksettings(dev, cmd);
2186         rtl_unlock_work(tp);
2187
2188         return rc;
2189 }
2190
2191 static void rtl8169_get_regs(struct ether *dev, struct ethtool_regs *regs,
2192                              void *p)
2193 {
2194         struct rtl8169_private *tp = netdev_priv(dev);
2195         uint32_t __iomem *data = tp->mmio_addr;
2196         uint32_t *dw = p;
2197         int i;
2198
2199         rtl_lock_work(tp);
2200         for (i = 0; i < R8169_REGS_SIZE; i += 4)
2201                 memcpy_fromio(dw++, data++, 4);
2202         rtl_unlock_work(tp);
2203 }
2204 #endif
2205
2206 static uint32_t rtl8169_get_msglevel(struct ether *dev)
2207 {
2208         struct rtl8169_private *tp = netdev_priv(dev);
2209
2210         return tp->msg_enable;
2211 }
2212
2213 static void rtl8169_set_msglevel(struct ether *dev, uint32_t value)
2214 {
2215         struct rtl8169_private *tp = netdev_priv(dev);
2216
2217         tp->msg_enable = value;
2218 }
2219
2220 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2221         "tx_packets",
2222         "rx_packets",
2223         "tx_errors",
2224         "rx_errors",
2225         "rx_missed",
2226         "align_errors",
2227         "tx_single_collisions",
2228         "tx_multi_collisions",
2229         "unicast",
2230         "broadcast",
2231         "multicast",
2232         "tx_aborted",
2233         "tx_underrun",
2234 };
2235
2236 static int rtl8169_get_sset_count(struct ether *dev, int sset)
2237 {
2238         switch (sset) {
2239         case ETH_SS_STATS:
2240                 return ARRAY_SIZE(rtl8169_gstrings);
2241         default:
2242                 return -EOPNOTSUPP;
2243         }
2244 }
2245
2246 DECLARE_RTL_COND(rtl_counters_cond)
2247 {
2248         void __iomem *ioaddr = tp->mmio_addr;
2249
2250         return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2251 }
2252
2253 static bool rtl8169_do_counters(struct ether *dev, uint32_t counter_cmd)
2254 {
2255         struct rtl8169_private *tp = netdev_priv(dev);
2256         void __iomem *ioaddr = tp->mmio_addr;
2257         dma_addr_t paddr = tp->counters_phys_addr;
2258         uint32_t cmd;
2259         bool ret;
2260
2261         RTL_W32(CounterAddrHigh, (uint64_t)paddr >> 32);
2262         cmd = (uint64_t)paddr & DMA_BIT_MASK(32);
2263         RTL_W32(CounterAddrLow, cmd);
2264         RTL_W32(CounterAddrLow, cmd | counter_cmd);
2265
2266         ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2267
2268         RTL_W32(CounterAddrLow, 0);
2269         RTL_W32(CounterAddrHigh, 0);
2270
2271         return ret;
2272 }
2273
2274 static bool rtl8169_reset_counters(struct ether *dev)
2275 {
2276         struct rtl8169_private *tp = netdev_priv(dev);
2277
2278         /*
2279          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2280          * tally counters.
2281          */
2282         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2283                 return true;
2284
2285         return rtl8169_do_counters(dev, CounterReset);
2286 }
2287
2288 static bool rtl8169_update_counters(struct ether *dev)
2289 {
2290         struct rtl8169_private *tp = netdev_priv(dev);
2291         void __iomem *ioaddr = tp->mmio_addr;
2292
2293         /*
2294          * Some chips are unable to dump tally counters when the receiver
2295          * is disabled.
2296          */
2297         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2298                 return true;
2299
2300         return rtl8169_do_counters(dev, CounterDump);
2301 }
2302
2303 static bool rtl8169_init_counter_offsets(struct ether *dev)
2304 {
2305         struct rtl8169_private *tp = netdev_priv(dev);
2306         struct rtl8169_counters *counters = tp->counters;
2307         bool ret = false;
2308
2309         /*
2310          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
2311          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2312          * reset by a power cycle, while the counter values collected by the
2313          * driver are reset at every driver unload/load cycle.
2314          *
2315          * To make sure the HW values returned by @get_stats64 match the SW
2316          * values, we collect the initial values at first open(*) and use them
2317          * as offsets to normalize the values returned by @get_stats64.
2318          *
2319          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2320          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2321          * set at open time by rtl_hw_start.
2322          */
2323
2324         if (tp->tc_offset.inited)
2325                 return true;
2326
2327         /* If both, reset and update fail, propagate to caller. */
2328         if (rtl8169_reset_counters(dev))
2329                 ret = true;
2330
2331         if (rtl8169_update_counters(dev))
2332                 ret = true;
2333
2334         tp->tc_offset.tx_errors = counters->tx_errors;
2335         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2336         tp->tc_offset.tx_aborted = counters->tx_aborted;
2337         tp->tc_offset.inited = true;
2338
2339         return ret;
2340 }
2341
2342 #if 0 // AKAROS_PORT
2343 static void rtl8169_get_ethtool_stats(struct ether *dev,
2344                                       struct ethtool_stats *stats,
2345                                       uint64_t *data)
2346 {
2347         struct rtl8169_private *tp = netdev_priv(dev);
2348         struct device *d = &tp->pci_dev->device;
2349         struct rtl8169_counters *counters = tp->counters;
2350
2351         ASSERT_RTNL();
2352
2353         pm_runtime_get_noresume(d);
2354
2355         if (pm_runtime_active(d))
2356                 rtl8169_update_counters(dev);
2357
2358         pm_runtime_put_noidle(d);
2359
2360         data[0] = le64_to_cpu(counters->tx_packets);
2361         data[1] = le64_to_cpu(counters->rx_packets);
2362         data[2] = le64_to_cpu(counters->tx_errors);
2363         data[3] = le32_to_cpu(counters->rx_errors);
2364         data[4] = le16_to_cpu(counters->rx_missed);
2365         data[5] = le16_to_cpu(counters->align_errors);
2366         data[6] = le32_to_cpu(counters->tx_one_collision);
2367         data[7] = le32_to_cpu(counters->tx_multi_collision);
2368         data[8] = le64_to_cpu(counters->rx_unicast);
2369         data[9] = le64_to_cpu(counters->rx_broadcast);
2370         data[10] = le32_to_cpu(counters->rx_multicast);
2371         data[11] = le16_to_cpu(counters->tx_aborted);
2372         data[12] = le16_to_cpu(counters->tx_underun);
2373 }
2374 #endif
2375
2376 static void rtl8169_get_strings(struct ether *dev, uint32_t stringset,
2377                                 uint8_t *data)
2378 {
2379         switch(stringset) {
2380         case ETH_SS_STATS:
2381                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2382                 break;
2383         }
2384 }
2385
2386 static int rtl8169_nway_reset(struct ether *dev)
2387 {
2388         struct rtl8169_private *tp = netdev_priv(dev);
2389
2390         return mii_nway_restart(&tp->mii);
2391 }
2392
2393 #if 0 // AKAROS_PORT
2394 static const struct ethtool_ops rtl8169_ethtool_ops = {
2395         .get_drvinfo            = rtl8169_get_drvinfo,
2396         .get_regs_len           = rtl8169_get_regs_len,
2397         .get_link               = ethtool_op_get_link,
2398         .set_settings           = rtl8169_set_settings,
2399         .get_msglevel           = rtl8169_get_msglevel,
2400         .set_msglevel           = rtl8169_set_msglevel,
2401         .get_regs               = rtl8169_get_regs,
2402         .get_wol                = rtl8169_get_wol,
2403         .set_wol                = rtl8169_set_wol,
2404         .get_strings            = rtl8169_get_strings,
2405         .get_sset_count         = rtl8169_get_sset_count,
2406         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2407         .get_ts_info            = ethtool_op_get_ts_info,
2408         .nway_reset             = rtl8169_nway_reset,
2409         .get_link_ksettings     = rtl8169_get_link_ksettings,
2410 };
2411 #endif
2412
2413 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2414                                     struct ether *dev,
2415                                     uint8_t default_version)
2416 {
2417         void __iomem *ioaddr = tp->mmio_addr;
2418         /*
2419          * The driver currently handles the 8168Bf and the 8168Be identically
2420          * but they can be identified more specifically through the test below
2421          * if needed:
2422          *
2423          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2424          *
2425          * Same thing for the 8101Eb and the 8101Ec:
2426          *
2427          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2428          */
2429         static const struct rtl_mac_info {
2430                 uint32_t mask;
2431                 uint32_t val;
2432                 int mac_version;
2433         } mac_info[] = {
2434                 /* 8168EP family. */
2435                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2436                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2437                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2438
2439                 /* 8168H family. */
2440                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2441                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2442
2443                 /* 8168G family. */
2444                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2445                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2446                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2447                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2448
2449                 /* 8168F family. */
2450                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2451                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2452                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2453
2454                 /* 8168E family. */
2455                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2456                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2457                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2458                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2459
2460                 /* 8168D family. */
2461                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2462                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2463                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2464
2465                 /* 8168DP family. */
2466                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2467                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2468                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2469
2470                 /* 8168C family. */
2471                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2472                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2473                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2474                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2475                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2476                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2477                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2478                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2479                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2480
2481                 /* 8168B family. */
2482                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2483                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2484                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2485                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2486
2487                 /* 8101 family. */
2488                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2489                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2490                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2491                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2492                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2493                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2494                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2495                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2496                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2497                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2498                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2499                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2500                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2501                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2502                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2503                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2504                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2505                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2506                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2507                 /* FIXME: where did these entries come from ? -- FR */
2508                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2509                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2510
2511                 /* 8110 family. */
2512                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2513                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2514                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2515                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2516                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2517                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2518
2519                 /* Catch-all */
2520                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2521         };
2522         const struct rtl_mac_info *p = mac_info;
2523         uint32_t reg;
2524
2525         reg = RTL_R32(TxConfig);
2526         while ((reg & p->mask) != p->val)
2527                 p++;
2528         tp->mac_version = p->mac_version;
2529
2530         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2531                 netif_notice(tp, probe, dev,
2532                              "unknown MAC, using family default\n");
2533                 tp->mac_version = default_version;
2534         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2535                 tp->mac_version = tp->mii.supports_gmii ?
2536                                   RTL_GIGA_MAC_VER_42 :
2537                                   RTL_GIGA_MAC_VER_43;
2538         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2539                 tp->mac_version = tp->mii.supports_gmii ?
2540                                   RTL_GIGA_MAC_VER_45 :
2541                                   RTL_GIGA_MAC_VER_47;
2542         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2543                 tp->mac_version = tp->mii.supports_gmii ?
2544                                   RTL_GIGA_MAC_VER_46 :
2545                                   RTL_GIGA_MAC_VER_48;
2546         }
2547 }
2548
2549 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2550 {
2551         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2552 }
2553
2554 struct phy_reg {
2555         uint16_t reg;
2556         uint16_t val;
2557 };
2558
2559 static void rtl_writephy_batch(struct rtl8169_private *tp,
2560                                const struct phy_reg *regs, int len)
2561 {
2562         while (len-- > 0) {
2563                 rtl_writephy(tp, regs->reg, regs->val);
2564                 regs++;
2565         }
2566 }
2567
2568 #define PHY_READ                0x00000000
2569 #define PHY_DATA_OR             0x10000000
2570 #define PHY_DATA_AND            0x20000000
2571 #define PHY_BJMPN               0x30000000
2572 #define PHY_MDIO_CHG            0x40000000
2573 #define PHY_CLEAR_READCOUNT     0x70000000
2574 #define PHY_WRITE               0x80000000
2575 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2576 #define PHY_COMP_EQ_SKIPN       0xa0000000
2577 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2578 #define PHY_WRITE_PREVIOUS      0xc0000000
2579 #define PHY_SKIPN               0xd0000000
2580 #define PHY_DELAY_MS            0xe0000000
2581
2582 struct fw_info {
2583         uint32_t        magic;
2584         char    version[RTL_VER_SIZE];
2585         __le32  fw_start;
2586         __le32  fw_len;
2587         uint8_t chksum;
2588 } __packed;
2589
2590 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2591
2592 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2593 {
2594         const struct firmware *fw = rtl_fw->fw;
2595         struct fw_info *fw_info = (struct fw_info *)fw->data;
2596         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2597         char *version = rtl_fw->version;
2598         bool rc = false;
2599
2600         if (fw->size < FW_OPCODE_SIZE)
2601                 goto out;
2602
2603         if (!fw_info->magic) {
2604                 size_t i, size, start;
2605                 uint8_t checksum = 0;
2606
2607                 if (fw->size < sizeof(*fw_info))
2608                         goto out;
2609
2610                 for (i = 0; i < fw->size; i++)
2611                         checksum += fw->data[i];
2612                 if (checksum != 0)
2613                         goto out;
2614
2615                 start = le32_to_cpu(fw_info->fw_start);
2616                 if (start > fw->size)
2617                         goto out;
2618
2619                 size = le32_to_cpu(fw_info->fw_len);
2620                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2621                         goto out;
2622
2623                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2624
2625                 pa->code = (__le32 *)(fw->data + start);
2626                 pa->size = size;
2627         } else {
2628                 if (fw->size % FW_OPCODE_SIZE)
2629                         goto out;
2630
2631                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2632
2633                 pa->code = (__le32 *)fw->data;
2634                 pa->size = fw->size / FW_OPCODE_SIZE;
2635         }
2636         version[RTL_VER_SIZE - 1] = 0;
2637
2638         rc = true;
2639 out:
2640         return rc;
2641 }
2642
2643 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct ether *dev,
2644                            struct rtl_fw_phy_action *pa)
2645 {
2646         bool rc = false;
2647         size_t index;
2648
2649         for (index = 0; index < pa->size; index++) {
2650                 uint32_t action = le32_to_cpu(pa->code[index]);
2651                 uint32_t regno = (action & 0x0fff0000) >> 16;
2652
2653                 switch(action & 0xf0000000) {
2654                 case PHY_READ:
2655                 case PHY_DATA_OR:
2656                 case PHY_DATA_AND:
2657                 case PHY_MDIO_CHG:
2658                 case PHY_CLEAR_READCOUNT:
2659                 case PHY_WRITE:
2660                 case PHY_WRITE_PREVIOUS:
2661                 case PHY_DELAY_MS:
2662                         break;
2663
2664                 case PHY_BJMPN:
2665                         if (regno > index) {
2666                                 netif_err(tp, ifup, tp->dev,
2667                                           "Out of range of firmware\n");
2668                                 goto out;
2669                         }
2670                         break;
2671                 case PHY_READCOUNT_EQ_SKIP:
2672                         if (index + 2 >= pa->size) {
2673                                 netif_err(tp, ifup, tp->dev,
2674                                           "Out of range of firmware\n");
2675                                 goto out;
2676                         }
2677                         break;
2678                 case PHY_COMP_EQ_SKIPN:
2679                 case PHY_COMP_NEQ_SKIPN:
2680                 case PHY_SKIPN:
2681                         if (index + 1 + regno >= pa->size) {
2682                                 netif_err(tp, ifup, tp->dev,
2683                                           "Out of range of firmware\n");
2684                                 goto out;
2685                         }
2686                         break;
2687
2688                 default:
2689                         netif_err(tp, ifup, tp->dev,
2690                                   "Invalid action 0x%08x\n", action);
2691                         goto out;
2692                 }
2693         }
2694         rc = true;
2695 out:
2696         return rc;
2697 }
2698
2699 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2700 {
2701         struct ether *dev = tp->dev;
2702         int rc = -EINVAL;
2703
2704         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2705                 netif_err(tp, ifup, dev, "invalid firmware\n");
2706                 goto out;
2707         }
2708
2709         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2710                 rc = 0;
2711 out:
2712         return rc;
2713 }
2714
2715 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2716 {
2717         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2718         struct mdio_ops org, *ops = &tp->mdio_ops;
2719         uint32_t predata, count;
2720         size_t index;
2721
2722         predata = count = 0;
2723         org.write = ops->write;
2724         org.read = ops->read;
2725
2726         for (index = 0; index < pa->size; ) {
2727                 uint32_t action = le32_to_cpu(pa->code[index]);
2728                 uint32_t data = action & 0x0000ffff;
2729                 uint32_t regno = (action & 0x0fff0000) >> 16;
2730
2731                 if (!action)
2732                         break;
2733
2734                 switch(action & 0xf0000000) {
2735                 case PHY_READ:
2736                         predata = rtl_readphy(tp, regno);
2737                         count++;
2738                         index++;
2739                         break;
2740                 case PHY_DATA_OR:
2741                         predata |= data;
2742                         index++;
2743                         break;
2744                 case PHY_DATA_AND:
2745                         predata &= data;
2746                         index++;
2747                         break;
2748                 case PHY_BJMPN:
2749                         index -= regno;
2750                         break;
2751                 case PHY_MDIO_CHG:
2752                         if (data == 0) {
2753                                 ops->write = org.write;
2754                                 ops->read = org.read;
2755                         } else if (data == 1) {
2756                                 ops->write = mac_mcu_write;
2757                                 ops->read = mac_mcu_read;
2758                         }
2759
2760                         index++;
2761                         break;
2762                 case PHY_CLEAR_READCOUNT:
2763                         count = 0;
2764                         index++;
2765                         break;
2766                 case PHY_WRITE:
2767                         rtl_writephy(tp, regno, data);
2768                         index++;
2769                         break;
2770                 case PHY_READCOUNT_EQ_SKIP:
2771                         index += (count == data) ? 2 : 1;
2772                         break;
2773                 case PHY_COMP_EQ_SKIPN:
2774                         if (predata == data)
2775                                 index += regno;
2776                         index++;
2777                         break;
2778                 case PHY_COMP_NEQ_SKIPN:
2779                         if (predata != data)
2780                                 index += regno;
2781                         index++;
2782                         break;
2783                 case PHY_WRITE_PREVIOUS:
2784                         rtl_writephy(tp, regno, predata);
2785                         index++;
2786                         break;
2787                 case PHY_SKIPN:
2788                         index += regno + 1;
2789                         break;
2790                 case PHY_DELAY_MS:
2791                         mdelay(data);
2792                         index++;
2793                         break;
2794
2795                 default:
2796                         panic("BUG");
2797                 }
2798         }
2799
2800         ops->write = org.write;
2801         ops->read = org.read;
2802 }
2803
2804 static void rtl_release_firmware(struct rtl8169_private *tp)
2805 {
2806         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2807                 release_firmware(tp->rtl_fw->fw);
2808                 kfree(tp->rtl_fw);
2809         }
2810         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2811 }
2812
2813 static void rtl_apply_firmware(struct rtl8169_private *tp)
2814 {
2815         struct rtl_fw *rtl_fw = tp->rtl_fw;
2816
2817         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2818         if (!IS_ERR_OR_NULL(rtl_fw))
2819                 rtl_phy_write_fw(tp, rtl_fw);
2820 }
2821
2822 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, uint8_t reg,
2823                                     uint16_t val)
2824 {
2825         if (rtl_readphy(tp, reg) != val)
2826                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2827         else
2828                 rtl_apply_firmware(tp);
2829 }
2830
2831 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2832 {
2833         static const struct phy_reg phy_reg_init[] = {
2834                 { 0x1f, 0x0001 },
2835                 { 0x06, 0x006e },
2836                 { 0x08, 0x0708 },
2837                 { 0x15, 0x4000 },
2838                 { 0x18, 0x65c7 },
2839
2840                 { 0x1f, 0x0001 },
2841                 { 0x03, 0x00a1 },
2842                 { 0x02, 0x0008 },
2843                 { 0x01, 0x0120 },
2844                 { 0x00, 0x1000 },
2845                 { 0x04, 0x0800 },
2846                 { 0x04, 0x0000 },
2847
2848                 { 0x03, 0xff41 },
2849                 { 0x02, 0xdf60 },
2850                 { 0x01, 0x0140 },
2851                 { 0x00, 0x0077 },
2852                 { 0x04, 0x7800 },
2853                 { 0x04, 0x7000 },
2854
2855                 { 0x03, 0x802f },
2856                 { 0x02, 0x4f02 },
2857                 { 0x01, 0x0409 },
2858                 { 0x00, 0xf0f9 },
2859                 { 0x04, 0x9800 },
2860                 { 0x04, 0x9000 },
2861
2862                 { 0x03, 0xdf01 },
2863                 { 0x02, 0xdf20 },
2864                 { 0x01, 0xff95 },
2865                 { 0x00, 0xba00 },
2866                 { 0x04, 0xa800 },
2867                 { 0x04, 0xa000 },
2868
2869                 { 0x03, 0xff41 },
2870                 { 0x02, 0xdf20 },
2871                 { 0x01, 0x0140 },
2872                 { 0x00, 0x00bb },
2873                 { 0x04, 0xb800 },
2874                 { 0x04, 0xb000 },
2875
2876                 { 0x03, 0xdf41 },
2877                 { 0x02, 0xdc60 },
2878                 { 0x01, 0x6340 },
2879                 { 0x00, 0x007d },
2880                 { 0x04, 0xd800 },
2881                 { 0x04, 0xd000 },
2882
2883                 { 0x03, 0xdf01 },
2884                 { 0x02, 0xdf20 },
2885                 { 0x01, 0x100a },
2886                 { 0x00, 0xa0ff },
2887                 { 0x04, 0xf800 },
2888                 { 0x04, 0xf000 },
2889
2890                 { 0x1f, 0x0000 },
2891                 { 0x0b, 0x0000 },
2892                 { 0x00, 0x9200 }
2893         };
2894
2895         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2896 }
2897
2898 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2899 {
2900         static const struct phy_reg phy_reg_init[] = {
2901                 { 0x1f, 0x0002 },
2902                 { 0x01, 0x90d0 },
2903                 { 0x1f, 0x0000 }
2904         };
2905
2906         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2907 }
2908
2909 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2910 {
2911         struct pci_device *pdev = tp->pci_dev;
2912
2913         if ((pci_get_subvendor(pdev) != PCI_VENDOR_ID_GIGABYTE) ||
2914             (pci_get_subdevice(pdev) != 0xe000))
2915                 return;
2916
2917         rtl_writephy(tp, 0x1f, 0x0001);
2918         rtl_writephy(tp, 0x10, 0xf01b);
2919         rtl_writephy(tp, 0x1f, 0x0000);
2920 }
2921
2922 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2923 {
2924         static const struct phy_reg phy_reg_init[] = {
2925                 { 0x1f, 0x0001 },
2926                 { 0x04, 0x0000 },
2927                 { 0x03, 0x00a1 },
2928                 { 0x02, 0x0008 },
2929                 { 0x01, 0x0120 },
2930                 { 0x00, 0x1000 },
2931                 { 0x04, 0x0800 },
2932                 { 0x04, 0x9000 },
2933                 { 0x03, 0x802f },
2934                 { 0x02, 0x4f02 },
2935                 { 0x01, 0x0409 },
2936                 { 0x00, 0xf099 },
2937                 { 0x04, 0x9800 },
2938                 { 0x04, 0xa000 },
2939                 { 0x03, 0xdf01 },
2940                 { 0x02, 0xdf20 },
2941                 { 0x01, 0xff95 },
2942                 { 0x00, 0xba00 },
2943                 { 0x04, 0xa800 },
2944                 { 0x04, 0xf000 },
2945                 { 0x03, 0xdf01 },
2946                 { 0x02, 0xdf20 },
2947                 { 0x01, 0x101a },
2948                 { 0x00, 0xa0ff },
2949                 { 0x04, 0xf800 },
2950                 { 0x04, 0x0000 },
2951                 { 0x1f, 0x0000 },
2952
2953                 { 0x1f, 0x0001 },
2954                 { 0x10, 0xf41b },
2955                 { 0x14, 0xfb54 },
2956                 { 0x18, 0xf5c7 },
2957                 { 0x1f, 0x0000 },
2958
2959                 { 0x1f, 0x0001 },
2960                 { 0x17, 0x0cc0 },
2961                 { 0x1f, 0x0000 }
2962         };
2963
2964         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2965
2966         rtl8169scd_hw_phy_config_quirk(tp);
2967 }
2968
2969 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2970 {
2971         static const struct phy_reg phy_reg_init[] = {
2972                 { 0x1f, 0x0001 },
2973                 { 0x04, 0x0000 },
2974                 { 0x03, 0x00a1 },
2975                 { 0x02, 0x0008 },
2976                 { 0x01, 0x0120 },
2977                 { 0x00, 0x1000 },
2978                 { 0x04, 0x0800 },
2979                 { 0x04, 0x9000 },
2980                 { 0x03, 0x802f },
2981                 { 0x02, 0x4f02 },
2982                 { 0x01, 0x0409 },
2983                 { 0x00, 0xf099 },
2984                 { 0x04, 0x9800 },
2985                 { 0x04, 0xa000 },
2986                 { 0x03, 0xdf01 },
2987                 { 0x02, 0xdf20 },
2988                 { 0x01, 0xff95 },
2989                 { 0x00, 0xba00 },
2990                 { 0x04, 0xa800 },
2991                 { 0x04, 0xf000 },
2992                 { 0x03, 0xdf01 },
2993                 { 0x02, 0xdf20 },
2994                 { 0x01, 0x101a },
2995                 { 0x00, 0xa0ff },
2996                 { 0x04, 0xf800 },
2997                 { 0x04, 0x0000 },
2998                 { 0x1f, 0x0000 },
2999
3000                 { 0x1f, 0x0001 },
3001                 { 0x0b, 0x8480 },
3002                 { 0x1f, 0x0000 },
3003
3004                 { 0x1f, 0x0001 },
3005                 { 0x18, 0x67c7 },
3006                 { 0x04, 0x2000 },
3007                 { 0x03, 0x002f },
3008                 { 0x02, 0x4360 },
3009                 { 0x01, 0x0109 },
3010                 { 0x00, 0x3022 },
3011                 { 0x04, 0x2800 },
3012                 { 0x1f, 0x0000 },
3013
3014                 { 0x1f, 0x0001 },
3015                 { 0x17, 0x0cc0 },
3016                 { 0x1f, 0x0000 }
3017         };
3018
3019         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3020 }
3021
3022 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
3023 {
3024         static const struct phy_reg phy_reg_init[] = {
3025                 { 0x10, 0xf41b },
3026                 { 0x1f, 0x0000 }
3027         };
3028
3029         rtl_writephy(tp, 0x1f, 0x0001);
3030         rtl_patchphy(tp, 0x16, 1 << 0);
3031
3032         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3033 }
3034
3035 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
3036 {
3037         static const struct phy_reg phy_reg_init[] = {
3038                 { 0x1f, 0x0001 },
3039                 { 0x10, 0xf41b },
3040                 { 0x1f, 0x0000 }
3041         };
3042
3043         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3044 }
3045
3046 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3047 {
3048         static const struct phy_reg phy_reg_init[] = {
3049                 { 0x1f, 0x0000 },
3050                 { 0x1d, 0x0f00 },
3051                 { 0x1f, 0x0002 },
3052                 { 0x0c, 0x1ec8 },
3053                 { 0x1f, 0x0000 }
3054         };
3055
3056         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3057 }
3058
3059 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3060 {
3061         static const struct phy_reg phy_reg_init[] = {
3062                 { 0x1f, 0x0001 },
3063                 { 0x1d, 0x3d98 },
3064                 { 0x1f, 0x0000 }
3065         };
3066
3067         rtl_writephy(tp, 0x1f, 0x0000);
3068         rtl_patchphy(tp, 0x14, 1 << 5);
3069         rtl_patchphy(tp, 0x0d, 1 << 5);
3070
3071         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3072 }
3073
3074 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3075 {
3076         static const struct phy_reg phy_reg_init[] = {
3077                 { 0x1f, 0x0001 },
3078                 { 0x12, 0x2300 },
3079                 { 0x1f, 0x0002 },
3080                 { 0x00, 0x88d4 },
3081                 { 0x01, 0x82b1 },
3082                 { 0x03, 0x7002 },
3083                 { 0x08, 0x9e30 },
3084                 { 0x09, 0x01f0 },
3085                 { 0x0a, 0x5500 },
3086                 { 0x0c, 0x00c8 },
3087                 { 0x1f, 0x0003 },
3088                 { 0x12, 0xc096 },
3089                 { 0x16, 0x000a },
3090                 { 0x1f, 0x0000 },
3091                 { 0x1f, 0x0000 },
3092                 { 0x09, 0x2000 },
3093                 { 0x09, 0x0000 }
3094         };
3095
3096         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3097
3098         rtl_patchphy(tp, 0x14, 1 << 5);
3099         rtl_patchphy(tp, 0x0d, 1 << 5);
3100         rtl_writephy(tp, 0x1f, 0x0000);
3101 }
3102
3103 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3104 {
3105         static const struct phy_reg phy_reg_init[] = {
3106                 { 0x1f, 0x0001 },
3107                 { 0x12, 0x2300 },
3108                 { 0x03, 0x802f },
3109                 { 0x02, 0x4f02 },
3110                 { 0x01, 0x0409 },
3111                 { 0x00, 0xf099 },
3112                 { 0x04, 0x9800 },
3113                 { 0x04, 0x9000 },
3114                 { 0x1d, 0x3d98 },
3115                 { 0x1f, 0x0002 },
3116                 { 0x0c, 0x7eb8 },
3117                 { 0x06, 0x0761 },
3118                 { 0x1f, 0x0003 },
3119                 { 0x16, 0x0f0a },
3120                 { 0x1f, 0x0000 }
3121         };
3122
3123         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3124
3125         rtl_patchphy(tp, 0x16, 1 << 0);
3126         rtl_patchphy(tp, 0x14, 1 << 5);
3127         rtl_patchphy(tp, 0x0d, 1 << 5);
3128         rtl_writephy(tp, 0x1f, 0x0000);
3129 }
3130
3131 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3132 {
3133         static const struct phy_reg phy_reg_init[] = {
3134                 { 0x1f, 0x0001 },
3135                 { 0x12, 0x2300 },
3136                 { 0x1d, 0x3d98 },
3137                 { 0x1f, 0x0002 },
3138                 { 0x0c, 0x7eb8 },
3139                 { 0x06, 0x5461 },
3140                 { 0x1f, 0x0003 },
3141                 { 0x16, 0x0f0a },
3142                 { 0x1f, 0x0000 }
3143         };
3144
3145         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3146
3147         rtl_patchphy(tp, 0x16, 1 << 0);
3148         rtl_patchphy(tp, 0x14, 1 << 5);
3149         rtl_patchphy(tp, 0x0d, 1 << 5);
3150         rtl_writephy(tp, 0x1f, 0x0000);
3151 }
3152
3153 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3154 {
3155         rtl8168c_3_hw_phy_config(tp);
3156 }
3157
3158 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3159 {
3160         static const struct phy_reg phy_reg_init_0[] = {
3161                 /* Channel Estimation */
3162                 { 0x1f, 0x0001 },
3163                 { 0x06, 0x4064 },
3164                 { 0x07, 0x2863 },
3165                 { 0x08, 0x059c },
3166                 { 0x09, 0x26b4 },
3167                 { 0x0a, 0x6a19 },
3168                 { 0x0b, 0xdcc8 },
3169                 { 0x10, 0xf06d },
3170                 { 0x14, 0x7f68 },
3171                 { 0x18, 0x7fd9 },
3172                 { 0x1c, 0xf0ff },
3173                 { 0x1d, 0x3d9c },
3174                 { 0x1f, 0x0003 },
3175                 { 0x12, 0xf49f },
3176                 { 0x13, 0x070b },
3177                 { 0x1a, 0x05ad },
3178                 { 0x14, 0x94c0 },
3179
3180                 /*
3181                  * Tx Error Issue
3182                  * Enhance line driver power
3183                  */
3184                 { 0x1f, 0x0002 },
3185                 { 0x06, 0x5561 },
3186                 { 0x1f, 0x0005 },
3187                 { 0x05, 0x8332 },
3188                 { 0x06, 0x5561 },
3189
3190                 /*
3191                  * Can not link to 1Gbps with bad cable
3192                  * Decrease SNR threshold form 21.07dB to 19.04dB
3193                  */
3194                 { 0x1f, 0x0001 },
3195                 { 0x17, 0x0cc0 },
3196
3197                 { 0x1f, 0x0000 },
3198                 { 0x0d, 0xf880 }
3199         };
3200
3201         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3202
3203         /*
3204          * Rx Error Issue
3205          * Fine Tune Switching regulator parameter
3206          */
3207         rtl_writephy(tp, 0x1f, 0x0002);
3208         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3209         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3210
3211         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3212                 static const struct phy_reg phy_reg_init[] = {
3213                         { 0x1f, 0x0002 },
3214                         { 0x05, 0x669a },
3215                         { 0x1f, 0x0005 },
3216                         { 0x05, 0x8330 },
3217                         { 0x06, 0x669a },
3218                         { 0x1f, 0x0002 }
3219                 };
3220                 int val;
3221
3222                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3223
3224                 val = rtl_readphy(tp, 0x0d);
3225
3226                 if ((val & 0x00ff) != 0x006c) {
3227                         static const uint32_t set[] = {
3228                                 0x0065, 0x0066, 0x0067, 0x0068,
3229                                 0x0069, 0x006a, 0x006b, 0x006c
3230                         };
3231                         int i;
3232
3233                         rtl_writephy(tp, 0x1f, 0x0002);
3234
3235                         val &= 0xff00;
3236                         for (i = 0; i < ARRAY_SIZE(set); i++)
3237                                 rtl_writephy(tp, 0x0d, val | set[i]);
3238                 }
3239         } else {
3240                 static const struct phy_reg phy_reg_init[] = {
3241                         { 0x1f, 0x0002 },
3242                         { 0x05, 0x6662 },
3243                         { 0x1f, 0x0005 },
3244                         { 0x05, 0x8330 },
3245                         { 0x06, 0x6662 }
3246                 };
3247
3248                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3249         }
3250
3251         /* RSET couple improve */
3252         rtl_writephy(tp, 0x1f, 0x0002);
3253         rtl_patchphy(tp, 0x0d, 0x0300);
3254         rtl_patchphy(tp, 0x0f, 0x0010);
3255
3256         /* Fine tune PLL performance */
3257         rtl_writephy(tp, 0x1f, 0x0002);
3258         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3259         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3260
3261         rtl_writephy(tp, 0x1f, 0x0005);
3262         rtl_writephy(tp, 0x05, 0x001b);
3263
3264         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3265
3266         rtl_writephy(tp, 0x1f, 0x0000);
3267 }
3268
3269 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3270 {
3271         static const struct phy_reg phy_reg_init_0[] = {
3272                 /* Channel Estimation */
3273                 { 0x1f, 0x0001 },
3274                 { 0x06, 0x4064 },
3275                 { 0x07, 0x2863 },
3276                 { 0x08, 0x059c },
3277                 { 0x09, 0x26b4 },
3278                 { 0x0a, 0x6a19 },
3279                 { 0x0b, 0xdcc8 },
3280                 { 0x10, 0xf06d },
3281                 { 0x14, 0x7f68 },
3282                 { 0x18, 0x7fd9 },
3283                 { 0x1c, 0xf0ff },
3284                 { 0x1d, 0x3d9c },
3285                 { 0x1f, 0x0003 },
3286                 { 0x12, 0xf49f },
3287                 { 0x13, 0x070b },
3288                 { 0x1a, 0x05ad },
3289                 { 0x14, 0x94c0 },
3290
3291                 /*
3292                  * Tx Error Issue
3293                  * Enhance line driver power
3294                  */
3295                 { 0x1f, 0x0002 },
3296                 { 0x06, 0x5561 },
3297                 { 0x1f, 0x0005 },
3298                 { 0x05, 0x8332 },
3299                 { 0x06, 0x5561 },
3300
3301                 /*
3302                  * Can not link to 1Gbps with bad cable
3303                  * Decrease SNR threshold form 21.07dB to 19.04dB
3304                  */
3305                 { 0x1f, 0x0001 },
3306                 { 0x17, 0x0cc0 },
3307
3308                 { 0x1f, 0x0000 },
3309                 { 0x0d, 0xf880 }
3310         };
3311
3312         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3313
3314         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3315                 static const struct phy_reg phy_reg_init[] = {
3316                         { 0x1f, 0x0002 },
3317                         { 0x05, 0x669a },
3318                         { 0x1f, 0x0005 },
3319                         { 0x05, 0x8330 },
3320                         { 0x06, 0x669a },
3321
3322                         { 0x1f, 0x0002 }
3323                 };
3324                 int val;
3325
3326                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3327
3328                 val = rtl_readphy(tp, 0x0d);
3329                 if ((val & 0x00ff) != 0x006c) {
3330                         static const uint32_t set[] = {
3331                                 0x0065, 0x0066, 0x0067, 0x0068,
3332                                 0x0069, 0x006a, 0x006b, 0x006c
3333                         };
3334                         int i;
3335
3336                         rtl_writephy(tp, 0x1f, 0x0002);
3337
3338                         val &= 0xff00;
3339                         for (i = 0; i < ARRAY_SIZE(set); i++)
3340                                 rtl_writephy(tp, 0x0d, val | set[i]);
3341                 }
3342         } else {
3343